X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fbus%2Fdpaa%2Frte_dpaa_bus.h;h=48d5cf4625b91b86d8f82ce406b1ce25a19ab11a;hb=c9a1c2e5883d71c799fb25fcf26fb9b81caed56d;hp=c2b2375343aa20f30c4d46019662f7881344047a;hpb=8c83f28cc8a4dc7ee0fab676051dd483695d4140;p=dpdk.git diff --git a/drivers/bus/dpaa/rte_dpaa_bus.h b/drivers/bus/dpaa/rte_dpaa_bus.h index c2b2375343..48d5cf4625 100644 --- a/drivers/bus/dpaa/rte_dpaa_bus.h +++ b/drivers/bus/dpaa/rte_dpaa_bus.h @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2017 NXP + * Copyright 2017-2020 NXP * */ #ifndef __RTE_DPAA_BUS_H__ #define __RTE_DPAA_BUS_H__ #include +#include #include #include @@ -16,6 +17,33 @@ #include #include +/* This sequence number field is used to store event entry index for + * driver specific usage. For parallel mode queues, invalid + * index will be set and for atomic mode queues, valid value + * ranging from 1 to 16. + */ +#define DPAA_INVALID_MBUF_SEQN 0 + +typedef uint32_t dpaa_seqn_t; +extern int dpaa_seqn_dynfield_offset; + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice + * + * Read dpaa sequence number from mbuf. + * + * @param mbuf Structure to read from. + * @return pointer to dpaa sequence number. + */ +__rte_experimental +static inline dpaa_seqn_t * +dpaa_seqn(struct rte_mbuf *mbuf) +{ + return RTE_MBUF_DYNFIELD(mbuf, dpaa_seqn_dynfield_offset, + dpaa_seqn_t *); +} + #define DPAA_MEMPOOL_OPS_NAME "dpaa" #define DEV_TO_DPAA_DEVICE(ptr) \ @@ -30,13 +58,14 @@ #define SVR_LS1046A_FAMILY 0x87070000 #define SVR_MASK 0xffff0000 +/** Device driver supports link state interrupt */ +#define RTE_DPAA_DRV_INTR_LSC 0x0008 + #define RTE_DEV_TO_DPAA_CONST(ptr) \ container_of(ptr, const struct rte_dpaa_device, device) extern unsigned int dpaa_svr_family; -extern RTE_DEFINE_PER_LCORE(bool, dpaa_io); - struct rte_dpaa_device; struct rte_dpaa_driver; @@ -44,9 +73,6 @@ struct rte_dpaa_driver; TAILQ_HEAD(rte_dpaa_device_list, rte_dpaa_device); TAILQ_HEAD(rte_dpaa_driver_list, rte_dpaa_driver); -/* Configuration variables exported from DPAA bus */ -extern struct netcfg_info *dpaa_netcfg; - enum rte_dpaa_type { FSL_DPAA_ETH = 1, FSL_DPAA_CRYPTO, @@ -91,14 +117,41 @@ struct rte_dpaa_driver { enum rte_dpaa_type drv_type; rte_dpaa_probe_t probe; rte_dpaa_remove_t remove; + uint32_t drv_flags; /**< Flags for controlling device.*/ +}; + +/* Create storage for dqrr entries per lcore */ +#define DPAA_PORTAL_DEQUEUE_DEPTH 16 +struct dpaa_portal_dqrr { + void *mbuf[DPAA_PORTAL_DEQUEUE_DEPTH]; + uint64_t dqrr_held; + uint8_t dqrr_size; }; struct dpaa_portal { uint32_t bman_idx; /**< BMAN Portal ID*/ uint32_t qman_idx; /**< QMAN Portal ID*/ + struct dpaa_portal_dqrr dpaa_held_bufs; + struct rte_crypto_op **dpaa_sec_ops; + int dpaa_sec_op_nb; uint64_t tid;/**< Parent Thread id for this portal */ }; +RTE_DECLARE_PER_LCORE(struct dpaa_portal *, dpaa_io); + +#define DPAA_PER_LCORE_PORTAL \ + RTE_PER_LCORE(dpaa_io) +#define DPAA_PER_LCORE_DQRR_SIZE \ + RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.dqrr_size +#define DPAA_PER_LCORE_DQRR_HELD \ + RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.dqrr_held +#define DPAA_PER_LCORE_DQRR_MBUF(i) \ + RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.mbuf[i] +#define DPAA_PER_LCORE_RTE_CRYPTO_OP \ + RTE_PER_LCORE(dpaa_io)->dpaa_sec_ops +#define DPAA_PER_LCORE_DPAA_SEC_OP_NB \ + RTE_PER_LCORE(dpaa_io)->dpaa_sec_op_nb + /* Various structures representing contiguous memory maps */ struct dpaa_memseg { TAILQ_ENTRY(dpaa_memseg) next; @@ -132,7 +185,23 @@ static inline void *rte_dpaa_mem_ptov(phys_addr_t paddr) } /* If not, Fallback to full memseg list searching */ - return rte_mem_iova2virt(paddr); + va = rte_mem_iova2virt(paddr); + + dpaax_iova_table_update(paddr, va, RTE_CACHE_LINE_SIZE); + + return va; +} + +static inline rte_iova_t +rte_dpaa_mem_vtop(void *vaddr) +{ + const struct rte_memseg *ms; + + ms = rte_mem_virt2memseg(vaddr, NULL); + if (ms) + return ms->iova + RTE_PTR_DIFF(vaddr, ms->addr); + + return (size_t)NULL; } /** @@ -142,6 +211,7 @@ static inline void *rte_dpaa_mem_ptov(phys_addr_t paddr) * A pointer to a rte_dpaa_driver structure describing the driver * to be registered. */ +__rte_internal void rte_dpaa_driver_register(struct rte_dpaa_driver *driver); /** @@ -151,6 +221,7 @@ void rte_dpaa_driver_register(struct rte_dpaa_driver *driver); * A pointer to a rte_dpaa_driver structure describing the driver * to be unregistered. */ +__rte_internal void rte_dpaa_driver_unregister(struct rte_dpaa_driver *driver); /** @@ -162,10 +233,13 @@ void rte_dpaa_driver_unregister(struct rte_dpaa_driver *driver); * @return * 0 in case of success, error otherwise */ +__rte_internal int rte_dpaa_portal_init(void *arg); +__rte_internal int rte_dpaa_portal_fq_init(void *arg, struct qman_fq *fq); +__rte_internal int rte_dpaa_portal_fq_close(struct qman_fq *fq); /** @@ -182,19 +256,8 @@ RTE_INIT(dpaainitfn_ ##nm) \ } \ RTE_PMD_EXPORT_NAME(nm, __COUNTER__) -/* Create storage for dqrr entries per lcore */ -#define DPAA_PORTAL_DEQUEUE_DEPTH 16 -struct dpaa_portal_dqrr { - void *mbuf[DPAA_PORTAL_DEQUEUE_DEPTH]; - uint64_t dqrr_held; - uint8_t dqrr_size; -}; - -RTE_DECLARE_PER_LCORE(struct dpaa_portal_dqrr, held_bufs); - -#define DPAA_PER_LCORE_DQRR_SIZE RTE_PER_LCORE(held_bufs).dqrr_size -#define DPAA_PER_LCORE_DQRR_HELD RTE_PER_LCORE(held_bufs).dqrr_held -#define DPAA_PER_LCORE_DQRR_MBUF(i) RTE_PER_LCORE(held_bufs).mbuf[i] +__rte_internal +struct fm_eth_port_cfg *dpaa_get_eth_port_cfg(int dev_id); #ifdef __cplusplus }