X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fcnxk%2Froc_mbox.h;h=8967858914ec898eaed341f190bbd01fa2490837;hb=da718c1919bd49faa83ded38b0549500c7e77f91;hp=9c529d7546eee7df8d3cb69adaf7fa96c98f32a6;hpb=9854e5db5d973e0b59330022cd1bfbb0ff3df3c8;p=dpdk.git diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 9c529d7546..8967858914 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -28,7 +28,7 @@ struct mbox_msghdr { #define MBOX_RSP_SIG (0xbeef) /* Signature, for validating corrupted msgs */ uint16_t __io sig; -#define MBOX_VERSION (0x000a) +#define MBOX_VERSION (0x000b) /* Version of msg's structure for this ID */ uint16_t __io ver; /* Offset of next msg within mailbox region */ @@ -131,6 +131,8 @@ struct mbox_msghdr { M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \ tim_enable_rsp) \ M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \ + M(TIM_GET_MIN_INTVL, 0x805, tim_get_min_intvl, tim_intvl_req, \ + tim_intvl_rsp) \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \ M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ @@ -143,11 +145,22 @@ struct mbox_msghdr { M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \ M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ msg_rsp) \ + M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \ cpt_rx_inline_lf_cfg_msg, msg_rsp) \ M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \ M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \ cpt_eng_grp_rsp) \ + /* REE mbox IDs (range 0xE00 - 0xFFF) */ \ + M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp) \ + M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg, \ + ree_rd_wr_reg_msg) \ + M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \ + msg_rsp) \ + M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg, \ + ree_rule_db_len_rsp_msg) \ + M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg, \ + ree_rule_db_get_rsp_msg) \ /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \ msg_rsp) \ @@ -234,7 +247,17 @@ struct mbox_msghdr { nix_inline_ipsec_lf_cfg, msg_rsp) \ M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ nix_cn10k_aq_enq_rsp) \ - M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) + M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ + M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \ + nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \ + M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ + msg_rsp) \ + M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ + nix_bandprof_get_hwinfo_rsp) \ + M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ + nix_bp_cfg_rsp) \ + M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ + msg_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -278,19 +301,44 @@ struct ready_msg_rsp { uint16_t __io rclk_freq; /* RCLK frequency */ }; +enum npc_pkind_type { + NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL, + NPC_RX_VLAN_EXDSA_PKIND = 56ULL, + NPC_RX_CHLEN24B_PKIND, + NPC_RX_CPT_HDR_PKIND, + NPC_RX_CHLEN90B_PKIND, + NPC_TX_HIGIG_PKIND, + NPC_RX_HIGIG_PKIND, + NPC_RX_EXDSA_PKIND, + NPC_RX_EDSA_PKIND, + NPC_TX_DEF_PKIND, +}; + /* Struct to set pkind */ struct npc_set_pkind { struct mbox_msghdr hdr; -#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0) -#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1) -#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2) -#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3) -#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63) +#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0) +#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1) +#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2) +#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3) +#define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4) +#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5) +#define ROC_PRIV_FLAGS_PRE_L2 BIT_ULL(6) +#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63) uint64_t __io mode; #define PKIND_TX BIT_ULL(0) #define PKIND_RX BIT_ULL(1) uint8_t __io dir; uint8_t __io pkind; /* valid only in case custom flag */ + uint8_t __io var_len_off; + /* Offset of custom header length field. + * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND + */ + uint8_t __io var_len_off_mask; /* Mask for length with in offset */ + uint8_t __io shift_dir; + /* Shift direction to get length of the + * header at var_len_off + */ }; /* Structure for requesting resource provisioning. @@ -709,6 +757,7 @@ struct nix_lf_alloc_req { uint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ uint64_t __io way_mask; #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) +#define NIX_LF_LBK_BLK_SEL BIT_ULL(1) uint64_t flags; }; @@ -757,6 +806,10 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss; /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce; + /* Valid when op == WRITE/INIT and + * ctype == NIX_AQ_CTYPE_BAND_PROF + */ + __io struct nix_band_prof_s prof; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -770,6 +823,8 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss_mask; /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce_mask; + /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */ + __io struct nix_band_prof_s prof_mask; }; }; @@ -781,6 +836,7 @@ struct nix_cn10k_aq_enq_rsp { struct nix_cq_ctx_s cq; struct nix_rsse_s rss; struct nix_rx_mce_s mce; + struct nix_band_prof_s prof; }; }; @@ -1034,6 +1090,7 @@ struct nix_rx_cfg { struct mbox_msghdr hdr; #define NIX_RX_OL3_VERIFY BIT(0) #define NIX_RX_OL4_VERIFY BIT(1) +#define NIX_RX_DROP_RE BIT(2) uint8_t __io len_verify; /* Outer L3/L4 len check */ #define NIX_RX_CSUM_OL4_VERIFY BIT(0) uint8_t __io csum_verify; /* Outer L4 checksum verification */ @@ -1115,6 +1172,33 @@ struct nix_hw_info { uint16_t __io rsvd[15]; }; +struct nix_bandprof_alloc_req { + struct mbox_msghdr hdr; + /* Count of profiles needed per layer */ + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; +}; + +struct nix_bandprof_alloc_rsp { + struct mbox_msghdr hdr; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + +#define BANDPROF_PER_PFFUNC 64 + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + +struct nix_bandprof_free_req { + struct mbox_msghdr hdr; + uint8_t __io free_all; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + +struct nix_bandprof_get_hwinfo_rsp { + struct mbox_msghdr hdr; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + uint32_t __io policer_timeunit; +}; + /* SSO mailbox error codes * Range 501 - 600. */ @@ -1331,6 +1415,9 @@ struct cpt_rxc_time_cfg_req { struct cpt_rx_inline_lf_cfg_msg { struct mbox_msghdr hdr; uint16_t __io sso_pf_func; + uint16_t __io param1; + uint16_t __io param2; + uint16_t __io reserved; }; enum cpt_eng_type { @@ -1376,6 +1463,96 @@ struct cpt_eng_grp_rsp { uint8_t __io eng_grp_num; }; +/* REE mailbox error codes + * Range 1001 - 1100. + */ +enum ree_af_status { + REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001, + REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002, + REE_AF_ERR_LF_INVALID = -1003, + REE_AF_ERR_ACCESS_DENIED = -1004, + REE_AF_ERR_RULE_DB_PARTIAL = -1005, + REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006, + REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007, + REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008, + REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009, + REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010, + REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011, + REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012, + REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013, + REE_AF_ERR_RULE_DB_TOO_BIG = -1014, + REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015, + REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016, + REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017, + REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018, + REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019, + REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020, + REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021, + REE_AF_ERR_LF_WRONG_PRIORITY = -1022, + REE_AF_ERR_LF_SIZE_TOO_BIG = -1023, +}; + +/* REE mbox message formats */ + +struct ree_req_msg { + struct mbox_msghdr hdr; + uint32_t __io blkaddr; +}; + +struct ree_lf_req_msg { + struct mbox_msghdr hdr; + uint32_t __io blkaddr; + uint32_t __io size; + uint8_t __io lf; + uint8_t __io pri; +}; + +struct ree_rule_db_prog_req_msg { + struct mbox_msghdr hdr; +#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1) + uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE]; + uint32_t __io blkaddr; /* REE0 or REE1 */ + uint32_t __io total_len; /* total len of rule db */ + uint32_t __io offset; /* offset of current rule db block */ + uint16_t __io len; /* length of rule db block */ + uint8_t __io is_last; /* is this the last block */ + uint8_t __io is_incremental; /* is incremental flow */ + uint8_t __io is_dbi; /* is rule db incremental */ +}; + +struct ree_rule_db_get_req_msg { + struct mbox_msghdr hdr; + uint32_t __io blkaddr; + uint32_t __io offset; /* retrieve db from this offset */ + uint8_t __io is_dbi; /* is request for rule db incremental */ +}; + +struct ree_rd_wr_reg_msg { + struct mbox_msghdr hdr; + uint64_t __io reg_offset; + uint64_t __io *ret_val; + uint64_t __io val; + uint32_t __io blkaddr; + uint8_t __io is_write; +}; + +struct ree_rule_db_len_rsp_msg { + struct mbox_msghdr hdr; + uint32_t __io blkaddr; + uint32_t __io len; + uint32_t __io inc_len; +}; + +struct ree_rule_db_get_rsp_msg { + struct mbox_msghdr hdr; +#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL) + uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE]; + uint32_t __io total_len; /* total len of rule db */ + uint32_t __io offset; /* offset of current rule db block */ + uint16_t __io len; /* length of rule db block */ + uint8_t __io is_last; /* is this the last block */ +}; + /* NPC mbox message structs */ #define NPC_MCAM_ENTRY_INVALID 0xFFFF @@ -1738,6 +1915,9 @@ struct tim_config_req { uint32_t __io chunksize; uint32_t __io interval; uint8_t __io gpioedge; + uint8_t __io rsvd[7]; + uint64_t __io intervalns; + uint64_t __io clockfreq; }; struct tim_lf_alloc_rsp { @@ -1751,6 +1931,18 @@ struct tim_enable_rsp { uint32_t __io currentbucket; }; +struct tim_intvl_req { + struct mbox_msghdr hdr; + uint8_t __io clocksource; + uint64_t __io clockfreq; +}; + +struct tim_intvl_rsp { + struct mbox_msghdr hdr; + uint64_t __io intvl_cyc; + uint64_t __io intvl_ns; +}; + struct sdp_node_info { /* Node to which this PF belons to */ uint8_t __io node_id;