X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fcnxk%2Froc_platform.h;h=241655b3347527b5fa716f360d79029be9c55819;hb=1ec23c7523b4c42b15f9e4880a5a38fd215ea1be;hp=5675359ade5af33f15dd7ae82d5f55565d00dd51;hpb=01bc01e1bb5631d137764e1edc13721f93784b41;p=dpdk.git diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 5675359ade..241655b334 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -23,15 +23,21 @@ #include "roc_bits.h" #if defined(__ARM_FEATURE_SVE) -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse+sve\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" \ + ".arch_extension sve\n" #else -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" #endif #define PLT_ASSERT RTE_ASSERT #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE #define PLT_STD_C11 RTE_STD_C11 #define PLT_PTR_ADD RTE_PTR_ADD +#define PLT_PTR_DIFF RTE_PTR_DIFF #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET #define PLT_MIN RTE_MIN @@ -44,6 +50,7 @@ #define PLT_MODEL_MZ_NAME "roc_model_mz" #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE #define BITMASK_ULL GENMASK_ULL +#define PLT_ALIGN_CEIL RTE_ALIGN_CEIL /** Divide ceil */ #define PLT_DIV_CEIL(x, y) \ @@ -71,6 +78,7 @@ #define plt_cpu_to_be_64 rte_cpu_to_be_64 #define plt_be_to_cpu_64 rte_be_to_cpu_64 +#define plt_align32pow2 rte_align32pow2 #define plt_align32prevpow2 rte_align32prevpow2 #define plt_bitmap rte_bitmap @@ -107,10 +115,11 @@ #define plt_write64(val, addr) \ rte_write64_relaxed((val), (volatile void *)(addr)) -#define plt_wmb() rte_wmb() -#define plt_rmb() rte_rmb() -#define plt_io_wmb() rte_io_wmb() -#define plt_io_rmb() rte_io_rmb() +#define plt_wmb() rte_wmb() +#define plt_rmb() rte_rmb() +#define plt_io_wmb() rte_io_wmb() +#define plt_io_rmb() rte_io_rmb() +#define plt_atomic_thread_fence rte_atomic_thread_fence #define plt_mmap mmap #define PLT_PROT_READ PROT_READ @@ -122,6 +131,8 @@ #define plt_memzone_reserve_cache_align(name, sz) \ rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) #define plt_memzone_free rte_memzone_free +#define plt_memzone_reserve_aligned(name, len, flags, align) \ + rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) #define plt_tsc_hz rte_get_tsc_hz #define plt_delay_ms rte_delay_ms @@ -133,6 +144,15 @@ /* Log */ extern int cnxk_logtype_base; +extern int cnxk_logtype_mbox; +extern int cnxk_logtype_cpt; +extern int cnxk_logtype_npa; +extern int cnxk_logtype_nix; +extern int cnxk_logtype_npc; +extern int cnxk_logtype_sso; +extern int cnxk_logtype_tim; +extern int cnxk_logtype_tm; + #define plt_err(fmt, args...) \ RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) @@ -148,24 +168,34 @@ extern int cnxk_logtype_base; ##args) #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) +#define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) +#define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) +#define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) +#define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) +#define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) +#define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) +#define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) +#define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) + +/* Datapath logs */ +#define plt_dp_err(fmt, args...) \ + RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) +#define plt_dp_info(fmt, args...) \ + RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args) #ifdef __cplusplus -#define CNXK_PCI_ID(subsystem_dev, dev) \ - { \ - RTE_CLASS_ANY_ID, \ - PCI_VENDOR_ID_CAVIUM, \ - (dev), \ - PCI_ANY_ID, \ - (subsystem_dev), \ +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ + (subsystem_dev), \ } #else -#define CNXK_PCI_ID(subsystem_dev, dev) \ - { \ - .class_id = RTE_CLASS_ANY_ID, \ - .vendor_id = PCI_VENDOR_ID_CAVIUM, \ - .device_id = (dev), \ - .subsystem_vendor_id = PCI_ANY_ID, \ - .subsystem_device_id = (subsystem_dev), \ +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + .class_id = RTE_CLASS_ANY_ID, \ + .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ + .subsystem_vendor_id = RTE_PCI_ANY_ID, \ + .subsystem_device_id = (subsystem_dev), \ } #endif @@ -176,4 +206,15 @@ int roc_plt_init(void); typedef int (*roc_plt_init_cb_t)(void); int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); +static inline const void * +plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) +{ + /* To ensure returned memory is physically contiguous, bounding + * the start and end address in 2M range. + */ + return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, + RTE_MEMZONE_IOVA_CONTIG, + align, RTE_PGSIZE_2M); +} + #endif /* _ROC_PLATFORM_H_ */