X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fcpt%2Fcpt_ucode.h;h=0dac12ee308d1b929e8bf9cd178f4e683e49cf76;hb=93520085efdaf5581710174555ab03dc31766391;hp=908566778103aa497c041e071d80c87d1269b3e2;hpb=ba48221f4a9eecd3ae213a9bd5c9078ea282c56e;p=dpdk.git diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h index 9085667781..0dac12ee30 100644 --- a/drivers/common/cpt/cpt_ucode.h +++ b/drivers/common/cpt/cpt_ucode.h @@ -4,7 +4,6 @@ #ifndef _CPT_UCODE_H_ #define _CPT_UCODE_H_ - #include #include "cpt_common.h" @@ -56,7 +55,7 @@ cpt_is_algo_supported(struct rte_crypto_sym_xform *xform) } static __rte_always_inline void -gen_key_snow3g(uint8_t *ck, uint32_t *keyx) +gen_key_snow3g(const uint8_t *ck, uint32_t *keyx) { int i, base; @@ -90,8 +89,7 @@ cpt_fc_ciph_validate_key_aes(uint16_t key_len) } static __rte_always_inline int -cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx, - uint16_t key_len) +cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len) { int fc_type = 0; switch (type) { @@ -126,7 +124,7 @@ cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx, if (unlikely(key_len != 16)) return -1; /* No support for AEAD yet */ - if (unlikely(cpt_ctx->hash_type)) + if (unlikely(ctx->hash_type)) return -1; fc_type = ZUC_SNOW3G; break; @@ -135,14 +133,16 @@ cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx, if (unlikely(key_len != 16)) return -1; /* No support for AEAD yet */ - if (unlikely(cpt_ctx->hash_type)) + if (unlikely(ctx->hash_type)) return -1; fc_type = KASUMI; break; default: return -1; } - return fc_type; + + ctx->fc_type = fc_type; + return 0; } static __rte_always_inline void @@ -175,63 +175,57 @@ cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len) } static __rte_always_inline void -cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, uint8_t *key, +cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, const uint8_t *key, uint16_t key_len) { uint32_t keyx[4]; cpt_ctx->snow3g = 1; gen_key_snow3g(key, keyx); memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len); - cpt_ctx->fc_type = ZUC_SNOW3G; cpt_ctx->zsk_flags = 0; } static __rte_always_inline void -cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, uint8_t *key, +cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, const uint8_t *key, uint16_t key_len) { cpt_ctx->snow3g = 0; memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len); memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32); - cpt_ctx->fc_type = ZUC_SNOW3G; cpt_ctx->zsk_flags = 0; } static __rte_always_inline void -cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, uint8_t *key, +cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, const uint8_t *key, uint16_t key_len) { cpt_ctx->k_ecb = 1; memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); cpt_ctx->zsk_flags = 0; - cpt_ctx->fc_type = KASUMI; } static __rte_always_inline void -cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, uint8_t *key, +cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, const uint8_t *key, uint16_t key_len) { memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); cpt_ctx->zsk_flags = 0; - cpt_ctx->fc_type = KASUMI; } static __rte_always_inline int -cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key, +cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key, uint16_t key_len, uint8_t *salt) { struct cpt_ctx *cpt_ctx = ctx; mc_fc_context_t *fctx = &cpt_ctx->fctx; uint64_t *ctrl_flags = NULL; - int fc_type; + int ret; - /* Validate key before proceeding */ - fc_type = cpt_fc_ciph_validate_key(type, cpt_ctx, key_len); - if (unlikely(fc_type == -1)) + ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len); + if (unlikely(ret)) return -1; - if (fc_type == FC_GEN) { - cpt_ctx->fc_type = FC_GEN; + if (cpt_ctx->fc_type == FC_GEN) { ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags); *ctrl_flags = rte_be_to_cpu_64(*ctrl_flags); /* @@ -459,7 +453,197 @@ fill_sg_comp_from_iov(sg_comp_t *list, return (uint32_t)i; } -static __rte_always_inline int +static __rte_always_inline void +cpt_digest_gen_prep(uint32_t flags, + uint64_t d_lens, + digest_params_t *params, + void *op, + void **prep_req) +{ + struct cpt_request_info *req; + uint32_t size, i; + uint16_t data_len, mac_len, key_len; + auth_type_t hash_type; + buf_ptr_t *meta_p; + struct cpt_ctx *ctx; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + void *c_vaddr, *m_vaddr; + uint64_t c_dma, m_dma; + opcode_info_t opcode; + + ctx = params->ctx_buf.vaddr; + meta_p = ¶ms->meta_buf; + + m_vaddr = meta_p->vaddr; + m_dma = meta_p->dma_addr; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + hash_type = ctx->hash_type; + mac_len = ctx->mac_len; + key_len = ctx->auth_key_len; + data_len = AUTH_DLEN(d_lens); + + /*GP op header */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8); + if (ctx->hmac) { + opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE; + vq_cmd_w0.s.param1 = key_len; + vq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len); + } else { + opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE; + vq_cmd_w0.s.param1 = 0; + vq_cmd_w0.s.dlen = data_len; + } + + opcode.s.minor = 0; + + /* Null auth only case enters the if */ + if (unlikely(!hash_type && !ctx->enc_cipher)) { + opcode.s.major = CPT_MAJOR_OP_MISC; + /* Minor op is passthrough */ + opcode.s.minor = 0x03; + /* Send out completion code only */ + vq_cmd_w0.s.param2 = 0x1; + } + + vq_cmd_w0.s.opcode = opcode.flags; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input gather list + */ + + i = 0; + + if (ctx->hmac) { + uint64_t k_dma = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, auth_key); + /* Key */ + i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len)); + } + + /* input data */ + size = data_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, + 0, &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short" + " by %dB", size); + return; + } + } else { + /* + * Looks like we need to support zero data + * gather ptr in case of hash & hmac + */ + i++; + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Gather list + */ + + i = 0; + scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags & VALID_MAC_BUF) { + if (unlikely(params->mac_buf.size < mac_len)) { + CPT_LOG_DP_ERR("Insufficient MAC size"); + return; + } + + size = mac_len; + i = fill_sg_comp_from_buf_min(scatter_comp, i, + ¶ms->mac_buf, &size); + } else { + size = mac_len; + i = fill_sg_comp_from_iov(scatter_comp, i, + params->src_iov, data_len, + &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient dst IOV size, short by" + " %dB", size); + return; + } + } + + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = size; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return; +} + +static __rte_always_inline void cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, @@ -484,13 +668,11 @@ cpt_enc_hmac_prep(uint32_t flags, vq_cmd_word3_t vq_cmd_w3; void *c_vaddr; uint64_t c_dma; - int32_t m_size; opcode_info_t opcode; meta_p = &fc_params->meta_buf; m_vaddr = meta_p->vaddr; m_dma = meta_p->dma_addr; - m_size = meta_p->size; encr_offset = ENCR_OFFSET(d_offs); auth_offset = AUTH_OFFSET(d_offs); @@ -526,7 +708,6 @@ cpt_enc_hmac_prep(uint32_t flags, m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; /* start cpt request info struct at 8 byte boundary */ size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) - @@ -537,7 +718,6 @@ cpt_enc_hmac_prep(uint32_t flags, size += sizeof(struct cpt_request_info); m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; if (hash_type == GMAC_TYPE) encr_data_len = 0; @@ -598,8 +778,8 @@ cpt_enc_hmac_prep(uint32_t flags, /* GP op header */ vq_cmd_w0.u64 = 0; - vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len); - vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len); + vq_cmd_w0.s.param1 = encr_data_len; + vq_cmd_w0.s.param2 = auth_data_len; /* * In 83XX since we have a limitation of * IV & Offset control word not part of instruction @@ -626,9 +806,9 @@ cpt_enc_hmac_prep(uint32_t flags, req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + outputlen - iv_len); - vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN); + vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN; - vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + vq_cmd_w0.s.opcode = opcode.flags; if (likely(iv_len)) { uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr @@ -657,11 +837,10 @@ cpt_enc_hmac_prep(uint32_t flags, m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; opcode.s.major |= CPT_DMA_MODE; - vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + vq_cmd_w0.s.opcode = opcode.flags; if (likely(iv_len)) { uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr @@ -715,7 +894,7 @@ cpt_enc_hmac_prep(uint32_t flags, if (unlikely(size)) { CPT_LOG_DP_ERR("Insufficient buffer space," " size %d needed", size); - return ERR_BAD_INPUT_ARG; + return; } } ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); @@ -757,8 +936,12 @@ cpt_enc_hmac_prep(uint32_t flags, aad_buf, aad_offset); } - if (size) - return ERR_BAD_INPUT_ARG; + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer" + " space, size %d needed", + size); + return; + } } /* mac_data */ if (mac_len) { @@ -791,7 +974,7 @@ cpt_enc_hmac_prep(uint32_t flags, CPT_LOG_DP_ERR("Insufficient buffer" " space, size %d needed", size); - return ERR_BAD_INPUT_ARG; + return; } } } @@ -801,11 +984,10 @@ cpt_enc_hmac_prep(uint32_t flags, size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; /* This is DPTR len incase of SG mode */ - vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size); + vq_cmd_w0.s.dlen = size; m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; /* cpt alternate completion address saved earlier */ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); @@ -816,12 +998,6 @@ cpt_enc_hmac_prep(uint32_t flags, req->ist.ei2 = rptr_dma; } - /* First 16-bit swap then 64-bit swap */ - /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions - * to eliminate all the swapping - */ - vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64); - ctx_dma = fc_params->ctx_buf.dma_addr + offsetof(struct cpt_ctx, fctx); /* vq command w3 */ @@ -841,10 +1017,10 @@ cpt_enc_hmac_prep(uint32_t flags, req->op = op; *prep_req = req; - return 0; + return; } -static __rte_always_inline int +static __rte_always_inline void cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, @@ -855,7 +1031,7 @@ cpt_dec_hmac_prep(uint32_t flags, uint32_t iv_offset = 0, size; int32_t inputlen, outputlen, enc_dlen, auth_dlen; struct cpt_ctx *cpt_ctx; - int32_t hash_type, mac_len, m_size; + int32_t hash_type, mac_len; uint8_t iv_len = 16; struct cpt_request_info *req; buf_ptr_t *meta_p, *aad_buf = NULL; @@ -873,7 +1049,6 @@ cpt_dec_hmac_prep(uint32_t flags, meta_p = &fc_params->meta_buf; m_vaddr = meta_p->vaddr; m_dma = meta_p->dma_addr; - m_size = meta_p->size; encr_offset = ENCR_OFFSET(d_offs); auth_offset = AUTH_OFFSET(d_offs); @@ -939,7 +1114,6 @@ cpt_dec_hmac_prep(uint32_t flags, m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; /* start cpt request info structure at 8 byte alignment */ size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) - @@ -950,7 +1124,6 @@ cpt_dec_hmac_prep(uint32_t flags, size += sizeof(struct cpt_request_info); m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; /* Decryption */ opcode.s.major = CPT_MAJOR_OP_FC; @@ -971,8 +1144,8 @@ cpt_dec_hmac_prep(uint32_t flags, encr_offset = inputlen; vq_cmd_w0.u64 = 0; - vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len); - vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len); + vq_cmd_w0.s.param1 = encr_data_len; + vq_cmd_w0.s.param2 = auth_data_len; /* * In 83XX since we have a limitation of @@ -1005,9 +1178,9 @@ cpt_dec_hmac_prep(uint32_t flags, * hmac. */ - vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN); + vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN; - vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + vq_cmd_w0.s.opcode = opcode.flags; if (likely(iv_len)) { uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + @@ -1037,11 +1210,10 @@ cpt_dec_hmac_prep(uint32_t flags, m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; opcode.s.major |= CPT_DMA_MODE; - vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags); + vq_cmd_w0.s.opcode = opcode.flags; if (likely(iv_len)) { uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr + @@ -1096,8 +1268,12 @@ cpt_dec_hmac_prep(uint32_t flags, aad_buf, aad_offset); } - if (size) - return ERR_BAD_INPUT_ARG; + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer" + " space, size %d needed", + size); + return; + } } /* mac data */ @@ -1118,8 +1294,10 @@ cpt_dec_hmac_prep(uint32_t flags, uint32_t aad_offset = aad_len ? passthrough_len : 0; - if (!fc_params->src_iov) - return ERR_BAD_INPUT_ARG; + if (unlikely(!fc_params->src_iov)) { + CPT_LOG_DP_ERR("Bad input args"); + return; + } i = fill_sg_comp_from_iov( gather_comp, i, @@ -1129,8 +1307,12 @@ cpt_dec_hmac_prep(uint32_t flags, aad_offset); } - if (size) - return ERR_BAD_INPUT_ARG; + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer" + " space, size %d needed", + size); + return; + } } } ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); @@ -1163,8 +1345,10 @@ cpt_dec_hmac_prep(uint32_t flags, uint32_t aad_offset = aad_len ? passthrough_len : 0; - if (!fc_params->dst_iov) - return ERR_BAD_INPUT_ARG; + if (unlikely(!fc_params->dst_iov)) { + CPT_LOG_DP_ERR("Bad input args"); + return; + } i = fill_sg_comp_from_iov(scatter_comp, i, fc_params->dst_iov, 0, @@ -1172,8 +1356,11 @@ cpt_dec_hmac_prep(uint32_t flags, aad_offset); } - if (unlikely(size)) - return ERR_BAD_INPUT_ARG; + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } } ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); @@ -1182,11 +1369,10 @@ cpt_dec_hmac_prep(uint32_t flags, size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; /* This is DPTR len incase of SG mode */ - vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size); + vq_cmd_w0.s.dlen = size; m_vaddr = (uint8_t *)m_vaddr + size; m_dma += size; - m_size -= size; /* cpt alternate completion address saved earlier */ req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); @@ -1198,12 +1384,6 @@ cpt_dec_hmac_prep(uint32_t flags, req->ist.ei2 = rptr_dma; } - /* First 16-bit swap then 64-bit swap */ - /* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions - * to eliminate all the swapping - */ - vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64); - ctx_dma = fc_params->ctx_buf.dma_addr + offsetof(struct cpt_ctx, fctx); /* vq command w3 */ @@ -1223,133 +1403,1158 @@ cpt_dec_hmac_prep(uint32_t flags, req->op = op; *prep_req = req; - return 0; + return; } -static __rte_always_inline void * -cpt_fc_dec_hmac_prep(uint32_t flags, - uint64_t d_offs, - uint64_t d_lens, - fc_params_t *fc_params, - void *op, int *ret_val) +static __rte_always_inline void +cpt_zuc_snow3g_enc_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) { - struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; - uint8_t fc_type; - void *prep_req = NULL; - int ret; + uint32_t size; + int32_t inputlen, outputlen; + struct cpt_ctx *cpt_ctx; + uint32_t mac_len = 0; + uint8_t snow3g, j; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset = 0, auth_offset = 0; + uint32_t encr_data_len = 0, auth_data_len = 0; + int flags, iv_len = 16; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma, offset_ctrl; + uint64_t *offset_vaddr, offset_dma; + uint32_t *iv_s, iv[4]; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; - fc_type = ctx->fc_type; + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; - if (likely(fc_type == FC_GEN)) { - ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, - fc_params, op, &prep_req); - } else { + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + mac_len = cpt_ctx->mac_len; + snow3g = cpt_ctx->snow3g; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G; + + /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ + + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) | + (0 << 3) | (flags & 0x7)); + + if (flags == 0x1) { /* - * For AUTH_ONLY case, - * MC only supports digest generation and verification - * should be done in software by memcmp() + * Microcode expects offsets in bytes + * TODO: Rounding off */ + auth_data_len = AUTH_DLEN(d_lens); - ret = ERR_EIO; - } + /* EIA3 or UIA2 */ + auth_offset = AUTH_OFFSET(d_offs); + auth_offset = auth_offset / 8; - if (unlikely(!prep_req)) - *ret_val = ret; - return prep_req; -} + /* consider iv len */ + auth_offset += iv_len; -static __rte_always_inline void *__hot -cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, - fc_params_t *fc_params, void *op, int *ret_val) -{ - struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; - uint8_t fc_type; - void *prep_req = NULL; - int ret; + inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; - fc_type = ctx->fc_type; + offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset); - /* Common api for rest of the ops */ - if (likely(fc_type == FC_GEN)) { - ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, - fc_params, op, &prep_req); } else { - ret = ERR_EIO; - } - - if (unlikely(!prep_req)) - *ret_val = ret; - return prep_req; -} + /* EEA3 or UEA2 */ + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + encr_data_len = ENCR_DLEN(d_lens); -static __rte_always_inline int -cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key, - uint16_t key_len, uint16_t mac_len) -{ - struct cpt_ctx *cpt_ctx = ctx; - mc_fc_context_t *fctx = &cpt_ctx->fctx; - uint64_t *ctrl_flags = NULL; + encr_offset = ENCR_OFFSET(d_offs); + encr_offset = encr_offset / 8; + /* consider iv len */ + encr_offset += iv_len; - if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) { - uint32_t keyx[4]; + inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; - if (key_len != 16) - return -1; - /* No support for AEAD yet */ - if (cpt_ctx->enc_cipher) - return -1; - /* For ZUC/SNOW3G/Kasumi */ - switch (type) { - case SNOW3G_UIA2: - cpt_ctx->snow3g = 1; - gen_key_snow3g(key, keyx); - memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len); - cpt_ctx->fc_type = ZUC_SNOW3G; - cpt_ctx->zsk_flags = 0x1; - break; - case ZUC_EIA3: - cpt_ctx->snow3g = 0; - memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len); - memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32); - cpt_ctx->fc_type = ZUC_SNOW3G; - cpt_ctx->zsk_flags = 0x1; - break; - case KASUMI_F9_ECB: - /* Kasumi ECB mode */ - cpt_ctx->k_ecb = 1; - memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); - cpt_ctx->fc_type = KASUMI; - cpt_ctx->zsk_flags = 0x1; - break; - case KASUMI_F9_CBC: - memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); - cpt_ctx->fc_type = KASUMI; - cpt_ctx->zsk_flags = 0x1; - break; - default: - return -1; - } - cpt_ctx->mac_len = 4; - cpt_ctx->hash_type = type; - return 0; + /* iv offset is 0 */ + offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16); } - if (!(cpt_ctx->fc_type == FC_GEN && !type)) { - if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher) - cpt_ctx->fc_type = HASH_HMAC; - } + /* IV */ + iv_s = (flags == 0x1) ? params->auth_iv_buf : + params->iv_buf; - ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags; - *ctrl_flags = rte_be_to_cpu_64(*ctrl_flags); + if (snow3g) { + /* + * DPDK seems to provide it in form of IV3 IV2 IV1 IV0 + * and BigEndian, MC needs it as IV0 IV1 IV2 IV3 + */ - /* For GMAC auth, cipher must be NULL */ - if (type == GMAC_TYPE) - CPT_P_ENC_CTRL(fctx).enc_cipher = 0; + for (j = 0; j < 4; j++) + iv[j] = iv_s[3 - j]; + } else { + /* ZUC doesn't need a swap */ + for (j = 0; j < 4; j++) + iv[j] = iv_s[j]; + } - CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type; - CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len; + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = encr_data_len; + vq_cmd_w0.s.param2 = auth_data_len; - if (key_len) { + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((req_flags & SINGLE_BUF_INPLACE) && + (req_flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = params->bufs[0].vaddr; + uint64_t dm_dma_addr = params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + OFF_CTRL_LEN - iv_len); + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + + /* DPTR */ + req->ist.ei1 = offset_dma; + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + + outputlen - iv_len); + + vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN; + + vq_cmd_w0.s.opcode = opcode.flags; + + if (likely(iv_len)) { + uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + } + + *offset_vaddr = offset_ctrl; + } else { + uint32_t i, g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t *iv_d; + + /* save space for iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + + opcode.s.major |= CPT_DMA_MODE; + + vq_cmd_w0.s.opcode = opcode.flags; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + i = fill_sg_comp(gather_comp, i, offset_dma, + OFF_CTRL_LEN + iv_len); + + /* iv offset is 0 */ + *offset_vaddr = offset_ctrl; + + iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + + /* input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for EEA3 & UEA2 */ + iv_len = 0; + } + + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, iv_len); + } + + /* Add output data */ + if (req_flags & VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = size; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, zs_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return; +} + +static __rte_always_inline void +cpt_zuc_snow3g_dec_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen; + struct cpt_ctx *cpt_ctx; + uint8_t snow3g, iv_len = 16; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset; + uint32_t encr_data_len; + int flags; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + uint32_t *iv_s, iv[4], j; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + + /* + * Microcode expects offsets in bytes + * TODO: Rounding off + */ + encr_offset = ENCR_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + snow3g = cpt_ctx->snow3g; + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G; + + /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */ + + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) | + (0 << 3) | (flags & 0x7)); + + /* consider iv len */ + encr_offset += iv_len; + + inputlen = encr_offset + + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* IV */ + iv_s = params->iv_buf; + if (snow3g) { + /* + * DPDK seems to provide it in form of IV3 IV2 IV1 IV0 + * and BigEndian, MC needs it as IV0 IV1 IV2 IV3 + */ + + for (j = 0; j < 4; j++) + iv[j] = iv_s[3 - j]; + } else { + /* ZUC doesn't need a swap */ + for (j = 0; j < 4; j++) + iv[j] = iv_s[j]; + } + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = encr_data_len; + + /* + * In 83XX since we have a limitation of + * IV & Offset control word not part of instruction + * and need to be part of Data Buffer, we check if + * head room is there and then only do the Direct mode processing + */ + if (likely((req_flags & SINGLE_BUF_INPLACE) && + (req_flags & SINGLE_BUF_HEADTAILROOM))) { + void *dm_vaddr = params->bufs[0].vaddr; + uint64_t dm_dma_addr = params->bufs[0].dma_addr; + /* + * This flag indicates that there is 24 bytes head room and + * 8 bytes tail room available, so that we get to do + * DIRECT MODE with limitation + */ + + offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - + OFF_CTRL_LEN - iv_len); + offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len; + + /* DPTR */ + req->ist.ei1 = offset_dma; + /* RPTR should just exclude offset control word */ + req->ist.ei2 = dm_dma_addr - iv_len; + req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr + + outputlen - iv_len); + + vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN; + + vq_cmd_w0.s.opcode = opcode.flags; + + if (likely(iv_len)) { + uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr + + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + } + + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + } else { + uint32_t i, g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + uint8_t *in_buffer; + uint32_t *iv_d; + + /* save space for offset and iv... */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + + opcode.s.major |= CPT_DMA_MODE; + + vq_cmd_w0.s.opcode = opcode.flags; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word */ + + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + + i = fill_sg_comp(gather_comp, i, offset_dma, + OFF_CTRL_LEN + iv_len); + + iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN); + memcpy(iv_d, iv, 16); + + /* Add input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = + (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* IV */ + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + iv_len); + + /* Add output data */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = size; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + } + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, zs_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return; +} + +static __rte_always_inline void +cpt_kasumi_enc_prep(uint32_t req_flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen = 0; + struct cpt_ctx *cpt_ctx; + uint32_t mac_len = 0; + uint8_t i = 0; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset, auth_offset; + uint32_t encr_data_len, auth_data_len; + int flags; + uint8_t *iv_s, *iv_d, iv_len = 8; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + auth_offset = AUTH_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + auth_data_len = AUTH_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + mac_len = cpt_ctx->mac_len; + + if (flags == 0x0) + iv_s = params->iv_buf; + else + iv_s = params->auth_iv_buf; + + dir = iv_s[8] & 0x1; + + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = encr_data_len; + vq_cmd_w0.s.param2 = auth_data_len; + vq_cmd_w0.s.opcode = opcode.flags; + + /* consider iv len */ + if (flags == 0x0) { + encr_offset += iv_len; + auth_offset += iv_len; + } + + /* save space for offset ctrl and iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + + if (flags == 0x0) { + inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + } else { + inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8); + outputlen = mac_len; + /* iv offset is 0 */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset); + } + + i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len); + + /* IV */ + iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN; + memcpy(iv_d, iv_s, iv_len); + + /* input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + if (flags == 0x1) { + /* IV in SLIST only for F8 */ + iv_len = 0; + } + + /* IV */ + if (iv_len) { + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + iv_len); + } + + /* Add output data */ + if (req_flags & VALID_MAC_BUF) { + size = outputlen - iv_len - mac_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + + /* mac data */ + if (mac_len) { + i = fill_sg_comp_from_buf(scatter_comp, i, + ¶ms->mac_buf); + } + } else { + /* Output including mac */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = size; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return; +} + +static __rte_always_inline void +cpt_kasumi_dec_prep(uint64_t d_offs, + uint64_t d_lens, + fc_params_t *params, + void *op, + void **prep_req) +{ + uint32_t size; + int32_t inputlen = 0, outputlen; + struct cpt_ctx *cpt_ctx; + uint8_t i = 0, iv_len = 8; + struct cpt_request_info *req; + buf_ptr_t *buf_p; + uint32_t encr_offset; + uint32_t encr_data_len; + int flags; + uint8_t dir = 0; + void *m_vaddr, *c_vaddr; + uint64_t m_dma, c_dma; + uint64_t *offset_vaddr, offset_dma; + vq_cmd_word0_t vq_cmd_w0; + vq_cmd_word3_t vq_cmd_w3; + opcode_info_t opcode; + uint8_t *in_buffer; + uint32_t g_size_bytes, s_size_bytes; + uint64_t dptr_dma, rptr_dma; + sg_comp_t *gather_comp; + sg_comp_t *scatter_comp; + + buf_p = ¶ms->meta_buf; + m_vaddr = buf_p->vaddr; + m_dma = buf_p->dma_addr; + + encr_offset = ENCR_OFFSET(d_offs) / 8; + encr_data_len = ENCR_DLEN(d_lens); + + cpt_ctx = params->ctx_buf.vaddr; + flags = cpt_ctx->zsk_flags; + /* + * Save initial space that followed app data for completion code & + * alternate completion code to fall in same cache line as app data + */ + m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE; + m_dma += COMPLETION_CODE_SIZE; + size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) - + (uint8_t *)m_vaddr; + + c_vaddr = (uint8_t *)m_vaddr + size; + c_dma = m_dma + size; + size += sizeof(cpt_res_s_t); + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* Reserve memory for cpt request info */ + req = m_vaddr; + + size = sizeof(struct cpt_request_info); + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE; + + /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ + opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) | + (dir << 4) | (0 << 3) | (flags & 0x7)); + + /* + * GP op header, lengths are expected in bits. + */ + vq_cmd_w0.u64 = 0; + vq_cmd_w0.s.param1 = encr_data_len; + vq_cmd_w0.s.opcode = opcode.flags; + + /* consider iv len */ + encr_offset += iv_len; + + inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8); + outputlen = inputlen; + + /* save space for offset ctrl & iv */ + offset_vaddr = m_vaddr; + offset_dma = m_dma; + + m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len; + m_dma += OFF_CTRL_LEN + iv_len; + + /* DPTR has SG list */ + in_buffer = m_vaddr; + dptr_dma = m_dma; + + ((uint16_t *)in_buffer)[0] = 0; + ((uint16_t *)in_buffer)[1] = 0; + + /* TODO Add error check if space will be sufficient */ + gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8); + + /* + * Input Gather List + */ + i = 0; + + /* Offset control word followed by iv */ + *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + + i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len); + + /* IV */ + memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN, + params->iv_buf, iv_len); + + /* Add input data */ + size = inputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(gather_comp, i, + params->src_iov, + 0, &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i); + g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + /* + * Output Scatter List + */ + + i = 0; + scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes); + + /* IV */ + i = fill_sg_comp(scatter_comp, i, + offset_dma + OFF_CTRL_LEN, + iv_len); + + /* Add output data */ + size = outputlen - iv_len; + if (size) { + i = fill_sg_comp_from_iov(scatter_comp, i, + params->dst_iov, 0, + &size, NULL, 0); + if (unlikely(size)) { + CPT_LOG_DP_ERR("Insufficient buffer space," + " size %d needed", size); + return; + } + } + ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i); + s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t); + + size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE; + + /* This is DPTR len incase of SG mode */ + vq_cmd_w0.s.dlen = size; + + m_vaddr = (uint8_t *)m_vaddr + size; + m_dma += size; + + /* cpt alternate completion address saved earlier */ + req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8); + *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT); + rptr_dma = c_dma - 8; + + req->ist.ei1 = dptr_dma; + req->ist.ei2 = rptr_dma; + + /* vq command w3 */ + vq_cmd_w3.u64 = 0; + vq_cmd_w3.s.grp = 0; + vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr + + offsetof(struct cpt_ctx, k_ctx); + + /* 16 byte aligned cpt res address */ + req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); + *req->completion_addr = COMPLETION_CODE_INIT; + req->comp_baddr = c_dma; + + /* Fill microcode part of instruction */ + req->ist.ei0 = vq_cmd_w0.u64; + req->ist.ei3 = vq_cmd_w3.u64; + + req->op = op; + + *prep_req = req; + return; +} + +static __rte_always_inline void * +cpt_fc_dec_hmac_prep(uint32_t flags, + uint64_t d_offs, + uint64_t d_lens, + fc_params_t *fc_params, + void *op) +{ + struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; + uint8_t fc_type; + void *prep_req = NULL; + + fc_type = ctx->fc_type; + + if (likely(fc_type == FC_GEN)) { + cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op, + &prep_req); + } else if (fc_type == ZUC_SNOW3G) { + cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op, + &prep_req); + } else if (fc_type == KASUMI) { + cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req); + } + + /* + * For AUTH_ONLY case, + * MC only supports digest generation and verification + * should be done in software by memcmp() + */ + + return prep_req; +} + +static __rte_always_inline void *__hot +cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, + fc_params_t *fc_params, void *op) +{ + struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr; + uint8_t fc_type; + void *prep_req = NULL; + + fc_type = ctx->fc_type; + + /* Common api for rest of the ops */ + if (likely(fc_type == FC_GEN)) { + cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op, + &prep_req); + } else if (fc_type == ZUC_SNOW3G) { + cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op, + &prep_req); + } else if (fc_type == KASUMI) { + cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op, + &prep_req); + } else if (fc_type == HASH_HMAC) { + cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req); + } + + return prep_req; +} + +static __rte_always_inline int +cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key, + uint16_t key_len, uint16_t mac_len) +{ + struct cpt_ctx *cpt_ctx = ctx; + mc_fc_context_t *fctx = &cpt_ctx->fctx; + uint64_t *ctrl_flags = NULL; + + if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) { + uint32_t keyx[4]; + + if (key_len != 16) + return -1; + /* No support for AEAD yet */ + if (cpt_ctx->enc_cipher) + return -1; + /* For ZUC/SNOW3G/Kasumi */ + switch (type) { + case SNOW3G_UIA2: + cpt_ctx->snow3g = 1; + gen_key_snow3g(key, keyx); + memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0x1; + break; + case ZUC_EIA3: + cpt_ctx->snow3g = 0; + memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len); + memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32); + cpt_ctx->fc_type = ZUC_SNOW3G; + cpt_ctx->zsk_flags = 0x1; + break; + case KASUMI_F9_ECB: + /* Kasumi ECB mode */ + cpt_ctx->k_ecb = 1; + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->fc_type = KASUMI; + cpt_ctx->zsk_flags = 0x1; + break; + case KASUMI_F9_CBC: + memcpy(cpt_ctx->k_ctx.ci_key, key, key_len); + cpt_ctx->fc_type = KASUMI; + cpt_ctx->zsk_flags = 0x1; + break; + default: + return -1; + } + cpt_ctx->mac_len = 4; + cpt_ctx->hash_type = type; + return 0; + } + + if (!(cpt_ctx->fc_type == FC_GEN && !type)) { + if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher) + cpt_ctx->fc_type = HASH_HMAC; + } + + ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags; + *ctrl_flags = rte_be_to_cpu_64(*ctrl_flags); + + /* For GMAC auth, cipher must be NULL */ + if (type == GMAC_TYPE) + CPT_P_ENC_CTRL(fctx).enc_cipher = 0; + + CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type; + CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len; + + if (key_len) { cpt_ctx->hmac = 1; memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key)); memcpy(cpt_ctx->auth_key, key, key_len); @@ -1371,9 +2576,9 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform, cipher_type_t enc_type = 0; /* NULL Cipher type */ auth_type_t auth_type = 0; /* NULL Auth type */ uint32_t cipher_key_len = 0; - uint8_t zsk_flag = 0, aes_gcm = 0; + uint8_t aes_gcm = 0; aead_form = &xform->aead; - void *ctx; + void *ctx = SESS_PRIV(sess); if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT && aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) { @@ -1407,13 +2612,12 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform, (unsigned int long)aead_form->key.length); return -1; } - sess->zsk_flag = zsk_flag; + sess->zsk_flag = 0; sess->aes_gcm = aes_gcm; sess->mac_len = aead_form->digest_length; sess->iv_offset = aead_form->iv.offset; sess->iv_length = aead_form->iv.length; sess->aad_length = aead_form->aad_length; - ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data, aead_form->key.length, NULL); @@ -1430,10 +2634,7 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct rte_crypto_cipher_xform *c_form; cipher_type_t enc_type = 0; /* NULL Cipher type */ uint32_t cipher_key_len = 0; - uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0, is_null = 0; - - if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) - return -1; + uint8_t zsk_flag = 0, aes_ctr = 0, is_null = 0; c_form = &xform->cipher; @@ -1515,7 +2716,7 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, } sess->zsk_flag = zsk_flag; - sess->aes_gcm = aes_gcm; + sess->aes_gcm = 0; sess->aes_ctr = aes_ctr; sess->iv_offset = c_form->iv.offset; sess->iv_length = c_form->iv.length; @@ -1535,9 +2736,6 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, auth_type_t auth_type = 0; /* NULL Auth type */ uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0; - if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH) - goto error_out; - a_form = &xform->auth; if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY) @@ -1609,11 +2807,11 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, case RTE_CRYPTO_AUTH_AES_CBC_MAC: CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u", a_form->algo); - goto error_out; + return -1; default: CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified", a_form->algo); - goto error_out; + return -1; } sess->zsk_flag = zsk_flag; @@ -1628,9 +2826,6 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, a_form->key.length, a_form->digest_length); return 0; - -error_out: - return -1; } static __rte_always_inline int @@ -1640,11 +2835,7 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform, struct rte_crypto_auth_xform *a_form; cipher_type_t enc_type = 0; /* NULL Cipher type */ auth_type_t auth_type = 0; /* NULL Auth type */ - uint8_t zsk_flag = 0, aes_gcm = 0; - void *ctx; - - if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH) - return -1; + void *ctx = SESS_PRIV(sess); a_form = &xform->auth; @@ -1668,13 +2859,12 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform, return -1; } - sess->zsk_flag = zsk_flag; - sess->aes_gcm = aes_gcm; + sess->zsk_flag = 0; + sess->aes_gcm = 0; sess->is_gmac = 1; sess->iv_offset = a_form->iv.offset; sess->iv_length = a_form->iv.length; sess->mac_len = a_form->digest_length; - ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)), cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data, a_form->key.length, NULL); @@ -1858,25 +3048,22 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt, return 0; } -static __rte_always_inline void * +static __rte_always_inline int fill_fc_params(struct rte_crypto_op *cop, struct cpt_sess_misc *sess_misc, + struct cpt_qp_meta_info *m_info, void **mdata_ptr, - int *op_ret) + void **prep_req) { uint32_t space = 0; struct rte_crypto_sym_op *sym_op = cop->sym; - void *mdata; + void *mdata = NULL; uintptr_t *op; uint32_t mc_hash_off; uint32_t flags = 0; uint64_t d_offs, d_lens; - void *prep_req = NULL; struct rte_mbuf *m_src, *m_dst; uint8_t cpt_op = sess_misc->cpt_op; - uint8_t zsk_flag = sess_misc->zsk_flag; - uint8_t aes_gcm = sess_misc->aes_gcm; - uint16_t mac_len = sess_misc->mac_len; #ifdef CPT_ALWAYS_USE_SG_MODE uint8_t inplace = 0; #else @@ -1886,8 +3073,7 @@ fill_fc_params(struct rte_crypto_op *cop, char src[SRC_IOV_SIZE]; char dst[SRC_IOV_SIZE]; uint32_t iv_buf[4]; - struct cptvf_meta_info *cpt_m_info = - (struct cptvf_meta_info *)(*mdata_ptr); + int ret; if (likely(sess_misc->iv_length)) { flags |= VALID_IV_BUF; @@ -1903,21 +3089,17 @@ fill_fc_params(struct rte_crypto_op *cop, } } - if (zsk_flag) { + if (sess_misc->zsk_flag) { fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, sess_misc->auth_iv_offset); - if (zsk_flag == K_F9) { - CPT_LOG_DP_ERR("Should not reach here for " - "kasumi F9\n"); - } - if (zsk_flag != ZS_EA) + if (sess_misc->zsk_flag != ZS_EA) inplace = 0; } m_src = sym_op->m_src; m_dst = sym_op->m_dst; - if (aes_gcm) { + if (sess_misc->aes_gcm) { uint8_t *salt; uint8_t *aad_data; uint16_t aad_len; @@ -1951,7 +3133,7 @@ fill_fc_params(struct rte_crypto_op *cop, sess_misc->salt = *(uint32_t *)salt; } fc_params.iv_buf = salt + 4; - if (likely(mac_len)) { + if (likely(sess_misc->mac_len)) { struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src; @@ -1994,7 +3176,7 @@ fill_fc_params(struct rte_crypto_op *cop, } fc_params.iv_buf = salt + 4; } - if (likely(mac_len)) { + if (likely(sess_misc->mac_len)) { struct rte_mbuf *m; m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src; @@ -2033,8 +3215,8 @@ fill_fc_params(struct rte_crypto_op *cop, &fc_params, &flags))) { CPT_LOG_DP_ERR("Prepare inplace src iov failed"); - *op_ret = -1; - return NULL; + ret = -EINVAL; + goto err_exit; } } else { @@ -2045,15 +3227,14 @@ fill_fc_params(struct rte_crypto_op *cop, /* Store SG I/O in the api for reuse */ if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) { CPT_LOG_DP_ERR("Prepare src iov failed"); - *op_ret = -1; - return NULL; + ret = -EINVAL; + goto err_exit; } if (unlikely(m_dst != NULL)) { uint32_t pkt_len; /* Try to make room as much as src has */ - m_dst = sym_op->m_dst; pkt_len = rte_pktmbuf_pkt_len(m_dst); if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) { @@ -2063,14 +3244,16 @@ fill_fc_params(struct rte_crypto_op *cop, "m_dst %p, need %u" " more", m_dst, pkt_len); - return NULL; + ret = -EINVAL; + goto err_exit; } } if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) { CPT_LOG_DP_ERR("Prepare dst iov failed for " "m_dst %p", m_dst); - return NULL; + ret = -EINVAL; + goto err_exit; } } else { fc_params.dst_iov = (void *)src; @@ -2078,19 +3261,16 @@ fill_fc_params(struct rte_crypto_op *cop, } if (likely(flags & SINGLE_BUF_HEADTAILROOM)) - mdata = alloc_op_meta(m_src, - &fc_params.meta_buf, - cpt_m_info->cptvf_op_sb_mlen, - cpt_m_info->cptvf_meta_pool); + mdata = alloc_op_meta(m_src, &fc_params.meta_buf, + m_info->lb_mlen, m_info->pool); else - mdata = alloc_op_meta(NULL, - &fc_params.meta_buf, - cpt_m_info->cptvf_op_mlen, - cpt_m_info->cptvf_meta_pool); + mdata = alloc_op_meta(NULL, &fc_params.meta_buf, + m_info->sg_mlen, m_info->pool); if (unlikely(mdata == NULL)) { CPT_LOG_DP_ERR("Error allocating meta buffer for request"); - return NULL; + ret = -ENOMEM; + goto err_exit; } op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull); @@ -2105,16 +3285,52 @@ fill_fc_params(struct rte_crypto_op *cop, /* Finally prepare the instruction */ if (cpt_op & CPT_OP_ENCODE) - prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, - &fc_params, op, op_ret); + *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, + &fc_params, op); else - prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens, - &fc_params, op, op_ret); + *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens, + &fc_params, op); + + if (unlikely(*prep_req == NULL)) { + CPT_LOG_DP_ERR("Preparing request failed due to bad input arg"); + ret = -EINVAL; + goto free_mdata_and_exit; + } - if (unlikely(!prep_req)) - free_op_meta(mdata, cpt_m_info->cptvf_meta_pool); *mdata_ptr = mdata; - return prep_req; + + return 0; + +free_mdata_and_exit: + free_op_meta(mdata, m_info->pool); +err_exit: + return ret; +} + +static __rte_always_inline void +compl_auth_verify(struct rte_crypto_op *op, + uint8_t *gen_mac, + uint64_t mac_len) +{ + uint8_t *mac; + struct rte_crypto_sym_op *sym_op = op->sym; + + if (sym_op->auth.digest.data) + mac = sym_op->auth.digest.data; + else + mac = rte_pktmbuf_mtod_offset(sym_op->m_src, + uint8_t *, + sym_op->auth.data.length + + sym_op->auth.data.offset); + if (!mac) { + op->status = RTE_CRYPTO_OP_STATUS_ERROR; + return; + } + + if (memcmp(mac, gen_mac, mac_len)) + op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED; + else + op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; } static __rte_always_inline int @@ -2160,4 +3376,205 @@ err: return -1; } +static __rte_always_inline void +find_kasumif9_direction_and_length(uint8_t *src, + uint32_t counter_num_bytes, + uint32_t *addr_length_in_bits, + uint8_t *addr_direction) +{ + uint8_t found = 0; + uint32_t pos; + uint8_t last_byte; + while (!found && counter_num_bytes > 0) { + counter_num_bytes--; + if (src[counter_num_bytes] == 0x00) + continue; + pos = rte_bsf32(src[counter_num_bytes]); + if (pos == 7) { + if (likely(counter_num_bytes > 0)) { + last_byte = src[counter_num_bytes - 1]; + *addr_direction = last_byte & 0x1; + *addr_length_in_bits = counter_num_bytes * 8 + - 1; + } + } else { + last_byte = src[counter_num_bytes]; + *addr_direction = (last_byte >> (pos + 1)) & 0x1; + *addr_length_in_bits = counter_num_bytes * 8 + + (8 - (pos + 2)); + } + found = 1; + } +} + +/* + * This handles all auth only except AES_GMAC + */ +static __rte_always_inline int +fill_digest_params(struct rte_crypto_op *cop, + struct cpt_sess_misc *sess, + struct cpt_qp_meta_info *m_info, + void **mdata_ptr, + void **prep_req) +{ + uint32_t space = 0; + struct rte_crypto_sym_op *sym_op = cop->sym; + void *mdata; + phys_addr_t mphys; + uint64_t *op; + uint32_t auth_range_off; + uint32_t flags = 0; + uint64_t d_offs = 0, d_lens; + struct rte_mbuf *m_src, *m_dst; + uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK; + uint16_t mac_len = sess->mac_len; + fc_params_t params; + char src[SRC_IOV_SIZE]; + uint8_t iv_buf[16]; + int ret; + + memset(¶ms, 0, sizeof(fc_params_t)); + + m_src = sym_op->m_src; + + /* For just digest lets force mempool alloc */ + mdata = alloc_op_meta(NULL, ¶ms.meta_buf, m_info->sg_mlen, + m_info->pool); + if (mdata == NULL) { + ret = -ENOMEM; + goto err_exit; + } + + mphys = params.meta_buf.dma_addr; + + op = mdata; + op[0] = (uintptr_t)mdata; + op[1] = (uintptr_t)cop; + op[2] = op[3] = 0; /* Used to indicate auth verify */ + space += 4 * sizeof(uint64_t); + + auth_range_off = sym_op->auth.data.offset; + + flags = VALID_MAC_BUF; + params.src_iov = (void *)src; + if (unlikely(sess->zsk_flag)) { + /* + * Since for Zuc, Kasumi, Snow3g offsets are in bits + * we will send pass through even for auth only case, + * let MC handle it + */ + d_offs = auth_range_off; + auth_range_off = 0; + params.auth_iv_buf = rte_crypto_op_ctod_offset(cop, + uint8_t *, sess->auth_iv_offset); + if (sess->zsk_flag == K_F9) { + uint32_t length_in_bits, num_bytes; + uint8_t *src, direction = 0; + + memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src, + uint8_t *), 8); + /* + * This is kasumi f9, take direction from + * source buffer + */ + length_in_bits = cop->sym->auth.data.length; + num_bytes = (length_in_bits >> 3); + src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *); + find_kasumif9_direction_and_length(src, + num_bytes, + &length_in_bits, + &direction); + length_in_bits -= 64; + cop->sym->auth.data.offset += 64; + d_offs = cop->sym->auth.data.offset; + auth_range_off = d_offs / 8; + cop->sym->auth.data.length = length_in_bits; + + /* Store it at end of auth iv */ + iv_buf[8] = direction; + params.auth_iv_buf = iv_buf; + } + } + + d_lens = sym_op->auth.data.length; + + params.ctx_buf.vaddr = SESS_PRIV(sess); + params.ctx_buf.dma_addr = sess->ctx_dma_addr; + + if (auth_op == CPT_OP_AUTH_GENERATE) { + if (sym_op->auth.digest.data) { + /* + * Digest to be generated + * in separate buffer + */ + params.mac_buf.size = + sess->mac_len; + params.mac_buf.vaddr = + sym_op->auth.digest.data; + params.mac_buf.dma_addr = + sym_op->auth.digest.phys_addr; + } else { + uint32_t off = sym_op->auth.data.offset + + sym_op->auth.data.length; + int32_t dlen, space; + + m_dst = sym_op->m_dst ? + sym_op->m_dst : sym_op->m_src; + dlen = rte_pktmbuf_pkt_len(m_dst); + + space = off + mac_len - dlen; + if (space > 0) + if (!rte_pktmbuf_append(m_dst, space)) { + CPT_LOG_DP_ERR("Failed to extend " + "mbuf by %uB", space); + ret = -EINVAL; + goto free_mdata_and_exit; + } + + params.mac_buf.vaddr = + rte_pktmbuf_mtod_offset(m_dst, void *, off); + params.mac_buf.dma_addr = + rte_pktmbuf_mtophys_offset(m_dst, off); + params.mac_buf.size = mac_len; + } + } else { + /* Need space for storing generated mac */ + params.mac_buf.vaddr = (uint8_t *)mdata + space; + params.mac_buf.dma_addr = mphys + space; + params.mac_buf.size = mac_len; + space += RTE_ALIGN_CEIL(mac_len, 8); + op[2] = (uintptr_t)params.mac_buf.vaddr; + op[3] = mac_len; + } + + params.meta_buf.vaddr = (uint8_t *)mdata + space; + params.meta_buf.dma_addr = mphys + space; + params.meta_buf.size -= space; + + /* Out of place processing */ + params.src_iov = (void *)src; + + /*Store SG I/O in the api for reuse */ + if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) { + CPT_LOG_DP_ERR("Prepare src iov failed"); + ret = -EINVAL; + goto free_mdata_and_exit; + } + + *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, ¶ms, op); + if (unlikely(*prep_req == NULL)) { + ret = -EINVAL; + goto free_mdata_and_exit; + } + + *mdata_ptr = mdata; + + return 0; + +free_mdata_and_exit: + free_op_meta(mdata, m_info->pool); +err_exit: + return ret; +} + #endif /*_CPT_UCODE_H_ */