X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_common.c;h=91de7b3e2cd4928da4b6233224823de45266aaae;hb=7af08c8f1a86a5f352a8f635d7ba75bb8713f683;hp=1c77763da9db16d4e21ecc3cbb8cca261503a1e4;hpb=4c204fe5e5d2bf0001ab0d017df9f0f578b0434c;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index 1c77763da9..91de7b3e2c 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -5,375 +5,450 @@ #include #include #include -#ifdef RTE_IBVERBS_LINK_DLOPEN -#include -#endif #include +#include +#include +#include #include "mlx5_common.h" -#include "mlx5_common_utils.h" -#include "mlx5_glue.h" - - -int mlx5_common_logtype; - -#ifdef MLX5_GLUE -const struct mlx5_glue *mlx5_glue; -#endif +#include "mlx5_common_os.h" +#include "mlx5_common_log.h" +#include "mlx5_common_private.h" uint8_t haswell_broadwell_cpu; +/* In case this is an x86_64 intel processor to check if + * we should use relaxed ordering. + */ +#ifdef RTE_ARCH_X86_64 /** - * Get PCI information by sysfs device path. - * - * @param dev_path - * Pointer to device sysfs folder name. - * @param[out] pci_addr - * PCI bus address output buffer. + * This function returns processor identification and feature information + * into the registers. * - * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. + * @param eax, ebx, ecx, edx + * Pointers to the registers that will hold cpu information. + * @param level + * The main category of information returned. */ -int -mlx5_dev_to_pci_addr(const char *dev_path, - struct rte_pci_addr *pci_addr) +static inline void mlx5_cpu_id(unsigned int level, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + __asm__("cpuid\n\t" + : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) + : "0" (level)); +} +#endif + +RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE) + +/* Head of list of drivers. */ +static TAILQ_HEAD(mlx5_drivers, mlx5_class_driver) drivers_list = + TAILQ_HEAD_INITIALIZER(drivers_list); + +/* Head of devices. */ +static TAILQ_HEAD(mlx5_devices, mlx5_common_device) devices_list = + TAILQ_HEAD_INITIALIZER(devices_list); +static pthread_mutex_t devices_list_lock; + +static const struct { + const char *name; + unsigned int drv_class; +} mlx5_classes[] = { + { .name = "vdpa", .drv_class = MLX5_CLASS_VDPA }, + { .name = "eth", .drv_class = MLX5_CLASS_ETH }, + /* Keep class "net" for backward compatibility. */ + { .name = "net", .drv_class = MLX5_CLASS_ETH }, + { .name = "regex", .drv_class = MLX5_CLASS_REGEX }, + { .name = "compress", .drv_class = MLX5_CLASS_COMPRESS }, + { .name = "crypto", .drv_class = MLX5_CLASS_CRYPTO }, +}; + +static int +class_name_to_value(const char *class_name) { - FILE *file; - char line[32]; - MKSTR(path, "%s/device/uevent", dev_path); - - file = fopen(path, "rb"); - if (file == NULL) { - rte_errno = errno; - return -rte_errno; + unsigned int i; + + for (i = 0; i < RTE_DIM(mlx5_classes); i++) { + if (strcmp(class_name, mlx5_classes[i].name) == 0) + return mlx5_classes[i].drv_class; } - while (fgets(line, sizeof(line), file) == line) { - size_t len = strlen(line); - int ret; - - /* Truncate long lines. */ - if (len == (sizeof(line) - 1)) - while (line[(len - 1)] != '\n') { - ret = fgetc(file); - if (ret == EOF) - break; - line[(len - 1)] = ret; - } - /* Extract information. */ - if (sscanf(line, - "PCI_SLOT_NAME=" - "%" SCNx32 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n", - &pci_addr->domain, - &pci_addr->bus, - &pci_addr->devid, - &pci_addr->function) == 4) { - ret = 0; - break; - } + return -EINVAL; +} + +static struct mlx5_class_driver * +driver_get(uint32_t class) +{ + struct mlx5_class_driver *driver; + + TAILQ_FOREACH(driver, &drivers_list, next) { + if ((uint32_t)driver->drv_class == class) + return driver; } - fclose(file); - return 0; + return NULL; } static int -mlx5_class_check_handler(__rte_unused const char *key, const char *value, - void *opaque) +devargs_class_handler(__rte_unused const char *key, + const char *class_names, void *opaque) { - enum mlx5_class *ret = opaque; - - if (strcmp(value, "vdpa") == 0) { - *ret = MLX5_CLASS_VDPA; - } else if (strcmp(value, "net") == 0) { - *ret = MLX5_CLASS_NET; - } else { - DRV_LOG(ERR, "Invalid mlx5 class %s. Maybe typo in device" - " class argument setting?", value); - *ret = MLX5_CLASS_INVALID; + int *ret = opaque; + int class_val; + char *scratch; + char *found; + char *refstr = NULL; + + *ret = 0; + scratch = strdup(class_names); + if (scratch == NULL) { + *ret = -ENOMEM; + return *ret; } - return 0; + found = strtok_r(scratch, ":", &refstr); + if (found == NULL) + /* Empty string. */ + goto err; + do { + /* Extract each individual class name. Multiple + * classes can be supplied as class=net:regex:foo:bar. + */ + class_val = class_name_to_value(found); + /* Check if its a valid class. */ + if (class_val < 0) { + *ret = -EINVAL; + goto err; + } + *ret |= class_val; + found = strtok_r(NULL, ":", &refstr); + } while (found != NULL); +err: + free(scratch); + if (*ret < 0) + DRV_LOG(ERR, "Invalid mlx5 class options: %s.\n", class_names); + return *ret; } -enum mlx5_class -mlx5_class_get(struct rte_devargs *devargs) +static int +parse_class_options(const struct rte_devargs *devargs) { struct rte_kvargs *kvlist; - const char *key = MLX5_CLASS_ARG_NAME; - enum mlx5_class ret = MLX5_CLASS_NET; + int ret = 0; if (devargs == NULL) - return ret; + return 0; + if (devargs->cls != NULL && devargs->cls->name != NULL) + /* Global syntax, only one class type. */ + return class_name_to_value(devargs->cls->name); + /* Legacy devargs support multiple classes. */ kvlist = rte_kvargs_parse(devargs->args, NULL); if (kvlist == NULL) - return ret; - if (rte_kvargs_count(kvlist, key)) - rte_kvargs_process(kvlist, key, mlx5_class_check_handler, &ret); + return 0; + rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_CLASS, + devargs_class_handler, &ret); rte_kvargs_free(kvlist); return ret; } -/** - * Extract port name, as a number, from sysfs or netlink information. - * - * @param[in] port_name_in - * String representing the port name. - * @param[out] port_info_out - * Port information, including port name as a number and port name - * type if recognized - * - * @return - * port_name field set according to recognized name format. - */ -void -mlx5_translate_port_name(const char *port_name_in, - struct mlx5_switch_info *port_info_out) +static const unsigned int mlx5_class_invalid_combinations[] = { + MLX5_CLASS_ETH | MLX5_CLASS_VDPA, + /* New class combination should be added here. */ +}; + +static int +is_valid_class_combination(uint32_t user_classes) { - char pf_c1, pf_c2, vf_c1, vf_c2; - char *end; - int sc_items; + unsigned int i; - /* - * Check for port-name as a string of the form pf0vf0 - * (support kernel ver >= 5.0 or OFED ver >= 4.6). - */ - sc_items = sscanf(port_name_in, "%c%c%d%c%c%d", - &pf_c1, &pf_c2, &port_info_out->pf_num, - &vf_c1, &vf_c2, &port_info_out->port_name); - if (sc_items == 6 && - pf_c1 == 'p' && pf_c2 == 'f' && - vf_c1 == 'v' && vf_c2 == 'f') { - port_info_out->name_type = MLX5_PHYS_PORT_NAME_TYPE_PFVF; - return; - } - /* - * Check for port-name as a string of the form p0 - * (support kernel ver >= 5.0, or OFED ver >= 4.6). - */ - sc_items = sscanf(port_name_in, "%c%d", - &pf_c1, &port_info_out->port_name); - if (sc_items == 2 && pf_c1 == 'p') { - port_info_out->name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK; - return; + /* Verify if user specified unsupported combination. */ + for (i = 0; i < RTE_DIM(mlx5_class_invalid_combinations); i++) { + if ((mlx5_class_invalid_combinations[i] & user_classes) == + mlx5_class_invalid_combinations[i]) + return -EINVAL; } - /* Check for port-name as a number (support kernel ver < 5.0 */ - errno = 0; - port_info_out->port_name = strtol(port_name_in, &end, 0); - if (!errno && - (size_t)(end - port_name_in) == strlen(port_name_in)) { - port_info_out->name_type = MLX5_PHYS_PORT_NAME_TYPE_LEGACY; - return; - } - port_info_out->name_type = MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN; - return; + /* Not found any invalid class combination. */ + return 0; } -#ifdef MLX5_GLUE +static bool +device_class_enabled(const struct mlx5_common_device *device, uint32_t class) +{ + return (device->classes_loaded & class) > 0; +} -/** - * Suffix RTE_EAL_PMD_PATH with "-glue". - * - * This function performs a sanity check on RTE_EAL_PMD_PATH before - * suffixing its last component. - * - * @param buf[out] - * Output buffer, should be large enough otherwise NULL is returned. - * @param size - * Size of @p out. - * - * @return - * Pointer to @p buf or @p NULL in case suffix cannot be appended. - */ -static char * -mlx5_glue_path(char *buf, size_t size) +static bool +mlx5_bus_match(const struct mlx5_class_driver *drv, + const struct rte_device *dev) { - static const char *const bad[] = { "/", ".", "..", NULL }; - const char *path = RTE_EAL_PMD_PATH; - size_t len = strlen(path); - size_t off; - int i; - - while (len && path[len - 1] == '/') - --len; - for (off = len; off && path[off - 1] != '/'; --off) - ; - for (i = 0; bad[i]; ++i) - if (!strncmp(path + off, bad[i], (int)(len - off))) - goto error; - i = snprintf(buf, size, "%.*s-glue", (int)len, path); - if (i == -1 || (size_t)i >= size) - goto error; - return buf; -error: - RTE_LOG(ERR, PMD, "unable to append \"-glue\" to last component of" - " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"), please" - " re-configure DPDK"); + if (mlx5_dev_is_pci(dev)) + return mlx5_dev_pci_match(drv, dev); + return true; +} + +static struct mlx5_common_device * +to_mlx5_device(const struct rte_device *rte_dev) +{ + struct mlx5_common_device *dev; + + TAILQ_FOREACH(dev, &devices_list, next) { + if (rte_dev == dev->dev) + return dev; + } return NULL; } -static int -mlx5_glue_dlopen(void) +int +mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size) { - char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; - void *handle = NULL; + struct rte_pci_addr pci_addr = { 0 }; + int ret; + + if (mlx5_dev_is_pci(dev)) { + /* Input might be , format PCI address to . */ + ret = rte_pci_addr_parse(dev->name, &pci_addr); + if (ret != 0) + return -ENODEV; + rte_pci_device_name(&pci_addr, addr, size); + return 0; + } +#ifdef RTE_EXEC_ENV_LINUX + return mlx5_auxiliary_get_pci_str(RTE_DEV_TO_AUXILIARY_CONST(dev), + addr, size); +#else + rte_errno = ENODEV; + return -rte_errno; +#endif +} - const char *path[] = { - /* - * A basic security check is necessary before trusting - * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. - */ - (geteuid() == getuid() && getegid() == getgid() ? - getenv("MLX5_GLUE_PATH") : NULL), - /* - * When RTE_EAL_PMD_PATH is set, use its glue-suffixed - * variant, otherwise let dlopen() look up libraries on its - * own. - */ - (*RTE_EAL_PMD_PATH ? - mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), - }; +static void +dev_release(struct mlx5_common_device *dev) +{ + pthread_mutex_lock(&devices_list_lock); + TAILQ_REMOVE(&devices_list, dev, next); + pthread_mutex_unlock(&devices_list_lock); + rte_free(dev); +} + +static int +drivers_remove(struct mlx5_common_device *dev, uint32_t enabled_classes) +{ + struct mlx5_class_driver *driver; + int local_ret = -ENODEV; unsigned int i = 0; - void **sym; - const char *dlmsg; + int ret = 0; + + enabled_classes &= dev->classes_loaded; + while (enabled_classes) { + driver = driver_get(RTE_BIT64(i)); + if (driver != NULL) { + local_ret = driver->remove(dev); + if (local_ret == 0) + dev->classes_loaded &= ~RTE_BIT64(i); + else if (ret == 0) + ret = local_ret; + } + enabled_classes &= ~RTE_BIT64(i); + i++; + } + if (local_ret != 0 && ret == 0) + ret = local_ret; + return ret; +} - while (!handle && i != RTE_DIM(path)) { - const char *end; - size_t len; - int ret; +static int +drivers_probe(struct mlx5_common_device *dev, uint32_t user_classes) +{ + struct mlx5_class_driver *driver; + uint32_t enabled_classes = 0; + bool already_loaded; + int ret; - if (!path[i]) { - ++i; + TAILQ_FOREACH(driver, &drivers_list, next) { + if ((driver->drv_class & user_classes) == 0) + continue; + if (!mlx5_bus_match(driver, dev->dev)) continue; + already_loaded = dev->classes_loaded & driver->drv_class; + if (already_loaded && driver->probe_again == 0) { + DRV_LOG(ERR, "Device %s is already probed", + dev->dev->name); + ret = -EEXIST; + goto probe_err; } - end = strpbrk(path[i], ":;"); - if (!end) - end = path[i] + strlen(path[i]); - len = end - path[i]; - ret = 0; - do { - char name[ret + 1]; - - ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, - (int)len, path[i], - (!len || *(end - 1) == '/') ? "" : "/"); - if (ret == -1) - break; - if (sizeof(name) != (size_t)ret + 1) - continue; - DRV_LOG(DEBUG, "Looking for rdma-core glue as " - "\"%s\"", name); - handle = dlopen(name, RTLD_LAZY); - break; - } while (1); - path[i] = end + 1; - if (!*end) - ++i; + ret = driver->probe(dev); + if (ret < 0) { + DRV_LOG(ERR, "Failed to load driver %s", + driver->name); + goto probe_err; + } + enabled_classes |= driver->drv_class; + } + dev->classes_loaded |= enabled_classes; + return 0; +probe_err: + /* Only unload drivers which are enabled which were enabled + * in this probe instance. + */ + drivers_remove(dev, enabled_classes); + return ret; +} + +int +mlx5_common_dev_probe(struct rte_device *eal_dev) +{ + struct mlx5_common_device *dev; + uint32_t classes = 0; + bool new_device = false; + int ret; + + DRV_LOG(INFO, "probe device \"%s\".", eal_dev->name); + ret = parse_class_options(eal_dev->devargs); + if (ret < 0) { + DRV_LOG(ERR, "Unsupported mlx5 class type: %s", + eal_dev->devargs->args); + return ret; } - if (!handle) { - rte_errno = EINVAL; - dlmsg = dlerror(); - if (dlmsg) - DRV_LOG(WARNING, "Cannot load glue library: %s", dlmsg); - goto glue_error; + classes = ret; + if (classes == 0) + /* Default to net class. */ + classes = MLX5_CLASS_ETH; + dev = to_mlx5_device(eal_dev); + if (!dev) { + dev = rte_zmalloc("mlx5_common_device", sizeof(*dev), 0); + if (!dev) + return -ENOMEM; + dev->dev = eal_dev; + pthread_mutex_lock(&devices_list_lock); + TAILQ_INSERT_HEAD(&devices_list, dev, next); + pthread_mutex_unlock(&devices_list_lock); + new_device = true; } - sym = dlsym(handle, "mlx5_glue"); - if (!sym || !*sym) { - rte_errno = EINVAL; - dlmsg = dlerror(); - if (dlmsg) - DRV_LOG(ERR, "Cannot resolve glue symbol: %s", dlmsg); - goto glue_error; + /* + * Validate combination here. + * For new device, the classes_loaded field is 0 and it check only + * the classes given as user device arguments. + */ + ret = is_valid_class_combination(classes | dev->classes_loaded); + if (ret != 0) { + DRV_LOG(ERR, "Unsupported mlx5 classes combination."); + goto class_err; } - mlx5_glue = *sym; + ret = drivers_probe(dev, classes); + if (ret) + goto class_err; return 0; - -glue_error: - if (handle) - dlclose(handle); - return -1; +class_err: + if (new_device) + dev_release(dev); + return ret; } -#endif +int +mlx5_common_dev_remove(struct rte_device *eal_dev) +{ + struct mlx5_common_device *dev; + int ret; + + dev = to_mlx5_device(eal_dev); + if (!dev) + return -ENODEV; + /* Matching device found, cleanup and unload drivers. */ + ret = drivers_remove(dev, dev->classes_loaded); + if (ret == 0) + dev_release(dev); + return ret; +} -/* In case this is an x86_64 intel processor to check if - * we should use relaxed ordering. - */ -#ifdef RTE_ARCH_X86_64 -/** - * This function returns processor identification and feature information - * into the registers. - * - * @param eax, ebx, ecx, edx - * Pointers to the registers that will hold cpu information. - * @param level - * The main category of information returned. - */ -static inline void mlx5_cpu_id(unsigned int level, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) +int +mlx5_common_dev_dma_map(struct rte_device *dev, void *addr, uint64_t iova, + size_t len) { - __asm__("cpuid\n\t" - : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) - : "0" (level)); + struct mlx5_class_driver *driver = NULL; + struct mlx5_class_driver *temp; + struct mlx5_common_device *mdev; + int ret = -EINVAL; + + mdev = to_mlx5_device(dev); + if (!mdev) + return -ENODEV; + TAILQ_FOREACH(driver, &drivers_list, next) { + if (!device_class_enabled(mdev, driver->drv_class) || + driver->dma_map == NULL) + continue; + ret = driver->dma_map(dev, addr, iova, len); + if (ret) + goto map_err; + } + return ret; +map_err: + TAILQ_FOREACH(temp, &drivers_list, next) { + if (temp == driver) + break; + if (device_class_enabled(mdev, temp->drv_class) && + temp->dma_map && temp->dma_unmap) + temp->dma_unmap(dev, addr, iova, len); + } + return ret; } -#endif -RTE_INIT_PRIO(mlx5_log_init, LOG) +int +mlx5_common_dev_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova, + size_t len) { - mlx5_common_logtype = rte_log_register("pmd.common.mlx5"); - if (mlx5_common_logtype >= 0) - rte_log_set_level(mlx5_common_logtype, RTE_LOG_NOTICE); + struct mlx5_class_driver *driver; + struct mlx5_common_device *mdev; + int local_ret = -EINVAL; + int ret = 0; + + mdev = to_mlx5_device(dev); + if (!mdev) + return -ENODEV; + /* There is no unmap error recovery in current implementation. */ + TAILQ_FOREACH_REVERSE(driver, &drivers_list, mlx5_drivers, next) { + if (!device_class_enabled(mdev, driver->drv_class) || + driver->dma_unmap == NULL) + continue; + local_ret = driver->dma_unmap(dev, addr, iova, len); + if (local_ret && (ret == 0)) + ret = local_ret; + } + if (local_ret) + ret = local_ret; + return ret; } -/** - * Initialization routine for run-time dependency on rdma-core. - */ -RTE_INIT_PRIO(mlx5_glue_init, CLASS) +void +mlx5_class_driver_register(struct mlx5_class_driver *driver) { - /* - * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use - * huge pages. Calling ibv_fork_init() during init allows - * applications to use fork() safely for purposes other than - * using this PMD, which is not supported in forked processes. - */ - setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); - /* Match the size of Rx completion entry to the size of a cacheline. */ - if (RTE_CACHE_LINE_SIZE == 128) - setenv("MLX5_CQE_SIZE", "128", 0); - /* - * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to - * cleanup all the Verbs resources even when the device was removed. - */ - setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); + mlx5_common_driver_on_register_pci(driver); + TAILQ_INSERT_TAIL(&drivers_list, driver, next); +} -#ifdef MLX5_GLUE - if (mlx5_glue_dlopen() != 0) - goto glue_error; +static void mlx5_common_driver_init(void) +{ + mlx5_common_pci_init(); +#ifdef RTE_EXEC_ENV_LINUX + mlx5_common_auxiliary_init(); #endif +} -#ifdef RTE_LIBRTE_MLX5_DEBUG - /* Glue structure must not contain any NULL pointers. */ - { - unsigned int i; +static bool mlx5_common_initialized; - for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) - MLX5_ASSERT(((const void *const *)mlx5_glue)[i]); - } -#endif - if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { - rte_errno = EINVAL; - DRV_LOG(ERR, "rdma-core glue \"%s\" mismatch: \"%s\" is " - "required", mlx5_glue->version, MLX5_GLUE_VERSION); - goto glue_error; - } - mlx5_glue->fork_init(); - return; - -glue_error: - DRV_LOG(WARNING, "Cannot initialize MLX5 common due to missing" - " run-time dependency on rdma-core libraries (libibverbs," - " libmlx5)"); - mlx5_glue = NULL; - return; +/** + * One time innitialization routine for run-time dependency on glue library + * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module, + * must invoke in its constructor. + */ +void +mlx5_common_init(void) +{ + if (mlx5_common_initialized) + return; + + pthread_mutex_init(&devices_list_lock, NULL); + mlx5_glue_constructor(); + mlx5_common_driver_init(); + mlx5_common_initialized = true; } /** @@ -432,3 +507,104 @@ RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) #endif haswell_broadwell_cpu = 0; } + +/** + * Allocate the User Access Region with DevX on specified device. + * + * @param [in] ctx + * Infiniband device context to perform allocation on. + * @param [in] mapping + * MLX5DV_UAR_ALLOC_TYPE_BF - allocate as cached memory with write-combining + * attributes (if supported by the host), the + * writes to the UAR registers must be followed + * by write memory barrier. + * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are + * promoted to the registers immediately, no + * memory barriers needed. + * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF, + * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC + * is performed. The drivers specifying negative values should + * always provide the write memory barrier operation after UAR + * register writings. + * If there is no definitions for the MLX5DV_UAR_ALLOC_TYPE_xx (older rdma + * library headers), the caller can specify 0. + * + * @return + * UAR object pointer on success, NULL otherwise and rte_errno is set. + */ +void * +mlx5_devx_alloc_uar(void *ctx, int mapping) +{ + void *uar; + uint32_t retry, uar_mapping; + void *base_addr; + + for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) { +#ifdef MLX5DV_UAR_ALLOC_TYPE_NC + /* Control the mapping type according to the settings. */ + uar_mapping = (mapping < 0) ? + MLX5DV_UAR_ALLOC_TYPE_NC : mapping; +#else + /* + * It seems we have no way to control the memory mapping type + * for the UAR, the default "Write-Combining" type is supposed. + */ + uar_mapping = 0; + RTE_SET_USED(mapping); +#endif + uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping); +#ifdef MLX5DV_UAR_ALLOC_TYPE_NC + if (!uar && + mapping < 0 && + uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) { + /* + * In some environments like virtual machine the + * Write Combining mapped might be not supported and + * UAR allocation fails. We tried "Non-Cached" mapping + * for the case. + */ + DRV_LOG(WARNING, "Failed to allocate DevX UAR (BF)"); + uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; + uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping); + } else if (!uar && + mapping < 0 && + uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) { + /* + * If Verbs/kernel does not support "Non-Cached" + * try the "Write-Combining". + */ + DRV_LOG(WARNING, "Failed to allocate DevX UAR (NC)"); + uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF; + uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping); + } +#endif + if (!uar) { + DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)"); + rte_errno = ENOMEM; + goto exit; + } + base_addr = mlx5_os_get_devx_uar_base_addr(uar); + if (base_addr) + break; + /* + * The UARs are allocated by rdma_core within the + * IB device context, on context closure all UARs + * will be freed, should be no memory/object leakage. + */ + DRV_LOG(WARNING, "Retrying to allocate DevX UAR"); + uar = NULL; + } + /* Check whether we finally succeeded with valid UAR allocation. */ + if (!uar) { + DRV_LOG(ERR, "Failed to allocate DevX UAR (NULL base)"); + rte_errno = ENOMEM; + } + /* + * Return void * instead of struct mlx5dv_devx_uar * + * is for compatibility with older rdma-core library headers. + */ +exit: + return uar; +} + +RTE_PMD_EXPORT_NAME(mlx5_common_driver, __COUNTER__);