X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_common.h;h=16de1b3973d67f9356179b78d286f6d1d86449f0;hb=770fabcd36ec11d64544e86ed7d2dda9f5c64daf;hp=9d464d43f4a48cf01e53005d62cafbf67fc6eedb;hpb=8fc742175945d05ee75a537b10c28a707364c9d3;p=dpdk.git

diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index 9d464d43f4..16de1b3973 100644
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -5,16 +5,44 @@
 #ifndef RTE_PMD_MLX5_COMMON_H_
 #define RTE_PMD_MLX5_COMMON_H_
 
-#include <assert.h>
 #include <stdio.h>
 
 #include <rte_pci.h>
+#include <rte_debug.h>
 #include <rte_atomic.h>
 #include <rte_log.h>
+#include <rte_kvargs.h>
+#include <rte_devargs.h>
 
 #include "mlx5_prm.h"
 
 
+/*
+ * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11.
+ * Otherwise there would be a type conflict between stdbool and altivec.
+ */
+#if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__)
+#undef bool
+/* redefine as in stdbool.h */
+#define bool _Bool
+#endif
+
+/* Bit-field manipulation. */
+#define BITFIELD_DECLARE(bf, type, size) \
+	type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
+		!!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
+#define BITFIELD_DEFINE(bf, type, size) \
+	BITFIELD_DECLARE((bf), type, (size)) = { 0 }
+#define BITFIELD_SET(bf, b) \
+	(void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
+		((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
+#define BITFIELD_RESET(bf, b) \
+	(void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
+		~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
+#define BITFIELD_ISSET(bf, b) \
+	!!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
+		((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
+
 /*
  * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
  * manner.
@@ -44,10 +72,10 @@ pmd_drv_log_basename(const char *s)
 		RTE_FMT_TAIL(__VA_ARGS__,)))
 
 /*
- * When debugging is enabled (NDEBUG not defined), file, line and function
+ * When debugging is enabled (MLX5_DEBUG not defined), file, line and function
  * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
  */
-#ifndef NDEBUG
+#ifdef RTE_LIBRTE_MLX5_DEBUG
 
 #define PMD_DRV_LOG__(level, type, name, ...) \
 	PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
@@ -59,28 +87,30 @@ pmd_drv_log_basename(const char *s)
 		__func__, \
 		__VA_ARGS__)
 
-#else /* NDEBUG */
+#else /* RTE_LIBRTE_MLX5_DEBUG */
 #define PMD_DRV_LOG__(level, type, name, ...) \
 	PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
 #define PMD_DRV_LOG_(level, type, name, s, ...) \
 	PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
 
-#endif /* NDEBUG */
+#endif /* RTE_LIBRTE_MLX5_DEBUG */
 
 /* claim_zero() does not perform any check when debugging is disabled. */
-#ifndef NDEBUG
+#ifdef RTE_LIBRTE_MLX5_DEBUG
 
 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
-#define claim_zero(...) assert((__VA_ARGS__) == 0)
-#define claim_nonzero(...) assert((__VA_ARGS__) != 0)
+#define MLX5_ASSERT(exp) RTE_VERIFY(exp)
+#define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
+#define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
 
-#else /* NDEBUG */
+#else /* RTE_LIBRTE_MLX5_DEBUG */
 
 #define DEBUG(...) (void)0
+#define MLX5_ASSERT(exp) RTE_ASSERT(exp)
 #define claim_zero(...) (__VA_ARGS__)
 #define claim_nonzero(...) (__VA_ARGS__)
 
-#endif /* NDEBUG */
+#endif /* RTE_LIBRTE_MLX5_DEBUG */
 
 /* Allocate a buffer on the stack and fill it with a printf format string. */
 #define MKSTR(name, ...) \
@@ -108,6 +138,34 @@ enum {
 	PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
 	PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
 	PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
+	PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
+};
+
+/* Maximum number of simultaneous unicast MAC addresses. */
+#define MLX5_MAX_UC_MAC_ADDRESSES 128
+/* Maximum number of simultaneous Multicast MAC addresses. */
+#define MLX5_MAX_MC_MAC_ADDRESSES 128
+/* Maximum number of simultaneous MAC addresses. */
+#define MLX5_MAX_MAC_ADDRESSES \
+	(MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
+
+/* Recognized Infiniband device physical port name types. */
+enum mlx5_nl_phys_port_name_type {
+	MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
+	MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
+	MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
+	MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
+	MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
+};
+
+/** Switch information returned by mlx5_nl_switch_info(). */
+struct mlx5_switch_info {
+	uint32_t master:1; /**< Master device. */
+	uint32_t representor:1; /**< Representor device. */
+	enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
+	int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
+	int32_t port_name; /**< Representor port name. */
+	uint64_t switch_id; /**< Switch identifier. */
 };
 
 /* CQE status. */
@@ -150,4 +208,16 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
 
 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
 
+#define MLX5_CLASS_ARG_NAME "class"
+
+enum mlx5_class {
+	MLX5_CLASS_NET,
+	MLX5_CLASS_VDPA,
+	MLX5_CLASS_INVALID,
+};
+
+enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
+void mlx5_translate_port_name(const char *port_name_in,
+			      struct mlx5_switch_info *port_info_out);
+
 #endif /* RTE_PMD_MLX5_COMMON_H_ */