X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_common.h;h=a484b74b9c154746951a3be31c5dc35fbbf04caa;hb=d02ef361865e2cdc2aeae1c41fe485079149b7dd;hp=884ec02ba0d6a97c1c61defee6177368f2c612f7;hpb=0afacb04f50648ed4a90cbcb24117bb65f03e845;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 884ec02ba0..a484b74b9c 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -5,46 +5,37 @@ #ifndef RTE_PMD_MLX5_COMMON_H_ #define RTE_PMD_MLX5_COMMON_H_ -#include #include #include +#include #include #include #include #include +#include #include "mlx5_prm.h" +#include "mlx5_devx_cmds.h" - -/* - * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11. - * Otherwise there would be a type conflict between stdbool and altivec. - */ -#if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__) -#undef bool -/* redefine as in stdbool.h */ -#define bool _Bool -#endif +/* Reported driver name. */ +#define MLX5_DRIVER_NAME "mlx5_pci" /* Bit-field manipulation. */ #define BITFIELD_DECLARE(bf, type, size) \ type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ - !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] + !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] #define BITFIELD_DEFINE(bf, type, size) \ BITFIELD_DECLARE((bf), type, (size)) = { 0 } #define BITFIELD_SET(bf, b) \ - (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \ - (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ - ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) + (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ + ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) #define BITFIELD_RESET(bf, b) \ - (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \ - (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ - ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) + (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ + ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) #define BITFIELD_ISSET(bf, b) \ - (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \ - !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ - ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))) + !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ + ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) /* * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant @@ -102,12 +93,14 @@ pmd_drv_log_basename(const char *s) #ifdef RTE_LIBRTE_MLX5_DEBUG #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) -#define claim_zero(...) assert((__VA_ARGS__) == 0) -#define claim_nonzero(...) assert((__VA_ARGS__) != 0) +#define MLX5_ASSERT(exp) RTE_VERIFY(exp) +#define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) +#define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) #else /* RTE_LIBRTE_MLX5_DEBUG */ #define DEBUG(...) (void)0 +#define MLX5_ASSERT(exp) RTE_ASSERT(exp) #define claim_zero(...) (__VA_ARGS__) #define claim_nonzero(...) (__VA_ARGS__) @@ -138,7 +131,11 @@ enum { PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, - PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, + PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, + PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, + PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, + PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, + PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, }; /* Maximum number of simultaneous unicast MAC addresses. */ @@ -155,6 +152,7 @@ enum mlx5_nl_phys_port_name_type { MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ + MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ }; @@ -199,25 +197,75 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) return MLX5_CQE_STATUS_HW_OWN; - rte_cio_rmb(); + rte_io_rmb(); if (unlikely(op_code == MLX5_CQE_RESP_ERR || op_code == MLX5_CQE_REQ_ERR)) return MLX5_CQE_STATUS_ERR; return MLX5_CQE_STATUS_SW_OWN; } +__rte_internal int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); +__rte_internal +int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); + #define MLX5_CLASS_ARG_NAME "class" enum mlx5_class { - MLX5_CLASS_NET, - MLX5_CLASS_VDPA, MLX5_CLASS_INVALID, + MLX5_CLASS_NET = RTE_BIT64(0), + MLX5_CLASS_VDPA = RTE_BIT64(1), + MLX5_CLASS_REGEX = RTE_BIT64(2), }; -enum mlx5_class mlx5_class_get(struct rte_devargs *devargs); +#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE +#define MLX5_DBR_PER_PAGE 64 +/* Must be >= CHAR_BIT * sizeof(uint64_t) */ +#define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE) +/* Page size must be >= 512. */ +#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t))) + +struct mlx5_devx_dbr_page { + /* Door-bell records, must be first member in structure. */ + uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; + LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ + void *umem; + uint32_t dbr_count; /* Number of door-bell records in use. */ + /* 1 bit marks matching door-bell is in use. */ + uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; +}; + +/* devX creation object */ +struct mlx5_devx_obj { + void *obj; /* The DV object. */ + int id; /* The object ID. */ +}; + +/* UMR memory buffer used to define 1 entry in indirect mkey. */ +struct mlx5_klm { + uint32_t byte_count; + uint32_t mkey; + uint64_t address; +}; + +LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page); + +__rte_internal void mlx5_translate_port_name(const char *port_name_in, struct mlx5_switch_info *port_info_out); +void mlx5_glue_constructor(void); +__rte_internal +int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head, + struct mlx5_devx_dbr_page **dbr_page); +__rte_internal +int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id, + uint64_t offset); +__rte_internal +void *mlx5_devx_alloc_uar(void *ctx, int mapping); +extern uint8_t haswell_broadwell_cpu; + +__rte_internal +void mlx5_common_init(void); #endif /* RTE_PMD_MLX5_COMMON_H_ */