X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=221fd54a3963ebd3430965d8c0b2b85c4fafebec;hb=21ca2494ac6cf5e98b5d107efdefad1de6774583;hp=581658b73ae754c26412f9e4edf5f4cd9240daa0;hpb=446c3781c46865de8fc18f738cd44b2ab9f13948;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 581658b73a..221fd54a39 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -7,20 +7,16 @@ #include "mlx5_glue.h" #include "mlx5_prm.h" +#include - -/* devX creation object */ -struct mlx5_devx_obj { - struct mlx5dv_devx_obj *obj; /* The DV object. */ - int id; /* The object ID. */ -}; - -/* UMR memory buffer used to define 1 entry in indirect mkey. */ -struct mlx5_klm { - uint32_t byte_count; - uint32_t mkey; - uint64_t address; -}; +/* + * Defines the amount of retries to allocate the first UAR in the page. + * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as + * UAR base address if UAR was not the first object in the UAR page. + * It caused the PMD failure and we should try to get another UAR + * till we get the first one with non-NULL base address returned. + */ +#define MLX5_ALLOC_UAR_RETRY 32 /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ @@ -33,6 +29,11 @@ struct mlx5_devx_mkey_attr { uint32_t pd; uint32_t log_entity_size; uint32_t pg_access:1; + uint32_t relaxed_ordering_write:1; + uint32_t relaxed_ordering_read:1; + uint32_t umr_en:1; + uint32_t crypto_en:2; + uint32_t set_remote_rw:1; struct mlx5_klm *klm_array; int klm_num; }; @@ -40,13 +41,29 @@ struct mlx5_devx_mkey_attr { /* HCA qos attributes. */ struct mlx5_hca_qos_attr { uint32_t sup:1; /* Whether QOS is supported. */ - uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ - uint32_t flow_meter_reg_share:1; - /* Whether reg_c share is supported. */ + uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ + uint32_t packet_pacing:1; /* Packet pacing is supported. */ + uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ + uint32_t flow_meter:1; + /* + * Flow meter is supported, updated version. + * When flow_meter is 1, it indicates that REG_C sharing is supported. + * If flow_meter is 1, flow_meter_old is also 1. + * Using older driver versions, flow_meter_old can be 1 + * while flow_meter is 0. + */ + uint32_t flow_meter_aso_sup:1; + /* Whether FLOW_METER_ASO Object is supported. */ uint8_t log_max_flow_meter; /* Power of the maximum supported meters. */ uint8_t flow_meter_reg_c_ids; /* Bitmap of the reg_Cs available for flow meter to use. */ + uint32_t log_meter_aso_granularity:5; + /* Power of the minimum allocation granularity Object. */ + uint32_t log_meter_aso_max_alloc:5; + /* Power of the maximum allocation granularity Object. */ + uint32_t log_max_num_meter_aso:5; + /* Power of the maximum number of supported objects. */ }; @@ -63,13 +80,12 @@ struct mlx5_hca_vdpa_attr { uint32_t event_mode:3; uint32_t log_doorbell_stride:5; uint32_t log_doorbell_bar_size:5; + uint32_t queue_counters_valid:1; uint32_t max_num_virtio_queues; - uint32_t umem_1_buffer_param_a; - uint32_t umem_1_buffer_param_b; - uint32_t umem_2_buffer_param_a; - uint32_t umem_2_buffer_param_b; - uint32_t umem_3_buffer_param_a; - uint32_t umem_3_buffer_param_b; + struct { + uint32_t a; + uint32_t b; + } umems[3]; uint64_t doorbell_bar_offset; }; @@ -80,6 +96,8 @@ struct mlx5_hca_vdpa_attr { struct mlx5_hca_attr { uint32_t eswitch_manager:1; uint32_t flow_counters_dump:1; + uint32_t log_max_rqt_size:5; + uint32_t parse_graph_flex_node:1; uint8_t flow_counter_bulk_alloc_bitmap; uint32_t eth_net_offloads:1; uint32_t eth_virt:1; @@ -94,14 +112,62 @@ struct mlx5_hca_attr { uint32_t tunnel_lro_vxlan:1; uint32_t lro_max_msg_sz_mode:2; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; + uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; + uint32_t max_geneve_tlv_options; + uint32_t max_geneve_tlv_option_data_len; uint32_t hairpin:1; uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; uint32_t log_max_hairpin_num_packets:5; uint32_t vhca_id:16; + uint32_t relaxed_ordering_write:1; + uint32_t relaxed_ordering_read:1; + uint32_t access_register_user:1; + uint32_t wqe_index_ignore:1; + uint32_t cross_channel:1; + uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ + uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ + uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ + uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ + uint32_t scatter_fcs_w_decap_disable:1; + uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ + uint32_t roce:1; + uint32_t rq_ts_format:2; + uint32_t sq_ts_format:2; + uint32_t qp_ts_format:2; + uint32_t regex:1; + uint32_t reg_c_preserve:1; + uint32_t crypto:1; /* Crypto engine is supported. */ + uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ + uint32_t dek:1; /* General obj type DEK is supported. */ + uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ + uint32_t regexp_num_of_engines; + uint32_t log_max_ft_sampler_num:8; + uint32_t geneve_tlv_opt; + uint32_t cqe_compression:1; + uint32_t mini_cqe_resp_flow_tag:1; + uint32_t mini_cqe_resp_l3_l4_tag:1; struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; + int log_max_qp_sz; + int log_max_cq_sz; + int log_max_qp; + int log_max_cq; + uint32_t log_max_pd; + uint32_t log_max_mrw_sz; + uint32_t log_max_srq; + uint32_t log_max_srq_sz; + uint32_t rss_ind_tbl_cap; + uint32_t mmo_dma_en:1; + uint32_t mmo_compress_en:1; + uint32_t mmo_decompress_en:1; + uint32_t compress_min_block_size:4; + uint32_t log_max_mmo_dma:5; + uint32_t log_max_mmo_compress:5; + uint32_t log_max_mmo_decompress:5; + uint32_t umr_modify_entity_size_disabled:1; + uint32_t umr_indirect_mkey_disabled:1; }; struct mlx5_devx_wq_attr { @@ -143,6 +209,7 @@ struct mlx5_devx_create_rq_attr { uint32_t state:4; uint32_t flush_in_error_en:1; uint32_t hairpin:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t counter_set_id:8; @@ -183,13 +250,21 @@ struct mlx5_devx_tir_attr { uint32_t rx_hash_fn:4; uint32_t self_lb_block:2; uint32_t transport_domain:24; - uint32_t rx_hash_toeplitz_key[10]; + uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; }; +/* TIR attributes structure, used by TIR modify. */ +struct mlx5_devx_modify_tir_attr { + uint32_t tirn:24; + uint64_t modify_bitmask; + struct mlx5_devx_tir_attr tir; +}; + /* RQT attributes structure, used by RQT operations. */ struct mlx5_devx_rqt_attr { + uint8_t rq_type; uint32_t rqt_max_size:16; uint32_t rqt_actual_size:16; uint32_t rq_list[]; @@ -216,6 +291,9 @@ struct mlx5_devx_create_sq_attr { uint32_t reg_umr:1; uint32_t allow_swp:1; uint32_t hairpin:1; + uint32_t non_wire:1; + uint32_t static_sq_wq:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; @@ -239,6 +317,9 @@ struct mlx5_devx_cq_attr { uint32_t db_umem_valid:1; uint32_t use_first_only:1; uint32_t overrun_ignore:1; + uint32_t cqe_comp_en:1; + uint32_t mini_cqe_res_format:2; + uint32_t mini_cqe_res_format_ext:2; uint32_t log_cq_size:5; uint32_t log_page_size:5; uint32_t uar_page_id; @@ -250,42 +331,291 @@ struct mlx5_devx_cq_attr { uint64_t db_addr; }; +/* Virtq attributes structure, used by VIRTQ operations. */ +struct mlx5_devx_virtq_attr { + uint16_t hw_available_index; + uint16_t hw_used_index; + uint16_t q_size; + uint32_t pd:24; + uint32_t virtio_version_1_0:1; + uint32_t tso_ipv4:1; + uint32_t tso_ipv6:1; + uint32_t tx_csum:1; + uint32_t rx_csum:1; + uint32_t event_mode:3; + uint32_t state:4; + uint32_t hw_latency_mode:2; + uint32_t hw_max_latency_us:12; + uint32_t hw_max_pending_comp:16; + uint32_t dirty_bitmap_dump_enable:1; + uint32_t dirty_bitmap_mkey; + uint32_t dirty_bitmap_size; + uint32_t mkey; + uint32_t qp_id; + uint32_t queue_index; + uint32_t tis_id; + uint32_t counters_obj_id; + uint64_t dirty_bitmap_addr; + uint64_t type; + uint64_t desc_addr; + uint64_t used_addr; + uint64_t available_addr; + struct { + uint32_t id; + uint32_t size; + uint64_t offset; + } umems[3]; + uint8_t error_type; +}; + + +struct mlx5_devx_qp_attr { + uint32_t pd:24; + uint32_t uar_index:24; + uint32_t cqn:24; + uint32_t log_page_size:5; + uint32_t rq_size:17; /* Must be power of 2. */ + uint32_t log_rq_stride:3; + uint32_t sq_size:17; /* Must be power of 2. */ + uint32_t ts_format:2; + uint32_t dbr_umem_valid:1; + uint32_t dbr_umem_id; + uint64_t dbr_address; + uint32_t wq_umem_id; + uint64_t wq_umem_offset; +}; + +struct mlx5_devx_virtio_q_couners_attr { + uint64_t received_desc; + uint64_t completed_desc; + uint32_t error_cqes; + uint32_t bad_desc_errors; + uint32_t exceed_max_chain; + uint32_t invalid_buffer; +}; + +/* + * graph flow match sample attributes structure, + * used by flex parser operations. + */ +struct mlx5_devx_match_sample_attr { + uint32_t flow_match_sample_en:1; + uint32_t flow_match_sample_field_offset:16; + uint32_t flow_match_sample_offset_mode:4; + uint32_t flow_match_sample_field_offset_mask; + uint32_t flow_match_sample_field_offset_shift:4; + uint32_t flow_match_sample_field_base_offset:8; + uint32_t flow_match_sample_tunnel_mode:3; + uint32_t flow_match_sample_field_id; +}; + +/* graph node arc attributes structure, used by flex parser operations. */ +struct mlx5_devx_graph_arc_attr { + uint32_t compare_condition_value:16; + uint32_t start_inner_tunnel:1; + uint32_t arc_parse_graph_node:8; + uint32_t parse_graph_node_handle; +}; + +/* Maximal number of samples per graph node. */ +#define MLX5_GRAPH_NODE_SAMPLE_NUM 8 + +/* Maximal number of input/output arcs per graph node. */ +#define MLX5_GRAPH_NODE_ARC_NUM 8 + +/* parse graph node attributes structure, used by flex parser operations. */ +struct mlx5_devx_graph_node_attr { + uint32_t modify_field_select; + uint32_t header_length_mode:4; + uint32_t header_length_base_value:16; + uint32_t header_length_field_shift:4; + uint32_t header_length_field_offset:16; + uint32_t header_length_field_mask; + struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; + uint32_t next_header_field_offset:16; + uint32_t next_header_field_size:5; + struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; + struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; +}; + +/* Encryption key size is up to 1024 bit, 128 bytes. */ +#define MLX5_CRYPTO_KEY_MAX_SIZE 128 + +struct mlx5_devx_dek_attr { + uint32_t key_size:4; + uint32_t has_keytag:1; + uint32_t key_purpose:4; + uint32_t pd:24; + uint64_t opaque; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + +struct mlx5_devx_import_kek_attr { + uint64_t modify_field_select; + uint32_t state:8; + uint32_t key_size:4; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + /* mlx5_devx_cmds.c */ -struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_sz); +__rte_internal int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); +__rte_internal int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, int clear, uint32_t n_counters, uint64_t *pkts, uint64_t *bytes, uint32_t mkey, void *addr, - struct mlx5dv_devx_cmd_comp *cmd_comp, + void *cmd_comp, uint64_t async_id); -int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, +__rte_internal +int mlx5_devx_cmd_query_hca_attr(void *ctx, struct mlx5_hca_attr *attr); -struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, struct mlx5_devx_mkey_attr *attr); +__rte_internal int mlx5_devx_get_out_command_status(void *out); -int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num, +__rte_internal +int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, uint32_t *tis_td); -struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, struct mlx5_devx_create_rq_attr *rq_attr, int socket); +__rte_internal int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, struct mlx5_devx_modify_rq_attr *rq_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, struct mlx5_devx_tir_attr *tir_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, struct mlx5_devx_rqt_attr *rqt_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, struct mlx5_devx_create_sq_attr *sq_attr); +__rte_internal int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx, +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, struct mlx5_devx_tis_attr *tis_attr); -struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); +__rte_internal int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, FILE *file); -struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx, +__rte_internal +int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, + struct mlx5_devx_virtq_attr *attr); +__rte_internal +int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, + struct mlx5_devx_virtq_attr *attr); +__rte_internal +int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, + struct mlx5_devx_virtq_attr *attr); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, + struct mlx5_devx_qp_attr *attr); +__rte_internal +int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, + uint32_t qp_st_mod_op, uint32_t remote_qp_id); +__rte_internal +int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, + struct mlx5_devx_rqt_attr *rqt_attr); +__rte_internal +int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, + struct mlx5_devx_modify_tir_attr *tir_attr); +__rte_internal +int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, + uint32_t ids[], uint32_t num); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, + struct mlx5_devx_graph_node_attr *data); + +__rte_internal +int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, + uint32_t arg, uint32_t *data, uint32_t dw_cnt); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, + uint16_t class, uint8_t type, uint8_t len); + +/** + * Create virtio queue counters object DevX API. + * + * @param[in] ctx + * Device context. + + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); + +/** + * Query virtio queue counters object using DevX API. + * + * @param[in] couners_obj + * Pointer to virtq object structure. + * @param [in/out] attr + * Pointer to virtio queue counters attributes structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +__rte_internal +int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, + struct mlx5_devx_virtio_q_couners_attr *attr); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, + uint32_t pd); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); + +__rte_internal +int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); +__rte_internal +int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, + uint32_t *out_of_buffers); +/** + * Create general object of type FLOW_METER_ASO using DevX API.. + * + * @param[in] ctx + * Device context. + * @param [in] pd + * PD value to associate the FLOW_METER_ASO object with. + * @param [in] log_obj_size + * log_obj_size define to allocate number of 2 * meters + * in one FLOW_METER_ASO object. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, + uint32_t pd, uint32_t log_obj_size); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_import_kek_obj(void *ctx, + struct mlx5_devx_import_kek_attr *attr); + #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */