X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=40e36fb914e30a24ecc5310914fe078eb149423b;hb=90a2ec4ae81f2ef52f7c14bfc9307e75a4127fa4;hp=e576e30f242b8d262a7415db1cc7d95589968544;hpb=96f85ec489dbf7e206cdf54906d1e1c1092bc38e;p=dpdk.git

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index e576e30f24..40e36fb914 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -5,18 +5,10 @@
 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
 #define RTE_PMD_MLX5_DEVX_CMDS_H_
 
-#include "mlx5_glue.h"
-#include "mlx5_prm.h"
 #include <rte_compat.h>
 
-/*
- * Defines the amount of retries to allocate the first UAR in the page.
- * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
- * UAR base address if UAR was not the first object in the UAR page.
- * It caused the PMD failure and we should try to get another UAR
- * till we get the first one with non-NULL base address returned.
- */
-#define MLX5_ALLOC_UAR_RETRY 32
+#include "mlx5_glue.h"
+#include "mlx5_prm.h"
 
 /* This is limitation of libibverbs: in length variable type is u16. */
 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
@@ -108,14 +100,22 @@ struct mlx5_hca_attr {
 	uint32_t eth_virt:1;
 	uint32_t wqe_vlan_insert:1;
 	uint32_t csum_cap:1;
+	uint32_t vlan_cap:1;
 	uint32_t wqe_inline_mode:2;
 	uint32_t vport_inline_mode:3;
 	uint32_t tunnel_stateless_geneve_rx:1;
 	uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
 	uint32_t tunnel_stateless_gtp:1;
+	uint32_t max_lso_cap;
+	uint32_t scatter_fcs:1;
 	uint32_t lro_cap:1;
 	uint32_t tunnel_lro_gre:1;
 	uint32_t tunnel_lro_vxlan:1;
+	uint32_t tunnel_stateless_gre:1;
+	uint32_t tunnel_stateless_vxlan:1;
+	uint32_t swp:1;
+	uint32_t swp_csum:1;
+	uint32_t swp_lso:1;
 	uint32_t lro_max_msg_sz_mode:2;
 	uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
 	uint16_t lro_min_mss_size;
@@ -143,7 +143,8 @@ struct mlx5_hca_attr {
 	uint32_t sq_ts_format:2;
 	uint32_t steering_format_version:4;
 	uint32_t qp_ts_format:2;
-	uint32_t regex:1;
+	uint32_t regexp_params:1;
+	uint32_t regexp_version:3;
 	uint32_t reg_c_preserve:1;
 	uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
 	uint32_t crypto:1; /* Crypto engine is supported. */
@@ -173,9 +174,14 @@ struct mlx5_hca_attr {
 	uint32_t log_max_srq;
 	uint32_t log_max_srq_sz;
 	uint32_t rss_ind_tbl_cap;
-	uint32_t mmo_dma_en:1;
-	uint32_t mmo_compress_en:1;
-	uint32_t mmo_decompress_en:1;
+	uint32_t mmo_dma_sq_en:1;
+	uint32_t mmo_compress_sq_en:1;
+	uint32_t mmo_decompress_sq_en:1;
+	uint32_t mmo_dma_qp_en:1;
+	uint32_t mmo_compress_qp_en:1;
+	uint32_t mmo_decompress_qp_en:1;
+	uint32_t mmo_regex_qp_en:1;
+	uint32_t mmo_regex_sq_en:1;
 	uint32_t compress_min_block_size:4;
 	uint32_t log_max_mmo_dma:5;
 	uint32_t log_max_mmo_compress:5;
@@ -184,6 +190,15 @@ struct mlx5_hca_attr {
 	uint32_t umr_indirect_mkey_disabled:1;
 };
 
+/* LAG Context. */
+struct mlx5_devx_lag_context {
+	uint32_t fdb_selection_mode:1;
+	uint32_t port_select_mode:3;
+	uint32_t lag_state:3;
+	uint32_t tx_remap_affinity_1:4;
+	uint32_t tx_remap_affinity_2:4;
+};
+
 struct mlx5_devx_wq_attr {
 	uint32_t wq_type:4;
 	uint32_t wq_signature:1;
@@ -397,6 +412,8 @@ struct mlx5_devx_qp_attr {
 	uint64_t dbr_address;
 	uint32_t wq_umem_id;
 	uint64_t wq_umem_offset;
+	uint32_t user_index:24;
+	uint32_t mmo:1;
 };
 
 struct mlx5_devx_virtio_q_couners_attr {
@@ -666,4 +683,8 @@ struct mlx5_devx_obj *
 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
 				      struct mlx5_devx_crypto_login_attr *attr);
 
+__rte_internal
+int
+mlx5_devx_cmd_query_lag(void *ctx,
+			struct mlx5_devx_lag_context *lag_ctx);
 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */