X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=67b5f771c60f9ee6a83df6f60bdcca272989b0ab;hb=45d62067c23746f9fd4eafc26099d8df859f318a;hp=0ea2427b7521d174c6a7ba07fec600921fc0eebd;hpb=aed98b664c9720568344b0cb2fd0cd28b4fc7eb5;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 0ea2427b75..67b5f771c6 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -7,7 +7,16 @@ #include "mlx5_glue.h" #include "mlx5_prm.h" +#include +/* + * Defines the amount of retries to allocate the first UAR in the page. + * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as + * UAR base address if UAR was not the first object in the UAR page. + * It caused the PMD failure and we should try to get another UAR + * till we get the first one with non-NULL base address returned. + */ +#define MLX5_ALLOC_UAR_RETRY 32 /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ @@ -20,7 +29,9 @@ struct mlx5_devx_mkey_attr { uint32_t pd; uint32_t log_entity_size; uint32_t pg_access:1; - uint32_t relaxed_ordering:1; + uint32_t relaxed_ordering_write:1; + uint32_t relaxed_ordering_read:1; + uint32_t umr_en:1; struct mlx5_klm *klm_array; int klm_num; }; @@ -28,11 +39,17 @@ struct mlx5_devx_mkey_attr { /* HCA qos attributes. */ struct mlx5_hca_qos_attr { uint32_t sup:1; /* Whether QOS is supported. */ - uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ + uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ uint32_t packet_pacing:1; /* Packet pacing is supported. */ uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ - uint32_t flow_meter_reg_share:1; - /* Whether reg_c share is supported. */ + uint32_t flow_meter:1; + /* + * Flow meter is supported, updated version. + * When flow_meter is 1, it indicates that REG_C sharing is supported. + * If flow_meter is 1, flow_meter_old is also 1. + * Using older driver versions, flow_meter_old can be 1 + * while flow_meter is 0. + */ uint8_t log_max_flow_meter; /* Power of the maximum supported meters. */ uint8_t flow_meter_reg_c_ids; @@ -87,6 +104,8 @@ struct mlx5_hca_attr { uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; + uint32_t max_geneve_tlv_options; + uint32_t max_geneve_tlv_option_data_len; uint32_t hairpin:1; uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; @@ -99,13 +118,42 @@ struct mlx5_hca_attr { uint32_t cross_channel:1; uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ + uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ uint32_t scatter_fcs_w_decap_disable:1; + uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ + uint32_t roce:1; + uint32_t rq_ts_format:2; + uint32_t sq_ts_format:2; + uint32_t qp_ts_format:2; uint32_t regex:1; + uint32_t reg_c_preserve:1; uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; + uint32_t geneve_tlv_opt; + uint32_t cqe_compression:1; + uint32_t mini_cqe_resp_flow_tag:1; + uint32_t mini_cqe_resp_l3_l4_tag:1; struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; + int log_max_qp_sz; + int log_max_cq_sz; + int log_max_qp; + int log_max_cq; + uint32_t log_max_pd; + uint32_t log_max_mrw_sz; + uint32_t log_max_srq; + uint32_t log_max_srq_sz; + uint32_t rss_ind_tbl_cap; + uint32_t mmo_dma_en:1; + uint32_t mmo_compress_en:1; + uint32_t mmo_decompress_en:1; + uint32_t compress_min_block_size:4; + uint32_t log_max_mmo_dma:5; + uint32_t log_max_mmo_compress:5; + uint32_t log_max_mmo_decompress:5; + uint32_t umr_modify_entity_size_disabled:1; + uint32_t umr_indirect_mkey_disabled:1; }; struct mlx5_devx_wq_attr { @@ -147,6 +195,7 @@ struct mlx5_devx_create_rq_attr { uint32_t state:4; uint32_t flush_in_error_en:1; uint32_t hairpin:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t counter_set_id:8; @@ -230,6 +279,7 @@ struct mlx5_devx_create_sq_attr { uint32_t hairpin:1; uint32_t non_wire:1; uint32_t static_sq_wq:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; @@ -255,7 +305,7 @@ struct mlx5_devx_cq_attr { uint32_t overrun_ignore:1; uint32_t cqe_comp_en:1; uint32_t mini_cqe_res_format:2; - uint32_t cqe_size:3; + uint32_t mini_cqe_res_format_ext:2; uint32_t log_cq_size:5; uint32_t log_page_size:5; uint32_t uar_page_id; @@ -280,6 +330,9 @@ struct mlx5_devx_virtq_attr { uint32_t rx_csum:1; uint32_t event_mode:3; uint32_t state:4; + uint32_t hw_latency_mode:2; + uint32_t hw_max_latency_us:12; + uint32_t hw_max_pending_comp:16; uint32_t dirty_bitmap_dump_enable:1; uint32_t dirty_bitmap_mkey; uint32_t dirty_bitmap_size; @@ -310,6 +363,7 @@ struct mlx5_devx_qp_attr { uint32_t rq_size:17; /* Must be power of 2. */ uint32_t log_rq_stride:3; uint32_t sq_size:17; /* Must be power of 2. */ + uint32_t ts_format:2; uint32_t dbr_umem_valid:1; uint32_t dbr_umem_id; uint64_t dbr_address; @@ -457,6 +511,12 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, uint32_t *data, uint32_t dw_cnt); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, + uint16_t class, uint8_t type, uint8_t len); + /** * Create virtio queue counters object DevX API. * @@ -483,5 +543,19 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); __rte_internal int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, struct mlx5_devx_virtio_q_couners_attr *attr); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, + uint32_t pd); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); +__rte_internal +int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); +__rte_internal +int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, + uint32_t *out_of_buffers); #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */