X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=8277fdbc396b41a46310b55bd0e093e834e113eb;hb=7fb1c77b681c4a3b58eb254b9475b862cad799ae;hp=59a70a0e047be4c5624724d5a28edc254748ba48;hpb=796ae7bb6a41fd87c2a975763f26775c2fe7d8b3;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 59a70a0e04..8277fdbc39 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -8,19 +8,14 @@ #include "mlx5_glue.h" #include "mlx5_prm.h" - -/* devX creation object */ -struct mlx5_devx_obj { - void *obj; /* The DV object. */ - int id; /* The object ID. */ -}; - -/* UMR memory buffer used to define 1 entry in indirect mkey. */ -struct mlx5_klm { - uint32_t byte_count; - uint32_t mkey; - uint64_t address; -}; +/* + * Defines the amount of retries to allocate the first UAR in the page. + * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as + * UAR base address if UAR was not the first object in the UAR page. + * It caused the PMD failure and we should try to get another UAR + * till we get the first one with non-NULL base address returned. + */ +#define MLX5_ALLOC_UAR_RETRY 32 /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ @@ -33,7 +28,8 @@ struct mlx5_devx_mkey_attr { uint32_t pd; uint32_t log_entity_size; uint32_t pg_access:1; - uint32_t relaxed_ordering:1; + uint32_t relaxed_ordering_write:1; + uint32_t relaxed_ordering_read:1; struct mlx5_klm *klm_array; int klm_num; }; @@ -42,6 +38,8 @@ struct mlx5_devx_mkey_attr { struct mlx5_hca_qos_attr { uint32_t sup:1; /* Whether QOS is supported. */ uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ + uint32_t packet_pacing:1; /* Packet pacing is supported. */ + uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ uint32_t flow_meter_reg_share:1; /* Whether reg_c share is supported. */ uint8_t log_max_flow_meter; @@ -81,6 +79,7 @@ struct mlx5_hca_attr { uint32_t eswitch_manager:1; uint32_t flow_counters_dump:1; uint32_t log_max_rqt_size:5; + uint32_t parse_graph_flex_node:1; uint8_t flow_counter_bulk_alloc_bitmap; uint32_t eth_net_offloads:1; uint32_t eth_virt:1; @@ -95,6 +94,7 @@ struct mlx5_hca_attr { uint32_t tunnel_lro_vxlan:1; uint32_t lro_max_msg_sz_mode:2; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; + uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; uint32_t hairpin:1; uint32_t log_max_hairpin_queues:5; @@ -103,8 +103,29 @@ struct mlx5_hca_attr { uint32_t vhca_id:16; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; + uint32_t access_register_user:1; + uint32_t wqe_index_ignore:1; + uint32_t cross_channel:1; + uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ + uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ + uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ + uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ + uint32_t scatter_fcs_w_decap_disable:1; + uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ + uint32_t regex:1; + uint32_t regexp_num_of_engines; + uint32_t log_max_ft_sampler_num:8; struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; + int log_max_qp_sz; + int log_max_cq_sz; + int log_max_qp; + int log_max_cq; + uint32_t log_max_pd; + uint32_t log_max_mrw_sz; + uint32_t log_max_srq; + uint32_t log_max_srq_sz; + uint32_t rss_ind_tbl_cap; }; struct mlx5_devx_wq_attr { @@ -191,6 +212,13 @@ struct mlx5_devx_tir_attr { struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; }; +/* TIR attributes structure, used by TIR modify. */ +struct mlx5_devx_modify_tir_attr { + uint32_t tirn:24; + uint64_t modify_bitmask; + struct mlx5_devx_tir_attr tir; +}; + /* RQT attributes structure, used by RQT operations. */ struct mlx5_devx_rqt_attr { uint8_t rq_type; @@ -220,6 +248,8 @@ struct mlx5_devx_create_sq_attr { uint32_t reg_umr:1; uint32_t allow_swp:1; uint32_t hairpin:1; + uint32_t non_wire:1; + uint32_t static_sq_wq:1; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; @@ -243,6 +273,10 @@ struct mlx5_devx_cq_attr { uint32_t db_umem_valid:1; uint32_t use_first_only:1; uint32_t overrun_ignore:1; + uint32_t cqe_comp_en:1; + uint32_t mini_cqe_res_format:2; + uint32_t mini_cqe_res_format_ext:2; + uint32_t cqe_size:3; uint32_t log_cq_size:5; uint32_t log_page_size:5; uint32_t uar_page_id; @@ -259,6 +293,7 @@ struct mlx5_devx_virtq_attr { uint16_t hw_available_index; uint16_t hw_used_index; uint16_t q_size; + uint32_t pd:24; uint32_t virtio_version_1_0:1; uint32_t tso_ipv4:1; uint32_t tso_ipv6:1; @@ -284,6 +319,7 @@ struct mlx5_devx_virtq_attr { uint32_t size; uint64_t offset; } umems[3]; + uint8_t error_type; }; @@ -311,6 +347,50 @@ struct mlx5_devx_virtio_q_couners_attr { uint32_t invalid_buffer; }; +/* + * graph flow match sample attributes structure, + * used by flex parser operations. + */ +struct mlx5_devx_match_sample_attr { + uint32_t flow_match_sample_en:1; + uint32_t flow_match_sample_field_offset:16; + uint32_t flow_match_sample_offset_mode:4; + uint32_t flow_match_sample_field_offset_mask; + uint32_t flow_match_sample_field_offset_shift:4; + uint32_t flow_match_sample_field_base_offset:8; + uint32_t flow_match_sample_tunnel_mode:3; + uint32_t flow_match_sample_field_id; +}; + +/* graph node arc attributes structure, used by flex parser operations. */ +struct mlx5_devx_graph_arc_attr { + uint32_t compare_condition_value:16; + uint32_t start_inner_tunnel:1; + uint32_t arc_parse_graph_node:8; + uint32_t parse_graph_node_handle; +}; + +/* Maximal number of samples per graph node. */ +#define MLX5_GRAPH_NODE_SAMPLE_NUM 8 + +/* Maximal number of input/output arcs per graph node. */ +#define MLX5_GRAPH_NODE_ARC_NUM 8 + +/* parse graph node attributes structure, used by flex parser operations. */ +struct mlx5_devx_graph_node_attr { + uint32_t modify_field_select; + uint32_t header_length_mode:4; + uint32_t header_length_base_value:16; + uint32_t header_length_field_shift:4; + uint32_t header_length_field_offset:16; + uint32_t header_length_field_mask; + struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; + uint32_t next_header_field_offset:16; + uint32_t next_header_field_size:5; + struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; + struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; +}; + /* mlx5_devx_cmds.c */ __rte_internal @@ -384,7 +464,20 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, __rte_internal int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, struct mlx5_devx_rqt_attr *rqt_attr); +__rte_internal +int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, + struct mlx5_devx_modify_tir_attr *tir_attr); +__rte_internal +int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, + uint32_t ids[], uint32_t num); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, + struct mlx5_devx_graph_node_attr *data); +__rte_internal +int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, + uint32_t arg, uint32_t *data, uint32_t dw_cnt); /** * Create virtio queue counters object DevX API. * @@ -411,5 +504,10 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); __rte_internal int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, struct mlx5_devx_virtio_q_couners_attr *attr); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, + uint32_t pd); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */