X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=979bc946d1bbf6be6b68c13cce1b566a9f9b9d0f;hb=fc59a1ec556b4464296b1fccec596ea08879e237;hp=553b26c0ba0b4f11d9642241472a7c6d3481a2f7;hpb=01b8b5b618eb071a7c6c419bfd88a96e42178ba3;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 553b26c0ba..979bc946d1 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -5,10 +5,11 @@ #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ #define RTE_PMD_MLX5_DEVX_CMDS_H_ +#include + #include "mlx5_glue.h" #include "mlx5_prm.h" - /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) @@ -20,7 +21,11 @@ struct mlx5_devx_mkey_attr { uint32_t pd; uint32_t log_entity_size; uint32_t pg_access:1; - uint32_t relaxed_ordering:1; + uint32_t relaxed_ordering_write:1; + uint32_t relaxed_ordering_read:1; + uint32_t umr_en:1; + uint32_t crypto_en:2; + uint32_t set_remote_rw:1; struct mlx5_klm *klm_array; int klm_num; }; @@ -28,15 +33,29 @@ struct mlx5_devx_mkey_attr { /* HCA qos attributes. */ struct mlx5_hca_qos_attr { uint32_t sup:1; /* Whether QOS is supported. */ - uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ + uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ uint32_t packet_pacing:1; /* Packet pacing is supported. */ uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ - uint32_t flow_meter_reg_share:1; - /* Whether reg_c share is supported. */ + uint32_t flow_meter:1; + /* + * Flow meter is supported, updated version. + * When flow_meter is 1, it indicates that REG_C sharing is supported. + * If flow_meter is 1, flow_meter_old is also 1. + * Using older driver versions, flow_meter_old can be 1 + * while flow_meter is 0. + */ + uint32_t flow_meter_aso_sup:1; + /* Whether FLOW_METER_ASO Object is supported. */ uint8_t log_max_flow_meter; /* Power of the maximum supported meters. */ uint8_t flow_meter_reg_c_ids; /* Bitmap of the reg_Cs available for flow meter to use. */ + uint32_t log_meter_aso_granularity:5; + /* Power of the minimum allocation granularity Object. */ + uint32_t log_meter_aso_max_alloc:5; + /* Power of the maximum allocation granularity Object. */ + uint32_t log_max_num_meter_aso:5; + /* Power of the maximum number of supported objects. */ }; @@ -62,6 +81,11 @@ struct mlx5_hca_vdpa_attr { uint64_t doorbell_bar_offset; }; +struct mlx5_hca_flow_attr { + uint32_t tunnel_header_0_1; + uint32_t tunnel_header_2_3; +}; + /* HCA supports this number of time periods for LRO. */ #define MLX5_LRO_NUM_SUPP_PERIODS 4 @@ -75,18 +99,29 @@ struct mlx5_hca_attr { uint32_t eth_net_offloads:1; uint32_t eth_virt:1; uint32_t wqe_vlan_insert:1; + uint32_t csum_cap:1; + uint32_t vlan_cap:1; uint32_t wqe_inline_mode:2; uint32_t vport_inline_mode:3; uint32_t tunnel_stateless_geneve_rx:1; uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ uint32_t tunnel_stateless_gtp:1; + uint32_t max_lso_cap; + uint32_t scatter_fcs:1; uint32_t lro_cap:1; uint32_t tunnel_lro_gre:1; uint32_t tunnel_lro_vxlan:1; + uint32_t tunnel_stateless_gre:1; + uint32_t tunnel_stateless_vxlan:1; + uint32_t swp:1; + uint32_t swp_csum:1; + uint32_t swp_lso:1; uint32_t lro_max_msg_sz_mode:2; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; + uint32_t max_geneve_tlv_options; + uint32_t max_geneve_tlv_option_data_len; uint32_t hairpin:1; uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; @@ -103,11 +138,55 @@ struct mlx5_hca_attr { uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ uint32_t scatter_fcs_w_decap_disable:1; uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ + uint32_t roce:1; + uint32_t rq_ts_format:2; + uint32_t sq_ts_format:2; + uint32_t steering_format_version:4; + uint32_t qp_ts_format:2; uint32_t regex:1; + uint32_t reg_c_preserve:1; + uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ + uint32_t crypto:1; /* Crypto engine is supported. */ + uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ + uint32_t dek:1; /* General obj type DEK is supported. */ + uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ + uint32_t credential:1; /* General obj type CREDENTIAL supported. */ + uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; + uint32_t inner_ipv4_ihl:1; + uint32_t outer_ipv4_ihl:1; + uint32_t geneve_tlv_opt; + uint32_t cqe_compression:1; + uint32_t mini_cqe_resp_flow_tag:1; + uint32_t mini_cqe_resp_l3_l4_tag:1; + uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; + struct mlx5_hca_flow_attr flow; + int log_max_qp_sz; + int log_max_cq_sz; + int log_max_qp; + int log_max_cq; + uint32_t log_max_pd; + uint32_t log_max_mrw_sz; + uint32_t log_max_srq; + uint32_t log_max_srq_sz; + uint32_t rss_ind_tbl_cap; + uint32_t mmo_dma_sq_en:1; + uint32_t mmo_compress_sq_en:1; + uint32_t mmo_decompress_sq_en:1; + uint32_t mmo_dma_qp_en:1; + uint32_t mmo_compress_qp_en:1; + uint32_t mmo_decompress_qp_en:1; + uint32_t mmo_regex_qp_en:1; + uint32_t mmo_regex_sq_en:1; + uint32_t compress_min_block_size:4; + uint32_t log_max_mmo_dma:5; + uint32_t log_max_mmo_compress:5; + uint32_t log_max_mmo_decompress:5; + uint32_t umr_modify_entity_size_disabled:1; + uint32_t umr_indirect_mkey_disabled:1; }; struct mlx5_devx_wq_attr { @@ -149,6 +228,7 @@ struct mlx5_devx_create_rq_attr { uint32_t state:4; uint32_t flush_in_error_en:1; uint32_t hairpin:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t counter_set_id:8; @@ -232,6 +312,7 @@ struct mlx5_devx_create_sq_attr { uint32_t hairpin:1; uint32_t non_wire:1; uint32_t static_sq_wq:1; + uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; @@ -258,7 +339,6 @@ struct mlx5_devx_cq_attr { uint32_t cqe_comp_en:1; uint32_t mini_cqe_res_format:2; uint32_t mini_cqe_res_format_ext:2; - uint32_t cqe_size:3; uint32_t log_cq_size:5; uint32_t log_page_size:5; uint32_t uar_page_id; @@ -283,6 +363,9 @@ struct mlx5_devx_virtq_attr { uint32_t rx_csum:1; uint32_t event_mode:3; uint32_t state:4; + uint32_t hw_latency_mode:2; + uint32_t hw_max_latency_us:12; + uint32_t hw_max_pending_comp:16; uint32_t dirty_bitmap_dump_enable:1; uint32_t dirty_bitmap_mkey; uint32_t dirty_bitmap_size; @@ -313,11 +396,14 @@ struct mlx5_devx_qp_attr { uint32_t rq_size:17; /* Must be power of 2. */ uint32_t log_rq_stride:3; uint32_t sq_size:17; /* Must be power of 2. */ + uint32_t ts_format:2; uint32_t dbr_umem_valid:1; uint32_t dbr_umem_id; uint64_t dbr_address; uint32_t wq_umem_id; uint64_t wq_umem_offset; + uint32_t user_index:24; + uint32_t mmo:1; }; struct mlx5_devx_virtio_q_couners_attr { @@ -373,6 +459,41 @@ struct mlx5_devx_graph_node_attr { struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; }; +/* Encryption key size is up to 1024 bit, 128 bytes. */ +#define MLX5_CRYPTO_KEY_MAX_SIZE 128 + +struct mlx5_devx_dek_attr { + uint32_t key_size:4; + uint32_t has_keytag:1; + uint32_t key_purpose:4; + uint32_t pd:24; + uint64_t opaque; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + +struct mlx5_devx_import_kek_attr { + uint64_t modify_field_select; + uint32_t state:8; + uint32_t key_size:4; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + +#define MLX5_CRYPTO_CREDENTIAL_SIZE 48 + +struct mlx5_devx_credential_attr { + uint64_t modify_field_select; + uint32_t state:8; + uint32_t credential_role:8; + uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; +}; + +struct mlx5_devx_crypto_login_attr { + uint64_t modify_field_select; + uint32_t credential_pointer:24; + uint32_t session_import_kek_ptr:24; + uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; +}; + /* mlx5_devx_cmds.c */ __rte_internal @@ -426,6 +547,8 @@ __rte_internal int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, FILE *file); __rte_internal +int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); +__rte_internal struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr); __rte_internal @@ -460,6 +583,16 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, uint32_t *data, uint32_t dw_cnt); + +__rte_internal +int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, + uint32_t arg, uint32_t *data, uint32_t dw_cnt); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, + uint16_t class, uint8_t type, uint8_t len); + /** * Create virtio queue counters object DevX API. * @@ -486,9 +619,58 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); __rte_internal int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, struct mlx5_devx_virtio_q_couners_attr *attr); - __rte_internal struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); + +__rte_internal +int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); + +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); +__rte_internal +int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, + uint32_t *out_of_buffers); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, + uint32_t pd, uint32_t log_obj_size); + +/** + * Create general object of type FLOW_METER_ASO using DevX API.. + * + * @param[in] ctx + * Device context. + * @param [in] pd + * PD value to associate the FLOW_METER_ASO object with. + * @param [in] log_obj_size + * log_obj_size define to allocate number of 2 * meters + * in one FLOW_METER_ASO object. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, + uint32_t pd, uint32_t log_obj_size); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_import_kek_obj(void *ctx, + struct mlx5_devx_import_kek_attr *attr); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_credential_obj(void *ctx, + struct mlx5_devx_credential_attr *attr); + +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_crypto_login_obj(void *ctx, + struct mlx5_devx_crypto_login_attr *attr); #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */