X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_prm.h;h=4835d0406ee53264ba816546c7ce2d7e68e4ea7c;hb=65be2ca6e0256836c0a74bfa27cc458f1f80b44d;hp=2bca175ebd45f0a1acbbd22afca1650768bd6a15;hpb=0111a74e13dd0c8fd5cdb240965d9a9857a12ee9;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2bca175ebd..4835d0406e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -412,6 +412,127 @@ struct mlx5_cqe_ts { uint8_t op_own; }; +struct mlx5_wqe_rseg { + uint64_t raddr; + uint32_t rkey; + uint32_t reserved; +} __rte_packed; + +#define MLX5_UMRC_IF_OFFSET 31u +#define MLX5_UMRC_KO_OFFSET 16u +#define MLX5_UMRC_TO_BS_OFFSET 0u + +struct mlx5_wqe_umr_cseg { + uint32_t if_cf_toe_cq_res; + uint32_t ko_to_bs; + uint64_t mkey_mask; + uint32_t rsvd1[8]; +} __rte_packed; + +struct mlx5_wqe_mkey_cseg { + uint32_t fr_res_af_sf; + uint32_t qpn_mkey; + uint32_t reserved2; + uint32_t flags_pd; + uint64_t start_addr; + uint64_t len; + uint32_t bsf_octword_size; + uint32_t reserved3[4]; + uint32_t translations_octword_size; + uint32_t res4_lps; + uint32_t reserved; +} __rte_packed; + +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +struct mlx5_umr_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_umr_cseg ucseg; + struct mlx5_wqe_mkey_cseg mkc; + union { + struct mlx5_wqe_dseg kseg[0]; + struct mlx5_wqe_umr_bsf_seg bsf[0]; + }; +} __rte_packed; + +struct mlx5_rdma_write_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_rseg rseg; + struct mlx5_wqe_dseg dseg[0]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + /* GGA */ /* MMO metadata segment */ @@ -732,7 +853,8 @@ struct mlx5_ifc_fte_match_set_misc_bits { u8 vxlan_vni[0x18]; u8 reserved_at_b8[0x8]; u8 geneve_vni[0x18]; - u8 reserved_at_e4[0x7]; + u8 reserved_at_e4[0x6]; + u8 geneve_tlv_option_0_exist[0x1]; u8 geneve_oam[0x1]; u8 reserved_at_e0[0xc]; u8 outer_ipv6_flow_label[0x14]; @@ -778,7 +900,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { u8 tcp_flags[0x9]; u8 tcp_sport[0x10]; u8 tcp_dport[0x10]; - u8 reserved_at_c0[0x18]; + u8 reserved_at_c0[0x10]; + u8 ipv4_ihl[0x4]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 ipv4_checksum_ok[0x1]; + u8 l4_checksum_ok[0x1]; u8 ip_ttl_hoplimit[0x8]; u8 udp_sport[0x10]; u8 udp_dport[0x10]; @@ -848,7 +975,26 @@ struct mlx5_ifc_fte_match_set_misc4_bits { u8 prog_sample_field_id_2[0x20]; u8 prog_sample_field_value_3[0x20]; u8 prog_sample_field_id_3[0x20]; - u8 reserved_at_100[0x100]; + u8 prog_sample_field_value_4[0x20]; + u8 prog_sample_field_id_4[0x20]; + u8 prog_sample_field_value_5[0x20]; + u8 prog_sample_field_id_5[0x20]; + u8 prog_sample_field_value_6[0x20]; + u8 prog_sample_field_id_6[0x20]; + u8 prog_sample_field_value_7[0x20]; + u8 prog_sample_field_id_7[0x20]; +}; + +struct mlx5_ifc_fte_match_set_misc5_bits { + u8 macsec_tag_0[0x20]; + u8 macsec_tag_1[0x20]; + u8 macsec_tag_2[0x20]; + u8 macsec_tag_3[0x20]; + u8 tunnel_header_0[0x20]; + u8 tunnel_header_1[0x20]; + u8 tunnel_header_2[0x20]; + u8 tunnel_header_3[0x20]; + u8 reserved[0x100]; }; /* Flow matcher. */ @@ -859,12 +1005,13 @@ struct mlx5_ifc_fte_match_param_bits { struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; + struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; /* * Add reserved bit to match the struct size with the size defined in PRM. * This extension is not required in Linux. */ #ifndef HAVE_INFINIBAND_VERBS_H - u8 reserved_0[0x400]; + u8 reserved_0[0x200]; #endif }; @@ -881,6 +1028,7 @@ enum { MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, + MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, }; enum { @@ -907,6 +1055,7 @@ enum { MLX5_CMD_OP_DEALLOC_PD = 0x801, MLX5_CMD_OP_ACCESS_REGISTER = 0x805, MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, + MLX5_CMD_OP_QUERY_LAG = 0x842, MLX5_CMD_OP_CREATE_TIR = 0x900, MLX5_CMD_OP_MODIFY_TIR = 0x901, MLX5_CMD_OP_CREATE_SQ = 0X904, @@ -1103,6 +1252,8 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ @@ -1117,8 +1268,16 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -1168,6 +1327,10 @@ enum { #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) +/* The device steering logic format. */ +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 + struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_0[0x30]; u8 vhca_id[0x10]; @@ -1186,16 +1349,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 wqe_index_ignore_cap[0x1]; u8 dynamic_qp_allocation[0x1]; u8 log_max_qp[0x5]; - u8 regexp[0x1]; - u8 reserved_at_a1[0x3]; + u8 reserved_at_a0[0x4]; u8 regexp_num_of_engines[0x4]; u8 reserved_at_a8[0x1]; u8 reg_c_preserve[0x1]; u8 reserved_at_aa[0x1]; u8 log_max_srq[0x5]; - u8 reserved_at_b0[0x3]; - u8 regexp_log_crspace_size[0x5]; - u8 reserved_at_b8[0x3]; + u8 reserved_at_b0[0xb]; u8 scatter_fcs_w_decap_disable[0x1]; u8 reserved_at_bc[0x4]; u8 reserved_at_c0[0x8]; @@ -1232,10 +1392,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 rtr2rts_qp_counters_set_id[0x1]; u8 rts2rts_udp_sport[0x1]; u8 rts2rts_lag_tx_port_affinity[0x1]; - u8 dma_mmo[0x1]; + u8 dma_mmo_sq[0x1]; u8 compress_min_block_size[0x4]; - u8 compress[0x1]; - u8 decompress[0x1]; + u8 compress_mmo_sq[0x1]; + u8 decompress_mmo_sq[0x1]; u8 log_max_ra_res_qp[0x6]; u8 end_pad[0x1]; u8 cc_query_allowed[0x1]; @@ -1351,9 +1511,11 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 uc[0x1]; u8 rc[0x1]; u8 uar_4k[0x1]; - u8 reserved_at_241[0x9]; + u8 reserved_at_241[0x8]; + u8 regexp_params[0x1]; u8 uar_sz[0x6]; - u8 reserved_at_250[0x8]; + u8 port_selection_cap[0x1]; + u8 reserved_at_251[0x7]; u8 log_pg_sz[0x8]; u8 bf[0x1]; u8 driver_version[0x1]; @@ -1365,7 +1527,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_lag_ports[0x4]; u8 reserved_at_280[0x10]; u8 max_wqe_sz_sq[0x10]; - u8 reserved_at_2a0[0x10]; + u8 reserved_at_2a0[0xc]; + u8 regexp_mmo_sq[0x1]; + u8 regexp_version[0x3]; u8 max_wqe_sz_rq[0x10]; u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; @@ -1436,7 +1600,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 general_obj_types[0x40]; u8 sq_ts_format[0x2]; u8 rq_ts_format[0x2]; - u8 reserved_at_444[0x1C]; + u8 steering_format_version[0x4]; + u8 reserved_at_448[0x18]; u8 reserved_at_460[0x8]; u8 aes_xts[0x1]; u8 crypto[0x1]; @@ -1477,7 +1642,12 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_vhca_ports[0x8]; u8 reserved_at_618[0x6]; u8 sw_owner_id[0x1]; - u8 reserved_at_61f[0x1e1]; + u8 reserved_at_61f[0x109]; + u8 dma_mmo_qp[0x1]; + u8 regexp_mmo_qp[0x1]; + u8 compress_mmo_qp[0x1]; + u8 decompress_mmo_qp[0x1]; + u8 reserved_at_624[0xd4]; }; struct mlx5_ifc_qos_cap_bits { @@ -1595,6 +1765,27 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_1c0[0x620]; }; +/** + * PARSE_GRAPH_NODE Capabilities Field Descriptions + */ +struct mlx5_ifc_parse_graph_node_cap_bits { + u8 node_in[0x20]; + u8 node_out[0x20]; + u8 header_length_mode[0x10]; + u8 sample_offset_mode[0x10]; + u8 max_num_arc_in[0x08]; + u8 max_num_arc_out[0x08]; + u8 max_num_sample[0x08]; + u8 reserved_at_78[0x07]; + u8 sample_id_in_out[0x1]; + u8 max_base_header_length[0x10]; + u8 reserved_at_90[0x08]; + u8 max_sample_base_offset[0x08]; + u8 max_next_header_offset[0x10]; + u8 reserved_at_b0[0x08]; + u8 header_length_mask_width[0x08]; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -1645,9 +1836,76 @@ struct mlx5_ifc_roce_caps_bits { u8 reserved_at_20[0x7e0]; }; +/* + * Table 1872 - Flow Table Fields Supported 2 Format + */ +struct mlx5_ifc_ft_fields_support_2_bits { + u8 reserved_at_0[0xf]; + u8 tunnel_header_2_3[0x1]; + u8 tunnel_header_0_1[0x1]; + u8 macsec_syndrome[0x1]; + u8 macsec_tag[0x1]; + u8 outer_lrh_sl[0x1]; + u8 inner_ipv4_ihl[0x1]; + u8 outer_ipv4_ihl[0x1]; + u8 psp_syndrome[0x1]; + u8 inner_l3_ok[0x1]; + u8 inner_l4_ok[0x1]; + u8 outer_l3_ok[0x1]; + u8 outer_l4_ok[0x1]; + u8 psp_header[0x1]; + u8 inner_ipv4_checksum_ok[0x1]; + u8 inner_l4_checksum_ok[0x1]; + u8 outer_ipv4_checksum_ok[0x1]; + u8 outer_l4_checksum_ok[0x1]; + u8 reserved_at_20[0x60]; +}; + struct mlx5_ifc_flow_table_nic_cap_bits { - u8 reserved_at_0[0x200]; - struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties; + u8 reserved_at_0[0x200]; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive_rdma; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive_sniffer; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit_rdma; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit_sniffer; + u8 reserved_at_e00[0x600]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_nic_receive; +}; + +/* + * HCA Capabilities 2 + */ +struct mlx5_ifc_cmd_hca_cap_2_bits { + u8 reserved_at_0[0x80]; /* End of DW4. */ + u8 reserved_at_80[0x3]; + u8 max_num_prog_sample_field[0x5]; + u8 reserved_at_88[0x3]; + u8 log_max_num_reserved_qpn[0x5]; + u8 reserved_at_90[0x3]; + u8 log_reserved_qpn_granularity[0x5]; + u8 reserved_at_98[0x3]; + u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ + u8 max_reformat_insert_size[0x8]; + u8 max_reformat_insert_offset[0x8]; + u8 max_reformat_remove_size[0x8]; + u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ + u8 aso_conntrack_reg_id[0x8]; + u8 reserved_at_c8[0x3]; + u8 log_conn_track_granularity[0x5]; + u8 reserved_at_d0[0x3]; + u8 log_conn_track_max_alloc[0x5]; + u8 reserved_at_d8[0x3]; + u8 log_max_conn_track_offload[0x5]; + u8 reserved_at_e0[0x20]; /* End of DW7. */ + u8 reserved_at_100[0x700]; }; union mlx5_ifc_hca_cap_union_bits { @@ -1750,6 +2008,14 @@ struct mlx5_ifc_query_nic_vport_context_in_bits { u8 reserved_at_68[0x18]; }; +/* + * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. + * Each TIS binds to one PF by setting lag_tx_port_affinity (>0). + * Once LAG enabled, we create multiple TISs and bind each one to + * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1. + */ +#define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \ + (index) % (num) + 1 : 0) struct mlx5_ifc_tisc_bits { u8 strict_lag_tx_port_affinity[0x1]; u8 reserved_at_1[0x3]; @@ -1783,6 +2049,39 @@ struct mlx5_ifc_query_tis_in_bits { u8 reserved_at_60[0x20]; }; +/* port_select_mode definition. */ +enum mlx5_lag_mode_type { + MLX5_LAG_MODE_TIS = 0, + MLX5_LAG_MODE_HASH = 1, +}; + +struct mlx5_ifc_lag_context_bits { + u8 fdb_selection_mode[0x1]; + u8 reserved_at_1[0x14]; + u8 port_select_mode[0x3]; + u8 reserved_at_18[0x5]; + u8 lag_state[0x3]; + u8 reserved_at_20[0x14]; + u8 tx_remap_affinity_2[0x4]; + u8 reserved_at_38[0x4]; + u8 tx_remap_affinity_1[0x4]; +}; + +struct mlx5_ifc_query_lag_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_query_lag_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + struct mlx5_ifc_lag_context_bits context; +}; + struct mlx5_ifc_alloc_transport_domain_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -2286,6 +2585,13 @@ struct mlx5_ifc_flow_meter_parameters_bits { #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 +enum { + MLX5_METER_MODE_IP_LEN = 0x0, + MLX5_METER_MODE_L2_LEN = 0x1, + MLX5_METER_MODE_L2_IPG_LEN = 0x2, + MLX5_METER_MODE_PKT = 0x3, +}; + enum { MLX5_CQE_SIZE_64B = 0x0, MLX5_CQE_SIZE_128B = 0x1, @@ -2412,9 +2718,13 @@ enum { MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, + MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, + MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, + MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, + MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, }; struct mlx5_ifc_general_obj_in_cmd_hdr_bits { @@ -2509,6 +2819,57 @@ struct mlx5_ifc_create_dek_in_bits { struct mlx5_ifc_dek_bits dek; }; +struct mlx5_ifc_import_kek_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0xc]; + u8 key_size[0x4]; + u8 reserved_at_58[0x1a8]; + u8 key[0x400]; + u8 reserved_at_600[0x200]; +}; + +struct mlx5_ifc_create_import_kek_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_import_kek_bits import_kek; +}; + +enum { + MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, + MLX5_CREDENTIAL_ROLE_USER = 0x1, +}; + +struct mlx5_ifc_credential_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0x10]; + u8 credential_role[0x8]; + u8 reserved_at_60[0x1a0]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_credential_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_credential_bits credential; +}; + +struct mlx5_ifc_crypto_login_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x48]; + u8 credential_pointer[0x18]; + u8 reserved_at_a0[0x8]; + u8 session_import_kek_ptr[0x18]; + u8 reserved_at_c0[0x140]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_crypto_login_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_crypto_login_bits crypto_login; +}; + enum { MLX5_VIRTQ_STATE_INIT = 0, MLX5_VIRTQ_STATE_RDY = 1, @@ -2618,6 +2979,67 @@ struct mlx5_ifc_create_flow_meter_aso_in_bits { struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; }; + +struct mlx5_ifc_tcp_window_params_bits { + u8 max_ack[0x20]; + u8 max_win[0x20]; + u8 reply_end[0x20]; + u8 sent_end[0x20]; +}; + +struct mlx5_ifc_conn_track_aso_bits { + struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ + struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ + u8 last_end[0x20]; /* End of DW8. */ + u8 last_ack[0x20]; /* End of DW9. */ + u8 last_seq[0x20]; /* End of DW10. */ + u8 last_win[0x10]; + u8 reserved_at_170[0xa]; + u8 last_dir[0x1]; + u8 last_index[0x5]; /* End of DW11. */ + u8 reserved_at_180[0x40]; /* End of DW13. */ + u8 reply_direction_tcp_scale[0x4]; + u8 reply_direction_tcp_close_initiated[0x1]; + u8 reply_direction_tcp_liberal_enabled[0x1]; + u8 reply_direction_tcp_data_unacked[0x1]; + u8 reply_direction_tcp_max_ack[0x1]; + u8 reserved_at_1c8[0x8]; + u8 original_direction_tcp_scale[0x4]; + u8 original_direction_tcp_close_initiated[0x1]; + u8 original_direction_tcp_liberal_enabled[0x1]; + u8 original_direction_tcp_data_unacked[0x1]; + u8 original_direction_tcp_max_ack[0x1]; + u8 reserved_at_1d8[0x8]; /* End of DW14. */ + u8 valid[0x1]; + u8 state[0x3]; + u8 freeze_track[0x1]; + u8 reserved_at_1e5[0xb]; + u8 reserved_at_1f0[0x1]; + u8 connection_assured[0x1]; + u8 sack_permitted[0x1]; + u8 challenged_acked[0x1]; + u8 heartbeat[0x1]; + u8 max_ack_window[0x3]; + u8 reserved_at_1f8[0x1]; + u8 retransmission_counter[0x3]; + u8 retranmission_limit_exceeded[0x1]; + u8 retranmission_limit[0x3]; /* End of DW15. */ +}; + +struct mlx5_ifc_conn_track_offload_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x40]; + u8 reserved_at_80[0x8]; + u8 conn_track_aso_access_pd[0x18]; + u8 reserved_at_a0[0x160]; + struct mlx5_ifc_conn_track_aso_bits conn_track_aso; +}; + +struct mlx5_ifc_create_conn_track_aso_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_conn_track_offload_bits conn_track_offload; +}; + enum mlx5_access_aso_opc_mod { ASO_OPC_MOD_IPSEC = 0x0, ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, @@ -2697,10 +3119,12 @@ struct mlx5_aso_mtr_dseg { #define ASO_DSEG_VALID_OFFSET 31 #define ASO_DSEG_BO_OFFSET 30 #define ASO_DSEG_SC_OFFSET 28 +#define ASO_DSEG_BBOG_OFFSET 27 +#define ASO_DSEG_MTR_MODE 24 #define ASO_DSEG_CBS_EXP_OFFSET 24 #define ASO_DSEG_CBS_MAN_OFFSET 16 -#define ASO_DSEG_CIR_EXP_MASK 0x1F -#define ASO_DSEG_CIR_EXP_OFFSET 8 +#define ASO_DSEG_XIR_EXP_MASK 0x1F +#define ASO_DSEG_XIR_EXP_OFFSET 8 #define ASO_DSEG_EBS_EXP_OFFSET 24 #define ASO_DSEG_EBS_MAN_OFFSET 16 #define ASO_DSEG_EXP_MASK 0x1F @@ -2894,6 +3318,28 @@ struct mlx5_ifc_create_qp_out_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_qpc_extension_bits { + u8 reserved_at_0[0x2]; + u8 mmo[0x1]; + u8 reserved_at_3[0x5fd]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_pas_list_bits { + u8 pas[0][0x40]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_extension_and_pas_list_bits { + struct mlx5_ifc_qpc_extension_bits qpc_data_extension; + u8 pas[0][0x40]; +}; + + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -2902,7 +3348,8 @@ struct mlx5_ifc_create_qp_in_bits { u8 uid[0x10]; u8 reserved_at_20[0x10]; u8 op_mod[0x10]; - u8 reserved_at_40[0x40]; + u8 qpc_ext[0x1]; + u8 reserved_at_41[0x3f]; u8 opt_param_mask[0x20]; u8 reserved_at_a0[0x20]; struct mlx5_ifc_qpc_bits qpc; @@ -2910,7 +3357,11 @@ struct mlx5_ifc_create_qp_in_bits { u8 wq_umem_id[0x20]; u8 wq_umem_valid[0x1]; u8 reserved_at_861[0x1f]; - u8 pas[0][0x40]; + union { + struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; + struct mlx5_ifc_qpc_extension_and_pas_list_bits + qpc_extension_and_pas_list; + }; }; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" @@ -3173,6 +3624,10 @@ enum { enum { MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, }; struct mlx5_ifc_register_mtutc_bits { @@ -3190,6 +3645,43 @@ struct mlx5_ifc_register_mtutc_bits { #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + struct mlx5_ifc_parse_graph_arc_bits { u8 start_inner_tunnel[0x1]; u8 reserved_at_1[0x7]; @@ -3252,17 +3744,20 @@ struct mlx5_ifc_parse_graph_flex_out_bits { }; struct regexp_params_field_select_bits { - u8 reserved_at_0[0x1e]; + u8 reserved_at_0[0x1d]; + u8 rof_mkey[0x1]; u8 stop_engine[0x1]; - u8 db_umem_id[0x1]; + u8 reserved_at_1f[0x1]; }; struct mlx5_ifc_regexp_params_bits { u8 reserved_at_0[0x1f]; u8 stop_engine[0x1]; - u8 db_umem_id[0x20]; - u8 db_umem_offset[0x40]; - u8 reserved_at_80[0x100]; + u8 reserved_at_20[0x60]; + u8 rof_mkey[0x20]; + u8 rof_size[0x20]; + u8 rof_mkey_va[0x40]; + u8 reserved_at_100[0x80]; }; struct mlx5_ifc_set_regexp_params_in_bits { @@ -3467,10 +3962,9 @@ enum { MLX5_FLOW_COLOR_UNDEFINED, }; -/* Maximum value of srTCM metering parameters. */ -#define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F)) -#define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF) -#define MLX5_SRTCM_EBS_MAX 0 +/* Maximum value of srTCM & trTCM metering parameters. */ +#define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) +#define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) /* The bits meter color use. */ #define MLX5_MTR_COLOR_BITS 8 @@ -3495,6 +3989,12 @@ enum mlx5_parse_graph_flow_match_sample_offset_mode { MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, }; +enum mlx5_parse_graph_flow_match_sample_tunnel_mode { + MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, + MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, + MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 +}; + /* Node index for an input / output arc of the flex parser graph. */ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_NULL = 0x0, @@ -3508,9 +4008,15 @@ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, + MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, + MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, }; +#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 +#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 +#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 + /** * Convert a user mark to flow mark. *