X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_prm.h;h=7896b94589c809d0dfb2bba7cbc55dbe443f05ea;hb=febcac7b46cdff5e3e12dd049ea191963cabbff7;hp=ec5f871c61f1d61281fbf359a28f5d6058f870e9;hpb=cbc4c13a255e3217f70357a9da82a3a6e14574a6;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ec5f871c61..7896b94589 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -393,7 +393,13 @@ struct mlx5_cqe { uint16_t hdr_type_etc; uint16_t vlan_info; uint8_t lro_num_seg; - uint8_t rsvd3[3]; + union { + uint8_t user_index_bytes[3]; + struct { + uint8_t user_index_hi; + uint16_t user_index_low; + } __rte_packed; + }; uint32_t flow_table_metadata; uint8_t rsvd4[4]; uint32_t byte_cnt; @@ -975,7 +981,14 @@ struct mlx5_ifc_fte_match_set_misc4_bits { u8 prog_sample_field_id_2[0x20]; u8 prog_sample_field_value_3[0x20]; u8 prog_sample_field_id_3[0x20]; - u8 reserved_at_100[0x100]; + u8 prog_sample_field_value_4[0x20]; + u8 prog_sample_field_id_4[0x20]; + u8 prog_sample_field_value_5[0x20]; + u8 prog_sample_field_id_5[0x20]; + u8 prog_sample_field_value_6[0x20]; + u8 prog_sample_field_id_6[0x20]; + u8 prog_sample_field_value_7[0x20]; + u8 prog_sample_field_id_7[0x20]; }; struct mlx5_ifc_fte_match_set_misc5_bits { @@ -1048,6 +1061,7 @@ enum { MLX5_CMD_OP_DEALLOC_PD = 0x801, MLX5_CMD_OP_ACCESS_REGISTER = 0x805, MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, + MLX5_CMD_OP_QUERY_LAG = 0x842, MLX5_CMD_OP_CREATE_TIR = 0x900, MLX5_CMD_OP_MODIFY_TIR = 0x901, MLX5_CMD_OP_CREATE_SQ = 0X904, @@ -1055,6 +1069,10 @@ enum { MLX5_CMD_OP_CREATE_RQ = 0x908, MLX5_CMD_OP_MODIFY_RQ = 0x909, MLX5_CMD_OP_QUERY_RQ = 0x90b, + MLX5_CMD_OP_CREATE_RMP = 0x90c, + MLX5_CMD_OP_MODIFY_RMP = 0x90d, + MLX5_CMD_OP_DESTROY_RMP = 0x90e, + MLX5_CMD_OP_QUERY_RMP = 0x90f, MLX5_CMD_OP_CREATE_TIS = 0x912, MLX5_CMD_OP_QUERY_TIS = 0x915, MLX5_CMD_OP_CREATE_RQT = 0x916, @@ -1244,6 +1262,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, + MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; @@ -1340,16 +1359,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 wqe_index_ignore_cap[0x1]; u8 dynamic_qp_allocation[0x1]; u8 log_max_qp[0x5]; - u8 regexp[0x1]; - u8 reserved_at_a1[0x3]; + u8 reserved_at_a0[0x4]; u8 regexp_num_of_engines[0x4]; u8 reserved_at_a8[0x1]; u8 reg_c_preserve[0x1]; u8 reserved_at_aa[0x1]; u8 log_max_srq[0x5]; - u8 reserved_at_b0[0x3]; - u8 regexp_log_crspace_size[0x5]; - u8 reserved_at_b8[0x3]; + u8 reserved_at_b0[0xb]; u8 scatter_fcs_w_decap_disable[0x1]; u8 reserved_at_bc[0x4]; u8 reserved_at_c0[0x8]; @@ -1505,9 +1521,11 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 uc[0x1]; u8 rc[0x1]; u8 uar_4k[0x1]; - u8 reserved_at_241[0x9]; + u8 reserved_at_241[0x8]; + u8 regexp_params[0x1]; u8 uar_sz[0x6]; - u8 reserved_at_250[0x8]; + u8 port_selection_cap[0x1]; + u8 reserved_at_251[0x7]; u8 log_pg_sz[0x8]; u8 bf[0x1]; u8 driver_version[0x1]; @@ -1521,7 +1539,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_wqe_sz_sq[0x10]; u8 reserved_at_2a0[0xc]; u8 regexp_mmo_sq[0x1]; - u8 reserved_at_2b0[0x3]; + u8 regexp_version[0x3]; u8 max_wqe_sz_rq[0x10]; u8 max_flow_counter_31_16[0x10]; u8 max_wqe_sz_sq_dc[0x10]; @@ -1553,7 +1571,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_378[0x3]; u8 log_max_tis[0x5]; u8 basic_cyclic_rcv_wqe[0x1]; - u8 reserved_at_381[0x2]; + u8 reserved_at_381[0x1]; + u8 mem_rq_rmp[0x1]; u8 log_max_rmp[0x5]; u8 reserved_at_388[0x3]; u8 log_max_rqt[0x5]; @@ -1757,6 +1776,27 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_1c0[0x620]; }; +/** + * PARSE_GRAPH_NODE Capabilities Field Descriptions + */ +struct mlx5_ifc_parse_graph_node_cap_bits { + u8 node_in[0x20]; + u8 node_out[0x20]; + u8 header_length_mode[0x10]; + u8 sample_offset_mode[0x10]; + u8 max_num_arc_in[0x08]; + u8 max_num_arc_out[0x08]; + u8 max_num_sample[0x08]; + u8 reserved_at_78[0x07]; + u8 sample_id_in_out[0x1]; + u8 max_base_header_length[0x10]; + u8 reserved_at_90[0x08]; + u8 max_sample_base_offset[0x08]; + u8 max_next_header_offset[0x10]; + u8 reserved_at_b0[0x08]; + u8 header_length_mask_width[0x08]; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -1851,9 +1891,14 @@ struct mlx5_ifc_flow_table_nic_cap_bits { ft_field_support_2_nic_receive; }; +/* + * HCA Capabilities 2 + */ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_0[0x80]; /* End of DW4. */ - u8 reserved_at_80[0xb]; + u8 reserved_at_80[0x3]; + u8 max_num_prog_sample_field[0x5]; + u8 reserved_at_88[0x3]; u8 log_max_num_reserved_qpn[0x5]; u8 reserved_at_90[0x3]; u8 log_reserved_qpn_granularity[0x5]; @@ -1974,6 +2019,14 @@ struct mlx5_ifc_query_nic_vport_context_in_bits { u8 reserved_at_68[0x18]; }; +/* + * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. + * Each TIS binds to one PF by setting lag_tx_port_affinity (>0). + * Once LAG enabled, we create multiple TISs and bind each one to + * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1. + */ +#define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \ + (index) % (num) + 1 : 0) struct mlx5_ifc_tisc_bits { u8 strict_lag_tx_port_affinity[0x1]; u8 reserved_at_1[0x3]; @@ -2007,6 +2060,39 @@ struct mlx5_ifc_query_tis_in_bits { u8 reserved_at_60[0x20]; }; +/* port_select_mode definition. */ +enum mlx5_lag_mode_type { + MLX5_LAG_MODE_TIS = 0, + MLX5_LAG_MODE_HASH = 1, +}; + +struct mlx5_ifc_lag_context_bits { + u8 fdb_selection_mode[0x1]; + u8 reserved_at_1[0x14]; + u8 port_select_mode[0x3]; + u8 reserved_at_18[0x5]; + u8 lag_state[0x3]; + u8 reserved_at_20[0x14]; + u8 tx_remap_affinity_2[0x4]; + u8 reserved_at_38[0x4]; + u8 tx_remap_affinity_1[0x4]; +}; + +struct mlx5_ifc_query_lag_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_query_lag_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + struct mlx5_ifc_lag_context_bits context; +}; + struct mlx5_ifc_alloc_transport_domain_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -2160,6 +2246,84 @@ struct mlx5_ifc_query_rq_in_bits { u8 reserved_at_60[0x20]; }; +enum { + MLX5_RMPC_STATE_RDY = 0x1, + MLX5_RMPC_STATE_ERR = 0x3, +}; + +struct mlx5_ifc_rmpc_bits { + u8 reserved_at_0[0x8]; + u8 state[0x4]; + u8 reserved_at_c[0x14]; + u8 basic_cyclic_rcv_wqe[0x1]; + u8 reserved_at_21[0x1f]; + u8 reserved_at_40[0x140]; + struct mlx5_ifc_wq_bits wq; +}; + +struct mlx5_ifc_query_rmp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0xc0]; + struct mlx5_ifc_rmpc_bits rmp_context; +}; + +struct mlx5_ifc_query_rmp_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x8]; + u8 rmpn[0x18]; + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_modify_rmp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_rmp_bitmask_bits { + u8 reserved_at_0[0x20]; + u8 reserved_at_20[0x1f]; + u8 lwm[0x1]; +}; + +struct mlx5_ifc_modify_rmp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 rmp_state[0x4]; + u8 reserved_at_44[0x4]; + u8 rmpn[0x18]; + u8 reserved_at_60[0x20]; + struct mlx5_ifc_rmp_bitmask_bits bitmask; + u8 reserved_at_c0[0x40]; + struct mlx5_ifc_rmpc_bits ctx; +}; + +struct mlx5_ifc_create_rmp_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x8]; + u8 rmpn[0x18]; + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_create_rmp_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0xc0]; + struct mlx5_ifc_rmpc_bits ctx; +}; + struct mlx5_ifc_create_tis_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -3243,6 +3407,28 @@ struct mlx5_ifc_create_qp_out_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_qpc_extension_bits { + u8 reserved_at_0[0x2]; + u8 mmo[0x1]; + u8 reserved_at_3[0x5fd]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_pas_list_bits { + u8 pas[0][0x40]; +}; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_qpc_extension_and_pas_list_bits { + struct mlx5_ifc_qpc_extension_bits qpc_data_extension; + u8 pas[0][0x40]; +}; + + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -3260,7 +3446,11 @@ struct mlx5_ifc_create_qp_in_bits { u8 wq_umem_id[0x20]; u8 wq_umem_valid[0x1]; u8 reserved_at_861[0x1f]; - u8 pas[0][0x40]; + union { + struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; + struct mlx5_ifc_qpc_extension_and_pas_list_bits + qpc_extension_and_pas_list; + }; }; #ifdef PEDANTIC #pragma GCC diagnostic error "-Wpedantic" @@ -3643,17 +3833,20 @@ struct mlx5_ifc_parse_graph_flex_out_bits { }; struct regexp_params_field_select_bits { - u8 reserved_at_0[0x1e]; + u8 reserved_at_0[0x1d]; + u8 rof_mkey[0x1]; u8 stop_engine[0x1]; - u8 db_umem_id[0x1]; + u8 reserved_at_1f[0x1]; }; struct mlx5_ifc_regexp_params_bits { u8 reserved_at_0[0x1f]; u8 stop_engine[0x1]; - u8 db_umem_id[0x20]; - u8 db_umem_offset[0x40]; - u8 reserved_at_80[0x100]; + u8 reserved_at_20[0x60]; + u8 rof_mkey[0x20]; + u8 rof_size[0x20]; + u8 rof_mkey_va[0x40]; + u8 reserved_at_100[0x80]; }; struct mlx5_ifc_set_regexp_params_in_bits { @@ -3885,6 +4078,12 @@ enum mlx5_parse_graph_flow_match_sample_offset_mode { MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, }; +enum mlx5_parse_graph_flow_match_sample_tunnel_mode { + MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, + MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, + MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 +}; + /* Node index for an input / output arc of the flex parser graph. */ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_NULL = 0x0, @@ -3898,9 +4097,15 @@ enum mlx5_parse_graph_arc_node_index { MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, + MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, + MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, }; +#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 +#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 +#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 + /** * Convert a user mark to flow mark. *