X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_prm.h;h=d361bcf90ef58a80b692a926d23f0882f9ee4199;hb=3b48087a8acd1348499d29cf504790db98d69b2c;hp=2f926637808f208ee1e10eef2e51bdac4c1e99cc;hpb=79a7e409a2f6d8ed1bc836b0456141860220225c;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2f92663780..d361bcf90e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -6,21 +6,12 @@ #ifndef RTE_PMD_MLX5_PRM_H_ #define RTE_PMD_MLX5_PRM_H_ -/* Verbs header. */ -/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ -#ifdef PEDANTIC -#pragma GCC diagnostic ignored "-Wpedantic" -#endif -#include -#ifdef PEDANTIC -#pragma GCC diagnostic error "-Wpedantic" -#endif - #include #include #include +#include #include "mlx5_autoconf.h" /* RSS hash key size. */ @@ -129,7 +120,7 @@ MLX5_WQE_DSEG_SIZE + \ MLX5_ESEG_MIN_INLINE_SIZE) -/* Missed in mlv5dv.h, should define here. */ +/* Missed in mlx5dv.h, should define here. */ #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW #define MLX5_OPCODE_ENHANCED_MPSW 0x29u #endif @@ -142,6 +133,10 @@ #define MLX5_OPCODE_WAIT 0x0fu #endif +#ifndef HAVE_MLX5_OPCODE_ACCESS_ASO +#define MLX5_OPCODE_ACCESS_ASO 0x2du +#endif + /* CQE value to inform that VLAN is stripped. */ #define MLX5_CQE_VLAN_STRIPPED (1u << 0) @@ -248,6 +243,9 @@ /* Default mark mask for metadata legacy mode. */ #define MLX5_FLOW_MARK_MASK 0xffffff +/* Byte length mask when mark is enable in miniCQE */ +#define MLX5_LEN_WITH_MARK_MASK 0xffffff00 + /* Maximum number of DS in WQE. Limited by 6-bit field. */ #define MLX5_DSEG_MAX 63 @@ -267,10 +265,10 @@ #define MLX5_MAX_LOG_RQ_SEGS 5u /* The alignment needed for WQ buffer. */ -#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE) +#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() /* The alignment needed for CQ buffer. */ -#define MLX5_CQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE) +#define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() /* Completion mode. */ enum mlx5_completion_mode { @@ -295,6 +293,15 @@ struct mlx5_wqe_cseg { uint32_t misc; } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); +/* + * WQE CSEG opcode field size is 32 bits, divided: + * Bits 31:24 OPC_MOD + * Bits 23:8 wqe_index + * Bits 7:0 OPCODE + */ +#define WQE_CSEG_OPC_MOD_OFFSET 24 +#define WQE_CSEG_WQE_INDEX_OFFSET 8 + /* Header of data segment. Minimal size Data Segment */ struct mlx5_wqe_dseg { uint32_t bcount; @@ -405,10 +412,144 @@ struct mlx5_cqe_ts { uint8_t op_own; }; +struct mlx5_wqe_rseg { + uint64_t raddr; + uint32_t rkey; + uint32_t reserved; +} __rte_packed; + +#define MLX5_UMRC_IF_OFFSET 31u +#define MLX5_UMRC_KO_OFFSET 16u +#define MLX5_UMRC_TO_BS_OFFSET 0u + +struct mlx5_wqe_umr_cseg { + uint32_t if_cf_toe_cq_res; + uint32_t ko_to_bs; + uint64_t mkey_mask; + uint32_t rsvd1[8]; +} __rte_packed; + +struct mlx5_wqe_mkey_cseg { + uint32_t fr_res_af_sf; + uint32_t qpn_mkey; + uint32_t reserved2; + uint32_t flags_pd; + uint64_t start_addr; + uint64_t len; + uint32_t bsf_octword_size; + uint32_t reserved3[4]; + uint32_t translations_octword_size; + uint32_t res4_lps; + uint32_t reserved; +} __rte_packed; + +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +struct mlx5_umr_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_umr_cseg ucseg; + struct mlx5_wqe_mkey_cseg mkc; + union { + struct mlx5_wqe_dseg kseg[0]; + struct mlx5_wqe_umr_bsf_seg bsf[0]; + }; +} __rte_packed; + +struct mlx5_rdma_write_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_rseg rseg; + struct mlx5_wqe_dseg dseg[0]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + +/* GGA */ /* MMO metadata segment */ -#define MLX5_OPCODE_MMO 0x2f -#define MLX5_OPC_MOD_MMO_REGEX 0x4 +#define MLX5_OPCODE_MMO 0x2fu +#define MLX5_OPC_MOD_MMO_REGEX 0x4u +#define MLX5_OPC_MOD_MMO_COMP 0x2u +#define MLX5_OPC_MOD_MMO_DECOMP 0x3u +#define MLX5_OPC_MOD_MMO_DMA 0x1u + +#define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u +#define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u +#define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u +#define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u +#define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) +#define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u +#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u +#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u struct mlx5_wqe_metadata_seg { uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ @@ -416,6 +557,30 @@ struct mlx5_wqe_metadata_seg { uint64_t addr; }; +struct mlx5_gga_wqe { + uint32_t opcode; + uint32_t sq_ds; + uint32_t flags; + uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ + uint32_t gga_ctrl2; + uint32_t opaque_lkey; + uint64_t opaque_vaddr; + struct mlx5_wqe_dseg gather; + struct mlx5_wqe_dseg scatter; +} __rte_packed; + +struct mlx5_gga_compress_opaque { + uint32_t syndrom; + uint32_t reserved0; + uint32_t scattered_length; + uint32_t gathered_length; + uint64_t scatter_crc; + uint64_t gather_crc; + uint32_t crc32; + uint32_t adler32; + uint8_t reserved1[216]; +} __rte_packed; + struct mlx5_ifc_regexp_mmo_control_bits { uint8_t reserved_at_31[0x2]; uint8_t le[0x1]; @@ -542,13 +707,14 @@ enum mlx5_modification_field { MLX5_MODI_IN_TCP_SEQ_NUM, MLX5_MODI_OUT_TCP_ACK_NUM, MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, + MLX5_MODI_GTP_TEID = 0x6E, }; /* Total number of metadata reg_c's. */ #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) enum modify_reg { - REG_NONE = 0, + REG_NON = 0, REG_A, REG_B, REG_C_0, @@ -587,13 +753,14 @@ struct mlx5_modification_cmd { }; }; +typedef uint64_t u64; typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) -#define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \ +#define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ (&(__mlx5_nullp(typ)->fld))) #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ (__mlx5_bit_off(typ, fld) & 0x1f)) @@ -617,7 +784,7 @@ typedef uint8_t u8; #define MLX5_SET(typ, p, fld, v) \ do { \ u32 _v = v; \ - *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ + *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ __mlx5_dw_off(typ, fld))) & \ (~__mlx5_dw_mask(typ, fld))) | \ @@ -628,15 +795,15 @@ typedef uint8_t u8; #define MLX5_SET64(typ, p, fld, v) \ do { \ MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ - *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \ + *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ rte_cpu_to_be_64(v); \ } while (0) #define MLX5_SET16(typ, p, fld, v) \ do { \ u16 _v = v; \ - *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ - rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \ + *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ + rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ __mlx5_16_off(typ, fld))) & \ (~__mlx5_16_mask(typ, fld))) | \ (((_v) & __mlx5_mask16(typ, fld)) << \ @@ -648,16 +815,17 @@ typedef uint8_t u8; __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ __mlx5_mask(typ, fld)) #define MLX5_GET(typ, p, fld) \ - ((rte_be_to_cpu_32(*((__be32 *)(p) +\ + ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ __mlx5_mask(typ, fld)) #define MLX5_GET16(typ, p, fld) \ - ((rte_be_to_cpu_16(*((__be16 *)(p) + \ + ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ __mlx5_mask16(typ, fld)) -#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \ +#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ __mlx5_64_off(typ, fld))) #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) +#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) struct mlx5_ifc_fte_match_set_misc_bits { u8 gre_c_present[0x1]; @@ -685,7 +853,8 @@ struct mlx5_ifc_fte_match_set_misc_bits { u8 vxlan_vni[0x18]; u8 reserved_at_b8[0x8]; u8 geneve_vni[0x18]; - u8 reserved_at_e4[0x7]; + u8 reserved_at_e4[0x6]; + u8 geneve_tlv_option_0_exist[0x1]; u8 geneve_oam[0x1]; u8 reserved_at_e0[0xc]; u8 outer_ipv6_flow_label[0x14]; @@ -731,7 +900,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { u8 tcp_flags[0x9]; u8 tcp_sport[0x10]; u8 tcp_dport[0x10]; - u8 reserved_at_c0[0x18]; + u8 reserved_at_c0[0x10]; + u8 ipv4_ihl[0x4]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 ipv4_checksum_ok[0x1]; + u8 l4_checksum_ok[0x1]; u8 ip_ttl_hoplimit[0x8]; u8 udp_sport[0x10]; u8 udp_dport[0x10]; @@ -780,11 +954,40 @@ struct mlx5_ifc_fte_match_set_misc3_bits { u8 icmp_code[0x8]; u8 icmpv6_type[0x8]; u8 icmpv6_code[0x8]; - u8 reserved_at_120[0x20]; + u8 geneve_tlv_option_0_data[0x20]; u8 gtpu_teid[0x20]; u8 gtpu_msg_type[0x08]; u8 gtpu_msg_flags[0x08]; - u8 reserved_at_170[0x90]; + u8 reserved_at_170[0x10]; + u8 gtpu_dw_2[0x20]; + u8 gtpu_first_ext_dw_0[0x20]; + u8 gtpu_dw_0[0x20]; + u8 reserved_at_240[0x20]; + +}; + +struct mlx5_ifc_fte_match_set_misc4_bits { + u8 prog_sample_field_value_0[0x20]; + u8 prog_sample_field_id_0[0x20]; + u8 prog_sample_field_value_1[0x20]; + u8 prog_sample_field_id_1[0x20]; + u8 prog_sample_field_value_2[0x20]; + u8 prog_sample_field_id_2[0x20]; + u8 prog_sample_field_value_3[0x20]; + u8 prog_sample_field_id_3[0x20]; + u8 reserved_at_100[0x100]; +}; + +struct mlx5_ifc_fte_match_set_misc5_bits { + u8 macsec_tag_0[0x20]; + u8 macsec_tag_1[0x20]; + u8 macsec_tag_2[0x20]; + u8 macsec_tag_3[0x20]; + u8 tunnel_header_0[0x20]; + u8 tunnel_header_1[0x20]; + u8 tunnel_header_2[0x20]; + u8 tunnel_header_3[0x20]; + u8 reserved[0x100]; }; /* Flow matcher. */ @@ -794,6 +997,21 @@ struct mlx5_ifc_fte_match_param_bits { struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; + struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; + struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; +/* + * Add reserved bit to match the struct size with the size defined in PRM. + * This extension is not required in Linux. + */ +#ifndef HAVE_INFINIBAND_VERBS_H + u8 reserved_0[0x200]; +#endif +}; + +struct mlx5_ifc_dest_format_struct_bits { + u8 destination_type[0x8]; + u8 destination_id[0x18]; + u8 reserved_0[0x20]; }; enum { @@ -801,7 +1019,9 @@ enum { MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, - MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT + MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, + MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, + MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, }; enum { @@ -822,12 +1042,19 @@ enum { MLX5_CMD_OP_SUSPEND_QP = 0x50F, MLX5_CMD_OP_RESUME_QP = 0x510, MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, + MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, + MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, + MLX5_CMD_OP_ALLOC_PD = 0x800, + MLX5_CMD_OP_DEALLOC_PD = 0x801, + MLX5_CMD_OP_ACCESS_REGISTER = 0x805, MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, MLX5_CMD_OP_CREATE_TIR = 0x900, + MLX5_CMD_OP_MODIFY_TIR = 0x901, MLX5_CMD_OP_CREATE_SQ = 0X904, MLX5_CMD_OP_MODIFY_SQ = 0X905, MLX5_CMD_OP_CREATE_RQ = 0x908, MLX5_CMD_OP_MODIFY_RQ = 0x909, + MLX5_CMD_OP_QUERY_RQ = 0x90b, MLX5_CMD_OP_CREATE_TIS = 0x912, MLX5_CMD_OP_QUERY_TIS = 0x915, MLX5_CMD_OP_CREATE_RQT = 0x916, @@ -841,6 +1068,7 @@ enum { MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, + MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, }; enum { @@ -861,178 +1089,186 @@ enum { */ #define MLX5_CNT_BATCH_OFFSET 0x800000 +/* The counter batch query requires ID align with 4. */ +#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 + /* Flow counters. */ struct mlx5_ifc_alloc_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 flow_counter_id[0x20]; - u8 reserved_at_60[0x20]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_alloc_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 flow_counter_id[0x20]; - u8 reserved_at_40[0x18]; - u8 flow_counter_bulk[0x8]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 flow_counter_id[0x20]; + u8 reserved_at_40[0x18]; + u8 flow_counter_bulk[0x8]; }; struct mlx5_ifc_dealloc_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 reserved_at_40[0x40]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; }; struct mlx5_ifc_dealloc_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 flow_counter_id[0x20]; - u8 reserved_at_60[0x20]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_traffic_counter_bits { - u8 packets[0x40]; - u8 octets[0x40]; + u8 packets[0x40]; + u8 octets[0x40]; }; struct mlx5_ifc_query_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 reserved_at_40[0x40]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; struct mlx5_ifc_traffic_counter_bits flow_statistics[]; }; struct mlx5_ifc_query_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 reserved_at_40[0x20]; - u8 mkey[0x20]; - u8 address[0x40]; - u8 clear[0x1]; - u8 dump_to_memory[0x1]; - u8 num_of_counters[0x1e]; - u8 flow_counter_id[0x20]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x20]; + u8 mkey[0x20]; + u8 address[0x40]; + u8 clear[0x1]; + u8 dump_to_memory[0x1]; + u8 num_of_counters[0x1e]; + u8 flow_counter_id[0x20]; }; #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u - struct mlx5_ifc_klm_bits { - u8 byte_count[0x20]; - u8 mkey[0x20]; - u8 address[0x40]; + u8 byte_count[0x20]; + u8 mkey[0x20]; + u8 address[0x40]; }; struct mlx5_ifc_mkc_bits { - u8 reserved_at_0[0x1]; - u8 free[0x1]; - u8 reserved_at_2[0x1]; - u8 access_mode_4_2[0x3]; - u8 reserved_at_6[0x7]; - u8 relaxed_ordering_write[0x1]; - u8 reserved_at_e[0x1]; - u8 small_fence_on_rdma_read_response[0x1]; - u8 umr_en[0x1]; - u8 a[0x1]; - u8 rw[0x1]; - u8 rr[0x1]; - u8 lw[0x1]; - u8 lr[0x1]; - u8 access_mode_1_0[0x2]; - u8 reserved_at_18[0x8]; - - u8 qpn[0x18]; - u8 mkey_7_0[0x8]; - - u8 reserved_at_40[0x20]; - - u8 length64[0x1]; - u8 bsf_en[0x1]; - u8 sync_umr[0x1]; - u8 reserved_at_63[0x2]; - u8 expected_sigerr_count[0x1]; - u8 reserved_at_66[0x1]; - u8 en_rinval[0x1]; - u8 pd[0x18]; - - u8 start_addr[0x40]; - - u8 len[0x40]; - - u8 bsf_octword_size[0x20]; - - u8 reserved_at_120[0x80]; - - u8 translations_octword_size[0x20]; - - u8 reserved_at_1c0[0x19]; - u8 relaxed_ordering_read[0x1]; - u8 reserved_at_1da[0x1]; - u8 log_page_size[0x5]; + u8 reserved_at_0[0x1]; + u8 free[0x1]; + u8 reserved_at_2[0x1]; + u8 access_mode_4_2[0x3]; + u8 reserved_at_6[0x7]; + u8 relaxed_ordering_write[0x1]; + u8 reserved_at_e[0x1]; + u8 small_fence_on_rdma_read_response[0x1]; + u8 umr_en[0x1]; + u8 a[0x1]; + u8 rw[0x1]; + u8 rr[0x1]; + u8 lw[0x1]; + u8 lr[0x1]; + u8 access_mode_1_0[0x2]; + u8 reserved_at_18[0x8]; + u8 qpn[0x18]; + u8 mkey_7_0[0x8]; + u8 reserved_at_40[0x20]; + u8 length64[0x1]; + u8 bsf_en[0x1]; + u8 sync_umr[0x1]; + u8 reserved_at_63[0x2]; + u8 expected_sigerr_count[0x1]; + u8 reserved_at_66[0x1]; + u8 en_rinval[0x1]; + u8 pd[0x18]; + u8 start_addr[0x40]; + u8 len[0x40]; + u8 bsf_octword_size[0x20]; + u8 reserved_at_120[0x80]; + u8 translations_octword_size[0x20]; + u8 reserved_at_1c0[0x19]; + u8 relaxed_ordering_read[0x1]; + u8 reserved_at_1da[0x1]; + u8 log_page_size[0x5]; + u8 reserved_at_1e0[0x3]; + u8 crypto_en[0x2]; + u8 reserved_at_1e5[0x1b]; +}; - u8 reserved_at_1e0[0x20]; +/* Range of values for MKEY context crypto_en field. */ +enum { + MLX5_MKEY_CRYPTO_DISABLED = 0x0, + MLX5_MKEY_CRYPTO_ENABLED = 0x1, }; struct mlx5_ifc_create_mkey_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - - u8 syndrome[0x20]; - - u8 reserved_at_40[0x8]; - u8 mkey_index[0x18]; - - u8 reserved_at_60[0x20]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x8]; + u8 mkey_index[0x18]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_create_mkey_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - - u8 reserved_at_40[0x20]; - - u8 pg_access[0x1]; - u8 reserved_at_61[0x1f]; - + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x20]; + u8 pg_access[0x1]; + u8 reserved_at_61[0x1f]; struct mlx5_ifc_mkc_bits memory_key_mkey_entry; - - u8 reserved_at_280[0x80]; - - u8 translations_octword_actual_size[0x20]; - - u8 mkey_umem_id[0x20]; - - u8 mkey_umem_offset[0x40]; - - u8 reserved_at_380[0x500]; - - u8 klm_pas_mtt[][0x20]; + u8 reserved_at_280[0x80]; + u8 translations_octword_actual_size[0x20]; + u8 mkey_umem_id[0x20]; + u8 mkey_umem_offset[0x40]; + u8 reserved_at_380[0x500]; + u8 klm_pas_mtt[][0x20]; }; enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, + MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, + MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, -}; - -enum { - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd), - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c), -}; + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, +}; + +#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) +#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) +#define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) +#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) +#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) +#define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) +#define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -1056,6 +1292,20 @@ enum { MLX5_INLINE_MODE_INNER_TCP_UDP, }; +/* The supported timestamp formats reported in HCA attributes. */ +enum { + MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, + MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, + MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, +}; + +/* The timestamp format attributes to configure queues (RQ/SQ/QP). */ +enum { + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, + MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, +}; + /* HCA bit masks indicating which Flex parser protocols are already enabled. */ #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) @@ -1068,10 +1318,22 @@ enum { #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) +/* The device steering logic format. */ +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 +#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 + struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_0[0x30]; u8 vhca_id[0x10]; - u8 reserved_at_40[0x40]; + u8 reserved_at_40[0x20]; + u8 reserved_at_60[0x3]; + u8 log_regexp_scatter_gather_size[0x5]; + u8 reserved_at_68[0x3]; + u8 log_dma_mmo_size[0x5]; + u8 reserved_at_70[0x3]; + u8 log_compress_mmo_size[0x5]; + u8 reserved_at_78[0x3]; + u8 log_decompress_mmo_size[0x5]; u8 log_max_srq_sz[0x8]; u8 log_max_qp_sz[0x8]; u8 reserved_at_90[0x9]; @@ -1081,11 +1343,15 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 regexp[0x1]; u8 reserved_at_a1[0x3]; u8 regexp_num_of_engines[0x4]; - u8 reserved_at_a8[0x3]; + u8 reserved_at_a8[0x1]; + u8 reg_c_preserve[0x1]; + u8 reserved_at_aa[0x1]; u8 log_max_srq[0x5]; u8 reserved_at_b0[0x3]; u8 regexp_log_crspace_size[0x5]; - u8 reserved_at_b8[0x8]; + u8 reserved_at_b8[0x3]; + u8 scatter_fcs_w_decap_disable[0x1]; + u8 reserved_at_bc[0x4]; u8 reserved_at_c0[0x8]; u8 log_max_cq_sz[0x8]; u8 reserved_at_d0[0xb]; @@ -1093,7 +1359,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_eq_sz[0x8]; u8 relaxed_ordering_write[0x1]; u8 relaxed_ordering_read[0x1]; - u8 log_max_mkey[0x6]; + u8 access_register_user[0x1]; + u8 log_max_mkey[0x5]; u8 reserved_at_f0[0x8]; u8 dump_fill_mkey[0x1]; u8 reserved_at_f9[0x3]; @@ -1116,7 +1383,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_ra_res_dc[0x6]; u8 reserved_at_140[0xa]; u8 log_max_ra_req_qp[0x6]; - u8 reserved_at_150[0xa]; + u8 rtr2rts_qp_counters_set_id[0x1]; + u8 rts2rts_udp_sport[0x1]; + u8 rts2rts_lag_tx_port_affinity[0x1]; + u8 dma_mmo[0x1]; + u8 compress_min_block_size[0x4]; + u8 compress[0x1]; + u8 decompress[0x1]; u8 log_max_ra_res_qp[0x6]; u8 end_pad[0x1]; u8 cc_query_allowed[0x1]; @@ -1315,8 +1588,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_3f8[0x3]; u8 log_max_current_uc_list[0x5]; u8 general_obj_types[0x40]; - u8 reserved_at_440[0x20]; - u8 reserved_at_460[0x10]; + u8 sq_ts_format[0x2]; + u8 rq_ts_format[0x2]; + u8 steering_format_version[0x4]; + u8 reserved_at_448[0x18]; + u8 reserved_at_460[0x8]; + u8 aes_xts[0x1]; + u8 crypto[0x1]; + u8 reserved_at_46a[0x6]; u8 max_num_eqs[0x10]; u8 reserved_at_480[0x3]; u8 log_max_l2_table[0x5]; @@ -1328,8 +1607,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_500[0x20]; u8 num_of_uars_per_page[0x20]; u8 flex_parser_protocols[0x20]; - u8 reserved_at_560[0x20]; - u8 reserved_at_580[0x3c]; + u8 max_geneve_tlv_options[0x8]; + u8 reserved_at_568[0x3]; + u8 max_geneve_tlv_option_data_len[0x5]; + u8 reserved_at_570[0x49]; + u8 mini_cqe_resp_l3_l4_tag[0x1]; + u8 mini_cqe_resp_flow_tag[0x1]; + u8 enhanced_cqe_compression[0x1]; u8 mini_cqe_resp_stride_index[0x1]; u8 cqe_128_always[0x1]; u8 cqe_compression_128[0x1]; @@ -1359,13 +1643,13 @@ struct mlx5_ifc_qos_cap_bits { u8 reserved_at_4[0x1]; u8 packet_pacing_burst_bound[0x1]; u8 packet_pacing_typical_size[0x1]; - u8 flow_meter_srtcm[0x1]; + u8 flow_meter_old[0x1]; u8 reserved_at_8[0x8]; u8 log_max_flow_meter[0x8]; u8 flow_meter_reg_id[0x8]; u8 wqe_rate_pp[0x1]; u8 reserved_at_25[0x7]; - u8 flow_meter_reg_share[0x1]; + u8 flow_meter[0x1]; u8 reserved_at_2e[0x17]; u8 packet_pacing_max_rate[0x20]; u8 packet_pacing_min_rate[0x20]; @@ -1376,7 +1660,15 @@ struct mlx5_ifc_qos_cap_bits { u8 reserved_at_c0[0x10]; u8 max_qos_para_vport[0x10]; u8 max_tsar_bw_share[0x20]; - u8 reserved_at_100[0x6e8]; + u8 nic_element_type[0x10]; + u8 nic_tsar_type[0x10]; + u8 reserved_at_120[0x3]; + u8 log_meter_aso_granularity[0x5]; + u8 reserved_at_128[0x3]; + u8 log_meter_aso_max_alloc[0x5]; + u8 reserved_at_130[0x3]; + u8 log_max_num_meter_aso[0x5]; + u8 reserved_at_138[0x6b0]; }; struct mlx5_ifc_per_protocol_networking_offload_caps_bits { @@ -1458,15 +1750,144 @@ struct mlx5_ifc_virtio_emulation_cap_bits { u8 reserved_at_1c0[0x620]; }; +struct mlx5_ifc_flow_table_prop_layout_bits { + u8 ft_support[0x1]; + u8 flow_tag[0x1]; + u8 flow_counter[0x1]; + u8 flow_modify_en[0x1]; + u8 modify_root[0x1]; + u8 identified_miss_table[0x1]; + u8 flow_table_modify[0x1]; + u8 reformat[0x1]; + u8 decap[0x1]; + u8 reset_root_to_default[0x1]; + u8 pop_vlan[0x1]; + u8 push_vlan[0x1]; + u8 fpga_vendor_acceleration[0x1]; + u8 pop_vlan_2[0x1]; + u8 push_vlan_2[0x1]; + u8 reformat_and_vlan_action[0x1]; + u8 modify_and_vlan_action[0x1]; + u8 sw_owner[0x1]; + u8 reformat_l3_tunnel_to_l2[0x1]; + u8 reformat_l2_to_l3_tunnel[0x1]; + u8 reformat_and_modify_action[0x1]; + u8 reserved_at_15[0x9]; + u8 sw_owner_v2[0x1]; + u8 reserved_at_1f[0x1]; + u8 reserved_at_20[0x2]; + u8 log_max_ft_size[0x6]; + u8 log_max_modify_header_context[0x8]; + u8 max_modify_header_actions[0x8]; + u8 max_ft_level[0x8]; + u8 reserved_at_40[0x8]; + u8 log_max_ft_sampler_num[8]; + u8 metadata_reg_b_width[0x8]; + u8 metadata_reg_a_width[0x8]; + u8 reserved_at_60[0x18]; + u8 log_max_ft_num[0x8]; + u8 reserved_at_80[0x10]; + u8 log_max_flow_counter[0x8]; + u8 log_max_destination[0x8]; + u8 reserved_at_a0[0x18]; + u8 log_max_flow[0x8]; + u8 reserved_at_c0[0x140]; +}; + +struct mlx5_ifc_roce_caps_bits { + u8 reserved_0[0x1e]; + u8 qp_ts_format[0x2]; + u8 reserved_at_20[0x7e0]; +}; + +/* + * Table 1872 - Flow Table Fields Supported 2 Format + */ +struct mlx5_ifc_ft_fields_support_2_bits { + u8 reserved_at_0[0xf]; + u8 tunnel_header_2_3[0x1]; + u8 tunnel_header_0_1[0x1]; + u8 macsec_syndrome[0x1]; + u8 macsec_tag[0x1]; + u8 outer_lrh_sl[0x1]; + u8 inner_ipv4_ihl[0x1]; + u8 outer_ipv4_ihl[0x1]; + u8 psp_syndrome[0x1]; + u8 inner_l3_ok[0x1]; + u8 inner_l4_ok[0x1]; + u8 outer_l3_ok[0x1]; + u8 outer_l4_ok[0x1]; + u8 psp_header[0x1]; + u8 inner_ipv4_checksum_ok[0x1]; + u8 inner_l4_checksum_ok[0x1]; + u8 outer_ipv4_checksum_ok[0x1]; + u8 outer_l4_checksum_ok[0x1]; + u8 reserved_at_20[0x60]; +}; + +struct mlx5_ifc_flow_table_nic_cap_bits { + u8 reserved_at_0[0x200]; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive_rdma; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive_sniffer; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit_rdma; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_transmit_sniffer; + u8 reserved_at_e00[0x600]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_nic_receive; +}; + +struct mlx5_ifc_cmd_hca_cap_2_bits { + u8 reserved_at_0[0x80]; /* End of DW4. */ + u8 reserved_at_80[0xb]; + u8 log_max_num_reserved_qpn[0x5]; + u8 reserved_at_90[0x3]; + u8 log_reserved_qpn_granularity[0x5]; + u8 reserved_at_98[0x3]; + u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ + u8 max_reformat_insert_size[0x8]; + u8 max_reformat_insert_offset[0x8]; + u8 max_reformat_remove_size[0x8]; + u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ + u8 aso_conntrack_reg_id[0x8]; + u8 reserved_at_c8[0x3]; + u8 log_conn_track_granularity[0x5]; + u8 reserved_at_d0[0x3]; + u8 log_conn_track_max_alloc[0x5]; + u8 reserved_at_d8[0x3]; + u8 log_max_conn_track_offload[0x5]; + u8 reserved_at_e0[0x20]; /* End of DW7. */ + u8 reserved_at_100[0x700]; +}; + union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; struct mlx5_ifc_qos_cap_bits qos_cap; struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; + struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; + struct mlx5_ifc_roce_caps_bits roce_caps; u8 reserved_at_0[0x8000]; }; +struct mlx5_ifc_set_action_in_bits { + u8 action_type[0x4]; + u8 field[0xc]; + u8 reserved_at_10[0x3]; + u8 offset[0x5]; + u8 reserved_at_18[0x3]; + u8 length[0x5]; + u8 data[0x20]; +}; + struct mlx5_ifc_query_hca_cap_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -1670,7 +2091,9 @@ struct mlx5_ifc_rqc_bits { u8 reserved_at_c[0x1]; u8 flush_in_error_en[0x1]; u8 hairpin[0x1]; - u8 reserved_at_f[0x11]; + u8 reserved_at_f[0xB]; + u8 ts_format[0x02]; + u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; u8 user_index[0x18]; u8 reserved_at_40[0x8]; @@ -1712,6 +2135,24 @@ struct mlx5_ifc_modify_rq_out_bits { u8 reserved_at_40[0x40]; }; +struct mlx5_ifc_query_rq_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0xc0]; + struct mlx5_ifc_rqc_bits rq_context; +}; + +struct mlx5_ifc_query_rq_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x8]; + u8 rqn[0x18]; + u8 reserved_at_60[0x20]; +}; + struct mlx5_ifc_create_tis_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -1846,6 +2287,34 @@ struct mlx5_ifc_create_tir_in_bits { struct mlx5_ifc_tirc_bits ctx; }; +enum { + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, + /* bit 3 - tunneled_offload_en modify not supported. */ + MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, +}; + +struct mlx5_ifc_modify_tir_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_modify_tir_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x8]; + u8 tirn[0x18]; + u8 reserved_at_60[0x20]; + u8 modify_bitmask[0x40]; + u8 reserved_at_c0[0x40]; + struct mlx5_ifc_tirc_bits ctx; +}; + enum { MLX5_INLINE_Q_TYPE_RQ = 0x0, MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, @@ -1930,7 +2399,9 @@ struct mlx5_ifc_sqc_bits { u8 hairpin[0x1]; u8 non_wire[0x1]; u8 static_sq_wq[0x1]; - u8 reserved_at_11[0xf]; + u8 reserved_at_11[0x9]; + u8 ts_format[0x02]; + u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; u8 user_index[0x18]; u8 reserved_at_40[0x8]; @@ -2007,27 +2478,36 @@ enum { }; struct mlx5_ifc_flow_meter_parameters_bits { - u8 valid[0x1]; // 00h - u8 bucket_overflow[0x1]; - u8 start_color[0x2]; - u8 both_buckets_on_green[0x1]; - u8 meter_mode[0x2]; - u8 reserved_at_1[0x19]; - u8 reserved_at_2[0x20]; //04h - u8 reserved_at_3[0x3]; - u8 cbs_exponent[0x5]; // 08h - u8 cbs_mantissa[0x8]; - u8 reserved_at_4[0x3]; - u8 cir_exponent[0x5]; - u8 cir_mantissa[0x8]; - u8 reserved_at_5[0x20]; // 0Ch - u8 reserved_at_6[0x3]; - u8 ebs_exponent[0x5]; // 10h - u8 ebs_mantissa[0x8]; - u8 reserved_at_7[0x3]; - u8 eir_exponent[0x5]; - u8 eir_mantissa[0x8]; - u8 reserved_at_8[0x60]; // 14h-1Ch + u8 valid[0x1]; + u8 bucket_overflow[0x1]; + u8 start_color[0x2]; + u8 both_buckets_on_green[0x1]; + u8 meter_mode[0x2]; + u8 reserved_at_1[0x19]; + u8 reserved_at_2[0x20]; + u8 reserved_at_3[0x3]; + u8 cbs_exponent[0x5]; + u8 cbs_mantissa[0x8]; + u8 reserved_at_4[0x3]; + u8 cir_exponent[0x5]; + u8 cir_mantissa[0x8]; + u8 reserved_at_5[0x20]; + u8 reserved_at_6[0x3]; + u8 ebs_exponent[0x5]; + u8 ebs_mantissa[0x8]; + u8 reserved_at_7[0x3]; + u8 eir_exponent[0x5]; + u8 eir_mantissa[0x8]; + u8 reserved_at_8[0x60]; +}; +#define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) +#define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 + +enum { + MLX5_METER_MODE_IP_LEN = 0x0, + MLX5_METER_MODE_L2_LEN = 0x1, + MLX5_METER_MODE_L2_IPG_LEN = 0x2, + MLX5_METER_MODE_PKT = 0x3, }; enum { @@ -2050,11 +2530,14 @@ struct mlx5_ifc_cqc_bits { u8 cqe_comp_en[0x1]; u8 mini_cqe_res_format[0x2]; u8 st[0x4]; - u8 reserved_at_18[0x8]; + u8 reserved_at_18[0x1]; + u8 cqe_comp_layout[0x7]; u8 dbr_umem_id[0x20]; u8 reserved_at_40[0x14]; u8 page_offset[0x6]; - u8 reserved_at_5a[0x6]; + u8 reserved_at_5a[0x2]; + u8 mini_cqe_res_format_ext[0x2]; + u8 cq_timestamp_format[0x2]; u8 reserved_at_60[0x3]; u8 log_cq_size[0x5]; u8 uar_page[0x18]; @@ -2081,6 +2564,49 @@ struct mlx5_ifc_cqc_bits { u8 dbr_addr[0x40]; }; +struct mlx5_ifc_health_buffer_bits { + u8 reserved_0[0x100]; + u8 assert_existptr[0x20]; + u8 assert_callra[0x20]; + u8 reserved_1[0x40]; + u8 fw_version[0x20]; + u8 hw_id[0x20]; + u8 reserved_2[0x20]; + u8 irisc_index[0x8]; + u8 synd[0x8]; + u8 ext_synd[0x10]; +}; + +struct mlx5_ifc_initial_seg_bits { + u8 fw_rev_minor[0x10]; + u8 fw_rev_major[0x10]; + u8 cmd_interface_rev[0x10]; + u8 fw_rev_subminor[0x10]; + u8 reserved_0[0x40]; + u8 cmdq_phy_addr_63_32[0x20]; + u8 cmdq_phy_addr_31_12[0x14]; + u8 reserved_1[0x2]; + u8 nic_interface[0x2]; + u8 log_cmdq_size[0x4]; + u8 log_cmdq_stride[0x4]; + u8 command_doorbell_vector[0x20]; + u8 reserved_2[0xf00]; + u8 initializing[0x1]; + u8 nic_interface_supported[0x7]; + u8 reserved_4[0x18]; + struct mlx5_ifc_health_buffer_bits health_buffer; + u8 no_dram_nic_offset[0x20]; + u8 reserved_5[0x6de0]; + u8 internal_timer_h[0x20]; + u8 internal_timer_l[0x20]; + u8 reserved_6[0x20]; + u8 reserved_7[0x1f]; + u8 clear_int[0x1]; + u8 health_syndrome[0x8]; + u8 health_counter[0x18]; + u8 reserved_8[0x17fc0]; +}; + struct mlx5_ifc_create_cq_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; @@ -2106,8 +2632,17 @@ struct mlx5_ifc_create_cq_in_bits { }; enum { + MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, + MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, + MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, + MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, + MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, + MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, + MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, + MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, + MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, }; struct mlx5_ifc_general_obj_in_cmd_hdr_bits { @@ -2115,7 +2650,9 @@ struct mlx5_ifc_general_obj_in_cmd_hdr_bits { u8 reserved_at_10[0x20]; u8 obj_type[0x10]; u8 obj_id[0x20]; - u8 reserved_at_60[0x20]; + u8 reserved_at_60[0x3]; + u8 log_obj_range[0x5]; + u8 reserved_at_58[0x18]; }; struct mlx5_ifc_general_obj_out_cmd_hdr_bits { @@ -2138,6 +2675,17 @@ struct mlx5_ifc_virtio_q_counters_bits { u8 reserved_at_180[0x50]; }; +struct mlx5_ifc_geneve_tlv_option_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x18]; + u8 geneve_option_fte_index[0x8]; + u8 option_class[0x10]; + u8 option_type[0x8]; + u8 reserved_at_78[0x3]; + u8 option_data_length[0x5]; + u8 reserved_at_80[0x180]; +}; + struct mlx5_ifc_create_virtio_q_counters_in_bits { struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; @@ -2147,6 +2695,99 @@ struct mlx5_ifc_query_virtio_q_counters_out_bits { struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; }; + +struct mlx5_ifc_create_geneve_tlv_option_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; +}; + +enum { + MLX5_CRYPTO_KEY_SIZE_128b = 0x0, + MLX5_CRYPTO_KEY_SIZE_256b = 0x1, +}; + +enum { + MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, + MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, + MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, + MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, + MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, + MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, +}; + +struct mlx5_ifc_dek_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0xc]; + u8 key_size[0x4]; + u8 has_keytag[0x1]; + u8 reserved_at_59[0x3]; + u8 key_purpose[0x4]; + u8 reserved_at_60[0x8]; + u8 pd[0x18]; + u8 reserved_at_80[0x100]; + u8 opaque[0x40]; + u8 reserved_at_1c0[0x40]; + u8 key[0x400]; + u8 reserved_at_600[0x200]; +}; + +struct mlx5_ifc_create_dek_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_dek_bits dek; +}; + +struct mlx5_ifc_import_kek_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0xc]; + u8 key_size[0x4]; + u8 reserved_at_58[0x1a8]; + u8 key[0x400]; + u8 reserved_at_600[0x200]; +}; + +struct mlx5_ifc_create_import_kek_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_import_kek_bits import_kek; +}; + +enum { + MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, + MLX5_CREDENTIAL_ROLE_USER = 0x1, +}; + +struct mlx5_ifc_credential_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0x10]; + u8 credential_role[0x8]; + u8 reserved_at_60[0x1a0]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_credential_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_credential_bits credential; +}; + +struct mlx5_ifc_crypto_login_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x48]; + u8 credential_pointer[0x18]; + u8 reserved_at_a0[0x8]; + u8 session_import_kek_ptr[0x18]; + u8 reserved_at_c0[0x140]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_crypto_login_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_crypto_login_bits crypto_login; +}; + enum { MLX5_VIRTQ_STATE_INIT = 0, MLX5_VIRTQ_STATE_RDY = 1, @@ -2177,7 +2818,8 @@ struct mlx5_ifc_virtio_q_bits { u8 used_addr[0x40]; u8 available_addr[0x40]; u8 virtio_q_mkey[0x20]; - u8 reserved_at_160[0x20]; + u8 reserved_at_160[0x18]; + u8 error_type[0x8]; u8 umem_1_id[0x20]; u8 umem_1_size[0x20]; u8 umem_1_offset[0x40]; @@ -2190,7 +2832,11 @@ struct mlx5_ifc_virtio_q_bits { u8 counter_set_id[0x20]; u8 reserved_at_320[0x8]; u8 pd[0x18]; - u8 reserved_at_340[0xc0]; + u8 reserved_at_340[0x2]; + u8 queue_period_mode[0x2]; + u8 queue_period_us[0xc]; + u8 queue_max_count[0x10]; + u8 reserved_at_360[0xa0]; }; struct mlx5_ifc_virtio_net_q_bits { @@ -2205,7 +2851,7 @@ struct mlx5_ifc_virtio_net_q_bits { u8 vhost_log_page[0x5]; u8 reserved_at_90[0xc]; u8 state[0x4]; - u8 error_type[0x8]; + u8 reserved_at_a0[0x8]; u8 tisn_or_qpn[0x18]; u8 dirty_bitmap_mkey[0x20]; u8 dirty_bitmap_size[0x20]; @@ -2226,6 +2872,205 @@ struct mlx5_ifc_query_virtq_out_bits { struct mlx5_ifc_virtio_net_q_bits virtq; }; +struct mlx5_ifc_flow_hit_aso_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x48]; + u8 access_pd[0x18]; + u8 reserved_at_a0[0x160]; + u8 flag[0x200]; +}; + +struct mlx5_ifc_create_flow_hit_aso_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; +}; + +struct mlx5_ifc_flow_meter_aso_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x48]; + u8 access_pd[0x18]; + u8 reserved_at_a0[0x160]; + u8 parameters[0x200]; +}; + +struct mlx5_ifc_create_flow_meter_aso_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; +}; + +struct mlx5_ifc_tcp_window_params_bits { + u8 max_ack[0x20]; + u8 max_win[0x20]; + u8 reply_end[0x20]; + u8 sent_end[0x20]; +}; + +struct mlx5_ifc_conn_track_aso_bits { + struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ + struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ + u8 last_end[0x20]; /* End of DW8. */ + u8 last_ack[0x20]; /* End of DW9. */ + u8 last_seq[0x20]; /* End of DW10. */ + u8 last_win[0x10]; + u8 reserved_at_170[0xa]; + u8 last_dir[0x1]; + u8 last_index[0x5]; /* End of DW11. */ + u8 reserved_at_180[0x40]; /* End of DW13. */ + u8 reply_direction_tcp_scale[0x4]; + u8 reply_direction_tcp_close_initiated[0x1]; + u8 reply_direction_tcp_liberal_enabled[0x1]; + u8 reply_direction_tcp_data_unacked[0x1]; + u8 reply_direction_tcp_max_ack[0x1]; + u8 reserved_at_1c8[0x8]; + u8 original_direction_tcp_scale[0x4]; + u8 original_direction_tcp_close_initiated[0x1]; + u8 original_direction_tcp_liberal_enabled[0x1]; + u8 original_direction_tcp_data_unacked[0x1]; + u8 original_direction_tcp_max_ack[0x1]; + u8 reserved_at_1d8[0x8]; /* End of DW14. */ + u8 valid[0x1]; + u8 state[0x3]; + u8 freeze_track[0x1]; + u8 reserved_at_1e5[0xb]; + u8 reserved_at_1f0[0x1]; + u8 connection_assured[0x1]; + u8 sack_permitted[0x1]; + u8 challenged_acked[0x1]; + u8 heartbeat[0x1]; + u8 max_ack_window[0x3]; + u8 reserved_at_1f8[0x1]; + u8 retransmission_counter[0x3]; + u8 retranmission_limit_exceeded[0x1]; + u8 retranmission_limit[0x3]; /* End of DW15. */ +}; + +struct mlx5_ifc_conn_track_offload_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x40]; + u8 reserved_at_80[0x8]; + u8 conn_track_aso_access_pd[0x18]; + u8 reserved_at_a0[0x160]; + struct mlx5_ifc_conn_track_aso_bits conn_track_aso; +}; + +struct mlx5_ifc_create_conn_track_aso_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_conn_track_offload_bits conn_track_offload; +}; + +enum mlx5_access_aso_opc_mod { + ASO_OPC_MOD_IPSEC = 0x0, + ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, + ASO_OPC_MOD_POLICER = 0x2, + ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, + ASO_OPC_MOD_FLOW_HIT = 0x4, +}; + +#define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 + +enum mlx5_aso_data_mask_mode { + BITWISE_64BIT = 0x0, + BYTEWISE_64BYTE = 0x1, + CALCULATED_64BYTE = 0x2, +}; + +#define ASO_CSEG_COND_0_OPER_OFFSET 20 +#define ASO_CSEG_COND_1_OPER_OFFSET 16 + +enum mlx5_aso_pre_cond_op { + ASO_OP_ALWAYS_FALSE = 0x0, + ASO_OP_ALWAYS_TRUE = 0x1, + ASO_OP_EQUAL = 0x2, + ASO_OP_NOT_EQUAL = 0x3, + ASO_OP_GREATER_OR_EQUAL = 0x4, + ASO_OP_LESSER_OR_EQUAL = 0x5, + ASO_OP_LESSER = 0x6, + ASO_OP_GREATER = 0x7, + ASO_OP_CYCLIC_GREATER = 0x8, + ASO_OP_CYCLIC_LESSER = 0x9, +}; + +#define ASO_CSEG_COND_OPER_OFFSET 6 + +enum mlx5_aso_op { + ASO_OPER_LOGICAL_AND = 0x0, + ASO_OPER_LOGICAL_OR = 0x1, +}; + +/* ASO WQE CTRL segment. */ +struct mlx5_aso_cseg { + uint32_t va_h; + uint32_t va_l_r; + uint32_t lkey; + uint32_t operand_masks; + uint32_t condition_0_data; + uint32_t condition_0_mask; + uint32_t condition_1_data; + uint32_t condition_1_mask; + uint64_t bitwise_data; + uint64_t data_mask; +} __rte_packed; + +/* A meter data segment - 2 per ASO WQE. */ +struct mlx5_aso_mtr_dseg { + uint32_t v_bo_sc_bbog_mm; + /* + * bit 31: valid, 30: bucket overflow, 28-29: start color, + * 27: both buckets on green, 24-25: meter mode. + */ + uint32_t reserved; + uint32_t cbs_cir; + /* + * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, + * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. + */ + uint32_t c_tokens; + uint32_t ebs_eir; + /* + * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, + * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. + */ + uint32_t e_tokens; + uint64_t timestamp; +} __rte_packed; + +#define ASO_DSEG_VALID_OFFSET 31 +#define ASO_DSEG_BO_OFFSET 30 +#define ASO_DSEG_SC_OFFSET 28 +#define ASO_DSEG_BBOG_OFFSET 27 +#define ASO_DSEG_MTR_MODE 24 +#define ASO_DSEG_CBS_EXP_OFFSET 24 +#define ASO_DSEG_CBS_MAN_OFFSET 16 +#define ASO_DSEG_XIR_EXP_MASK 0x1F +#define ASO_DSEG_XIR_EXP_OFFSET 8 +#define ASO_DSEG_EBS_EXP_OFFSET 24 +#define ASO_DSEG_EBS_MAN_OFFSET 16 +#define ASO_DSEG_EXP_MASK 0x1F +#define ASO_DSEG_MAN_MASK 0xFF + +#define MLX5_ASO_WQE_DSEG_SIZE 0x40 +#define MLX5_ASO_METERS_PER_WQE 2 +#define MLX5_ASO_MTRS_PER_POOL 128 + +/* ASO WQE data segment. */ +struct mlx5_aso_dseg { + union { + uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; + struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; + }; +} __rte_packed; + +/* ASO WQE. */ +struct mlx5_aso_wqe { + struct mlx5_wqe_cseg general_cseg; + struct mlx5_aso_cseg aso_cseg; + struct mlx5_aso_dseg aso_dseg; +} __rte_packed; + +enum { + MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, +}; + enum { MLX5_QP_ST_RC = 0x0, }; @@ -2302,7 +3147,9 @@ struct mlx5_ifc_qpc_bits { u8 log_rq_stride[0x3]; u8 no_sq[0x1]; u8 log_sq_size[0x4]; - u8 reserved_at_55[0x6]; + u8 reserved_at_55[0x3]; + u8 ts_format[0x2]; + u8 reserved_at_5a[0x1]; u8 rlky[0x1]; u8 ulp_stateless_offload_mode[0x4]; u8 counter_set_id[0x8]; @@ -2558,6 +3405,40 @@ struct mlx5_ifc_init2init_qp_in_bits { u8 reserved_at_800[0x80]; }; +struct mlx5_ifc_dealloc_pd_out_bits { + u8 status[0x8]; + u8 reserved_0[0x18]; + u8 syndrome[0x20]; + u8 reserved_1[0x40]; +}; + +struct mlx5_ifc_dealloc_pd_in_bits { + u8 opcode[0x10]; + u8 reserved_0[0x10]; + u8 reserved_1[0x10]; + u8 op_mod[0x10]; + u8 reserved_2[0x8]; + u8 pd[0x18]; + u8 reserved_3[0x20]; +}; + +struct mlx5_ifc_alloc_pd_out_bits { + u8 status[0x8]; + u8 reserved_0[0x18]; + u8 syndrome[0x20]; + u8 reserved_1[0x8]; + u8 pd[0x18]; + u8 reserved_2[0x20]; +}; + +struct mlx5_ifc_alloc_pd_in_bits { + u8 opcode[0x10]; + u8 reserved_0[0x10]; + u8 reserved_1[0x10]; + u8 op_mod[0x10]; + u8 reserved_2[0x40]; +}; + #ifdef PEDANTIC #pragma GCC diagnostic ignored "-Wpedantic" #endif @@ -2600,6 +3481,159 @@ struct mlx5_ifc_set_pp_rate_limit_context_bits { u8 reserved_at_60[0x120]; }; +#define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif +struct mlx5_ifc_access_register_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; + u8 register_data[0][0x20]; +}; + +struct mlx5_ifc_access_register_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x10]; + u8 register_id[0x10]; + u8 argument[0x20]; + u8 register_data[0][0x20]; +}; +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + +enum { + MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, + MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, +}; + +enum { + MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, +}; + +struct mlx5_ifc_register_mtutc_bits { + u8 time_stamp_mode[0x2]; + u8 time_stamp_state[0x2]; + u8 reserved_at_4[0x18]; + u8 operation[0x4]; + u8 freq_adjustment[0x20]; + u8 reserved_at_40[0x40]; + u8 utc_sec[0x20]; + u8 utc_nsec[0x20]; + u8 time_adjustment[0x20]; +}; + +#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 +#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 + +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + +struct mlx5_ifc_parse_graph_arc_bits { + u8 start_inner_tunnel[0x1]; + u8 reserved_at_1[0x7]; + u8 arc_parse_graph_node[0x8]; + u8 compare_condition_value[0x10]; + u8 parse_graph_node_handle[0x20]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_parse_graph_flow_match_sample_bits { + u8 flow_match_sample_en[0x1]; + u8 reserved_at_1[0x3]; + u8 flow_match_sample_offset_mode[0x4]; + u8 reserved_at_5[0x8]; + u8 flow_match_sample_field_offset[0x10]; + u8 reserved_at_32[0x4]; + u8 flow_match_sample_field_offset_shift[0x4]; + u8 flow_match_sample_field_base_offset[0x8]; + u8 reserved_at_48[0xd]; + u8 flow_match_sample_tunnel_mode[0x3]; + u8 flow_match_sample_field_offset_mask[0x20]; + u8 flow_match_sample_field_id[0x20]; +}; + +struct mlx5_ifc_parse_graph_flex_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_64[0x20]; + u8 header_length_base_value[0x10]; + u8 reserved_at_112[0x4]; + u8 header_length_field_shift[0x4]; + u8 reserved_at_120[0x4]; + u8 header_length_mode[0x4]; + u8 header_length_field_offset[0x10]; + u8 next_header_field_offset[0x10]; + u8 reserved_at_160[0x1b]; + u8 next_header_field_size[0x5]; + u8 header_length_field_mask[0x20]; + u8 reserved_at_224[0x20]; + struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; + struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; + struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; +}; + +struct mlx5_ifc_create_flex_parser_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_parse_graph_flex_bits flex; +}; + +struct mlx5_ifc_create_flex_parser_out_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_parse_graph_flex_bits flex; +}; + +struct mlx5_ifc_parse_graph_flex_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; + struct mlx5_ifc_parse_graph_flex_bits capability; +}; + struct regexp_params_field_select_bits { u8 reserved_at_0[0x1e]; u8 stop_engine[0x1]; @@ -2659,7 +3693,7 @@ struct mlx5_ifc_set_regexp_register_in_bits { u8 engine_id[0x8]; u8 register_address[0x20]; u8 register_data[0x20]; - u8 reserved[0x40]; + u8 reserved[0x60]; }; struct mlx5_ifc_set_regexp_register_out_bits { @@ -2687,6 +3721,85 @@ struct mlx5_ifc_query_regexp_register_out_bits { u8 register_data[0x20]; }; +/* Queue counters. */ +struct mlx5_ifc_alloc_q_counter_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x18]; + u8 counter_set_id[0x8]; + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_alloc_q_counter_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_query_q_counter_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; + u8 rx_write_requests[0x20]; + u8 reserved_at_a0[0x20]; + u8 rx_read_requests[0x20]; + u8 reserved_at_e0[0x20]; + u8 rx_atomic_requests[0x20]; + u8 reserved_at_120[0x20]; + u8 rx_dct_connect[0x20]; + u8 reserved_at_160[0x20]; + u8 out_of_buffer[0x20]; + u8 reserved_at_1a0[0x20]; + u8 out_of_sequence[0x20]; + u8 reserved_at_1e0[0x20]; + u8 duplicate_request[0x20]; + u8 reserved_at_220[0x20]; + u8 rnr_nak_retry_err[0x20]; + u8 reserved_at_260[0x20]; + u8 packet_seq_err[0x20]; + u8 reserved_at_2a0[0x20]; + u8 implied_nak_seq_err[0x20]; + u8 reserved_at_2e0[0x20]; + u8 local_ack_timeout_err[0x20]; + u8 reserved_at_320[0xa0]; + u8 resp_local_length_error[0x20]; + u8 req_local_length_error[0x20]; + u8 resp_local_qp_error[0x20]; + u8 local_operation_error[0x20]; + u8 resp_local_protection[0x20]; + u8 req_local_protection[0x20]; + u8 resp_cqe_error[0x20]; + u8 req_cqe_error[0x20]; + u8 req_mw_binding[0x20]; + u8 req_bad_response[0x20]; + u8 req_remote_invalid_request[0x20]; + u8 resp_remote_invalid_request[0x20]; + u8 req_remote_access_errors[0x20]; + u8 resp_remote_access_errors[0x20]; + u8 req_remote_operation_errors[0x20]; + u8 req_transport_retries_exceeded[0x20]; + u8 cq_overflow[0x20]; + u8 resp_cqe_flush_error[0x20]; + u8 req_cqe_flush_error[0x20]; + u8 reserved_at_620[0x1e0]; +}; + +struct mlx5_ifc_query_q_counter_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x80]; + u8 clear[0x1]; + u8 reserved_at_c1[0x1f]; + u8 reserved_at_e0[0x18]; + u8 counter_set_id[0x8]; +}; + /* CQE format mask. */ #define MLX5E_CQE_FORMAT_MASK 0xc @@ -2698,7 +3811,14 @@ struct mlx5_mini_cqe8 { union { uint32_t rx_hash_result; struct { - uint16_t checksum; + union { + uint16_t checksum; + uint16_t flow_tag_high; + struct { + uint8_t reserved; + uint8_t hdr_type; + }; + }; uint16_t stride_idx; }; struct { @@ -2707,7 +3827,19 @@ struct mlx5_mini_cqe8 { uint8_t reserved; } s_wqe_info; }; - uint32_t byte_cnt; + union { + uint32_t byte_cnt_flow; + uint32_t byte_cnt; + }; +}; + +/* Mini CQE responder format. */ +enum { + MLX5_CQE_RESP_FORMAT_HASH = 0x0, + MLX5_CQE_RESP_FORMAT_CSUM = 0x1, + MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, + MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, + MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, }; /* srTCM PRM flow meter parameters. */ @@ -2718,14 +3850,49 @@ enum { MLX5_FLOW_COLOR_UNDEFINED, }; -/* Maximum value of srTCM metering parameters. */ -#define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F)) -#define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF) -#define MLX5_SRTCM_EBS_MAX 0 +/* Maximum value of srTCM & trTCM metering parameters. */ +#define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) +#define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) /* The bits meter color use. */ #define MLX5_MTR_COLOR_BITS 8 +/* The bit size of one register. */ +#define MLX5_REG_BITS 32 + +/* Idle bits for non-color usage in color register. */ +#define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) + +/* Length mode of dynamic flex parser graph node. */ +enum mlx5_parse_graph_node_len_mode { + MLX5_GRAPH_NODE_LEN_FIXED = 0x0, + MLX5_GRAPH_NODE_LEN_FIELD = 0x1, + MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, +}; + +/* Offset mode of the samples of flex parser. */ +enum mlx5_parse_graph_flow_match_sample_offset_mode { + MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, + MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, + MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, +}; + +/* Node index for an input / output arc of the flex parser graph. */ +enum mlx5_parse_graph_arc_node_index { + MLX5_GRAPH_ARC_NODE_NULL = 0x0, + MLX5_GRAPH_ARC_NODE_HEAD = 0x1, + MLX5_GRAPH_ARC_NODE_MAC = 0x2, + MLX5_GRAPH_ARC_NODE_IP = 0x3, + MLX5_GRAPH_ARC_NODE_GRE = 0x4, + MLX5_GRAPH_ARC_NODE_UDP = 0x5, + MLX5_GRAPH_ARC_NODE_MPLS = 0x6, + MLX5_GRAPH_ARC_NODE_TCP = 0x7, + MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, + MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, + MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, + MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, +}; + /** * Convert a user mark to flow mark. * @@ -2784,4 +3951,21 @@ mlx5_flow_mark_get(uint32_t val) #endif } +/** + * Convert a timestamp format to configure settings in the queue context. + * + * @param val + * timestamp format supported by the queue. + * + * @return + * Converted timstamp format settings. + */ +static inline uint32_t +mlx5_ts_format_conv(uint32_t ts_format) +{ + return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? + MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : + MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; +} + #endif /* RTE_PMD_MLX5_PRM_H_ */