X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Focteontx2%2Fotx2_common.h;h=cd52e098e690cd2ce90e2b6c17809afdf40633cb;hb=9dfc2d6fdac7a82b7aa55dcd59d41a5d6c3ffca3;hp=17470268704f003f480cb28ae6d51dc02042bebc;hpb=8614cb6afdedb10eaa41cac458cd3fe898498d27;p=dpdk.git

diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index 1747026870..cd52e098e6 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -8,6 +8,7 @@
 #include <rte_atomic.h>
 #include <rte_common.h>
 #include <rte_cycles.h>
+#include <rte_kvargs.h>
 #include <rte_memory.h>
 #include <rte_memzone.h>
 #include <rte_io.h>
@@ -20,6 +21,7 @@
 #include "hw/otx2_sso.h"
 #include "hw/otx2_ssow.h"
 #include "hw/otx2_tim.h"
+#include "hw/otx2_ree.h"
 
 /* Alignment */
 #define OTX2_ALIGN  128
@@ -49,6 +51,8 @@
 	 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
 #endif
 
+#define OTX2_NPA_LOCK_MASK "npa_lock_mask"
+
 /* Intra device related functions */
 struct otx2_npa_lf;
 struct otx2_idev_cfg {
@@ -60,6 +64,7 @@ struct otx2_idev_cfg {
 		rte_atomic16_t npa_refcnt;
 		uint16_t npa_refcnt_u16;
 	};
+	uint64_t npa_lock_mask;
 };
 
 __rte_internal
@@ -78,6 +83,8 @@ __rte_internal
 int otx2_npa_lf_active(void *dev);
 __rte_internal
 int otx2_npa_lf_obj_ref(void);
+__rte_internal
+void otx2_parse_common_devargs(struct rte_kvargs *kvlist);
 
 /* Log */
 extern int otx2_logtype_base;
@@ -90,6 +97,7 @@ extern int otx2_logtype_tm;
 extern int otx2_logtype_tim;
 extern int otx2_logtype_dpi;
 extern int otx2_logtype_ep;
+extern int otx2_logtype_ree;
 
 #define otx2_err(fmt, args...)			\
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n",	\
@@ -113,6 +121,7 @@ extern int otx2_logtype_ep;
 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
 #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
+#define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* PCI IDs */
 #define PCI_VENDOR_ID_CAVIUM			0x177D
@@ -127,9 +136,14 @@ extern int otx2_logtype_ep;
 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF		0xA0FE
 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF		0xA0f8
 #define PCI_DEVID_OCTEONTX2_DPI_VF		0xA081
-#define PCI_DEVID_OCTEONTX2_EP_VF		0xB203 /* OCTEON TX2 EP mode */
+#define PCI_DEVID_OCTEONTX2_EP_NET_VF		0xB203 /* OCTEON TX2 EP mode */
+/* OCTEON TX2 98xx EP mode */
+#define PCI_DEVID_CN98XX_EP_NET_VF		0xB103
+#define PCI_DEVID_OCTEONTX2_EP_RAW_VF		0xB204 /* OCTEON TX2 EP mode */
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF		0xA0f6
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF		0xA0f7
+#define PCI_DEVID_OCTEONTX2_RVU_REE_PF		0xA0f4
+#define PCI_DEVID_OCTEONTX2_RVU_REE_VF		0xA0f5
 
 /*
  * REVID for RVU PCIe devices.