X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Focteontx2%2Fotx2_dev.h;h=cd4fe517db9f0ad1326d8534a388851f9da9d53b;hb=f0f5d844d138;hp=a89570b622e84378f9f069876f4162091d6e2fab;hpb=e1d9a02ad8f0fa06ef6ade96d4d14ccd646cea3d;p=dpdk.git

diff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h
index a89570b622..cd4fe517db 100644
--- a/drivers/common/octeontx2/otx2_dev.h
+++ b/drivers/common/octeontx2/otx2_dev.h
@@ -10,19 +10,64 @@
 #include "otx2_common.h"
 #include "otx2_irq.h"
 #include "otx2_mbox.h"
+#include "otx2_mempool.h"
 
 /* Common HWCAP flags. Use from LSB bits */
-#define OTX2_HWCAP_F_VF		BIT_ULL(0) /* VF device */
+#define OTX2_HWCAP_F_VF		BIT_ULL(8) /* VF device */
 #define otx2_dev_is_vf(dev)	(dev->hwcap & OTX2_HWCAP_F_VF)
 #define otx2_dev_is_pf(dev)	(!(dev->hwcap & OTX2_HWCAP_F_VF))
 #define otx2_dev_is_lbk(dev)	((dev->hwcap & OTX2_HWCAP_F_VF) && \
 				 (dev->tx_chan_base < 0x700))
+#define otx2_dev_revid(dev)	(dev->hwcap & 0xFF)
+#define otx2_dev_is_sdp(dev)	(dev->sdp_link)
 
-#define OTX2_HWCAP_F_A0		BIT_ULL(1) /* A0 device */
-#define otx2_dev_is_A0(dev)	(dev->hwcap & OTX2_HWCAP_F_A0)
+#define otx2_dev_is_vf_or_sdp(dev)				\
+	(otx2_dev_is_vf(dev) || otx2_dev_is_sdp(dev))
+
+#define otx2_dev_is_A0(dev)					\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0))
+#define otx2_dev_is_Ax(dev)					\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0))
+
+#define otx2_dev_is_95xx_A0(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))
+#define otx2_dev_is_95xx_Ax(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))
+
+#define otx2_dev_is_96xx_A0(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
+#define otx2_dev_is_96xx_Ax(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
+
+#define otx2_dev_is_96xx_Cx(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x2) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
+
+#define otx2_dev_is_96xx_C0(dev)				\
+	((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x2) &&	\
+	 (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&	\
+	 (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))
 
 struct otx2_dev;
 
+/* Link status callback */
+typedef void (*otx2_link_status_t)(struct otx2_dev *dev,
+				   struct cgx_link_user_info *link);
+/* PTP info callback */
+typedef int (*otx2_ptp_info_t)(struct otx2_dev *dev, bool ptp_en);
+
+struct otx2_dev_ops {
+	otx2_link_status_t link_status_update;
+	otx2_ptp_info_t ptp_info_update;
+};
+
 #define OTX2_DEV					\
 	int node __rte_cache_aligned;			\
 	uint16_t pf;					\
@@ -40,6 +85,7 @@ struct otx2_dev;
 	otx2_intr_t intr;				\
 	int timer_set;	/* ~0 : no alarm handling */	\
 	uint64_t hwcap;					\
+	struct otx2_npa_lf npalf;			\
 	struct otx2_mbox *mbox;				\
 	uint16_t maxvf;					\
 	const struct otx2_dev_ops *ops
@@ -48,8 +94,32 @@ struct otx2_dev {
 	OTX2_DEV;
 };
 
-int otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev);
+__rte_internal
+int otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev);
+
+/* Common dev init and fini routines */
+
+static __rte_always_inline int
+otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
+{
+	struct otx2_dev *dev = otx2_dev;
+	uint8_t rev_id;
+	int rc;
+
+	rc = rte_pci_read_config(pci_dev, &rev_id,
+				 1, RVU_PCI_REVISION_ID);
+	if (rc != 1) {
+		otx2_err("Failed to read pci revision id, rc=%d", rc);
+		return rc;
+	}
+
+	dev->hwcap = rev_id;
+	return otx2_dev_priv_init(pci_dev, otx2_dev);
+}
+
+__rte_internal
 void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);
+__rte_internal
 int otx2_dev_active_vfs(void *otx2_dev);
 
 #define RVU_PFVF_PF_SHIFT	10