X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fsfc_efx%2Fbase%2Fef10_nic.c;h=7a119302421db2167520ecb239fe6950cb8d7195;hb=798672850cfc68615b305a720f3638e643e2de2e;hp=c5990f16cce264fa3429f2bc7a5e1491165eab9a;hpb=4d0af0db83bb7e2b17b2bb834b8e73b83985799f;p=dpdk.git

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index c5990f16cc..7a11930242 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -10,7 +10,7 @@
 #include "mcdi_mon.h"
 #endif
 
-#if EFX_OPTS_EF10()
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 
 #include "ef10_tlv_layout.h"
 
@@ -24,7 +24,7 @@ efx_mcdi_get_port_assignment(
 		MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
 	efx_rc_t rc;
 
-	EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+	EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
 
 	req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
 	req.emr_in_buf = payload;
@@ -68,7 +68,7 @@ efx_mcdi_get_port_modes(
 		MC_CMD_GET_PORT_MODES_OUT_LEN);
 	efx_rc_t rc;
 
-	EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+	EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
 
 	req.emr_cmd = MC_CMD_GET_PORT_MODES;
 	req.emr_in_buf = payload;
@@ -223,6 +223,10 @@ fail1:
 	return (rc);
 }
 
+#endif	/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
+
+#if EFX_OPTS_EF10()
+
 	__checkReturn		efx_rc_t
 efx_mcdi_vadaptor_alloc(
 	__in			efx_nic_t *enp,
@@ -292,6 +296,10 @@ fail1:
 	return (rc);
 }
 
+#endif	/* EFX_OPTS_EF10() */
+
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
+
 	__checkReturn	efx_rc_t
 efx_mcdi_get_mac_address_pf(
 	__in			efx_nic_t *enp,
@@ -302,7 +310,7 @@ efx_mcdi_get_mac_address_pf(
 		MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 	efx_rc_t rc;
 
-	EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+	EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
 
 	req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
 	req.emr_in_buf = payload;
@@ -358,7 +366,7 @@ efx_mcdi_get_mac_address_vf(
 		MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 	efx_rc_t rc;
 
-	EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+	EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
 
 	req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
 	req.emr_in_buf = payload;
@@ -420,7 +428,7 @@ efx_mcdi_get_clock(
 		MC_CMD_GET_CLOCK_OUT_LEN);
 	efx_rc_t rc;
 
-	EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
+	EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
 
 	req.emr_cmd = MC_CMD_GET_CLOCK;
 	req.emr_in_buf = payload;
@@ -569,7 +577,7 @@ fail1:
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_alloc_vis(
 	__in		efx_nic_t *enp,
 	__in		uint32_t min_vi_count,
@@ -631,7 +639,7 @@ fail1:
 }
 
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_free_vis(
 	__in		efx_nic_t *enp)
 {
@@ -663,6 +671,9 @@ fail1:
 	return (rc);
 }
 
+#endif	/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
+
+#if EFX_OPTS_EF10()
 
 static	__checkReturn	efx_rc_t
 efx_mcdi_alloc_piobuf(
@@ -978,6 +989,10 @@ ef10_nic_pio_unlink(
 	return (efx_mcdi_unlink_piobuf(enp, vi_index));
 }
 
+#endif	/* EFX_OPTS_EF10() */
+
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
+
 static	__checkReturn	efx_rc_t
 ef10_mcdi_get_pf_count(
 	__in		efx_nic_t *enp,
@@ -1094,6 +1109,12 @@ ef10_get_datapath_caps(
 	else
 		encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
 
+	/* Check if TSOv3 is supported */
+	if (CAP_FLAGS2(req, TX_TSO_V3))
+		encp->enc_tso_v3_enabled = B_TRUE;
+	else
+		encp->enc_tso_v3_enabled = B_FALSE;
+
 	/* Check if the firmware has vadapter/vport/vswitch support */
 	if (CAP_FLAGS1(req, EVB))
 		encp->enc_datapath_cap_evb = B_TRUE;
@@ -1667,6 +1688,19 @@ static struct ef10_external_port_map_s {
 		(1U << TLV_PORT_MODE_NA_2x2),			/* mode 14 */
 		{ EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
 	},
+	/*
+	 * Modes that on Riverhead allocate each port number to a separate
+	 * cage.
+	 *	port 0 -> cage 1
+	 *	port 1 -> cage 2
+	 */
+	{
+		EFX_FAMILY_RIVERHEAD,
+		(1U << TLV_PORT_MODE_1x1_NA) |			/* mode 0 */
+		(1U << TLV_PORT_MODE_1x4_NA) |			/* mode 1 */
+		(1U << TLV_PORT_MODE_1x1_1x1),			/* mode 2 */
+		{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+	},
 };
 
 static	__checkReturn	efx_rc_t
@@ -1757,7 +1791,7 @@ fail1:
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_nic_board_cfg(
 	__in		efx_nic_t *enp)
 {
@@ -1921,7 +1955,7 @@ fail1:
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+	__checkReturn	efx_rc_t
 efx_mcdi_entity_reset(
 	__in		efx_nic_t *enp)
 {
@@ -1954,6 +1988,10 @@ fail1:
 	return (rc);
 }
 
+#endif	/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
+
+#if EFX_OPTS_EF10()
+
 static	__checkReturn	efx_rc_t
 ef10_set_workaround_bug26807(
 	__in		efx_nic_t *enp)
@@ -2039,6 +2077,27 @@ ef10_nic_board_cfg(
 	 */
 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
+	/* EF10 TSO engine demands that packet header be contiguous. */
+	encp->enc_tx_tso_max_header_ndescs = 1;
+
+	/* The overall TSO header length is not limited. */
+	encp->enc_tx_tso_max_header_length = UINT32_MAX;
+
+	/*
+	 * There are no specific limitations on the number of
+	 * TSO payload descriptors.
+	 */
+	encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX;
+
+	/* TSO superframe payload length is not limited. */
+	encp->enc_tx_tso_max_payload_length = UINT32_MAX;
+
+	/*
+	 * Limitation on the maximum number of outgoing packets per
+	 * TSO transaction described in SF-108452-SW.
+	 */
+	encp->enc_tx_tso_max_nframes = 32767;
+
 	/*
 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@@ -2262,7 +2321,11 @@ fail1:
 	return (rc);
 }
 
-static	__checkReturn	efx_rc_t
+#endif	/* EFX_OPTS_EF10() */
+
+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
+
+	__checkReturn	efx_rc_t
 ef10_upstream_port_vadaptor_alloc(
 	__in		efx_nic_t *enp)
 {
@@ -2314,6 +2377,10 @@ fail1:
 	return (rc);
 }
 
+#endif	/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
+
+#if EFX_OPTS_EF10()
+
 	__checkReturn	efx_rc_t
 ef10_nic_init(
 	__in		efx_nic_t *enp)