X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fsfc_efx%2Fbase%2Fef10_nic.c;h=eda0ad30683b195bdd0334b752f81f82f8c4d04a;hb=c4f4a0e60dcb2a3877a4a751d7641fa1d9c46c29;hp=34fa45e8c10450798be255cf86dfc7d2366e16b1;hpb=5e111ed87999b2df4084b4d9c95643c98df1ba48;p=dpdk.git diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c index 34fa45e8c1..eda0ad3068 100644 --- a/drivers/common/sfc_efx/base/ef10_nic.c +++ b/drivers/common/sfc_efx/base/ef10_nic.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright(c) 2019-2020 Xilinx, Inc. + * Copyright(c) 2019-2021 Xilinx, Inc. * Copyright(c) 2012-2019 Solarflare Communications Inc. */ @@ -10,7 +10,7 @@ #include "mcdi_mon.h" #endif -#if EFX_OPTS_EF10() +#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() #include "ef10_tlv_layout.h" @@ -24,7 +24,7 @@ efx_mcdi_get_port_assignment( MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN); efx_rc_t rc; - EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); + EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT; req.emr_in_buf = payload; @@ -68,7 +68,7 @@ efx_mcdi_get_port_modes( MC_CMD_GET_PORT_MODES_OUT_LEN); efx_rc_t rc; - EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); + EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); req.emr_cmd = MC_CMD_GET_PORT_MODES; req.emr_in_buf = payload; @@ -223,6 +223,10 @@ fail1: return (rc); } +#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ + +#if EFX_OPTS_EF10() + __checkReturn efx_rc_t efx_mcdi_vadaptor_alloc( __in efx_nic_t *enp, @@ -292,6 +296,10 @@ fail1: return (rc); } +#endif /* EFX_OPTS_EF10() */ + +#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() + __checkReturn efx_rc_t efx_mcdi_get_mac_address_pf( __in efx_nic_t *enp, @@ -302,7 +310,7 @@ efx_mcdi_get_mac_address_pf( MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); efx_rc_t rc; - EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); + EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES; req.emr_in_buf = payload; @@ -358,7 +366,7 @@ efx_mcdi_get_mac_address_vf( MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); efx_rc_t rc; - EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); + EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES; req.emr_in_buf = payload; @@ -420,7 +428,7 @@ efx_mcdi_get_clock( MC_CMD_GET_CLOCK_OUT_LEN); efx_rc_t rc; - EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); + EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); req.emr_cmd = MC_CMD_GET_CLOCK; req.emr_in_buf = payload; @@ -483,11 +491,17 @@ efx_mcdi_get_rxdp_config( req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; efx_mcdi_execute(enp, &req); + if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } + if (req.emr_out_length_used < MC_CMD_GET_RXDP_CONFIG_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { /* RX DMA end padding is disabled */ @@ -506,7 +520,7 @@ efx_mcdi_get_rxdp_config( break; default: rc = ENOTSUP; - goto fail2; + goto fail3; } } @@ -514,6 +528,8 @@ efx_mcdi_get_rxdp_config( return (0); +fail3: + EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: @@ -569,7 +585,7 @@ fail1: return (rc); } -static __checkReturn efx_rc_t + __checkReturn efx_rc_t efx_mcdi_alloc_vis( __in efx_nic_t *enp, __in uint32_t min_vi_count, @@ -631,7 +647,7 @@ fail1: } -static __checkReturn efx_rc_t + __checkReturn efx_rc_t efx_mcdi_free_vis( __in efx_nic_t *enp) { @@ -663,6 +679,9 @@ fail1: return (rc); } +#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ + +#if EFX_OPTS_EF10() static __checkReturn efx_rc_t efx_mcdi_alloc_piobuf( @@ -978,6 +997,10 @@ ef10_nic_pio_unlink( return (efx_mcdi_unlink_piobuf(enp, vi_index)); } +#endif /* EFX_OPTS_EF10() */ + +#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() + static __checkReturn efx_rc_t ef10_mcdi_get_pf_count( __in efx_nic_t *enp, @@ -1028,29 +1051,25 @@ ef10_get_datapath_caps( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mcdi_req_t req; EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN, - MC_CMD_GET_CAPABILITIES_V5_OUT_LEN); + MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); efx_rc_t rc; - if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) - goto fail1; - - req.emr_cmd = MC_CMD_GET_CAPABILITIES; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN; + req.emr_out_length = MC_CMD_GET_CAPABILITIES_V7_OUT_LEN; efx_mcdi_execute_quiet(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; - goto fail2; + goto fail1; } if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) { rc = EMSGSIZE; - goto fail3; + goto fail2; } #define CAP_FLAGS1(_req, _flag) \ @@ -1062,15 +1081,16 @@ ef10_get_datapath_caps( (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \ (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))) - /* - * Huntington RXDP firmware inserts a 0 or 14 byte prefix. - * We only support the 14 byte prefix here. - */ - if (CAP_FLAGS1(req, RX_PREFIX_LEN_14) == 0) { - rc = ENOTSUP; - goto fail4; - } - encp->enc_rx_prefix_size = 14; +#define CAP_FLAGS3(_req, _flag) \ + (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) && \ + (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V7_OUT_FLAGS3) & \ + (1u << (MC_CMD_GET_CAPABILITIES_V7_OUT_ ## _flag ## _LBN)))) + + /* Check if RXDP firmware inserts 14 byte prefix */ + if (CAP_FLAGS1(req, RX_PREFIX_LEN_14)) + encp->enc_rx_prefix_size = 14; + else + encp->enc_rx_prefix_size = 0; #if EFSYS_OPT_RX_SCALE /* Check if the firmware supports additional RSS modes */ @@ -1102,6 +1122,12 @@ ef10_get_datapath_caps( else encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE; + /* Check if TSOv3 is supported */ + if (CAP_FLAGS2(req, TX_TSO_V3)) + encp->enc_tso_v3_enabled = B_TRUE; + else + encp->enc_tso_v3_enabled = B_FALSE; + /* Check if the firmware has vadapter/vport/vswitch support */ if (CAP_FLAGS1(req, EVB)) encp->enc_datapath_cap_evb = B_TRUE; @@ -1138,6 +1164,9 @@ ef10_get_datapath_caps( else encp->enc_rx_disable_scatter_supported = B_FALSE; + /* No limit on maximum number of Rx scatter elements per packet. */ + encp->enc_rx_scatter_max = -1; + /* Check if the firmware supports packed stream mode */ if (CAP_FLAGS1(req, RX_PACKED_STREAM)) encp->enc_rx_packed_stream_supported = B_TRUE; @@ -1189,6 +1218,15 @@ ef10_get_datapath_caps( else encp->enc_init_evq_v2_supported = B_FALSE; + /* + * Check if firmware supports extended width event queues, which have + * a different event descriptor layout. + */ + if (CAP_FLAGS3(req, EXTENDED_WIDTH_EVQS_SUPPORTED)) + encp->enc_init_evq_extended_width_supported = B_TRUE; + else + encp->enc_init_evq_extended_width_supported = B_FALSE; + /* * Check if the NO_CONT_EV mode for RX events is supported. */ @@ -1348,7 +1386,7 @@ ef10_get_datapath_caps( default: rc = EINVAL; - goto fail5; + goto fail3; } /* Port numbers cannot contribute to the hash value */ @@ -1391,19 +1429,38 @@ ef10_get_datapath_caps( else encp->enc_filter_action_mark_max = 0; +#if EFSYS_OPT_MAE + /* + * Check support for EF100 Match Action Engine (MAE). + * MAE hardware is present on Riverhead boards (from R2), + * and on Keystone, and requires support in firmware. + * + * MAE control operations require MAE control privilege, + * which is not available for VFs. + * + * Privileges can change dynamically at runtime: we assume + * MAE support requires the privilege is granted initially, + * and ignore later dynamic changes. + */ + if (CAP_FLAGS3(req, MAE_SUPPORTED) && + EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE)) + encp->enc_mae_supported = B_TRUE; + else + encp->enc_mae_supported = B_FALSE; +#else + encp->enc_mae_supported = B_FALSE; +#endif /* EFSYS_OPT_MAE */ + #undef CAP_FLAGS1 #undef CAP_FLAGS2 +#undef CAP_FLAGS3 return (0); #if EFSYS_OPT_RX_SCALE -fail5: - EFSYS_PROBE(fail5); -#endif /* EFSYS_OPT_RX_SCALE */ -fail4: - EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); +#endif /* EFSYS_OPT_RX_SCALE */ fail2: EFSYS_PROBE(fail2); fail1: @@ -1679,6 +1736,19 @@ static struct ef10_external_port_map_s { (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */ { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } }, + /* + * Modes that on Riverhead allocate each port number to a separate + * cage. + * port 0 -> cage 1 + * port 1 -> cage 2 + */ + { + EFX_FAMILY_RIVERHEAD, + (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ + (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ + (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ + { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } + }, }; static __checkReturn efx_rc_t @@ -1769,61 +1839,10 @@ fail1: return (rc); } -static __checkReturn efx_rc_t -ef10_set_workaround_bug26807( - __in efx_nic_t *enp) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t flags; - efx_rc_t rc; - - /* - * If the bug26807 workaround is enabled, then firmware has enabled - * support for chained multicast filters. Firmware will reset (FLR) - * functions which have filters in the hardware filter table when the - * workaround is enabled/disabled. - * - * We must recheck if the workaround is enabled after inserting the - * first hardware filter, in case it has been changed since this check. - */ - rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, - B_TRUE, &flags); - if (rc == 0) { - encp->enc_bug26807_workaround = B_TRUE; - if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { - /* - * Other functions had installed filters before the - * workaround was enabled, and they have been reset - * by firmware. - */ - EFSYS_PROBE(bug26807_workaround_flr_done); - /* FIXME: bump MC warm boot count ? */ - } - } else if (rc == EACCES) { - /* - * Unprivileged functions cannot enable the workaround in older - * firmware. - */ - encp->enc_bug26807_workaround = B_FALSE; - } else if ((rc == ENOTSUP) || (rc == ENOENT)) { - encp->enc_bug26807_workaround = B_FALSE; - } else { - goto fail1; - } - - return (0); - -fail1: - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - return (rc); -} - -static __checkReturn efx_rc_t -ef10_nic_board_cfg( + __checkReturn efx_rc_t +efx_mcdi_nic_board_cfg( __in efx_nic_t *enp) { - const efx_nic_ops_t *enop = enp->en_enop; efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); ef10_link_state_t els; @@ -1862,6 +1881,9 @@ ef10_nic_board_cfg( encp->enc_pf = pf; encp->enc_vf = vf; + if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) + goto fail4; + /* MAC address for this function */ if (EFX_PCI_FUNCTION_IS_PF(encp)) { rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); @@ -1886,10 +1908,22 @@ ef10_nic_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail4; + goto fail5; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); + /* + * Get the current privilege mask. Note that this may be modified + * dynamically, so for most cases the value is informational only. + * If the privilege being discovered can't be granted dynamically, + * it's fine to rely on the value. In all other cases, DO NOT use + * the privilege mask to check for sufficient privileges, as that + * can result in time-of-check/time-of-use bugs. + */ + if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) + goto fail6; + encp->enc_privilege_mask = mask; + /* Board configuration (legacy) */ rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); if (rc != 0) { @@ -1897,15 +1931,14 @@ ef10_nic_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail5; + goto fail7; } encp->enc_board_type = board_type; - encp->enc_clk_mult = 1; /* not used for EF10 */ /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail6; + goto fail8; /* * Firmware with support for *_FEC capability bits does not @@ -1924,13 +1957,162 @@ ef10_nic_board_cfg( /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail7; + goto fail9; epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail8; + goto fail10; + + /* Get interrupt vector limits */ + if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { + if (EFX_PCI_FUNCTION_IS_PF(encp)) + goto fail11; + + /* Ignore error (cannot query vector limits from a VF). */ + base = 0; + nvec = 1024; + } + encp->enc_intr_vec_base = base; + encp->enc_intr_limit = nvec; + + return (0); + +fail11: + EFSYS_PROBE(fail11); +fail10: + EFSYS_PROBE(fail10); +fail9: + EFSYS_PROBE(fail9); +fail8: + EFSYS_PROBE(fail8); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + + __checkReturn efx_rc_t +efx_mcdi_entity_reset( + __in efx_nic_t *enp) +{ + efx_mcdi_req_t req; + EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN, + MC_CMD_ENTITY_RESET_OUT_LEN); + efx_rc_t rc; + + req.emr_cmd = MC_CMD_ENTITY_RESET; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN; + + MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG, + ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + +#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ + +#if EFX_OPTS_EF10() + +static __checkReturn efx_rc_t +ef10_set_workaround_bug26807( + __in efx_nic_t *enp) +{ + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t flags; + efx_rc_t rc; + + /* + * If the bug26807 workaround is enabled, then firmware has enabled + * support for chained multicast filters. Firmware will reset (FLR) + * functions which have filters in the hardware filter table when the + * workaround is enabled/disabled. + * + * We must recheck if the workaround is enabled after inserting the + * first hardware filter, in case it has been changed since this check. + */ + rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, + B_TRUE, &flags); + if (rc == 0) { + encp->enc_bug26807_workaround = B_TRUE; + if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { + /* + * Other functions had installed filters before the + * workaround was enabled, and they have been reset + * by firmware. + */ + EFSYS_PROBE(bug26807_workaround_flr_done); + /* FIXME: bump MC warm boot count ? */ + } + } else if (rc == EACCES) { + /* + * Unprivileged functions cannot enable the workaround in older + * firmware. + */ + encp->enc_bug26807_workaround = B_FALSE; + } else if ((rc == ENOTSUP) || (rc == ENOENT)) { + encp->enc_bug26807_workaround = B_FALSE; + } else { + goto fail1; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + +static __checkReturn efx_rc_t +ef10_nic_board_cfg( + __in efx_nic_t *enp) +{ + const efx_nic_ops_t *enop = enp->en_enop; + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + efx_rc_t rc; + + if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0) + goto fail1; + + /* + * Huntington RXDP firmware inserts a 0 or 14 byte prefix. + * We only support the 14 byte prefix here. + */ + if (encp->enc_rx_prefix_size != 14) { + rc = ENOTSUP; + goto fail2; + } + + encp->enc_clk_mult = 1; /* not used for EF10 */ /* Alignment for WPTR updates */ encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; @@ -1945,6 +2127,27 @@ ef10_nic_board_cfg( */ encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; + /* EF10 TSO engine demands that packet header be contiguous. */ + encp->enc_tx_tso_max_header_ndescs = 1; + + /* The overall TSO header length is not limited. */ + encp->enc_tx_tso_max_header_length = UINT32_MAX; + + /* + * There are no specific limitations on the number of + * TSO payload descriptors. + */ + encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX; + + /* TSO superframe payload length is not limited. */ + encp->enc_tx_tso_max_payload_length = UINT32_MAX; + + /* + * Limitation on the maximum number of outgoing packets per + * TSO transaction described in SF-108452-SW. + */ + encp->enc_tx_tso_max_nframes = 32767; + /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -1957,54 +2160,16 @@ ef10_nic_board_cfg( encp->enc_buftbl_limit = UINT32_MAX; - /* Get interrupt vector limits */ - if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { - if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail9; - - /* Ignore error (cannot query vector limits from a VF). */ - base = 0; - nvec = 1024; - } - encp->enc_intr_vec_base = base; - encp->enc_intr_limit = nvec; - - /* - * Get the current privilege mask. Note that this may be modified - * dynamically, so this value is informational only. DO NOT use - * the privilege mask to check for sufficient privileges, as that - * can result in time-of-check/time-of-use bugs. - */ - if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail10; - encp->enc_privilege_mask = mask; - if ((rc = ef10_set_workaround_bug26807(enp)) != 0) - goto fail11; + goto fail3; /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) if (rc != EACCES) - goto fail12; + goto fail4; return (0); -fail12: - EFSYS_PROBE(fail12); -fail11: - EFSYS_PROBE(fail11); -fail10: - EFSYS_PROBE(fail10); -fail9: - EFSYS_PROBE(fail9); -fail8: - EFSYS_PROBE(fail8); -fail7: - EFSYS_PROBE(fail7); -fail6: - EFSYS_PROBE(fail6); -fail5: - EFSYS_PROBE(fail5); fail4: EFSYS_PROBE(fail4); fail3: @@ -2075,8 +2240,6 @@ ef10_nic_probe( } #endif - encp->enc_features = enp->en_features; - return (0); #if EFSYS_OPT_MON_STATS @@ -2182,9 +2345,6 @@ fail1: ef10_nic_reset( __in efx_nic_t *enp) { - efx_mcdi_req_t req; - EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN, - MC_CMD_ENTITY_RESET_OUT_LEN); efx_rc_t rc; /* ef10_nic_reset() is called to recover from BADASSERT failures. */ @@ -2193,21 +2353,8 @@ ef10_nic_reset( if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) goto fail2; - req.emr_cmd = MC_CMD_ENTITY_RESET; - req.emr_in_buf = payload; - req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN; - req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN; - - MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG, - ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); - - efx_mcdi_execute(enp, &req); - - if (req.emr_rc != 0) { - rc = req.emr_rc; + if ((rc = efx_mcdi_entity_reset(enp)) != 0) goto fail3; - } /* Clear RX/TX DMA queue errors */ enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR); @@ -2224,7 +2371,11 @@ fail1: return (rc); } -static __checkReturn efx_rc_t +#endif /* EFX_OPTS_EF10() */ + +#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() + + __checkReturn efx_rc_t ef10_upstream_port_vadaptor_alloc( __in efx_nic_t *enp) { @@ -2276,6 +2427,10 @@ fail1: return (rc); } +#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ + +#if EFX_OPTS_EF10() + __checkReturn efx_rc_t ef10_nic_init( __in efx_nic_t *enp)