X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcommon%2Fsfc_efx%2Fbase%2Fef10_nic.c;h=eda0ad30683b195bdd0334b752f81f82f8c4d04a;hb=c4f4a0e60dcb2a3877a4a751d7641fa1d9c46c29;hp=80dc99aed50a4fad6d0b81457bc3e0b2476b9a2a;hpb=3c1c5cc4a7860bb8dd211919a4e946b2a8c43c3c;p=dpdk.git diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c index 80dc99aed5..eda0ad3068 100644 --- a/drivers/common/sfc_efx/base/ef10_nic.c +++ b/drivers/common/sfc_efx/base/ef10_nic.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright(c) 2019-2020 Xilinx, Inc. + * Copyright(c) 2019-2021 Xilinx, Inc. * Copyright(c) 2012-2019 Solarflare Communications Inc. */ @@ -491,11 +491,17 @@ efx_mcdi_get_rxdp_config( req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; efx_mcdi_execute(enp, &req); + if (req.emr_rc != 0) { rc = req.emr_rc; goto fail1; } + if (req.emr_out_length_used < MC_CMD_GET_RXDP_CONFIG_OUT_LEN) { + rc = EMSGSIZE; + goto fail2; + } + if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { /* RX DMA end padding is disabled */ @@ -514,7 +520,7 @@ efx_mcdi_get_rxdp_config( break; default: rc = ENOTSUP; - goto fail2; + goto fail3; } } @@ -522,6 +528,8 @@ efx_mcdi_get_rxdp_config( return (0); +fail3: + EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: @@ -1043,14 +1051,14 @@ ef10_get_datapath_caps( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mcdi_req_t req; EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN, - MC_CMD_GET_CAPABILITIES_V5_OUT_LEN); + MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); efx_rc_t rc; req.emr_cmd = MC_CMD_GET_CAPABILITIES; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN; + req.emr_out_length = MC_CMD_GET_CAPABILITIES_V7_OUT_LEN; efx_mcdi_execute_quiet(enp, &req); @@ -1073,6 +1081,11 @@ ef10_get_datapath_caps( (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \ (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))) +#define CAP_FLAGS3(_req, _flag) \ + (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) && \ + (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V7_OUT_FLAGS3) & \ + (1u << (MC_CMD_GET_CAPABILITIES_V7_OUT_ ## _flag ## _LBN)))) + /* Check if RXDP firmware inserts 14 byte prefix */ if (CAP_FLAGS1(req, RX_PREFIX_LEN_14)) encp->enc_rx_prefix_size = 14; @@ -1109,6 +1122,12 @@ ef10_get_datapath_caps( else encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE; + /* Check if TSOv3 is supported */ + if (CAP_FLAGS2(req, TX_TSO_V3)) + encp->enc_tso_v3_enabled = B_TRUE; + else + encp->enc_tso_v3_enabled = B_FALSE; + /* Check if the firmware has vadapter/vport/vswitch support */ if (CAP_FLAGS1(req, EVB)) encp->enc_datapath_cap_evb = B_TRUE; @@ -1145,6 +1164,9 @@ ef10_get_datapath_caps( else encp->enc_rx_disable_scatter_supported = B_FALSE; + /* No limit on maximum number of Rx scatter elements per packet. */ + encp->enc_rx_scatter_max = -1; + /* Check if the firmware supports packed stream mode */ if (CAP_FLAGS1(req, RX_PACKED_STREAM)) encp->enc_rx_packed_stream_supported = B_TRUE; @@ -1196,6 +1218,15 @@ ef10_get_datapath_caps( else encp->enc_init_evq_v2_supported = B_FALSE; + /* + * Check if firmware supports extended width event queues, which have + * a different event descriptor layout. + */ + if (CAP_FLAGS3(req, EXTENDED_WIDTH_EVQS_SUPPORTED)) + encp->enc_init_evq_extended_width_supported = B_TRUE; + else + encp->enc_init_evq_extended_width_supported = B_FALSE; + /* * Check if the NO_CONT_EV mode for RX events is supported. */ @@ -1398,8 +1429,31 @@ ef10_get_datapath_caps( else encp->enc_filter_action_mark_max = 0; +#if EFSYS_OPT_MAE + /* + * Check support for EF100 Match Action Engine (MAE). + * MAE hardware is present on Riverhead boards (from R2), + * and on Keystone, and requires support in firmware. + * + * MAE control operations require MAE control privilege, + * which is not available for VFs. + * + * Privileges can change dynamically at runtime: we assume + * MAE support requires the privilege is granted initially, + * and ignore later dynamic changes. + */ + if (CAP_FLAGS3(req, MAE_SUPPORTED) && + EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE)) + encp->enc_mae_supported = B_TRUE; + else + encp->enc_mae_supported = B_FALSE; +#else + encp->enc_mae_supported = B_FALSE; +#endif /* EFSYS_OPT_MAE */ + #undef CAP_FLAGS1 #undef CAP_FLAGS2 +#undef CAP_FLAGS3 return (0); @@ -1858,6 +1912,18 @@ efx_mcdi_nic_board_cfg( EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); + /* + * Get the current privilege mask. Note that this may be modified + * dynamically, so for most cases the value is informational only. + * If the privilege being discovered can't be granted dynamically, + * it's fine to rely on the value. In all other cases, DO NOT use + * the privilege mask to check for sufficient privileges, as that + * can result in time-of-check/time-of-use bugs. + */ + if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) + goto fail6; + encp->enc_privilege_mask = mask; + /* Board configuration (legacy) */ rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); if (rc != 0) { @@ -1865,14 +1931,14 @@ efx_mcdi_nic_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail6; + goto fail7; } encp->enc_board_type = board_type; /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail7; + goto fail8; /* * Firmware with support for *_FEC capability bits does not @@ -1891,18 +1957,18 @@ efx_mcdi_nic_board_cfg( /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail8; + goto fail9; epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail9; + goto fail10; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail10; + goto fail11; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -1911,16 +1977,6 @@ efx_mcdi_nic_board_cfg( encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - /* - * Get the current privilege mask. Note that this may be modified - * dynamically, so this value is informational only. DO NOT use - * the privilege mask to check for sufficient privileges, as that - * can result in time-of-check/time-of-use bugs. - */ - if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail11; - encp->enc_privilege_mask = mask; - return (0); fail11: @@ -2071,6 +2127,27 @@ ef10_nic_board_cfg( */ encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; + /* EF10 TSO engine demands that packet header be contiguous. */ + encp->enc_tx_tso_max_header_ndescs = 1; + + /* The overall TSO header length is not limited. */ + encp->enc_tx_tso_max_header_length = UINT32_MAX; + + /* + * There are no specific limitations on the number of + * TSO payload descriptors. + */ + encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX; + + /* TSO superframe payload length is not limited. */ + encp->enc_tx_tso_max_payload_length = UINT32_MAX; + + /* + * Limitation on the maximum number of outgoing packets per + * TSO transaction described in SF-108452-SW. + */ + encp->enc_tx_tso_max_nframes = 32767; + /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -2294,7 +2371,11 @@ fail1: return (rc); } -static __checkReturn efx_rc_t +#endif /* EFX_OPTS_EF10() */ + +#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() + + __checkReturn efx_rc_t ef10_upstream_port_vadaptor_alloc( __in efx_nic_t *enp) { @@ -2346,6 +2427,10 @@ fail1: return (rc); } +#endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ + +#if EFX_OPTS_EF10() + __checkReturn efx_rc_t ef10_nic_init( __in efx_nic_t *enp)