X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcompress%2Fmlx5%2Fmlx5_compress.c;h=80c564f10b574e306acfb6b3197f8858e0768aef;hb=eeded2044af5bbe88220120b14933536cbb3edb6;hp=9826f6e3a569b2bb0926c47dbc6d5222a7c115fe;hpb=ccfd891a50ae2988a3a4980f2ef26d3bed35030d;p=dpdk.git diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 9826f6e3a5..80c564f10b 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -23,7 +23,6 @@ #include "mlx5_compress_utils.h" #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress -#define MLX5_COMPRESS_LOG_NAME pmd.compress.mlx5 #define MLX5_COMPRESS_MAX_QPS 1024 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u @@ -43,12 +42,17 @@ struct mlx5_compress_priv { void *uar; uint32_t pdn; /* Protection Domain number. */ uint8_t min_block_size; + uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ /* Minimum huffman block size supported by the device. */ struct ibv_pd *pd; struct rte_compressdev_config dev_config; LIST_HEAD(xform_list, mlx5_compress_xform) xform_list; rte_spinlock_t xform_sl; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ + volatile uint64_t *uar_addr; +#ifndef RTE_ARCH_64 + rte_spinlock_t uar32_sl; +#endif /* RTE_ARCH_64 */ }; struct mlx5_compress_qp { @@ -56,7 +60,6 @@ struct mlx5_compress_qp { uint16_t entries_n; uint16_t pi; uint16_t ci; - volatile uint64_t *uar_addr; struct mlx5_mr_ctrl mr_ctrl; int socket_id; struct mlx5_devx_cq cq; @@ -73,8 +76,28 @@ static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; int mlx5_compress_logtype; -const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END]; - +static const struct rte_compressdev_capabilities mlx5_caps[] = { + { + .algo = RTE_COMP_ALGO_NULL, + .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | + RTE_COMP_FF_CRC32_CHECKSUM | + RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | + RTE_COMP_FF_SHAREABLE_PRIV_XFORM, + }, + { + .algo = RTE_COMP_ALGO_DEFLATE, + .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM | + RTE_COMP_FF_CRC32_CHECKSUM | + RTE_COMP_FF_CRC32_ADLER32_CHECKSUM | + RTE_COMP_FF_SHAREABLE_PRIV_XFORM | + RTE_COMP_FF_HUFFMAN_FIXED | + RTE_COMP_FF_HUFFMAN_DYNAMIC, + .window_size = {.min = 10, .max = 15, .increment = 1}, + }, + { + .algo = RTE_COMP_ALGO_LIST_END, + } +}; static void mlx5_compress_dev_info_get(struct rte_compressdev *dev, @@ -207,8 +230,6 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, qp->priv = priv; qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1), RTE_CACHE_LINE_SIZE); - qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); - MLX5_ASSERT(qp->uar_addr); if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n * sizeof(struct mlx5_gga_compress_opaque), &qp->opaque_mr) != 0) { @@ -224,6 +245,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, goto err; } sq_attr.cqn = qp->cq.cq->id; + sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format); ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, socket_id); if (ret != 0) { @@ -236,7 +258,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, DRV_LOG(ERR, "Can't change SQ state to ready."); goto err; } - DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u\n", + DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n); return 0; err: @@ -422,6 +444,24 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, return dseg->lkey; } +/* + * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and + * 64bit architectures. + */ +static __rte_always_inline void +mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv) +{ +#ifdef RTE_ARCH_64 + *priv->uar_addr = val; +#else /* !RTE_ARCH_64 */ + rte_spinlock_lock(&priv->uar32_sl); + *(volatile uint32_t *)priv->uar_addr = val; + rte_io_wmb(); + *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32; + rte_spinlock_unlock(&priv->uar32_sl); +#endif +} + static uint16_t mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, uint16_t nb_ops) @@ -485,7 +525,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops, rte_io_wmb(); qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi); rte_wmb(); - *qp->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/ + mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv); rte_wmb(); return nb_ops; } @@ -575,7 +615,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, op->consumed = op->src.length; op->produced = rte_be_to_cpu_32(cqe->byte_cnt); MLX5_ASSERT(cqe->byte_cnt == - qp->opaque_buf[idx].scattered_length); + opaq[idx].scattered_length); switch (xform->csum_type) { case RTE_COMP_CHECKSUM_CRC32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 @@ -606,34 +646,6 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, return i; } -static struct ibv_device * -mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr) -{ - int n; - struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); - struct ibv_device *ibv_match = NULL; - - if (ibv_list == NULL) { - rte_errno = ENOSYS; - return NULL; - } - while (n-- > 0) { - struct rte_pci_addr paddr; - - DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); - if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0) - continue; - if (rte_pci_addr_cmp(addr, &paddr) != 0) - continue; - ibv_match = ibv_list[n]; - break; - } - if (ibv_match == NULL) - rte_errno = ENOENT; - mlx5_glue->free_device_list(ibv_list); - return ibv_match; -} - static void mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv) { @@ -691,6 +703,11 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv) DRV_LOG(ERR, "Failed to allocate UAR."); return -1; } + priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); + MLX5_ASSERT(priv->uar_addr); +#ifndef RTE_ARCH_64 + rte_spinlock_init(&priv->uar32_sl); +#endif /* RTE_ARCH_64 */ return 0; } @@ -728,7 +745,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr); + ibv = mlx5_os_get_ibv_device(&pci_dev->addr); if (ibv == NULL) { DRV_LOG(ERR, "No matching IB device for PCI slot " PCI_PRI_FMT ".", pci_dev->addr.domain, @@ -770,6 +787,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, priv->pci_dev = pci_dev; priv->cdev = cdev; priv->min_block_size = att.compress_min_block_size; + priv->sq_ts_format = att.sq_ts_format; if (mlx5_compress_hw_global_prepare(priv) != 0) { rte_compressdev_pmd_destroy(priv->cdev); claim_zero(mlx5_glue->close_device(priv->ctx)); @@ -854,7 +872,7 @@ RTE_INIT(rte_mlx5_compress_init) mlx5_pci_driver_register(&mlx5_compress_driver); } -RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE) +RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__); RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map); RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");