X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcompress%2Fqat%2Fqat_comp.h;h=2231451a19269ac4cb0d110cbac2a5aceda79f5c;hb=c3e33304a7f6;hp=19f48df590f23da42eb644713cb1eb075c102efc;hpb=ba83e5c0062936dab5c017da574036788c64fb6b;p=dpdk.git diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h index 19f48df590..2231451a19 100644 --- a/drivers/compress/qat/qat_comp.h +++ b/drivers/compress/qat/qat_comp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2015-2018 Intel Corporation + * Copyright(c) 2015-2019 Intel Corporation */ #ifndef _QAT_COMP_H_ @@ -21,6 +21,21 @@ #define ERR_CODE_QAT_COMP_WRONG_FW -99 +/* fallback to fixed compression threshold */ +#define QAT_FALLBACK_THLD ((uint32_t)(RTE_PMD_QAT_COMP_IM_BUFFER_SIZE / 1.1)) + +#define QAT_MIN_OUT_BUF_SIZE 46 + +/* maximum size of the state registers */ +#define QAT_STATE_REGISTERS_MAX_SIZE 64 + +/* decompressor context size */ +#define QAT_INFLATE_CONTEXT_SIZE_GEN1 36864 +#define QAT_INFLATE_CONTEXT_SIZE_GEN2 34032 +#define QAT_INFLATE_CONTEXT_SIZE_GEN3 34032 +#define QAT_INFLATE_CONTEXT_SIZE RTE_MAX(RTE_MAX(QAT_INFLATE_CONTEXT_SIZE_GEN1,\ + QAT_INFLATE_CONTEXT_SIZE_GEN2), QAT_INFLATE_CONTEXT_SIZE_GEN3) + enum qat_comp_request_type { QAT_COMP_REQUEST_FIXED_COMP_STATELESS, QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS, @@ -37,16 +52,17 @@ struct qat_inter_sgl { struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL]; } __rte_packed __rte_cache_aligned; -struct qat_comp_sgl { - qat_sgl_hdr; - struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS]; -} __rte_packed __rte_cache_aligned; struct qat_comp_op_cookie { - struct qat_comp_sgl qat_sgl_src; - struct qat_comp_sgl qat_sgl_dst; phys_addr_t qat_sgl_src_phys_addr; phys_addr_t qat_sgl_dst_phys_addr; + /* dynamically created SGLs */ + uint8_t error; + uint8_t socket_id; + uint16_t src_nb_elems; + uint16_t dst_nb_elems; + struct qat_sgl *qat_sgl_src_d; + struct qat_sgl *qat_sgl_dst_d; }; struct qat_comp_xform { @@ -55,12 +71,23 @@ struct qat_comp_xform { enum rte_comp_checksum_type checksum_type; }; +struct qat_comp_stream { + struct qat_comp_xform qat_xform; + void *state_registers_decomp; + phys_addr_t state_registers_decomp_phys; + void *inflate_context; + phys_addr_t inflate_context_phys; + const struct rte_memzone *memzone; + uint8_t start_of_packet; + volatile uint8_t op_in_progress; +}; + int qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie, enum qat_device_gen qat_dev_gen __rte_unused); int -qat_comp_process_response(void **op, uint8_t *resp, +qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie, uint64_t *dequeue_err_count); int @@ -74,5 +101,16 @@ qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform); unsigned int qat_comp_xform_size(void); +unsigned int +qat_comp_stream_size(void); + +int +qat_comp_stream_create(struct rte_compressdev *dev, + const struct rte_comp_xform *xform, + void **stream); + +int +qat_comp_stream_free(struct rte_compressdev *dev, void *stream); + #endif #endif