X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcrypto%2Focteontx2%2Fotx2_cryptodev.h;h=7e8c5de83990af4b6a27403fdd2099a0e0bc1f0a;hb=e863fe3a13da89787fdf3b5c590101a3c0f10af6;hp=f329741b386ba9198b5c08b4f7b74fe80fbb795e;hpb=fab634eb87ca3883562c95a20f9a69eba645456b;p=dpdk.git

diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index f329741b38..7e8c5de839 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -13,8 +13,11 @@
 /* Marvell OCTEON TX2 Crypto PMD device name */
 #define CRYPTODEV_NAME_OCTEONTX2_PMD	crypto_octeontx2
 
-#define OTX2_CPT_MAX_LFS		64
+#define OTX2_CPT_MAX_LFS		128
 #define OTX2_CPT_MAX_QUEUES_PER_VF	64
+#define OTX2_CPT_MAX_BLKS		2
+#define OTX2_CPT_PMD_VERSION		3
+#define OTX2_CPT_REVISION_ID_3		3
 
 /**
  * Device private data
@@ -28,6 +31,10 @@ struct otx2_cpt_vf {
 	/**< Number of crypto queues attached */
 	uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
 	/**< MSI-X offsets */
+	uint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];
+	/**<  CPT0/1 BLKADDR of LFs */
+	uint8_t cpt_revision;
+	/**<  CPT revision */
 	uint8_t err_intr_registered:1;
 	/**< Are error interrupts registered? */
 	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
@@ -35,10 +42,10 @@ struct otx2_cpt_vf {
 };
 
 struct cpt_meta_info {
-	uint64_t deq_op_info[4];
+	uint64_t deq_op_info[5];
 	uint64_t comp_code_sz;
 	union cpt_res_s cpt_res __rte_aligned(16);
-	struct cpt_request_info cpt_req __rte_aligned(8);
+	struct cpt_request_info cpt_req;
 };
 
 #define CPT_LOGTYPE otx2_cpt_logtype
@@ -50,4 +57,6 @@ extern int otx2_cpt_logtype;
  */
 extern uint8_t otx2_cryptodev_driver_id;
 
+void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
+
 #endif /* _OTX2_CRYPTODEV_H_ */