X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fcrypto%2Focteontx2%2Fotx2_cryptodev_hw_access.c;h=bf90d095fecc86c69072cd0d1e1013736d6f1e7f;hb=e863fe3a13da89787fdf3b5c590101a3c0f10af6;hp=663f9ca4ba90d6a0ef7138681ce6d6c6574402c3;hpb=dfacd1f9f726e0e5419f36a982dc51ec7c95cfcc;p=dpdk.git

diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
index 663f9ca4ba..bf90d095fe 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
@@ -1,10 +1,14 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright (C) 2019 Marvell International Ltd.
  */
+#include <rte_cryptodev.h>
 
 #include "otx2_common.h"
 #include "otx2_cryptodev.h"
 #include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_cryptodev_ops.h"
+#include "otx2_dev.h"
 
 #include "cpt_pmd_logs.h"
 
@@ -49,7 +53,7 @@ otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)
 	uint32_t i;
 
 	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_CPT_LF_BAR2(vf, i);
+		base = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);
 		otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
 	}
 
@@ -95,7 +99,7 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
 	}
 
 	for (i = 0; i < vf->nb_queues; i++) {
-		base = OTX2_CPT_LF_BAR2(vf, i);
+		base = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);
 		ret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],
 						   base);
 		if (ret)
@@ -108,7 +112,7 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
 intr_unregister:
 	/* Unregister the ones already registered */
 	for (j = 0; j < i; j++) {
-		base = OTX2_CPT_LF_BAR2(vf, j);
+		base = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[j], j);
 		otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
 	}
 
@@ -124,3 +128,98 @@ intr_unregister:
 	 */
 	return 0;
 }
+
+int
+otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
+		   const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri,
+		   uint32_t size_div40)
+{
+	union otx2_cpt_af_lf_ctl af_lf_ctl;
+	union otx2_cpt_lf_inprog inprog;
+	union otx2_cpt_lf_q_base base;
+	union otx2_cpt_lf_q_size size;
+	union otx2_cpt_lf_ctl lf_ctl;
+	int ret;
+
+	/* Set engine group mask and priority */
+
+	ret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+				   qp->blkaddr, &af_lf_ctl.u);
+	if (ret)
+		return ret;
+	af_lf_ctl.s.grp = grp_mask;
+	af_lf_ctl.s.pri = pri ? 1 : 0;
+	ret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+				    qp->blkaddr, af_lf_ctl.u);
+	if (ret)
+		return ret;
+
+	/* Set instruction queue base address */
+
+	base.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE);
+	base.s.fault = 0;
+	base.s.stopped = 0;
+	base.s.addr = qp->iq_dma_addr >> 7;
+	otx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE);
+
+	/* Set instruction queue size */
+
+	size.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE);
+	size.s.size_div40 = size_div40;
+	otx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE);
+
+	/* Enable instruction queue */
+
+	lf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+	lf_ctl.s.ena = 1;
+	otx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+	/* Start instruction execution */
+
+	inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+	inprog.s.eena = 1;
+	otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+	return 0;
+}
+
+void
+otx2_cpt_iq_disable(struct otx2_cpt_qp *qp)
+{
+	union otx2_cpt_lf_q_grp_ptr grp_ptr;
+	union otx2_cpt_lf_inprog inprog;
+	union otx2_cpt_lf_ctl ctl;
+	int cnt;
+
+	/* Stop instruction execution */
+	inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+	inprog.s.eena = 0x0;
+	otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+	/* Disable instructions enqueuing */
+	ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+	ctl.s.ena = 0;
+	otx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+	/* Wait for instruction queue to become empty */
+	cnt = 0;
+	do {
+		inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+		if (inprog.s.grb_partial)
+			cnt = 0;
+		else
+			cnt++;
+		grp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR);
+	} while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));
+
+	cnt = 0;
+	do {
+		inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+		if ((inprog.s.inflight == 0) &&
+		    (inprog.s.gwb_cnt < 40) &&
+		    ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40)))
+			cnt++;
+		else
+			cnt = 0;
+	} while (cnt < 10);
+}