X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fevent%2Fcnxk%2Fcn9k_eventdev.c;h=f8652d4fbc0a83f8ef5f47ff49cdb33d3b9190cf;hb=1f5b3d55c0419952c6cdeff89cc10c12d7ea00c0;hp=806dcb0a454c675bc462637c02f1014e80741df5;hpb=1a7da795f64a354138f63073b14b126b7f8df3aa;p=dpdk.git diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 806dcb0a45..f8652d4fbc 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -10,33 +10,10 @@ #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) #define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \ - (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)] \ - [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)]) + deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)] #define CN9K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \ - (enq_op = enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \ - [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)]) - -static void -cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base) -{ - ws->tag_op = base + SSOW_LF_GWS_TAG; - ws->wqp_op = base + SSOW_LF_GWS_WQP; - ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0; - ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH; - ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM; - ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED; -} + enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)] static int cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link) @@ -87,7 +64,7 @@ cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) } static void -cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) +cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) { struct cnxk_sso_evdev *dev = arg; struct cn9k_sso_hws_dual *dws; @@ -95,21 +72,19 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) uint64_t val; /* Set get_work tmo for HWS */ - val = NSEC2USEC(dev->deq_tmo_ns) - 1; + val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0; if (dev->dual_ws) { dws = hws; - rte_memcpy(dws->grps_base, grps_base, - sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); - dws->fc_mem = dev->fc_mem; + dws->grp_base = grp_base; + dws->fc_mem = (uint64_t *)dev->fc_iova; dws->xaq_lmt = dev->xaq_lmt; plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM); plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM); } else { ws = hws; - rte_memcpy(ws->grps_base, grps_base, - sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); - ws->fc_mem = dev->fc_mem; + ws->grp_base = grp_base; + ws->fc_mem = (uint64_t *)dev->fc_iova; ws->xaq_lmt = dev->xaq_lmt; plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); @@ -150,7 +125,6 @@ cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base, { struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg); struct cn9k_sso_hws_dual *dws; - struct cn9k_sso_hws_state *st; struct cn9k_sso_hws *ws; uint64_t cq_ds_cnt = 1; uint64_t aq_cnt = 1; @@ -172,22 +146,21 @@ cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base, if (dev->dual_ws) { dws = hws; - st = &dws->ws_state[0]; ws_base = dws->base[0]; } else { ws = hws; - st = (struct cn9k_sso_hws_state *)ws; ws_base = ws->base; } while (aq_cnt || cq_ds_cnt || ds_cnt) { - plt_write64(req, st->getwrk_op); - cn9k_sso_hws_get_work_empty(st, &ev); + plt_write64(req, ws_base + SSOW_LF_GWS_OP_GET_WORK0); + cn9k_sso_hws_get_work_empty(ws_base, &ev); if (fn != NULL && ev.u64 != 0) fn(arg, ev); if (ev.sched_type != SSO_TT_EMPTY) - cnxk_sso_hws_swtag_flush(st->tag_op, - st->swtag_flush_op); + cnxk_sso_hws_swtag_flush( + ws_base + SSOW_LF_GWS_TAG, + ws_base + SSOW_LF_GWS_OP_SWTAG_FLUSH); do { val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE); } while (val & BIT_ULL(56)); @@ -286,17 +259,14 @@ cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev) ws_cookie, sizeof(struct cnxk_sso_hws_cookie) + sizeof(struct cn9k_sso_hws_dual) + - (sizeof(uint64_t) * - (dev->max_port_id + 1) * - RTE_MAX_QUEUES_PER_PORT), + dev->tx_adptr_data_sz, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); if (ws_cookie == NULL) return -ENOMEM; dws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie)); memcpy(&dws->tx_adptr_data, dev->tx_adptr_data, - sizeof(uint64_t) * (dev->max_port_id + 1) * - RTE_MAX_QUEUES_PER_PORT); + dev->tx_adptr_data_sz); event_dev->data->ports[i] = dws; } else { struct cn9k_sso_hws *ws = event_dev->data->ports[i]; @@ -307,17 +277,14 @@ cn9k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev) ws_cookie, sizeof(struct cnxk_sso_hws_cookie) + sizeof(struct cn9k_sso_hws_dual) + - (sizeof(uint64_t) * - (dev->max_port_id + 1) * - RTE_MAX_QUEUES_PER_PORT), + dev->tx_adptr_data_sz, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); if (ws_cookie == NULL) return -ENOMEM; ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie)); memcpy(&ws->tx_adptr_data, dev->tx_adptr_data, - sizeof(uint64_t) * (dev->max_port_id + 1) * - RTE_MAX_QUEUES_PER_PORT); + dev->tx_adptr_data_sz); event_dev->data->ports[i] = ws; } } @@ -331,221 +298,223 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) { struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); /* Single WS modes */ - const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name, + const event_dequeue_t sso_hws_deq[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_deq_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name, + const event_dequeue_t sso_hws_deq_tmo[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name, + const event_dequeue_burst_t sso_hws_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name, + const event_dequeue_t sso_hws_deq_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name, + const event_dequeue_burst_t sso_hws_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name, + const event_dequeue_t sso_hws_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name, + const event_dequeue_burst_t sso_hws_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name, + const event_dequeue_t sso_hws_deq_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name, + const event_dequeue_burst_t sso_hws_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_seg_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_t sso_hws_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_##name, + NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name, + const event_dequeue_burst_t sso_hws_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_seg_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_t sso_hws_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_deq_tmo_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES #undef R }; /* Dual WS modes */ - const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name, + const event_dequeue_t sso_hws_dual_deq[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_dual_deq_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_dual_deq_tmo[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name, + const event_dequeue_burst_t sso_hws_dual_deq_tmo_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name, + const event_dequeue_t sso_hws_dual_deq_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_burst_t sso_hws_dual_deq_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_burst_##name, + NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name, + const event_dequeue_t sso_hws_dual_deq_tmo_ca[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_ca_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_burst_##name, + NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name, + const event_dequeue_t sso_hws_dual_deq_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_burst_t sso_hws_dual_deq_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_seg_burst_##name, + NIX_RX_FASTPATH_MODES #undef R - }; + }; - const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name, + const event_dequeue_t sso_hws_dual_deq_tmo_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = \ - cn9k_sso_hws_dual_deq_tmo_seg_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_burst_t sso_hws_dual_deq_tmo_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name, + NIX_RX_FASTPATH_MODES #undef R - }; + }; - const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name, + const event_dequeue_t sso_hws_dual_deq_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t - sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2][2] = { -#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = \ - cn9k_sso_hws_dual_deq_ca_seg_burst_##name, - NIX_RX_FASTPATH_MODES + const event_dequeue_burst_t sso_hws_dual_deq_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_t sso_hws_dual_deq_tmo_ca_seg[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_##name, + NIX_RX_FASTPATH_MODES +#undef R + }; + + const event_dequeue_burst_t sso_hws_dual_deq_tmo_ca_seg_burst[NIX_RX_OFFLOAD_MAX] = { +#define R(name, flags)[flags] = cn9k_sso_hws_dual_deq_tmo_ca_seg_burst_##name, + NIX_RX_FASTPATH_MODES #undef R }; /* Tx modes */ - const event_tx_adapter_enqueue - sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = { -#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_##name, - NIX_TX_FASTPATH_MODES + const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = { +#define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_##name, + NIX_TX_FASTPATH_MODES #undef T - }; + }; - const event_tx_adapter_enqueue - sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = { -#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_tx_adptr_enq_seg_##name, - NIX_TX_FASTPATH_MODES + const event_tx_adapter_enqueue_t sso_hws_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = { +#define T(name, sz, flags)[flags] = cn9k_sso_hws_tx_adptr_enq_seg_##name, + NIX_TX_FASTPATH_MODES #undef T - }; + }; - const event_tx_adapter_enqueue - sso_hws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = { -#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_tx_adptr_enq_##name, - NIX_TX_FASTPATH_MODES + const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq[NIX_TX_OFFLOAD_MAX] = { +#define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_##name, + NIX_TX_FASTPATH_MODES #undef T - }; - - const event_tx_adapter_enqueue - sso_hws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = { -#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \ - [f6][f5][f4][f3][f2][f1][f0] = \ - cn9k_sso_hws_dual_tx_adptr_enq_seg_##name, - NIX_TX_FASTPATH_MODES + }; + + const event_tx_adapter_enqueue_t sso_hws_dual_tx_adptr_enq_seg[NIX_TX_OFFLOAD_MAX] = { +#define T(name, sz, flags)[flags] = cn9k_sso_hws_dual_tx_adptr_enq_seg_##name, + NIX_TX_FASTPATH_MODES #undef T - }; + }; event_dev->enqueue = cn9k_sso_hws_enq; event_dev->enqueue_burst = cn9k_sso_hws_enq_burst; @@ -567,6 +536,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, sso_hws_deq_ca_seg_burst); } + + if (dev->is_ca_internal_port && dev->is_timeout_deq) { + CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_deq_tmo_ca_seg); + CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_ca_seg_burst); + } } else { CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq); CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, @@ -583,6 +559,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, sso_hws_deq_ca_burst); } + + if (dev->is_ca_internal_port && dev->is_timeout_deq) { + CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_deq_tmo_ca); + CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst, + sso_hws_deq_tmo_ca_burst); + } } event_dev->ca_enqueue = cn9k_sso_hws_ca_enq; @@ -620,6 +603,14 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) dev, event_dev->dequeue_burst, sso_hws_dual_deq_ca_seg_burst); } + if (dev->is_ca_internal_port && dev->is_timeout_deq) { + CN9K_SET_EVDEV_DEQ_OP( + dev, event_dev->dequeue, + sso_hws_dual_deq_tmo_ca_seg); + CN9K_SET_EVDEV_DEQ_OP( + dev, event_dev->dequeue_burst, + sso_hws_dual_deq_tmo_ca_seg_burst); + } } else { CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_dual_deq); @@ -639,6 +630,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) dev, event_dev->dequeue_burst, sso_hws_dual_deq_ca_burst); } + if (dev->is_ca_internal_port && dev->is_timeout_deq) { + CN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, + sso_hws_dual_deq_tmo_ca); + CN9K_SET_EVDEV_DEQ_OP( + dev, event_dev->dequeue_burst, + sso_hws_dual_deq_tmo_ca_burst); + } } if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) @@ -676,8 +674,6 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0)); dws->base[1] = roc_sso_hws_base_get( &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1)); - cn9k_init_hws_ops(&dws->ws_state[0], dws->base[0]); - cn9k_init_hws_ops(&dws->ws_state[1], dws->base[1]); dws->hws_id = port_id; dws->swtag_req = 0; dws->vws = 0; @@ -697,7 +693,6 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) /* First cache line is reserved for cookie */ ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie)); ws->base = roc_sso_hws_base_get(&dev->sso, port_id); - cn9k_init_hws_ops((struct cn9k_sso_hws_state *)ws, ws->base); ws->hws_id = port_id; ws->swtag_req = 0; @@ -729,8 +724,6 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) return -EINVAL; } - roc_sso_rsrc_fini(&dev->sso); - rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues); if (rc < 0) { plt_err("Failed to initialize SSO resources"); @@ -988,17 +981,36 @@ cn9k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev, int32_t tx_queue_id) { + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint64_t tx_offloads; int rc; RTE_SET_USED(id); rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id); if (rc < 0) return rc; + + /* Can't enable tstamp if all the ports don't have it enabled. */ + tx_offloads = cnxk_eth_dev->tx_offload_flags; + if (dev->tx_adptr_configured) { + uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F); + uint8_t tstmp_ena = + !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F); + + if (tstmp_ena && !tstmp_req) + dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F); + else if (!tstmp_ena && tstmp_req) + tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F); + } + + dev->tx_offloads |= tx_offloads; cn9k_sso_txq_fc_update(eth_dev, tx_queue_id, true); rc = cn9k_sso_updt_tx_adptr_data(event_dev); if (rc < 0) return rc; cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + dev->tx_adptr_configured = 1; return 0; } @@ -1060,7 +1072,7 @@ cn9k_crypto_adapter_qp_del(const struct rte_eventdev *event_dev, return cnxk_crypto_adapter_qp_del(cdev, queue_pair_id); } -static struct rte_eventdev_ops cn9k_sso_dev_ops = { +static struct eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, @@ -1147,6 +1159,16 @@ cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) } static const struct rte_pci_id cn9k_pci_sso_map[] = { + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), { .vendor_id = 0, },