X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fevent%2Fdpaa2%2Fdpaa2_eventdev.h;h=785e52032ea451507cd5f838985ffb3bed5fcf3e;hb=8716f9942a408a79a114ac0496e4e7d55bc9944c;hp=d2f98c621aa84c4026b11348df22db57fa081acb;hpb=047188552bc5ed74f74ff701b6808feecf0501e1;p=dpdk.git

diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h
index d2f98c621a..785e52032e 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.h
+++ b/drivers/event/dpaa2/dpaa2_eventdev.h
@@ -1,8 +1,5 @@
-/*
- * SPDX-License-Identifier: BSD-3-Clause
- *
- *   Copyright 2017 NXP
- *
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2017 NXP
  */
 
 #ifndef __DPAA2_EVENTDEV_H__
@@ -21,6 +18,7 @@
 #define DPAA2_EVENT_MAX_QUEUES			16
 #define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT		1
 #define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT		(UINT32_MAX - 1)
+#define DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS	100UL
 #define DPAA2_EVENT_MAX_QUEUE_FLOWS		2048
 #define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS	8
 #define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS	0
@@ -40,32 +38,40 @@ enum {
 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \
 		(RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
 		RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
-		RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
+		RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID | \
+		RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT)
+
+/**< Crypto Rx adapter cap to return If the packet transfers from
+ * the cryptodev to eventdev with DPAA2 devices.
+ */
+#define RTE_EVENT_CRYPTO_ADAPTER_DPAA2_CAP \
+		(RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \
+		RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \
+		RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)
+
 /**< Ethernet Rx adapter cap to return If the packet transfers from
  * the ethdev to eventdev with DPAA2 devices.
  */
 
-struct dpaa2_dpcon_dev {
-	TAILQ_ENTRY(dpaa2_dpcon_dev) next;
-	struct fsl_mc_io dpcon;
-	uint16_t token;
-	rte_atomic16_t in_use;
-	uint32_t dpcon_id;
-	uint16_t qbman_ch_id;
-	uint8_t num_priorities;
-	uint8_t channel_index;
-};
-
 struct dpaa2_eventq {
 	/* DPcon device */
 	struct dpaa2_dpcon_dev *dpcon;
 	/* Attached DPCI device */
 	struct dpaa2_dpci_dev *dpci;
+	/* Mapped event port */
+	struct dpaa2_io_portal_t *event_port;
 	/* Configuration provided by the user */
 	uint32_t event_queue_cfg;
 	uint32_t event_queue_id;
 };
 
+struct dpaa2_port {
+	struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
+	uint8_t num_linked_evq;
+	uint8_t is_port_linked;
+	uint64_t timeout_us;
+};
+
 struct dpaa2_eventdev {
 	struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
 	uint32_t dequeue_timeout_ns;
@@ -82,4 +88,6 @@ struct dpaa2_eventdev {
 struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
 void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
 
+int test_eventdev_dpaa2(void);
+
 #endif /* __DPAA2_EVENTDEV_H__ */