X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fevent%2Focteontx2%2Fotx2_evdev.h;h=96e5799be12f766b36cce75bc67f34873fd5d3e7;hb=300b796262a1;hp=9c9718f6f17e522ef558fc72908ed278c0d5a7ce;hpb=9c0a9024bef2fc59bef7f19ce01b5c0f3329a003;p=dpdk.git diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 9c9718f6f1..96e5799be1 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -6,7 +6,7 @@ #define __OTX2_EVDEV_H__ #include -#include +#include #include #include @@ -14,8 +14,9 @@ #include "otx2_dev.h" #include "otx2_ethdev.h" #include "otx2_mempool.h" +#include "otx2_tim_evdev.h" -#define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev +#define EVENTDEV_NAME_OCTEONTX2_PMD event_octeontx2 #define sso_func_trace otx2_sso_dbg @@ -25,6 +26,7 @@ #define OTX2_SSO_SQB_LIMIT (0x180) #define OTX2_SSO_XAQ_SLACK (8) #define OTX2_SSO_XAQ_CACHE_CNT (0x7) +#define OTX2_SSO_WQE_SG_PTR (9) /* SSO LF register offsets (BAR2) */ #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull) @@ -77,6 +79,8 @@ #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull) #define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK) +#define OTX2_SSOW_TT_FROM_TAG(x) (((x) >> 32) & SSO_TT_EMPTY) +#define OTX2_SSOW_GRP_FROM_TAG(x) (((x) >> 36) & 0x3ff) #define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us) * 1E3) @@ -136,12 +140,15 @@ struct otx2_sso_evdev { struct rte_mempool *xaq_pool; uint64_t rx_offloads; uint64_t tx_offloads; + uint64_t adptr_xae_cnt; uint16_t rx_adptr_pool_cnt; - uint32_t adptr_xae_cnt; uint64_t *rx_adptr_pools; + uint16_t max_port_id; + uint16_t tim_adptr_ring_cnt; + uint16_t *timer_adptr_rings; + uint64_t *timer_adptr_sz; /* Dev args */ uint8_t dual_ws; - uint8_t selftest; uint32_t xae_cnt; uint8_t qos_queue_cnt; struct otx2_sso_qos *qos_parse_data; @@ -156,30 +163,31 @@ struct otx2_sso_evdev { struct otx2_timesync_info *tstamp; } __rte_cache_aligned; -#define OTX2_SSOGWS_OPS \ - /* WS ops */ \ - uintptr_t getwrk_op; \ - uintptr_t tag_op; \ - uintptr_t wqp_op; \ - uintptr_t swtp_op; \ - uintptr_t swtag_norm_op; \ - uintptr_t swtag_desched_op; \ - uint8_t cur_tt; \ - uint8_t cur_grp +#define OTX2_SSOGWS_OPS \ + /* WS ops */ \ + uintptr_t getwrk_op; \ + uintptr_t tag_op; \ + uintptr_t wqp_op; \ + uintptr_t swtag_flush_op; \ + uintptr_t swtag_norm_op; \ + uintptr_t swtag_desched_op; /* Event port aka GWS */ struct otx2_ssogws { /* Get Work Fastpath data */ OTX2_SSOGWS_OPS; - uint8_t swtag_req; + /* PTP timestamp */ + struct otx2_timesync_info *tstamp; void *lookup_mem; + uint8_t swtag_req; uint8_t port; /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; uintptr_t grps_base[OTX2_SSO_MAX_VHGRP]; - /* PTP timestamp */ - struct otx2_timesync_info *tstamp; + /* Tx Fastpath data */ + uint64_t base __rte_cache_aligned; + uint8_t tx_adptr_data[]; } __rte_cache_aligned; struct otx2_ssogws_state { @@ -189,16 +197,19 @@ struct otx2_ssogws_state { struct otx2_ssogws_dual { /* Get Work Fastpath data */ struct otx2_ssogws_state ws_state[2]; /* Ping and Pong */ + /* PTP timestamp */ + struct otx2_timesync_info *tstamp; + void *lookup_mem; uint8_t swtag_req; uint8_t vws; /* Ping pong bit */ - void *lookup_mem; uint8_t port; /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; uintptr_t grps_base[OTX2_SSO_MAX_VHGRP]; - /* PTP timestamp */ - struct otx2_timesync_info *tstamp; + /* Tx Fastpath data */ + uint64_t base[2] __rte_cache_aligned; + uint8_t tx_adptr_data[]; } __rte_cache_aligned; static inline struct otx2_sso_evdev * @@ -207,6 +218,18 @@ sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +struct otx2_ssogws_cookie { + const struct rte_eventdev *event_dev; + bool configured; +}; + +static inline struct otx2_ssogws_cookie * +ssogws_get_cookie(void *ws) +{ + return (struct otx2_ssogws_cookie *) + ((uint8_t *)ws - RTE_CACHE_LINE_SIZE); +} + static const union mbuf_initializer mbuf_init = { .fields = { .data_off = RTE_PKTMBUF_HEADROOM, @@ -222,10 +245,14 @@ otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id, const void * const lookup_mem) { struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1; + uint64_t val = mbuf_init.value | (uint64_t)port_id << 48; + + if (flags & NIX_RX_OFFLOAD_TSTAMP_F) + val |= NIX_TIMESYNC_RX_OFFSET; otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct rte_mbuf *)mbuf, lookup_mem, - mbuf_init.value | (uint64_t)port_id << 48, flags); + val, flags); } @@ -269,7 +296,7 @@ uint16_t otx2_ssogws_dual_enq_fwd_burst(void *port, const struct rte_event ev[], uint16_t nb_events); /* Auto generated API's */ -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev, \ uint64_t timeout_ticks); \ uint16_t otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[], \ @@ -326,7 +353,7 @@ uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port, \ SSO_RX_ADPTR_ENQ_FASTPATH_FUNC #undef R -#define T(name, f4, f3, f2, f1, f0, sz, flags) \ +#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \ uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\ uint16_t nb_events); \ uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, \ @@ -374,6 +401,17 @@ int otx2_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eth_dev *eth_dev, int32_t tx_queue_id); +/* Event crypto adapter API's */ +int otx2_ca_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps); + +int otx2_ca_qp_add(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id, + const struct rte_event *event); + +int otx2_ca_qp_del(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id); + /* Clean up API's */ typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev); void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,