X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fevent%2Focteontx2%2Fotx2_evdev_irq.c;h=a2033646e6b2c6ac3aa240c7c5f354bc29c30df6;hb=f5cd3a9f6016c4940dc615afe9a1adf9d015a8be;hp=7df21cc249386e88ad6ab08d48b0b94f9d1d3cff;hpb=8c77f483371ffc9c9d3bea6ec8dc7d70a4532d8c;p=dpdk.git

diff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c
index 7df21cc249..a2033646e6 100644
--- a/drivers/event/octeontx2/otx2_evdev_irq.c
+++ b/drivers/event/octeontx2/otx2_evdev_irq.c
@@ -3,6 +3,7 @@
  */
 
 #include "otx2_evdev.h"
+#include "otx2_tim_evdev.h"
 
 static void
 sso_lf_irq(void *param)
@@ -117,7 +118,7 @@ sso_register_irqs(const struct rte_eventdev *event_dev)
 	int i, rc = -EINVAL;
 	uint8_t nb_ports;
 
-	nb_ports = dev->nb_event_ports;
+	nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
 
 	for (i = 0; i < dev->nb_event_queues; i++) {
 		if (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {
@@ -159,7 +160,7 @@ sso_unregister_irqs(const struct rte_eventdev *event_dev)
 	uint8_t nb_ports;
 	int i;
 
-	nb_ports = dev->nb_event_ports;
+	nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
 
 	for (i = 0; i < dev->nb_event_queues; i++) {
 		uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |
@@ -173,3 +174,99 @@ sso_unregister_irqs(const struct rte_eventdev *event_dev)
 		ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);
 	}
 }
+
+static void
+tim_lf_irq(void *param)
+{
+	uintptr_t base = (uintptr_t)param;
+	uint64_t intr;
+	uint8_t ring;
+
+	ring = (base >> 12) & 0xFF;
+
+	intr = otx2_read64(base + TIM_LF_NRSPERR_INT);
+	otx2_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
+	intr = otx2_read64(base + TIM_LF_RAS_INT);
+	otx2_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
+
+	/* Clear interrupt */
+	otx2_write64(intr, base + TIM_LF_NRSPERR_INT);
+	otx2_write64(intr, base + TIM_LF_RAS_INT);
+}
+
+static int
+tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
+		    uintptr_t base)
+{
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int rc, vec;
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT);
+	/* Set used interrupt vectors */
+	rc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);
+	/* Enable hw interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
+
+	return rc;
+}
+
+static void
+tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,
+		      uintptr_t base)
+{
+	struct rte_intr_handle *handle = &pci_dev->intr_handle;
+	int vec;
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
+	otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
+
+	vec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;
+
+	/* Clear err interrupt */
+	otx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
+	otx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);
+}
+
+int
+tim_register_irq(uint16_t ring_id)
+{
+	struct otx2_tim_evdev *dev = tim_priv_get();
+	int rc = -EINVAL;
+	uintptr_t base;
+
+	if (dev->tim_msixoff[ring_id] == MSIX_VECTOR_INVALID) {
+		otx2_err("Invalid TIMLF MSIX offset[%d] vector: 0x%x",
+			 ring_id, dev->tim_msixoff[ring_id]);
+		goto fail;
+	}
+
+	base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
+	rc = tim_lf_register_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);
+fail:
+	return rc;
+}
+
+void
+tim_unregister_irq(uint16_t ring_id)
+{
+	struct otx2_tim_evdev *dev = tim_priv_get();
+	uintptr_t base;
+
+	base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
+	tim_lf_unregister_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);
+}