X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fmempool%2Fcnxk%2Fcnxk_mempool.c;h=57be33b8629f78f8c6bb5bcbba25dba5bb781599;hb=7ce1032edbf5105c5538f645572def3af7d28707;hp=dd4d74ca05bd710c9acd09faabac5dfe13b0e7ec;hpb=0a50a5aad299cdeddf92d3e09b35eff4707d725e;p=dpdk.git

diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c
index dd4d74ca05..57be33b862 100644
--- a/drivers/mempool/cnxk/cnxk_mempool.c
+++ b/drivers/mempool/cnxk/cnxk_mempool.c
@@ -31,25 +31,25 @@ npa_aura_size_to_u32(uint8_t val)
 }
 
 static int
-parse_max_pools(const char *key, const char *value, void *extra_args)
+parse_max_pools_handler(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	val = rte_align32pow2(atoi(value));
 	if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128))
 		val = 128;
 	if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M))
 		val = BIT_ULL(20);
 
-	*(uint8_t *)extra_args = rte_log2_u32(val) - 6;
+	*(uint32_t *)extra_args = val;
 	return 0;
 }
 
-static inline uint8_t
-parse_aura_size(struct rte_devargs *devargs)
+static inline uint32_t
+parse_max_pools(struct rte_devargs *devargs)
 {
-	uint8_t aura_sz = NPA_AURA_SZ_128;
+	uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128);
 	struct rte_kvargs *kvlist;
 
 	if (devargs == NULL)
@@ -58,11 +58,18 @@ parse_aura_size(struct rte_devargs *devargs)
 	if (kvlist == NULL)
 		goto exit;
 
-	rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools,
-			   &aura_sz);
+	rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM,
+			   &parse_max_pools_handler, &max_pools);
 	rte_kvargs_free(kvlist);
 exit:
-	return aura_sz;
+	return max_pools;
+}
+
+static int
+cnxk_mempool_plt_parse_devargs(struct rte_pci_device *pci_dev)
+{
+	roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
+	return 0;
 }
 
 static inline char *
@@ -92,7 +99,6 @@ npa_init(struct rte_pci_device *pci_dev)
 	dev = mz->addr;
 	dev->pci_dev = pci_dev;
 
-	roc_idev_npa_maxpools_set(parse_aura_size(pci_dev->device.devargs));
 	rc = roc_npa_dev_init(dev);
 	if (rc)
 		goto mz_free;
@@ -169,6 +175,13 @@ static const struct rte_pci_id npa_pci_map[] = {
 		.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 		.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
 	},
+	{
+		.class_id = RTE_CLASS_ANY_ID,
+		.vendor_id = PCI_VENDOR_ID_CAVIUM,
+		.device_id = PCI_DEVID_CNXK_RVU_NPA_PF,
+		.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
+		.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
+	},
 	{
 		.class_id = RTE_CLASS_ANY_ID,
 		.vendor_id = PCI_VENDOR_ID_CAVIUM,
@@ -183,6 +196,13 @@ static const struct rte_pci_id npa_pci_map[] = {
 		.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 		.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,
 	},
+	{
+		.class_id = RTE_CLASS_ANY_ID,
+		.vendor_id = PCI_VENDOR_ID_CAVIUM,
+		.device_id = PCI_DEVID_CNXK_RVU_NPA_VF,
+		.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
+		.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,
+	},
 	{
 		.vendor_id = 0,
 	},
@@ -200,3 +220,8 @@ RTE_PMD_REGISTER_PCI_TABLE(mempool_cnxk, npa_pci_map);
 RTE_PMD_REGISTER_KMOD_DEP(mempool_cnxk, "vfio-pci");
 RTE_PMD_REGISTER_PARAM_STRING(mempool_cnxk,
 			      CNXK_NPA_MAX_POOLS_PARAM "=<128-1048576>");
+
+RTE_INIT(cnxk_mempool_parse_devargs)
+{
+	roc_npa_lf_init_cb_register(cnxk_mempool_plt_parse_devargs);
+}