X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_common.h;h=df0aa21a9bdf54a92d7f5d2628fce07bc2c5877d;hb=05b405d581486651305551a9f7295f40388d95db;hp=298e7945595f22c0c3c44102ac7a24b89e7d3fff;hpb=69e209be54640d1d1f833ee47053cf4edf057eb4;p=dpdk.git diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 298e794559..df0aa21a9b 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -34,18 +35,18 @@ #include #include #include -#include -#include +#include #include #include #include #define BIT(nr) (1 << (nr)) #ifndef ARRAY_SIZE -#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define ARRAY_SIZE(arr) RTE_DIM(arr) #endif #define AXGBE_HZ 250 +#define NSEC_PER_SEC 1000000000L /* DMA register offsets */ #define DMA_MR 0x3000 @@ -258,6 +259,7 @@ #define MAC_HWF0R 0x011c #define MAC_HWF1R 0x0120 #define MAC_HWF2R 0x0124 +#define MAC_HWF3R 0x0128 #define MAC_MDIOSCAR 0x0200 #define MAC_MDIOSCCDR 0x0204 #define MAC_MDIOISR 0x0214 @@ -283,6 +285,19 @@ #define MAC_TXSNR 0x0d30 #define MAC_TXSSR 0x0d34 +/*VLAN control bit mask*/ +#define AXGBE_VLNCTRL_MASK 0x0000FFFF +#define VLAN_PRIO_MASK 0xe000 /* Priority Code Point */ +#define VLAN_PRIO_SHIFT 13 +#define VLAN_CFI_MASK 0x1000 /* Canonical Format Indicator */ +#define VLAN_TAG_PRESENT VLAN_CFI_MASK +#define VLAN_VID_MASK 0x0fff /* VLAN Identifier */ +#define VLAN_N_VID 4096 +#define VLAN_TABLE_SIZE 64 +#define VLAN_TABLE_BIT(vlan_id) (1UL << ((vlan_id) & 0x3F)) +#define VLAN_TABLE_IDX(vlan_id) ((vlan_id) >> 6) +#define RX_CVLAN_TAG_PRESENT 9 + #define MAC_QTFCR_INC 4 #define MAC_MACA_INC 4 #define MAC_HTR_INC 4 @@ -290,6 +305,11 @@ #define MAC_RQC2_INC 4 #define MAC_RQC2_Q_PER_REG 4 +#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8)) +#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8)) + +#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC)) + /* MAC register entry bit positions and sizes */ #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 @@ -355,6 +375,10 @@ #define MAC_HWF2R_TXCHCNT_WIDTH 4 #define MAC_HWF2R_TXQCNT_INDEX 6 #define MAC_HWF2R_TXQCNT_WIDTH 4 +#define MAC_HWF3R_CBTISEL_INDEX 4 +#define MAC_HWF3R_CBTISEL_WIDTH 1 +#define MAC_HWF3R_NRVF_INDEX 0 +#define MAC_HWF3R_NRVF_WIDTH 3 #define MAC_IER_TSIE_INDEX 12 #define MAC_IER_TSIE_WIDTH 1 #define MAC_ISR_MMCRXIS_INDEX 9 @@ -487,6 +511,8 @@ #define MAC_TSCR_TSEVNTENA_WIDTH 1 #define MAC_TSCR_TSINIT_INDEX 2 #define MAC_TSCR_TSINIT_WIDTH 1 +#define MAC_TSCR_TSUPDT_INDEX 3 +#define MAC_TSCR_TSUPDT_WIDTH 1 #define MAC_TSCR_TSIPENA_INDEX 11 #define MAC_TSCR_TSIPENA_WIDTH 1 #define MAC_TSCR_TSIPV4ENA_INDEX 13 @@ -501,6 +527,8 @@ #define MAC_TSCR_TXTSSTSM_WIDTH 1 #define MAC_TSSR_TXTSC_INDEX 15 #define MAC_TSSR_TXTSC_WIDTH 1 +#define MAC_STNUR_ADDSUB_INDEX 31 +#define MAC_STNUR_ADDSUB_WIDTH 1 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 #define MAC_VLANHTR_VLHT_INDEX 0 @@ -509,6 +537,8 @@ #define MAC_VLANIR_VLTI_WIDTH 1 #define MAC_VLANIR_CSVL_INDEX 19 #define MAC_VLANIR_CSVL_WIDTH 1 +#define MAC_VLANIR_VLC_INDEX 16 +#define MAC_VLANIR_VLC_WIDTH 2 #define MAC_VLANTR_DOVLTC_INDEX 20 #define MAC_VLANTR_DOVLTC_WIDTH 1 #define MAC_VLANTR_ERSVLM_INDEX 19 @@ -519,12 +549,18 @@ #define MAC_VLANTR_ETV_WIDTH 1 #define MAC_VLANTR_EVLS_INDEX 21 #define MAC_VLANTR_EVLS_WIDTH 2 +#define MAC_VLANTR_EIVLS_INDEX 21 +#define MAC_VLANTR_EIVLS_WIDTH 2 #define MAC_VLANTR_EVLRXS_INDEX 24 #define MAC_VLANTR_EVLRXS_WIDTH 1 +#define MAC_VLANTR_EIVLRXS_INDEX 31 +#define MAC_VLANTR_EIVLRXS_WIDTH 1 #define MAC_VLANTR_VL_INDEX 0 #define MAC_VLANTR_VL_WIDTH 16 #define MAC_VLANTR_VTHM_INDEX 25 #define MAC_VLANTR_VTHM_WIDTH 1 +#define MAC_VLANTR_EDVLP_INDEX 26 +#define MAC_VLANTR_EDVLP_WIDTH 1 #define MAC_VLANTR_VTIM_INDEX 17 #define MAC_VLANTR_VTIM_WIDTH 1 #define MAC_VR_DEVID_INDEX 8 @@ -533,6 +569,11 @@ #define MAC_VR_SNPSVER_WIDTH 8 #define MAC_VR_USERVER_INDEX 16 #define MAC_VR_USERVER_WIDTH 8 +#define MAC_VLANIR_VLT_INDEX 0 +#define MAC_VLANIR_VLT_WIDTH 16 +#define MAC_VLANTR_ERIVLT_INDEX 27 +#define MAC_VLANTR_ERIVLT_WIDTH 1 + /* MMC register offsets */ #define MMC_CR 0x0800 @@ -833,6 +874,22 @@ #define MTL_TC_ETSCR_TSA_WIDTH 2 #define MTL_TC_QWR_QW_INDEX 0 #define MTL_TC_QWR_QW_WIDTH 21 +#define MTL_TCPM0R_PSTC0_INDEX 0 +#define MTL_TCPM0R_PSTC0_WIDTH 8 +#define MTL_TCPM0R_PSTC1_INDEX 8 +#define MTL_TCPM0R_PSTC1_WIDTH 8 +#define MTL_TCPM0R_PSTC2_INDEX 16 +#define MTL_TCPM0R_PSTC2_WIDTH 8 +#define MTL_TCPM0R_PSTC3_INDEX 24 +#define MTL_TCPM0R_PSTC3_WIDTH 8 +#define MTL_TCPM1R_PSTC4_INDEX 0 +#define MTL_TCPM1R_PSTC4_WIDTH 8 +#define MTL_TCPM1R_PSTC5_INDEX 8 +#define MTL_TCPM1R_PSTC5_WIDTH 8 +#define MTL_TCPM1R_PSTC6_INDEX 16 +#define MTL_TCPM1R_PSTC6_WIDTH 8 +#define MTL_TCPM1R_PSTC7_INDEX 24 +#define MTL_TCPM1R_PSTC7_WIDTH 8 /* MTL traffic class register value */ #define MTL_TSA_SP 0x00 @@ -842,6 +899,8 @@ #define PCS_V1_WINDOW_SELECT 0x03fc #define PCS_V2_WINDOW_DEF 0x9060 #define PCS_V2_WINDOW_SELECT 0x9064 +#define PCS_V2_RV_WINDOW_DEF 0x1060 +#define PCS_V2_RV_WINDOW_SELECT 0x1064 /* PCS register entry bit positions and sizes */ #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 @@ -1134,6 +1193,8 @@ #define RX_NORMAL_DESC3_PL_WIDTH 14 #define RX_NORMAL_DESC3_RSV_INDEX 26 #define RX_NORMAL_DESC3_RSV_WIDTH 1 +#define RX_NORMAL_DESC3_LD_INDEX 28 +#define RX_NORMAL_DESC3_LD_WIDTH 1 #define RX_DESC3_L34T_IPV4_TCP 1 #define RX_DESC3_L34T_IPV4_UDP 2 @@ -1146,6 +1207,8 @@ #define RX_CONTEXT_DESC3_TSA_WIDTH 1 #define RX_CONTEXT_DESC3_TSD_INDEX 6 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 +#define RX_CONTEXT_DESC3_PMT_INDEX 0 +#define RX_CONTEXT_DESC3_PMT_WIDTH 4 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 @@ -1247,6 +1310,10 @@ #define MDIO_VEND2_AN_STAT 0x8002 #endif +#ifndef MDIO_VEND2_PMA_CDR_CONTROL +#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056 +#endif + #ifndef MDIO_CTRL1_SPEED1G #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) #endif @@ -1293,6 +1360,11 @@ #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08 +#define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100 + +#define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01 +#define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00 +#define AXGBE_PMA_CDR_TRACK_EN_ON 0x01 /*generic*/ #define __iomem @@ -1344,9 +1416,9 @@ do { \ #define SET_BITS_LE(_var, _index, _width, _val) \ do { \ - (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\ + (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\ (_var) |= rte_cpu_to_le_32((((_val) & \ - ((0x1 << (_width)) - 1)) << (_index))); \ + ((0x1U << (_width)) - 1)) << (_index))); \ } while (0) /* Bit setting and getting macros based on register fields @@ -1385,7 +1457,7 @@ do { \ * register definitions formed using the input names */ #define AXGMAC_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xgmac_regs) + (_reg)) #define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \ @@ -1393,7 +1465,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xgmac_regs) + (_reg)) #define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1409,8 +1482,8 @@ do { \ * base register value is calculated by the queue or traffic class number */ #define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \ - rte_read32((void *)((_pdata)->xgmac_regs + \ - MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) + rte_read32((uint8_t *)((_pdata)->xgmac_regs) + \ + MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)) #define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \ @@ -1418,8 +1491,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xgmac_regs + \ - MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))) + rte_write32((_val), (uint8_t *)((_pdata)->xgmac_regs) +\ + MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)) #define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ do { \ @@ -1435,7 +1508,7 @@ do { \ * base register value is obtained from the ring */ #define AXGMAC_DMA_IOREAD(_channel, _reg) \ - rte_read32((void *)((_channel)->dma_regs + (_reg))) + rte_read32((uint8_t *)((_channel)->dma_regs) + (_reg)) #define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \ @@ -1443,7 +1516,8 @@ do { \ _reg##_##_field##_WIDTH) #define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \ - rte_write32((_val), (void *)((_channel)->dma_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_channel)->dma_regs) + (_reg)) #define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ do { \ @@ -1468,16 +1542,18 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XPCS32_IOWRITE(_pdata, _off, _val) \ - rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write32(_val, \ + (uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS32_IOREAD(_pdata, _off) \ - rte_read32((void *)((_pdata)->xpcs_regs + (_off))) + rte_read32((uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS16_IOWRITE(_pdata, _off, _val) \ - rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off))) + rte_write16(_val, \ + (uint8_t *)((_pdata)->xpcs_regs) + (_off)) #define XPCS16_IOREAD(_pdata, _off) \ - rte_read16((void *)((_pdata)->xpcs_regs + (_off))) + rte_read16((uint8_t *)((_pdata)->xpcs_regs) + (_off)) /* Macros for building, reading or writing register values or bits * within the register values of SerDes integration registers. @@ -1493,7 +1569,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XSIR0_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir0_regs + (_reg))) + rte_read16((uint8_t *)((_pdata)->sir0_regs) + (_reg)) #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ @@ -1501,7 +1577,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR0_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->sir0_regs) + (_reg)) #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1513,7 +1590,7 @@ do { \ } while (0) #define XSIR1_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->sir1_regs + _reg)) + rte_read16((uint8_t *)((_pdata)->sir1_regs) + _reg) #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ @@ -1521,7 +1598,8 @@ do { \ _reg##_##_field##_WIDTH) #define XSIR1_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->sir1_regs) + (_reg)) #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1536,7 +1614,7 @@ do { \ * within the register values of SerDes RxTx registers. */ #define XRXTX_IOREAD(_pdata, _reg) \ - rte_read16((void *)((_pdata)->rxtx_regs + (_reg))) + rte_read16((uint8_t *)((_pdata)->rxtx_regs) + (_reg)) #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ @@ -1544,7 +1622,8 @@ do { \ _reg##_##_field##_WIDTH) #define XRXTX_IOWRITE(_pdata, _reg, _val) \ - rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg))) + rte_write16((_val), \ + (uint8_t *)((_pdata)->rxtx_regs) + (_reg)) #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1569,7 +1648,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XP_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xprop_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xprop_regs) + (_reg)) #define XP_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XP_IOREAD((_pdata), (_reg)), \ @@ -1577,7 +1656,8 @@ do { \ _reg##_##_field##_WIDTH) #define XP_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xprop_regs) + (_reg)) #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1602,7 +1682,7 @@ do { \ _prefix##_##_field##_WIDTH, (_val)) #define XI2C_IOREAD(_pdata, _reg) \ - rte_read32((void *)((_pdata)->xi2c_regs + (_reg))) + rte_read32((uint8_t *)((_pdata)->xi2c_regs) + (_reg)) #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ @@ -1610,7 +1690,8 @@ do { \ _reg##_##_field##_WIDTH) #define XI2C_IOWRITE(_pdata, _reg, _val) \ - rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg))) + rte_write32((_val), \ + (uint8_t *)((_pdata)->xi2c_regs) + (_reg)) #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ do { \ @@ -1658,34 +1739,6 @@ do { \ #define time_after_eq(a, b) ((long)((a) - (b)) >= 0) #define time_before_eq(a, b) time_after_eq(b, a) -/*---bitmap support apis---*/ -static inline int axgbe_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - rte_mb(); - res = ((*addr) & (1UL << nr)) != 0; - rte_mb(); - return res; -} - -static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_and(addr, ~mask) & mask; -} - static inline unsigned long msecs_to_timer_cycles(unsigned int m) { return rte_get_timer_hz() * (m / 1000);