X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_ethdev.h;h=a6226729fe4d3e8c4bebcc3eaa9f0c4cd1dbf300;hb=83680d371592fcf1b66cbbfecb0fb8b3aa4ccc8d;hp=7bd290094bf244dfaa85afbc4054f62e05c2ae13;hpb=7784d0d3d0d9807c3db1a786b0190e660ec3fd86;p=dpdk.git diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 7bd290094b..a6226729fe 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -9,14 +9,16 @@ #include #include #include "axgbe_common.h" +#include "rte_time.h" #define IRQ 0xff #define VLAN_HLEN 4 #define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) -#define AXGBE_RX_MIN_BUF_SIZE (ETHER_MAX_LEN + VLAN_HLEN) -#define AXGBE_MAX_MAC_ADDRS 1 +#define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) +#define AXGBE_MAX_MAC_ADDRS 32 +#define AXGBE_MAX_HASH_MAC_ADDRS 256 #define AXGBE_RX_BUF_ALIGN 64 @@ -62,6 +64,13 @@ #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 +/* Timestamp support - values based on 50MHz PTP clock + * 50MHz => 20 nsec + */ +#define AXGBE_TSTAMP_SSINC 20 +#define AXGBE_TSTAMP_SNSINC 0 +#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL + #define AXGMAC_FIFO_MIN_ALLOC 2048 #define AXGMAC_FIFO_UNIT 256 #define AXGMAC_FIFO_ALIGN(_x) \ @@ -83,7 +92,7 @@ (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) #define AXGMAC_FLOW_CONTROL_MAX 33280 -/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +/* Maximum MAC address hash table size (256 bits = 8 dword) */ #define AXGBE_MAC_HASH_TABLE_SIZE 8 /* Receive Side Scaling */ @@ -116,6 +125,12 @@ /* MDIO port types */ #define AXGMAC_MAX_C22_PORT 3 +/* The max frame size with default MTU */ +#define AXGBE_ETH_MAX_LEN ( \ + RTE_ETHER_MTU + \ + RTE_ETHER_HDR_LEN + \ + RTE_ETHER_CRC_LEN) + /* Helper macro for descriptor handling * Always use AXGBE_GET_DESC_DATA to access the descriptor data * since the index is free-running and needs to be and-ed @@ -290,6 +305,13 @@ struct axgbe_hw_if { int (*config_tx_flow_control)(struct axgbe_port *); int (*config_rx_flow_control)(struct axgbe_port *); + /* vlan */ + int (*enable_rx_vlan_stripping)(struct axgbe_port *); + int (*disable_rx_vlan_stripping)(struct axgbe_port *); + int (*enable_rx_vlan_filtering)(struct axgbe_port *); + int (*disable_rx_vlan_filtering)(struct axgbe_port *); + int (*update_vlan_hash_table)(struct axgbe_port *); + int (*exit)(struct axgbe_port *); }; @@ -337,6 +359,10 @@ struct axgbe_phy_impl_if { /* Process results of auto-negotiation */ enum axgbe_mode (*an_outcome)(struct axgbe_port *); + /* Pre/Post auto-negotiation support */ + void (*an_pre)(struct axgbe_port *port); + void (*an_post)(struct axgbe_port *port); + /* Pre/Post KR training enablement support */ void (*kr_training_pre)(struct axgbe_port *); void (*kr_training_post)(struct axgbe_port *); @@ -420,6 +446,12 @@ struct axgbe_hw_features { unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ unsigned int pps_out_num; /* Number of PPS outputs */ unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ + + /* HW Feature Register3 */ + unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */ + /* insertion on Tx Enable */ + unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */ + /* Filters Enabled */ }; struct axgbe_version_data { @@ -431,6 +463,64 @@ struct axgbe_version_data { unsigned int tx_tstamp_workaround; unsigned int ecc_support; unsigned int i2c_support; + unsigned int an_cdr_workaround; +}; + +struct axgbe_mmc_stats { + /* Tx Stats */ + uint64_t txoctetcount_gb; + uint64_t txframecount_gb; + uint64_t txbroadcastframes_g; + uint64_t txmulticastframes_g; + uint64_t tx64octets_gb; + uint64_t tx65to127octets_gb; + uint64_t tx128to255octets_gb; + uint64_t tx256to511octets_gb; + uint64_t tx512to1023octets_gb; + uint64_t tx1024tomaxoctets_gb; + uint64_t txunicastframes_gb; + uint64_t txmulticastframes_gb; + uint64_t txbroadcastframes_gb; + uint64_t txunderflowerror; + uint64_t txoctetcount_g; + uint64_t txframecount_g; + uint64_t txpauseframes; + uint64_t txvlanframes_g; + + /* Rx Stats */ + uint64_t rxframecount_gb; + uint64_t rxoctetcount_gb; + uint64_t rxoctetcount_g; + uint64_t rxbroadcastframes_g; + uint64_t rxmulticastframes_g; + uint64_t rxcrcerror; + uint64_t rxrunterror; + uint64_t rxjabbererror; + uint64_t rxundersize_g; + uint64_t rxoversize_g; + uint64_t rx64octets_gb; + uint64_t rx65to127octets_gb; + uint64_t rx128to255octets_gb; + uint64_t rx256to511octets_gb; + uint64_t rx512to1023octets_gb; + uint64_t rx1024tomaxoctets_gb; + uint64_t rxunicastframes_g; + uint64_t rxlengtherror; + uint64_t rxoutofrangetype; + uint64_t rxpauseframes; + uint64_t rxfifooverflow; + uint64_t rxvlanframes_gb; + uint64_t rxwatchdogerror; +}; + +/* Flow control parameters */ +struct xgbe_fc_info { + uint32_t high_water[AXGBE_PRIORITY_QUEUES]; + uint32_t low_water[AXGBE_PRIORITY_QUEUES]; + uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; + uint16_t send_xon; + enum rte_eth_fc_mode mode; + uint8_t autoneg; }; /* @@ -450,6 +540,7 @@ struct axgbe_port { void *xprop_regs; /* AXGBE property registers */ void *xi2c_regs; /* AXGBE I2C CSRs */ + bool cdr_track_early; /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; unsigned int xpcs_window_sel_reg; @@ -458,7 +549,7 @@ struct axgbe_port { unsigned int xpcs_window_mask; /* Flags representing axgbe_state */ - unsigned long dev_state; + uint32_t dev_state; struct axgbe_hw_if hw_if; struct axgbe_phy_if phy_if; @@ -523,17 +614,19 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; uint32_t rss_options; int rss_enable; + uint64_t rss_hf; /* Hardware features of the device */ struct axgbe_hw_features hw_feat; - struct ether_addr mac_addr; + struct rte_ether_addr mac_addr; /* Software Tx/Rx structure pointers*/ void **rx_queues; @@ -570,11 +663,34 @@ struct axgbe_port { int crc_strip_enable; /* csum enable to hardware */ uint32_t rx_csum_enable; + + struct axgbe_mmc_stats mmc_stats; + struct xgbe_fc_info fc; + + /* Hash filtering */ + unsigned int hash_table_shift; + unsigned int hash_table_count; + unsigned int uc_hash_mac_addr; + unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; + + /* Filtering support */ + unsigned long active_vlans[VLAN_TABLE_SIZE]; + + /* For IEEE1588 PTP */ + struct rte_timecounter systime_tc; + struct rte_timecounter tx_tstamp; + unsigned int tstamp_addend; + }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); +void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, + uint32_t index); +void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); +int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); +int axgbe_write_rss_hash_key(struct axgbe_port *pdata); #endif /* RTE_ETH_AXGBE_H_ */