X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_ethdev.h;h=a6226729fe4d3e8c4bebcc3eaa9f0c4cd1dbf300;hb=83680d371592fcf1b66cbbfecb0fb8b3aa4ccc8d;hp=effb132970d4d35ba501a919dc63b315ebe2477f;hpb=572890ef662595f2fac87d781bd376db849a821e;p=dpdk.git diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index effb132970..a6226729fe 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -9,6 +9,18 @@ #include #include #include "axgbe_common.h" +#include "rte_time.h" + +#define IRQ 0xff +#define VLAN_HLEN 4 + +#define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) +#define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) +#define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) +#define AXGBE_MAX_MAC_ADDRS 32 +#define AXGBE_MAX_HASH_MAC_ADDRS 256 + +#define AXGBE_RX_BUF_ALIGN 64 #define AXGBE_MAX_DMA_CHANNELS 16 #define AXGBE_MAX_QUEUES 16 @@ -25,6 +37,23 @@ #define AXGBE_DMA_SYS_ARCACHE 0x0 #define AXGBE_DMA_SYS_AWCACHE 0x0 +/* DMA channel interrupt modes */ +#define AXGBE_IRQ_MODE_EDGE 0 +#define AXGBE_IRQ_MODE_LEVEL 1 + +#define AXGBE_DMA_INTERRUPT_MASK 0x31c7 + +#define AXGMAC_MIN_PACKET 60 +#define AXGMAC_STD_PACKET_MTU 1500 +#define AXGMAC_MAX_STD_PACKET 1518 +#define AXGMAC_JUMBO_PACKET_MTU 9000 +#define AXGMAC_MAX_JUMBO_PACKET 9018 +/* Inter-frame gap + preamble */ +#define AXGMAC_ETH_PREAMBLE (12 + 8) + +#define AXGMAC_PFC_DATA_LEN 46 +#define AXGMAC_PFC_DELAYS 14000 + /* PCI BAR mapping */ #define AXGBE_AXGMAC_BAR 0 #define AXGBE_XPCS_BAR 1 @@ -35,6 +64,13 @@ #define AXGBE_V2_DMA_CLOCK_FREQ 500000000 #define AXGBE_V2_PTP_CLOCK_FREQ 125000000 +/* Timestamp support - values based on 50MHz PTP clock + * 50MHz => 20 nsec + */ +#define AXGBE_TSTAMP_SSINC 20 +#define AXGBE_TSTAMP_SNSINC 0 +#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL + #define AXGMAC_FIFO_MIN_ALLOC 2048 #define AXGMAC_FIFO_UNIT 256 #define AXGMAC_FIFO_ALIGN(_x) \ @@ -56,7 +92,7 @@ (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) #define AXGMAC_FLOW_CONTROL_MAX 33280 -/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +/* Maximum MAC address hash table size (256 bits = 8 dword) */ #define AXGBE_MAC_HASH_TABLE_SIZE 8 /* Receive Side Scaling */ @@ -89,6 +125,12 @@ /* MDIO port types */ #define AXGMAC_MAX_C22_PORT 3 +/* The max frame size with default MTU */ +#define AXGBE_ETH_MAX_LEN ( \ + RTE_ETHER_MTU + \ + RTE_ETHER_HDR_LEN + \ + RTE_ETHER_CRC_LEN) + /* Helper macro for descriptor handling * Always use AXGBE_GET_DESC_DATA to access the descriptor data * since the index is free-running and needs to be and-ed @@ -189,6 +231,61 @@ enum axgbe_mdio_mode { AXGBE_MDIO_MODE_CL45, }; +struct axgbe_phy { + uint32_t supported; + uint32_t advertising; + uint32_t lp_advertising; + + int address; + + int autoneg; + int speed; + int duplex; + + int link; + + int pause_autoneg; + int tx_pause; + int rx_pause; +}; + +enum axgbe_i2c_cmd { + AXGBE_I2C_CMD_READ = 0, + AXGBE_I2C_CMD_WRITE, +}; + +struct axgbe_i2c_op { + enum axgbe_i2c_cmd cmd; + + unsigned int target; + + uint8_t *buf; + unsigned int len; +}; + +struct axgbe_i2c_op_state { + struct axgbe_i2c_op *op; + + unsigned int tx_len; + unsigned char *tx_buf; + + unsigned int rx_len; + unsigned char *rx_buf; + + unsigned int tx_abort_source; + + int ret; +}; + +struct axgbe_i2c { + unsigned int started; + unsigned int max_speed_mode; + unsigned int rx_fifo_size; + unsigned int tx_fifo_size; + + struct axgbe_i2c_op_state op_state; +}; + struct axgbe_hw_if { void (*config_flow_control)(struct axgbe_port *); int (*config_rx_mode)(struct axgbe_port *); @@ -208,9 +305,103 @@ struct axgbe_hw_if { int (*config_tx_flow_control)(struct axgbe_port *); int (*config_rx_flow_control)(struct axgbe_port *); + /* vlan */ + int (*enable_rx_vlan_stripping)(struct axgbe_port *); + int (*disable_rx_vlan_stripping)(struct axgbe_port *); + int (*enable_rx_vlan_filtering)(struct axgbe_port *); + int (*disable_rx_vlan_filtering)(struct axgbe_port *); + int (*update_vlan_hash_table)(struct axgbe_port *); + int (*exit)(struct axgbe_port *); }; +/* This structure represents implementation specific routines for an + * implementation of a PHY. All routines are required unless noted below. + * Optional routines: + * kr_training_pre, kr_training_post + */ +struct axgbe_phy_impl_if { + /* Perform Setup/teardown actions */ + int (*init)(struct axgbe_port *); + void (*exit)(struct axgbe_port *); + + /* Perform start/stop specific actions */ + int (*reset)(struct axgbe_port *); + int (*start)(struct axgbe_port *); + void (*stop)(struct axgbe_port *); + + /* Return the link status */ + int (*link_status)(struct axgbe_port *, int *); + + /* Indicate if a particular speed is valid */ + int (*valid_speed)(struct axgbe_port *, int); + + /* Check if the specified mode can/should be used */ + bool (*use_mode)(struct axgbe_port *, enum axgbe_mode); + /* Switch the PHY into various modes */ + void (*set_mode)(struct axgbe_port *, enum axgbe_mode); + /* Retrieve mode needed for a specific speed */ + enum axgbe_mode (*get_mode)(struct axgbe_port *, int); + /* Retrieve new/next mode when trying to auto-negotiate */ + enum axgbe_mode (*switch_mode)(struct axgbe_port *); + /* Retrieve current mode */ + enum axgbe_mode (*cur_mode)(struct axgbe_port *); + + /* Retrieve current auto-negotiation mode */ + enum axgbe_an_mode (*an_mode)(struct axgbe_port *); + + /* Configure auto-negotiation settings */ + int (*an_config)(struct axgbe_port *); + + /* Set/override auto-negotiation advertisement settings */ + unsigned int (*an_advertising)(struct axgbe_port *port); + + /* Process results of auto-negotiation */ + enum axgbe_mode (*an_outcome)(struct axgbe_port *); + + /* Pre/Post auto-negotiation support */ + void (*an_pre)(struct axgbe_port *port); + void (*an_post)(struct axgbe_port *port); + + /* Pre/Post KR training enablement support */ + void (*kr_training_pre)(struct axgbe_port *); + void (*kr_training_post)(struct axgbe_port *); +}; + +struct axgbe_phy_if { + /* For PHY setup/teardown */ + int (*phy_init)(struct axgbe_port *); + void (*phy_exit)(struct axgbe_port *); + + /* For PHY support when setting device up/down */ + int (*phy_reset)(struct axgbe_port *); + int (*phy_start)(struct axgbe_port *); + void (*phy_stop)(struct axgbe_port *); + + /* For PHY support while device is up */ + void (*phy_status)(struct axgbe_port *); + int (*phy_config_aneg)(struct axgbe_port *); + + /* For PHY settings validation */ + int (*phy_valid_speed)(struct axgbe_port *, int); + /* For single interrupt support */ + void (*an_isr)(struct axgbe_port *); + /* PHY implementation specific services */ + struct axgbe_phy_impl_if phy_impl; +}; + +struct axgbe_i2c_if { + /* For initial I2C setup */ + int (*i2c_init)(struct axgbe_port *); + + /* For I2C support when setting device up/down */ + int (*i2c_start)(struct axgbe_port *); + void (*i2c_stop)(struct axgbe_port *); + + /* For performing I2C operations */ + int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *); +}; + /* This structure contains flags that indicate what hardware features * or configurations are present in the device. */ @@ -255,9 +446,16 @@ struct axgbe_hw_features { unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ unsigned int pps_out_num; /* Number of PPS outputs */ unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ + + /* HW Feature Register3 */ + unsigned int tx_q_vlan_tag_ins; /* Queue/Channel based VLAN tag */ + /* insertion on Tx Enable */ + unsigned int no_of_vlan_extn; /* Number of Extended VLAN Tag */ + /* Filters Enabled */ }; struct axgbe_version_data { + void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *); enum axgbe_xpcs_access xpcs_access; unsigned int mmc_64bit; unsigned int tx_max_fifo_size; @@ -265,6 +463,64 @@ struct axgbe_version_data { unsigned int tx_tstamp_workaround; unsigned int ecc_support; unsigned int i2c_support; + unsigned int an_cdr_workaround; +}; + +struct axgbe_mmc_stats { + /* Tx Stats */ + uint64_t txoctetcount_gb; + uint64_t txframecount_gb; + uint64_t txbroadcastframes_g; + uint64_t txmulticastframes_g; + uint64_t tx64octets_gb; + uint64_t tx65to127octets_gb; + uint64_t tx128to255octets_gb; + uint64_t tx256to511octets_gb; + uint64_t tx512to1023octets_gb; + uint64_t tx1024tomaxoctets_gb; + uint64_t txunicastframes_gb; + uint64_t txmulticastframes_gb; + uint64_t txbroadcastframes_gb; + uint64_t txunderflowerror; + uint64_t txoctetcount_g; + uint64_t txframecount_g; + uint64_t txpauseframes; + uint64_t txvlanframes_g; + + /* Rx Stats */ + uint64_t rxframecount_gb; + uint64_t rxoctetcount_gb; + uint64_t rxoctetcount_g; + uint64_t rxbroadcastframes_g; + uint64_t rxmulticastframes_g; + uint64_t rxcrcerror; + uint64_t rxrunterror; + uint64_t rxjabbererror; + uint64_t rxundersize_g; + uint64_t rxoversize_g; + uint64_t rx64octets_gb; + uint64_t rx65to127octets_gb; + uint64_t rx128to255octets_gb; + uint64_t rx256to511octets_gb; + uint64_t rx512to1023octets_gb; + uint64_t rx1024tomaxoctets_gb; + uint64_t rxunicastframes_g; + uint64_t rxlengtherror; + uint64_t rxoutofrangetype; + uint64_t rxpauseframes; + uint64_t rxfifooverflow; + uint64_t rxvlanframes_gb; + uint64_t rxwatchdogerror; +}; + +/* Flow control parameters */ +struct xgbe_fc_info { + uint32_t high_water[AXGBE_PRIORITY_QUEUES]; + uint32_t low_water[AXGBE_PRIORITY_QUEUES]; + uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; + uint16_t send_xon; + enum rte_eth_fc_mode mode; + uint8_t autoneg; }; /* @@ -279,11 +535,12 @@ struct axgbe_port { struct axgbe_version_data *vdata; /* AXGMAC/XPCS related mmio registers */ - uint64_t xgmac_regs; /* AXGMAC CSRs */ - uint64_t xpcs_regs; /* XPCS MMD registers */ - uint64_t xprop_regs; /* AXGBE property registers */ - uint64_t xi2c_regs; /* AXGBE I2C CSRs */ + void *xgmac_regs; /* AXGMAC CSRs */ + void *xpcs_regs; /* XPCS MMD registers */ + void *xprop_regs; /* AXGBE property registers */ + void *xi2c_regs; /* AXGBE I2C CSRs */ + bool cdr_track_early; /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; unsigned int xpcs_window_sel_reg; @@ -292,9 +549,11 @@ struct axgbe_port { unsigned int xpcs_window_mask; /* Flags representing axgbe_state */ - unsigned long dev_state; + uint32_t dev_state; struct axgbe_hw_if hw_if; + struct axgbe_phy_if phy_if; + struct axgbe_i2c_if i2c_if; /* AXI DMA settings */ unsigned int coherent; @@ -355,18 +614,83 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; uint32_t rss_options; int rss_enable; + uint64_t rss_hf; /* Hardware features of the device */ struct axgbe_hw_features hw_feat; - struct ether_addr mac_addr; + struct rte_ether_addr mac_addr; + + /* Software Tx/Rx structure pointers*/ + void **rx_queues; + void **tx_queues; + + /* MDIO/PHY related settings */ + unsigned int phy_started; + void *phy_data; + struct axgbe_phy phy; + int mdio_mmd; + unsigned long link_check; + volatile int mdio_completion; + + unsigned int kr_redrv; + + /* Auto-negotiation atate machine support */ + unsigned int an_int; + unsigned int an_status; + enum axgbe_an an_result; + enum axgbe_an an_state; + enum axgbe_rx kr_state; + enum axgbe_rx kx_state; + unsigned int an_supported; + unsigned int parallel_detect; + unsigned int fec_ability; + unsigned long an_start; + enum axgbe_an_mode an_mode; + + /* I2C support */ + struct axgbe_i2c i2c; + volatile int i2c_complete; + + /* CRC stripping by H/w for Rx packet*/ + int crc_strip_enable; + /* csum enable to hardware */ + uint32_t rx_csum_enable; + + struct axgbe_mmc_stats mmc_stats; + struct xgbe_fc_info fc; + + /* Hash filtering */ + unsigned int hash_table_shift; + unsigned int hash_table_count; + unsigned int uc_hash_mac_addr; + unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; + + /* Filtering support */ + unsigned long active_vlans[VLAN_TABLE_SIZE]; + + /* For IEEE1588 PTP */ + struct rte_timecounter systime_tc; + struct rte_timecounter tx_tstamp; + unsigned int tstamp_addend; + }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); +void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); +void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); +void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); +void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, + uint32_t index); +void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); +int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); +int axgbe_write_rss_hash_key(struct axgbe_port *pdata); + #endif /* RTE_ETH_AXGBE_H_ */