X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_ethdev.h;h=bb759ffe3506aba0b0b688557dfad41c916a6d4e;hb=675911d0330b0802e845657c3f4edc5886cf8685;hp=17e9e4146593b0755beb75479bc5ddd42382c8e0;hpb=4ac7516b8b390038a29481aacfb461565f177b29;p=dpdk.git diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 17e9e41465..bb759ffe35 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -10,6 +10,17 @@ #include #include "axgbe_common.h" +#define IRQ 0xff +#define VLAN_HLEN 4 + +#define AXGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) +#define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) +#define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) +#define AXGBE_MAX_MAC_ADDRS 32 +#define AXGBE_MAX_HASH_MAC_ADDRS 256 + +#define AXGBE_RX_BUF_ALIGN 64 + #define AXGBE_MAX_DMA_CHANNELS 16 #define AXGBE_MAX_QUEUES 16 #define AXGBE_PRIORITY_QUEUES 8 @@ -25,6 +36,23 @@ #define AXGBE_DMA_SYS_ARCACHE 0x0 #define AXGBE_DMA_SYS_AWCACHE 0x0 +/* DMA channel interrupt modes */ +#define AXGBE_IRQ_MODE_EDGE 0 +#define AXGBE_IRQ_MODE_LEVEL 1 + +#define AXGBE_DMA_INTERRUPT_MASK 0x31c7 + +#define AXGMAC_MIN_PACKET 60 +#define AXGMAC_STD_PACKET_MTU 1500 +#define AXGMAC_MAX_STD_PACKET 1518 +#define AXGMAC_JUMBO_PACKET_MTU 9000 +#define AXGMAC_MAX_JUMBO_PACKET 9018 +/* Inter-frame gap + preamble */ +#define AXGMAC_ETH_PREAMBLE (12 + 8) + +#define AXGMAC_PFC_DATA_LEN 46 +#define AXGMAC_PFC_DELAYS 14000 + /* PCI BAR mapping */ #define AXGBE_AXGMAC_BAR 0 #define AXGBE_XPCS_BAR 1 @@ -56,7 +84,7 @@ (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) #define AXGMAC_FLOW_CONTROL_MAX 33280 -/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +/* Maximum MAC address hash table size (256 bits = 8 dword) */ #define AXGBE_MAC_HASH_TABLE_SIZE 8 /* Receive Side Scaling */ @@ -310,6 +338,10 @@ struct axgbe_phy_impl_if { /* Process results of auto-negotiation */ enum axgbe_mode (*an_outcome)(struct axgbe_port *); + /* Pre/Post auto-negotiation support */ + void (*an_pre)(struct axgbe_port *port); + void (*an_post)(struct axgbe_port *port); + /* Pre/Post KR training enablement support */ void (*kr_training_pre)(struct axgbe_port *); void (*kr_training_post)(struct axgbe_port *); @@ -404,6 +436,64 @@ struct axgbe_version_data { unsigned int tx_tstamp_workaround; unsigned int ecc_support; unsigned int i2c_support; + unsigned int an_cdr_workaround; +}; + +struct axgbe_mmc_stats { + /* Tx Stats */ + uint64_t txoctetcount_gb; + uint64_t txframecount_gb; + uint64_t txbroadcastframes_g; + uint64_t txmulticastframes_g; + uint64_t tx64octets_gb; + uint64_t tx65to127octets_gb; + uint64_t tx128to255octets_gb; + uint64_t tx256to511octets_gb; + uint64_t tx512to1023octets_gb; + uint64_t tx1024tomaxoctets_gb; + uint64_t txunicastframes_gb; + uint64_t txmulticastframes_gb; + uint64_t txbroadcastframes_gb; + uint64_t txunderflowerror; + uint64_t txoctetcount_g; + uint64_t txframecount_g; + uint64_t txpauseframes; + uint64_t txvlanframes_g; + + /* Rx Stats */ + uint64_t rxframecount_gb; + uint64_t rxoctetcount_gb; + uint64_t rxoctetcount_g; + uint64_t rxbroadcastframes_g; + uint64_t rxmulticastframes_g; + uint64_t rxcrcerror; + uint64_t rxrunterror; + uint64_t rxjabbererror; + uint64_t rxundersize_g; + uint64_t rxoversize_g; + uint64_t rx64octets_gb; + uint64_t rx65to127octets_gb; + uint64_t rx128to255octets_gb; + uint64_t rx256to511octets_gb; + uint64_t rx512to1023octets_gb; + uint64_t rx1024tomaxoctets_gb; + uint64_t rxunicastframes_g; + uint64_t rxlengtherror; + uint64_t rxoutofrangetype; + uint64_t rxpauseframes; + uint64_t rxfifooverflow; + uint64_t rxvlanframes_gb; + uint64_t rxwatchdogerror; +}; + +/* Flow control parameters */ +struct xgbe_fc_info { + uint32_t high_water[AXGBE_PRIORITY_QUEUES]; + uint32_t low_water[AXGBE_PRIORITY_QUEUES]; + uint16_t pause_time[AXGBE_PRIORITY_QUEUES]; + uint16_t send_xon; + enum rte_eth_fc_mode mode; + uint8_t autoneg; }; /* @@ -418,11 +508,12 @@ struct axgbe_port { struct axgbe_version_data *vdata; /* AXGMAC/XPCS related mmio registers */ - uint64_t xgmac_regs; /* AXGMAC CSRs */ - uint64_t xpcs_regs; /* XPCS MMD registers */ - uint64_t xprop_regs; /* AXGBE property registers */ - uint64_t xi2c_regs; /* AXGBE I2C CSRs */ + void *xgmac_regs; /* AXGMAC CSRs */ + void *xpcs_regs; /* XPCS MMD registers */ + void *xprop_regs; /* AXGBE property registers */ + void *xi2c_regs; /* AXGBE I2C CSRs */ + bool cdr_track_early; /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; unsigned int xpcs_window_sel_reg; @@ -431,7 +522,7 @@ struct axgbe_port { unsigned int xpcs_window_mask; /* Flags representing axgbe_state */ - unsigned long dev_state; + uint32_t dev_state; struct axgbe_hw_if hw_if; struct axgbe_phy_if phy_if; @@ -496,17 +587,23 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE]; uint32_t rss_options; int rss_enable; + uint64_t rss_hf; /* Hardware features of the device */ struct axgbe_hw_features hw_feat; - struct ether_addr mac_addr; + struct rte_ether_addr mac_addr; + + /* Software Tx/Rx structure pointers*/ + void **rx_queues; + void **tx_queues; /* MDIO/PHY related settings */ unsigned int phy_started; @@ -534,11 +631,30 @@ struct axgbe_port { /* I2C support */ struct axgbe_i2c i2c; volatile int i2c_complete; + + /* CRC stripping by H/w for Rx packet*/ + int crc_strip_enable; + /* csum enable to hardware */ + uint32_t rx_csum_enable; + + struct axgbe_mmc_stats mmc_stats; + struct xgbe_fc_info fc; + + /* Hash filtering */ + unsigned int hash_table_shift; + unsigned int hash_table_count; + unsigned int uc_hash_mac_addr; + unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if); void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); +void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, + uint32_t index); +void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); +int axgbe_write_rss_lookup_table(struct axgbe_port *pdata); +int axgbe_write_rss_hash_key(struct axgbe_port *pdata); #endif /* RTE_ETH_AXGBE_H_ */