X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_ethdev.h;h=e4c7c8f83669db723c90ab606d362d1dc08e2ccf;hb=cf97f33e8b2a3e9039836ed6337dccc67c4d2696;hp=e977448d15bcd092721fdebb767647c86dfbd0ea;hpb=9e890103267ebe1f680f88d58ff2a0bb229c603b;p=dpdk.git

diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index e977448d15..e4c7c8f836 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -15,8 +15,9 @@
 
 #define AXGBE_TX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
 #define AXGBE_RX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
-#define AXGBE_RX_MIN_BUF_SIZE		(ETHER_MAX_LEN + VLAN_HLEN)
-#define AXGBE_MAX_MAC_ADDRS		1
+#define AXGBE_RX_MIN_BUF_SIZE		(RTE_ETHER_MAX_LEN + VLAN_HLEN)
+#define AXGBE_MAX_MAC_ADDRS		32
+#define AXGBE_MAX_HASH_MAC_ADDRS	256
 
 #define AXGBE_RX_BUF_ALIGN		64
 
@@ -83,7 +84,7 @@
 	(((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
 #define AXGMAC_FLOW_CONTROL_MAX		33280
 
-/* Maximum MAC address hash table size (256 bits = 8 bytes) */
+/* Maximum MAC address hash table size (256 bits = 8 dword) */
 #define AXGBE_MAC_HASH_TABLE_SIZE	8
 
 /* Receive Side Scaling */
@@ -337,6 +338,10 @@ struct axgbe_phy_impl_if {
 	/* Process results of auto-negotiation */
 	enum axgbe_mode (*an_outcome)(struct axgbe_port *);
 
+	/* Pre/Post auto-negotiation support */
+	void (*an_pre)(struct axgbe_port *port);
+	void (*an_post)(struct axgbe_port *port);
+
 	/* Pre/Post KR training enablement support */
 	void (*kr_training_pre)(struct axgbe_port *);
 	void (*kr_training_post)(struct axgbe_port *);
@@ -431,6 +436,64 @@ struct axgbe_version_data {
 	unsigned int tx_tstamp_workaround;
 	unsigned int ecc_support;
 	unsigned int i2c_support;
+	unsigned int an_cdr_workaround;
+};
+
+struct axgbe_mmc_stats {
+	/* Tx Stats */
+	uint64_t txoctetcount_gb;
+	uint64_t txframecount_gb;
+	uint64_t txbroadcastframes_g;
+	uint64_t txmulticastframes_g;
+	uint64_t tx64octets_gb;
+	uint64_t tx65to127octets_gb;
+	uint64_t tx128to255octets_gb;
+	uint64_t tx256to511octets_gb;
+	uint64_t tx512to1023octets_gb;
+	uint64_t tx1024tomaxoctets_gb;
+	uint64_t txunicastframes_gb;
+	uint64_t txmulticastframes_gb;
+	uint64_t txbroadcastframes_gb;
+	uint64_t txunderflowerror;
+	uint64_t txoctetcount_g;
+	uint64_t txframecount_g;
+	uint64_t txpauseframes;
+	uint64_t txvlanframes_g;
+
+	/* Rx Stats */
+	uint64_t rxframecount_gb;
+	uint64_t rxoctetcount_gb;
+	uint64_t rxoctetcount_g;
+	uint64_t rxbroadcastframes_g;
+	uint64_t rxmulticastframes_g;
+	uint64_t rxcrcerror;
+	uint64_t rxrunterror;
+	uint64_t rxjabbererror;
+	uint64_t rxundersize_g;
+	uint64_t rxoversize_g;
+	uint64_t rx64octets_gb;
+	uint64_t rx65to127octets_gb;
+	uint64_t rx128to255octets_gb;
+	uint64_t rx256to511octets_gb;
+	uint64_t rx512to1023octets_gb;
+	uint64_t rx1024tomaxoctets_gb;
+	uint64_t rxunicastframes_g;
+	uint64_t rxlengtherror;
+	uint64_t rxoutofrangetype;
+	uint64_t rxpauseframes;
+	uint64_t rxfifooverflow;
+	uint64_t rxvlanframes_gb;
+	uint64_t rxwatchdogerror;
+};
+
+/* Flow control parameters */
+struct xgbe_fc_info {
+	uint32_t high_water[AXGBE_PRIORITY_QUEUES];
+	uint32_t low_water[AXGBE_PRIORITY_QUEUES];
+	uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
+	uint16_t send_xon;
+	enum rte_eth_fc_mode mode;
+	uint8_t autoneg;
 };
 
 /*
@@ -445,11 +508,12 @@ struct axgbe_port {
 	struct axgbe_version_data *vdata;
 
 	/* AXGMAC/XPCS related mmio registers */
-	uint64_t xgmac_regs;	/* AXGMAC CSRs */
-	uint64_t xpcs_regs;	/* XPCS MMD registers */
-	uint64_t xprop_regs;	/* AXGBE property registers */
-	uint64_t xi2c_regs;	/* AXGBE I2C CSRs */
+	void *xgmac_regs;	/* AXGMAC CSRs */
+	void *xpcs_regs;	/* XPCS MMD registers */
+	void *xprop_regs;	/* AXGBE property registers */
+	void *xi2c_regs;	/* AXGBE I2C CSRs */
 
+	bool cdr_track_early;
 	/* XPCS indirect addressing lock */
 	unsigned int xpcs_window_def_reg;
 	unsigned int xpcs_window_sel_reg;
@@ -533,7 +597,7 @@ struct axgbe_port {
 	/* Hardware features of the device */
 	struct axgbe_hw_features hw_feat;
 
-	struct ether_addr mac_addr;
+	struct rte_ether_addr mac_addr;
 
 	/* Software Tx/Rx structure pointers*/
 	void **rx_queues;
@@ -570,11 +634,23 @@ struct axgbe_port {
 	int crc_strip_enable;
 	/* csum enable to hardware */
 	uint32_t rx_csum_enable;
+
+	struct axgbe_mmc_stats mmc_stats;
+	struct xgbe_fc_info fc;
+
+	/* Hash filtering */
+	unsigned int hash_table_shift;
+	unsigned int hash_table_count;
+	unsigned int uc_hash_mac_addr;
+	unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE];
 };
 
 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
+void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr,
+			     uint32_t index);
+void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add);
 
 #endif /* RTE_ETH_AXGBE_H_ */