X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2x%2Fbnx2x.c;h=fb02d0f35220e9d331872d0d85f4dc5c965a5113;hb=b853efa574b4823be7c3bfb9bffae92c93433dd3;hp=44222af2f1d59447424cbb34949eea16971a6c8f;hpb=ea859a45b85db4de1361dda23c932b9243b0fab9;p=dpdk.git diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index 44222af2f1..fb02d0f352 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -184,7 +184,7 @@ bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma, PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg); return -ENOMEM; } - dma->paddr = (uint64_t) z->phys_addr; + dma->paddr = (uint64_t) z->iova; dma->vaddr = z->addr; PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr); @@ -419,7 +419,7 @@ void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32) } void -bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr, +bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr, uint32_t len32) { struct dmae_command dmae; @@ -447,7 +447,7 @@ bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr } static void -bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr, +bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr, uint32_t addr, uint32_t len) { uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc); @@ -823,14 +823,14 @@ bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param) static void __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr, - phys_addr_t mapping) + rte_iova_t mapping) { REG_WR(sc, addr, U64_LO(mapping)); REG_WR(sc, (addr + 4), U64_HI(mapping)); } static void -storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping, +storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping, uint16_t abs_fid) { uint32_t addr = (XSEM_REG_FAST_MEMORY + @@ -1130,9 +1130,7 @@ static void bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) { -#ifdef RTE_LIBRTE_BNX2X_DEBUG int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); -#endif int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX; struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj; @@ -1498,7 +1496,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id, ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata); ramrod_param.rdata_mapping = - (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata), bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); ramrod_param.ramrod_flags = ramrod_flags; @@ -2135,7 +2133,7 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0) tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd; tx_start_bd->addr = - rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0)); + rte_cpu_to_le_64(rte_mbuf_data_iova(m0)); tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len); tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; tx_start_bd->general_data = @@ -4599,9 +4597,9 @@ static void bnx2x_init_func_obj(struct bnx2x_softc *sc) ecore_init_func_obj(sc, &sc->func_obj, BNX2X_SP(sc, func_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata), BNX2X_SP(sc, func_afex_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata), &bnx2x_func_sp_drv); } @@ -4772,7 +4770,7 @@ static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) } static void -bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid, +bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid, uint8_t vf_valid, int fw_sb_id, int igu_sb_id) { struct hc_status_block_data_e2 sb_data_e2; @@ -4918,7 +4916,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx) sc->max_cos, SC_FUNC(sc), BNX2X_SP(sc, q_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata), q_type); /* configure classification DBs */ @@ -4928,7 +4926,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx) idx, SC_FUNC(sc), BNX2X_SP(sc, mac_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata), ECORE_FILTER_MAC_PENDING, &sc->sp_state, ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool); } @@ -5028,7 +5026,7 @@ static void bnx2x_init_tx_rings(struct bnx2x_softc *sc) static void bnx2x_init_def_sb(struct bnx2x_softc *sc) { struct host_sp_status_block *def_sb = sc->def_sb; - phys_addr_t mapping = sc->def_sb_dma.paddr; + rte_iova_t mapping = sc->def_sb_dma.paddr; int igu_sp_sb_index; int igu_seg_id; int port = SC_PORT(sc); @@ -5700,7 +5698,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc) SC_FUNC(sc), SC_FUNC(sc), BNX2X_SP(sc, mcast_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata), ECORE_FILTER_MCAST_PENDING, &sc->sp_state, o_type); @@ -5724,7 +5722,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc) SC_FUNC(sc), SC_FUNC(sc), BNX2X_SP(sc, rss_rdata), - (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata), + (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata), ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state, ECORE_OBJ_TYPE_RX); } @@ -6445,9 +6443,9 @@ bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, pause->pri_map = 1; /* rxq setup */ - rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr; - rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr; - rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr + + rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr; + rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr; + rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr + BNX2X_PAGE_SIZE); /* @@ -6486,7 +6484,7 @@ bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, PMD_TX_LOG(ERR, "ERROR: TX queue is NULL"); return; } - txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr; + txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr; txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; txq_init->fw_sb_id = fp->fw_sb_id; @@ -7547,9 +7545,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc) struct bnx2x_pci_cap *caps; uint16_t link_status; -#ifdef RTE_LIBRTE_BNX2X_DEBUG int reg = 0; -#endif /* check if PCI Power Management is enabled */ caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP); @@ -8137,7 +8133,7 @@ static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc) continue; } fid = IGU_FID(val); - if ((fid & IGU_FID_ENCODE_IS_PF)) { + if (fid & IGU_FID_ENCODE_IS_PF) { if ((fid & IGU_FID_PF_NUM_MASK) != pfid) { continue; } @@ -11059,7 +11055,7 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc) for (i = 0; i < L2_ILT_LINES(sc); i++) { ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt; ilt->lines[cdu_ilt_start + i].page_mapping = - (phys_addr_t)sc->context[i].vcxt_dma.paddr; + (rte_iova_t)sc->context[i].vcxt_dma.paddr; ilt->lines[cdu_ilt_start + i].size = sc->context[i].size; } ecore_ilt_init_op(sc, INITOP_SET); @@ -11357,7 +11353,7 @@ static void bnx2x_reset_port(struct bnx2x_softc *sc) } } -static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr) +static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr) { int reg; uint32_t wb_write[2]; @@ -11587,7 +11583,7 @@ static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len) } static void -ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr, +ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr, uint32_t addr, uint32_t len) { bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);