X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2x%2Fbnx2x.h;h=1dbc98197d70e9c6b7b7448e5b1eddcf3f7235e3;hb=acec04c4b2f5c75d244319e1d0ca17ea7d4da72d;hp=4150fd85a30622bb790088cc1f41561aff1467ff;hpb=e3de5dad2a5dcb2594371bf3288b789002a1f7b5;p=dpdk.git diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 4150fd85a3..1dbc98197d 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1,4 +1,4 @@ -/*- +/* SPDX-License-Identifier: BSD-3-Clause * Copyright (c) 2007-2013 Broadcom Corporation. * * Eric Davis @@ -9,8 +9,6 @@ * Copyright (c) 2015-2018 Cavium Inc. * All rights reserved. * www.cavium.com - * - * See LICENSE.bnx2x_pmd for copyright and licensing details. */ #ifndef __BNX2X_H__ @@ -21,18 +19,7 @@ #include #include -#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN -#ifndef __LITTLE_ENDIAN -#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN -#endif -#undef __BIG_ENDIAN -#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN -#ifndef __BIG_ENDIAN -#define __BIG_ENDIAN RTE_BIG_ENDIAN -#endif -#undef __LITTLE_ENDIAN -#endif - +#include "bnx2x_osal.h" #include "bnx2x_ethdev.h" #include "ecore_mfw_req.h" #include "ecore_fw_defs.h" @@ -43,7 +30,7 @@ #include "elink.h" -#ifndef __FreeBSD__ +#ifndef RTE_EXEC_ENV_FREEBSD #include #define PCIY_PMG PCI_CAP_ID_PM @@ -73,7 +60,7 @@ #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */ #define IFM_10G_T 26 /* 10GBase-T - RJ45 */ -#ifndef __FreeBSD__ +#ifndef RTE_EXEC_ENV_FREEBSD #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA @@ -96,9 +83,6 @@ #ifndef ARRAY_SIZE #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) #endif -#ifndef ARRSIZE -#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) -#endif #ifndef DIV_ROUND_UP #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) #endif @@ -121,6 +105,8 @@ int bnx2x_ilog2(int x) #define ilog2(x) bnx2x_ilog2(x) #endif +#define BNX2X_BC_VER 0x040200 + #include "ecore_sp.h" struct bnx2x_device_type { @@ -155,13 +141,14 @@ struct bnx2x_device_type { * Transmit Buffer Descriptor (tx_bd) definitions* */ /* NUM_TX_PAGES must be a power of 2. */ +#define NUM_TX_PAGES 16 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */ #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */ #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */ #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */ #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */ - +#define MAX_TX_AVAIL (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES - 2) #define NEXT_TX_BD(x) \ ((((x) & USABLE_TX_BD_PER_PAGE) == \ (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1) @@ -182,13 +169,14 @@ struct bnx2x_device_type { /* * Receive Buffer Descriptor (rx_bd) definitions* */ -//#define NUM_RX_PAGES 1 +#define MAX_RX_PAGES 8 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */ #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */ #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */ #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */ #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */ #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */ +#define MAX_RX_AVAIL (USABLE_RX_BD_PER_PAGE * MAX_RX_PAGES - 2) #define RX_BD_NEXT_PAGE_DESC_CNT 2 #define NEXT_RX_BD(x) \ @@ -244,6 +232,10 @@ struct bnx2x_device_type { #define MIN_RX_AVAIL(sc) \ ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) +#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA +#define MIN_RX_SIZE_NONTPA (RTE_MAX((uint32_t)MIN_RX_SIZE_NONTPA_HW,\ + (uint32_t)MIN_RX_AVAIL(sc))) + /* * dropless fc calculations for RCQs * Number of RCQs should be as number of buffers in BRB: @@ -321,6 +313,7 @@ struct bnx2x_dma { rte_iova_t paddr; void *vaddr; int nseg; + const void *mzone; char msg[RTE_MEMZONE_NAMESIZE - 6]; }; @@ -367,6 +360,9 @@ struct bnx2x_fastpath { /* pointer back to parent structure */ struct bnx2x_softc *sc; + /* Used to synchronize fastpath Rx access */ + rte_spinlock_t rx_mtx; + /* status block */ struct bnx2x_dma sb_dma; union bnx2x_host_hc_status_block status_block; @@ -727,6 +723,13 @@ struct bnx2x_port { uint32_t phy_addr; + /* Used to synchronize phy accesses. */ + rte_spinlock_t phy_mtx; + char phy_mtx_name[32]; + +#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx) +#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx) + /* * MCP scratchpad address for port specific statistics. * The device is responsible for writing statistcss @@ -805,6 +808,10 @@ struct bnx2x_mf_info { /* Device information data structure. */ struct bnx2x_devinfo { +#if 1 +#define NAME_SIZE 128 + char name[NAME_SIZE]; +#endif /* PCIe info */ uint16_t vendor_id; uint16_t device_id; @@ -822,6 +829,7 @@ struct bnx2x_devinfo { #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) /* device ids */ +#define CHIP_NUM_57710 0x164e #define CHIP_NUM_57711 0x164f #define CHIP_NUM_57711E 0x1650 #define CHIP_NUM_57712 0x1662 @@ -863,6 +871,8 @@ struct bnx2x_devinfo { #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) +#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) +#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ @@ -1010,6 +1020,8 @@ struct bnx2x_pci_cap { uint16_t addr; }; +struct ecore_ilt; + struct bnx2x_vfdb; /* Top level device private data structure. */ @@ -1077,7 +1089,7 @@ struct bnx2x_softc { #define PERIODIC_STOP 0 #define PERIODIC_GO 1 volatile unsigned long periodic_flags; - + rte_atomic32_t scan_fp; struct bnx2x_fastpath fp[MAX_RSS_CHAINS]; struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS]; @@ -1420,7 +1432,7 @@ struct bnx2x_func_init_params { static inline void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) { - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } @@ -1430,10 +1442,10 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) { #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 2) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx", (unsigned long)offset); #endif - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val); rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); @@ -1444,11 +1456,11 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) { #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 4) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx", (unsigned long)offset); #endif - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } @@ -1459,7 +1471,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) uint8_t val; val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); return val; @@ -1472,12 +1484,12 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 2) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx", (unsigned long)offset); #endif val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return val; @@ -1490,12 +1502,12 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 4) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx", (unsigned long)offset); #endif val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return val; @@ -1693,6 +1705,73 @@ static const uint32_t dmae_reg_go_c[] = { GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) +#define HW_INTERRUT_ASSERT_SET_0 \ + (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) +#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) +#define HW_INTERRUT_ASSERT_SET_1 \ + (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) +#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) +#define HW_INTERRUT_ASSERT_SET_2 \ + (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ + AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) +#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) + +#define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \ + (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) + +#define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) + +#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ + AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) + #define MULTI_MASK 0x7f #define PFS_PER_PORT(sc) \ @@ -1741,7 +1820,7 @@ int bnx2x_cmpxchg(volatile int *addr, int old, int new); int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma, const char *msg, uint32_t align); - +void bnx2x_dma_free(struct bnx2x_dma *dma); uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode); uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type, @@ -1823,16 +1902,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm, { uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 + COMMAND_REG_INT_ACK); - union igu_ack_register igu_ack; + struct igu_ack_register igu_ack; + uint32_t *val = NULL; - igu_ack.sb.status_block_index = index; - igu_ack.sb.sb_id_and_flags = + igu_ack.status_block_index = index; + igu_ack.sb_id_and_flags = ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); - REG_WR(sc, hc_addr, igu_ack.raw_data); + val = (uint32_t *)&igu_ack; + REG_WR(sc, hc_addr, *val); /* Make sure that ACK is written */ mb(); @@ -1925,11 +2006,13 @@ void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count); int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0); uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp); void bnx2x_print_adapter_info(struct bnx2x_softc *sc); -int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp); +void bnx2x_print_device_info(struct bnx2x_softc *sc); +int bnx2x_intr_legacy(struct bnx2x_softc *sc); void bnx2x_link_status_update(struct bnx2x_softc *sc); int bnx2x_complete_sp(struct bnx2x_softc *sc); int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc); void bnx2x_periodic_callout(struct bnx2x_softc *sc); +void bnx2x_periodic_stop(void *param); int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count); void bnx2x_vf_close(struct bnx2x_softc *sc); @@ -1971,7 +2054,7 @@ bnx2x_set_rx_mode(struct bnx2x_softc *sc) bnx2x_vf_set_rx_mode(sc); } } else { - PMD_DRV_LOG(NOTICE, "Card is not ready to change mode"); + PMD_DRV_LOG(INFO, sc, "Card is not ready to change mode"); } } @@ -1979,7 +2062,7 @@ static inline int pci_read(struct bnx2x_softc *sc, size_t addr, void *val, uint8_t size) { if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't read from PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space"); return ENXIO; } @@ -1992,7 +2075,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val) if (rte_pci_write_config(sc->pci_dev, &val16, sizeof(val16), addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't write to PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); return ENXIO; } @@ -2004,7 +2087,7 @@ static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val) uint32_t val32 = val; if (rte_pci_write_config(sc->pci_dev, &val32, sizeof(val32), addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't write to PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); return ENXIO; }