X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2x%2Fecore_hsi.h;h=74189eed66a40cb2d2825769af5ab1e7a1c277fe;hb=902f389f9b4cad1feba320e8b779432eeb76cada;hp=5cce66474e0a6935eeb14bc4c12c8d06414d4723;hpb=98a7ea332ba3da0f74ec951595d36a616165b255;p=dpdk.git

diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h
index 5cce66474e..74189eed66 100644
--- a/drivers/net/bnx2x/ecore_hsi.h
+++ b/drivers/net/bnx2x/ecore_hsi.h
@@ -1,15 +1,13 @@
-/*-
- * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2007-2013 Broadcom Corporation.
  *
  * Eric Davis        <edavis@broadcom.com>
  * David Christensen <davidch@broadcom.com>
  * Gary Zambrano     <zambrano@broadcom.com>
  *
- * Copyright (c) 2014-2015 QLogic Corporation.
+ * Copyright (c) 2014-2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.bnx2x_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 #ifndef ECORE_HSI_H
@@ -502,6 +500,18 @@ struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */
 	#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
 	#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
 
+	/*  Set non-default values for TXFIR in SFP mode. */
+	#define PORT_HW_CFG_TX_DRV_IFIR_MASK                          0x00F00000
+	#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT                         20
+
+	/*  Set non-default values for IPREDRIVER in SFP mode. */
+	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK                    0x0F000000
+	#define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT                   24
+
+	/*  Set non-default values for POST2 in SFP mode. */
+	#define PORT_HW_CFG_TX_DRV_POST2_MASK                         0xF0000000
+	#define PORT_HW_CFG_TX_DRV_POST2_SHIFT                        28
+
 	uint32_t reserved0[5];				    /* 0x17c */
 
 	uint32_t aeu_int_mask;				    /* 0x190 */
@@ -785,6 +795,7 @@ struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722        0x00000f00
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616       0x00001000
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834       0x00001100
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858     0x00001200
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
 		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
@@ -2534,7 +2545,12 @@ struct shmem2_region {
 	uint32_t drv_func_info_addr;			/* Offset 0x14C */
 	uint32_t drv_func_info_size;			/* Offset 0x150 */
 	uint32_t link_attr_sync[PORT_MAX];		/* Offset 0x154 */
-	#define LINK_ATTR_SYNC_KR2_ENABLE	(1<<0)
+	#define LINK_ATTR_SYNC_KR2_ENABLE       0x00000001
+	#define LINK_ATTR_84858                 0x00000002
+	#define LINK_SFP_EEPROM_COMP_CODE_MASK  0x0000ff00
+	#define LINK_SFP_EEPROM_COMP_CODE_SHIFT          8
+
+	uint32_t link_change_count[PORT_MAX];		/* Offset 0x160-0x164 */
 };
 
 
@@ -3529,7 +3545,7 @@ struct igu_regular
 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags	 */
 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
-#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags	 */
 #define IGU_REGULAR_BCLEANUP_SHIFT 31
 	uint32_t reserved_2;
 };