X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt.h;h=8797b032ee146170296f1c721d1439156f306b47;hb=df6cd7c1f73a;hp=bdca2622fc05afa0c3b95daf752103da0d721462;hpb=472193a710567bfe245f697cdf688968fa485b02;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index bdca2622fc..8797b032ee 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -20,9 +20,39 @@ #include "bnxt_cpr.h" -#define BNXT_MAX_MTU 9500 +#define BNXT_MAX_MTU 9574 #define VLAN_TAG_SIZE 4 +#define BNXT_VF_RSV_NUM_RSS_CTX 1 +#define BNXT_VF_RSV_NUM_L2_CTX 4 +/* TODO: For now, do not support VMDq/RFS on VFs. */ +#define BNXT_VF_RSV_NUM_VNIC 1 #define BNXT_MAX_LED 4 +#define BNXT_NUM_VLANS 2 +#define BNXT_MIN_RING_DESC 16 +#define BNXT_MAX_TX_RING_DESC 4096 +#define BNXT_MAX_RX_RING_DESC 8192 +#define BNXT_DB_SIZE 0x80 + +#ifdef RTE_ARCH_ARM64 +#define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1) +#else +#define BNXT_NUM_ASYNC_CPR(bp) 1 +#endif + +/* Chimp Communication Channel */ +#define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 +#define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 +/* Kong Communication Channel */ +#define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 +#define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 + +#define BNXT_INT_LAT_TMR_MIN 75 +#define BNXT_INT_LAT_TMR_MAX 150 +#define BNXT_NUM_CMPL_AGGR_INT 36 +#define BNXT_CMPL_AGGR_DMA_TMR 37 +#define BNXT_NUM_CMPL_DMA_AGGR 36 +#define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 +#define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 struct bnxt_led_info { uint8_t led_id; @@ -97,6 +127,7 @@ struct bnxt_child_vf_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs) +#define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp)) @@ -104,6 +135,9 @@ struct bnxt_pf_info { uint16_t first_vf_id; uint16_t active_vfs; uint16_t max_vfs; + uint16_t total_vfs; /* Total VFs possible. + * Not necessarily enabled. + */ uint32_t func_cfg_flags; void *vf_req_buf; rte_iova_t vf_req_buf_dma_addr; @@ -201,6 +235,114 @@ struct bnxt_ptp_cfg { uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; }; +struct bnxt_coal { + uint16_t num_cmpl_aggr_int; + uint16_t num_cmpl_dma_aggr; + uint16_t num_cmpl_dma_aggr_during_int; + uint16_t int_lat_tmr_max; + uint16_t int_lat_tmr_min; + uint16_t cmpl_aggr_dma_tmr; + uint16_t cmpl_aggr_dma_tmr_during_int; +}; + +/* 64-bit doorbell */ +#define DBR_XID_SFT 32 +#define DBR_PATH_L2 (0x1ULL << 56) +#define DBR_TYPE_SQ (0x0ULL << 60) +#define DBR_TYPE_SRQ (0x2ULL << 60) +#define DBR_TYPE_CQ (0x4ULL << 60) +#define DBR_TYPE_NQ (0xaULL << 60) +#define DBR_TYPE_NQ_ARM (0xbULL << 60) + +#define BNXT_RSS_TBL_SIZE_THOR 512 +#define BNXT_RSS_ENTRIES_PER_CTX_THOR 64 +#define BNXT_MAX_RSS_CTXTS_THOR \ + (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR) + +#define BNXT_MAX_TC 8 +#define BNXT_MAX_QUEUE 8 +#define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) +#define BNXT_MAX_Q (bp->max_q + 1) +#define BNXT_PAGE_SHFT 12 +#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) +#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) + +#define PTU_PTE_VALID 0x1UL +#define PTU_PTE_LAST 0x2UL +#define PTU_PTE_NEXT_TO_LAST 0x4UL + +struct bnxt_ring_mem_info { + int nr_pages; + int page_size; + uint32_t flags; +#define BNXT_RMEM_VALID_PTE_FLAG 1 +#define BNXT_RMEM_RING_PTE_FLAG 2 + + void **pg_arr; + rte_iova_t *dma_arr; + const struct rte_memzone *mz; + + uint64_t *pg_tbl; + rte_iova_t pg_tbl_map; + const struct rte_memzone *pg_tbl_mz; + + int vmem_size; + void **vmem; +}; + +struct bnxt_ctx_pg_info { + uint32_t entries; + void *ctx_pg_arr[MAX_CTX_PAGES]; + rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; + struct bnxt_ring_mem_info ring_mem; +}; + +struct bnxt_ctx_mem_info { + uint32_t qp_max_entries; + uint16_t qp_min_qp1_entries; + uint16_t qp_max_l2_entries; + uint16_t qp_entry_size; + uint16_t srq_max_l2_entries; + uint32_t srq_max_entries; + uint16_t srq_entry_size; + uint16_t cq_max_l2_entries; + uint32_t cq_max_entries; + uint16_t cq_entry_size; + uint16_t vnic_max_vnic_entries; + uint16_t vnic_max_ring_table_entries; + uint16_t vnic_entry_size; + uint32_t stat_max_entries; + uint16_t stat_entry_size; + uint16_t tqm_entry_size; + uint32_t tqm_min_entries_per_ring; + uint32_t tqm_max_entries_per_ring; + uint32_t mrav_max_entries; + uint16_t mrav_entry_size; + uint16_t tim_entry_size; + uint32_t tim_max_entries; + uint8_t tqm_entries_multiple; + + uint32_t flags; +#define BNXT_CTX_FLAG_INITED 0x01 + + struct bnxt_ctx_pg_info qp_mem; + struct bnxt_ctx_pg_info srq_mem; + struct bnxt_ctx_pg_info cq_mem; + struct bnxt_ctx_pg_info vnic_mem; + struct bnxt_ctx_pg_info stat_mem; + struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; +}; + +/* Maximum Firmware Reset bail out value in milliseconds */ +#define BNXT_MAX_FW_RESET_TIMEOUT 6000 +/* Minimum time required for the firmware readiness in milliseconds */ +#define BNXT_MIN_FW_READY_TIMEOUT 2000 +/* Frequency for the firmware readiness check in milliseconds */ +#define BNXT_FW_READY_WAIT_INTERVAL 100 + +#define US_PER_MS 1000 +#define NS_PER_US 1000 + #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) struct bnxt { void *bar0; @@ -208,6 +350,7 @@ struct bnxt { struct rte_eth_dev *eth_dev; struct rte_eth_rss_conf rss_conf; struct rte_pci_device *pdev; + void *doorbell_base; uint32_t flags; #define BNXT_FLAG_REGISTERED (1 << 0) @@ -218,12 +361,30 @@ struct bnxt { #define BNXT_FLAG_UPDATE_HASH (1 << 5) #define BNXT_FLAG_PTP_SUPPORTED (1 << 6) #define BNXT_FLAG_MULTI_HOST (1 << 7) -#define BNXT_FLAG_INIT_DONE (1 << 31) +#define BNXT_FLAG_EXT_RX_PORT_STATS (1 << 8) +#define BNXT_FLAG_EXT_TX_PORT_STATS (1 << 9) +#define BNXT_FLAG_KONG_MB_EN (1 << 10) +#define BNXT_FLAG_TRUSTED_VF_EN (1 << 11) +#define BNXT_FLAG_DFLT_VNIC_SET (1 << 12) +#define BNXT_FLAG_THOR_CHIP (1 << 13) +#define BNXT_FLAG_STINGRAY (1 << 14) +#define BNXT_FLAG_FW_RESET (1 << 15) +#define BNXT_FLAG_FATAL_ERROR (1 << 16) +#define BNXT_FLAG_EXT_STATS_SUPPORTED (1 << 29) +#define BNXT_FLAG_NEW_RM (1 << 30) +#define BNXT_FLAG_INIT_DONE (1U << 31) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->port_partition_type) #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) +#define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. +#define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) +#define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) +#define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP) +#define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) +#define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) +#define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; @@ -231,6 +392,9 @@ struct bnxt { const void *rx_mem_zone; struct rx_port_stats *hw_rx_port_stats; rte_iova_t hw_rx_port_stats_map; + struct rx_port_stats_ext *hw_rx_port_stats_ext; + rte_iova_t hw_rx_port_stats_ext_map; + uint16_t fw_rx_port_stats_ext_size; unsigned int tx_nr_rings; unsigned int tx_cp_nr_rings; @@ -238,30 +402,31 @@ struct bnxt { const void *tx_mem_zone; struct tx_port_stats *hw_tx_port_stats; rte_iova_t hw_tx_port_stats_map; + struct tx_port_stats_ext *hw_tx_port_stats_ext; + rte_iova_t hw_tx_port_stats_ext_map; + uint16_t fw_tx_port_stats_ext_size; /* Default completion ring */ - struct bnxt_cp_ring_info *def_cp_ring; + struct bnxt_cp_ring_info *async_cp_ring; uint32_t max_ring_grps; struct bnxt_ring_grp_info *grp_info; unsigned int nr_vnics; +#define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) struct bnxt_vnic_info *vnic_info; STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; struct bnxt_filter_info *filter_info; STAILQ_HEAD(, bnxt_filter_info) free_filter_list; - /* VNIC pointer for flow filter (VMDq) pools */ -#define MAX_FF_POOLS 256 - STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS]; - struct bnxt_irq *irq_tbl; #define MAX_NUM_MAC_ADDR 32 - uint8_t mac_addr[ETHER_ADDR_LEN]; + uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; uint16_t hwrm_cmd_seq; + uint16_t kong_cmd_seq; void *hwrm_cmd_resp_addr; rte_iova_t hwrm_cmd_resp_dma_addr; void *hwrm_short_cmd_req_addr; @@ -269,22 +434,29 @@ struct bnxt { rte_spinlock_t hwrm_lock; uint16_t max_req_len; uint16_t max_resp_len; + uint16_t hwrm_max_ext_req_len; struct bnxt_link_info link_info; struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT]; uint8_t tx_cosq_id; + uint8_t max_tc; + uint8_t max_lltc; + uint8_t max_q; uint16_t fw_fid; - uint8_t dflt_mac_addr[ETHER_ADDR_LEN]; + uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; uint16_t max_rsscos_ctx; uint16_t max_cp_rings; uint16_t max_tx_rings; uint16_t max_rx_rings; + uint16_t max_nq_rings; uint16_t max_l2_ctx; + uint16_t max_rx_em_flows; uint16_t max_vnics; uint16_t max_stat_ctx; + uint16_t first_vf_id; uint16_t vlan; - struct bnxt_pf_info pf; + struct bnxt_pf_info pf; uint8_t port_partition_type; uint8_t dev_stopped; uint8_t vxlan_port_cnt; @@ -299,14 +471,19 @@ struct bnxt { struct bnxt_led_info leds[BNXT_MAX_LED]; uint8_t num_leds; struct bnxt_ptp_cfg *ptp_cfg; + uint16_t vf_resv_strategy; + struct bnxt_ctx_mem_info *ctx; + + uint16_t fw_reset_min_msecs; + uint16_t fw_reset_max_msecs; }; int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete); int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); - -#define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG 0x6 +int is_bnxt_in_error(struct bnxt *bp); bool is_bnxt_supported(struct rte_eth_dev *dev); +bool bnxt_stratus_device(struct bnxt *bp); extern const struct rte_flow_ops bnxt_flow_ops; extern int bnxt_logtype_driver;