X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt.h;h=a951bca7aa8f9bc239942e21f316e9632f9135de;hb=952ebacce4f2;hp=d455f8d841baafcdc81742a2ab22b3632f2fb7e6;hpb=c7020c212d50295793456394d72baf15a3efb1fa;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index d455f8d841..a951bca7aa 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -23,6 +23,7 @@ #include "tf_core.h" #include "bnxt_ulp.h" +#include "bnxt_tf_common.h" /* Vendor ID */ #define PCI_VENDOR_ID_BROADCOM 0x14E4 @@ -80,6 +81,10 @@ #define BROADCOM_DEV_ID_58808 0x16f0 #define BROADCOM_DEV_ID_58802_VF 0xd800 +#define BROADCOM_DEV_957508_N2100 0x5208 +#define IS_BNXT_DEV_957508_N2100(bp) \ + ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) + #define BNXT_MAX_MTU 9574 #define VLAN_TAG_SIZE 4 #define BNXT_NUM_VLANS 2 @@ -114,20 +119,19 @@ (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \ TPA_MAX_SEGS) -#ifdef RTE_ARCH_ARM64 -#define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1) +/* + * Define the number of async completion rings to be used. Set to zero for + * configurations in which the maximum number of packet completion rings + * for packet completions is desired or when async completion handling + * cannot be interrupt-driven. + */ +#ifdef RTE_EXEC_ENV_FREEBSD +/* In FreeBSD OS, nic_uio driver does not support interrupts */ +#define BNXT_NUM_ASYNC_CPR(bp) 0 #else #define BNXT_NUM_ASYNC_CPR(bp) 1 #endif -/* In FreeBSD OS, nic_uio driver does not support interrupts */ -#ifdef RTE_EXEC_ENV_FREEBSD -#ifdef BNXT_NUM_ASYNC_CPR -#undef BNXT_NUM_ASYNC_CPR -#endif -#define BNXT_NUM_ASYNC_CPR(bp) 0 -#endif - #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET @@ -146,6 +150,26 @@ #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 +#define BNXT_DEFAULT_VNIC_STATE_MASK \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK +#define BNXT_DEFAULT_VNIC_STATE_SFT \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT +#define BNXT_DEFAULT_VNIC_ALLOC \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC +#define BNXT_DEFAULT_VNIC_FREE \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE +#define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK +#define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT +#define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK +#define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT + +#define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ + (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) + struct bnxt_led_info { uint8_t num_leds; uint8_t led_id; @@ -182,13 +206,6 @@ struct bnxt_led_cfg { #define BNXT_LED_DFLT_ENABLES(x) \ rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) -enum bnxt_hw_context { - HW_CONTEXT_NONE = 0, - HW_CONTEXT_IS_RSS = 1, - HW_CONTEXT_IS_COS = 2, - HW_CONTEXT_IS_LB = 3, -}; - struct bnxt_vlan_table_entry { uint16_t tpid; uint16_t vid; @@ -217,9 +234,18 @@ struct bnxt_child_vf_info { bool persist_stats; }; +struct bnxt_parent_info { +#define BNXT_PF_FID_INVALID 0xFFFF + uint16_t fid; + uint16_t vnic; + uint16_t port_id; + uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; +}; + struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) +#define BNXT_MAX_VF_REPS 64 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) @@ -245,8 +271,8 @@ struct bnxt_pf_info { }; /* Max wait time for link up is 10s and link down is 500ms */ -#define BNXT_LINK_UP_WAIT_CNT 200 -#define BNXT_LINK_DOWN_WAIT_CNT 10 +#define BNXT_MAX_LINK_WAIT_CNT 200 +#define BNXT_MIN_LINK_WAIT_CNT 10 #define BNXT_LINK_WAIT_INTERVAL 50 struct bnxt_link_info { uint32_t phy_flags; @@ -269,6 +295,13 @@ struct bnxt_link_info { uint32_t preemphasis; uint8_t phy_type; uint8_t media_type; + uint16_t support_auto_speeds; + uint8_t link_signal_mode; + uint16_t force_pam4_link_speed; + uint16_t support_pam4_speeds; + uint16_t auto_pam4_link_speeds; + uint16_t support_pam4_auto_speeds; + uint8_t req_signal_mode; }; #define BNXT_COS_QUEUE_COUNT 8 @@ -492,6 +525,13 @@ struct bnxt_mark_info { bool valid; }; +struct bnxt_rep_info { + struct rte_eth_dev *vfr_eth_dev; + pthread_mutex_t vfr_lock; + pthread_mutex_t vfr_start_lock; + bool conduit_valid; +}; + /* address space location of register */ #define BNXT_FW_STATUS_REG_TYPE_MASK 3 /* register is located in PCIe config space */ @@ -515,6 +555,48 @@ struct bnxt_mark_info { #define BNXT_FW_STATUS_HEALTHY 0x8000 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 +#define BNXT_ETH_RSS_SUPPORT ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP | \ + ETH_RSS_LEVEL_MASK) + +#define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ + DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_TSO | \ + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ + DEV_TX_OFFLOAD_GRE_TNL_TSO | \ + DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ + DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ + DEV_TX_OFFLOAD_QINQ_INSERT | \ + DEV_TX_OFFLOAD_MULTI_SEGS) + +#define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ + DEV_RX_OFFLOAD_VLAN_STRIP | \ + DEV_RX_OFFLOAD_IPV4_CKSUM | \ + DEV_RX_OFFLOAD_UDP_CKSUM | \ + DEV_RX_OFFLOAD_TCP_CKSUM | \ + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ + DEV_RX_OFFLOAD_JUMBO_FRAME | \ + DEV_RX_OFFLOAD_KEEP_CRC | \ + DEV_RX_OFFLOAD_VLAN_EXTEND | \ + DEV_RX_OFFLOAD_TCP_LRO | \ + DEV_RX_OFFLOAD_SCATTER | \ + DEV_RX_OFFLOAD_RSS_HASH) + +#define MAX_TABLE_SUPPORT 4 +#define MAX_DIR_SUPPORT 2 +struct bnxt_dmabuf_info { + uint32_t entry_num; + int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT]; +}; + #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) struct bnxt_flow_stat_info { @@ -585,16 +667,16 @@ struct bnxt { #define BNXT_FW_CAP_IF_CHANGE BIT(1) #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) +#define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) -#define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7) +#define BNXT_FW_CAP_LINK_ADMIN BIT(7) - uint32_t flow_flags; -#define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0) pthread_mutex_t flow_lock; uint32_t vnic_cap_flags; #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) +#define BNXT_VNIC_CAP_OUTER_RSS BIT(1) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; unsigned int rx_num_qs_per_vnic; @@ -643,6 +725,7 @@ struct bnxt { rte_iova_t hwrm_short_cmd_req_dma_addr; rte_spinlock_t hwrm_lock; pthread_mutex_t def_cp_lock; + pthread_mutex_t health_check_lock; uint16_t max_req_len; uint16_t max_resp_len; uint16_t hwrm_max_ext_req_len; @@ -682,6 +765,9 @@ struct bnxt { #define BNXT_MAX_RINGS(bp) \ (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ BNXT_MAX_TX_RINGS(bp))) + +#define BNXT_MAX_VF_REP_RINGS 8 + uint16_t max_nq_rings; uint16_t max_l2_ctx; uint16_t max_rx_em_flows; @@ -695,6 +781,8 @@ struct bnxt { #define BNXT_OUTER_TPID_BD_SHFT 16 uint32_t outer_tpid_bd; struct bnxt_pf_info *pf; + struct bnxt_parent_info *parent; + uint8_t port_cnt; uint8_t vxlan_port_cnt; uint8_t geneve_port_cnt; uint16_t vxlan_port; @@ -711,7 +799,10 @@ struct bnxt { uint16_t fw_reset_min_msecs; uint16_t fw_reset_max_msecs; - + uint16_t switch_domain_id; + uint16_t num_reps; + struct bnxt_rep_info *rep_info; + uint16_t *cfa_code_map; /* Struct to hold adapter error recovery related info */ struct bnxt_error_recovery_info *recovery_info; #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) @@ -724,14 +815,61 @@ struct bnxt { uint16_t port_svif; struct tf tfp; + struct bnxt_dmabuf_info dmabuf; struct bnxt_ulp_context *ulp_ctx; struct bnxt_flow_stat_info *flow_stat; uint8_t flow_xstat; uint16_t max_num_kflows; + uint16_t tx_cfa_action; }; #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ +/** + * Structure to store private data for each VF representor instance + */ +struct bnxt_representor { + uint16_t switch_domain_id; + uint16_t vf_id; +#define BNXT_REP_IS_PF BIT(0) +#define BNXT_REP_Q_R2F_VALID BIT(1) +#define BNXT_REP_Q_F2R_VALID BIT(2) +#define BNXT_REP_FC_R2F_VALID BIT(3) +#define BNXT_REP_FC_F2R_VALID BIT(4) + uint32_t flags; + uint16_t fw_fid; +#define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF + uint16_t dflt_vnic_id; + uint16_t svif; + uint16_t vfr_tx_cfa_action; + uint32_t dpdk_port_id; + uint32_t rep_based_pf; + uint8_t rep_q_r2f; + uint8_t rep_q_f2r; + uint8_t rep_fc_r2f; + uint8_t rep_fc_f2r; + /* Private data store of associated PF/Trusted VF */ + struct rte_eth_dev *parent_dev; + uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; + uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; + struct bnxt_rx_queue **rx_queues; + unsigned int rx_nr_rings; + unsigned int tx_nr_rings; + uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; +}; + +#define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) + +struct bnxt_vf_rep_tx_queue { + struct bnxt_tx_queue *txq; + struct bnxt_representor *bp; +}; + int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, bool exp_link_status); @@ -744,7 +882,13 @@ void bnxt_schedule_fw_health_check(struct bnxt *bp); bool is_bnxt_supported(struct rte_eth_dev *dev); bool bnxt_stratus_device(struct bnxt *bp); +void bnxt_print_link_info(struct rte_eth_dev *eth_dev); +uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); +int bnxt_link_update_op(struct rte_eth_dev *eth_dev, + int wait_to_complete); + extern const struct rte_flow_ops bnxt_flow_ops; + #define bnxt_acquire_flow_lock(bp) \ pthread_mutex_lock(&(bp)->flow_lock) @@ -763,6 +907,9 @@ extern const struct rte_flow_ops bnxt_flow_ops; } \ } while (0) +#define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ + ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) + extern int bnxt_logtype_driver; #define PMD_DRV_LOG_RAW(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ @@ -772,16 +919,33 @@ extern int bnxt_logtype_driver; PMD_DRV_LOG_RAW(level, fmt, ## args) extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; -int32_t bnxt_ulp_init(struct bnxt *bp); -void bnxt_ulp_deinit(struct bnxt *bp); - -uint16_t bnxt_get_vnic_id(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif); -uint16_t bnxt_get_fw_func_id(uint16_t port); +int32_t bnxt_ulp_port_init(struct bnxt *bp); +void bnxt_ulp_port_deinit(struct bnxt *bp); +int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); +void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); +int32_t +bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); +int32_t +bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); +uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, + enum bnxt_ulp_intf_type type); +uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); +uint16_t bnxt_get_phy_port_id(uint16_t port); +uint16_t bnxt_get_vport(uint16_t port); +enum bnxt_ulp_intf_type +bnxt_get_interface_type(uint16_t port); +int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); void bnxt_flow_cnt_alarm_cb(void *arg); int bnxt_flow_stats_req(struct bnxt *bp); int bnxt_flow_stats_cnt(struct bnxt *bp); uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); + +int +bnxt_filter_ctrl_op(struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, void *arg); #endif