X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt.h;h=aede112692215a3b5109adf4d9aa2d21e8930db0;hb=3684541b86f5277d9cd17667c13c08d93180fb04;hp=5020cd3415f6fa02e80b6e5de9077abc06c6cb1e;hpb=458f0360e8dc72ccc6f98ca724ab3d55325ad493;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5020cd3415..aede112692 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -21,12 +21,71 @@ #include "bnxt_cpr.h" #include "bnxt_util.h" +/* Vendor ID */ +#define PCI_VENDOR_ID_BROADCOM 0x14E4 + +/* Device IDs */ +#define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 +#define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 +#define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 +#define BROADCOM_DEV_ID_57414_VF 0x16c1 +#define BROADCOM_DEV_ID_57301 0x16c8 +#define BROADCOM_DEV_ID_57302 0x16c9 +#define BROADCOM_DEV_ID_57304_PF 0x16ca +#define BROADCOM_DEV_ID_57304_VF 0x16cb +#define BROADCOM_DEV_ID_57417_MF 0x16cc +#define BROADCOM_DEV_ID_NS2 0x16cd +#define BROADCOM_DEV_ID_57311 0x16ce +#define BROADCOM_DEV_ID_57312 0x16cf +#define BROADCOM_DEV_ID_57402 0x16d0 +#define BROADCOM_DEV_ID_57404 0x16d1 +#define BROADCOM_DEV_ID_57406_PF 0x16d2 +#define BROADCOM_DEV_ID_57406_VF 0x16d3 +#define BROADCOM_DEV_ID_57402_MF 0x16d4 +#define BROADCOM_DEV_ID_57407_RJ45 0x16d5 +#define BROADCOM_DEV_ID_57412 0x16d6 +#define BROADCOM_DEV_ID_57414 0x16d7 +#define BROADCOM_DEV_ID_57416_RJ45 0x16d8 +#define BROADCOM_DEV_ID_57417_RJ45 0x16d9 +#define BROADCOM_DEV_ID_5741X_VF 0x16dc +#define BROADCOM_DEV_ID_57412_MF 0x16de +#define BROADCOM_DEV_ID_57314 0x16df +#define BROADCOM_DEV_ID_57317_RJ45 0x16e0 +#define BROADCOM_DEV_ID_5731X_VF 0x16e1 +#define BROADCOM_DEV_ID_57417_SFP 0x16e2 +#define BROADCOM_DEV_ID_57416_SFP 0x16e3 +#define BROADCOM_DEV_ID_57317_SFP 0x16e4 +#define BROADCOM_DEV_ID_57404_MF 0x16e7 +#define BROADCOM_DEV_ID_57406_MF 0x16e8 +#define BROADCOM_DEV_ID_57407_SFP 0x16e9 +#define BROADCOM_DEV_ID_57407_MF 0x16ea +#define BROADCOM_DEV_ID_57414_MF 0x16ec +#define BROADCOM_DEV_ID_57416_MF 0x16ee +#define BROADCOM_DEV_ID_57508 0x1750 +#define BROADCOM_DEV_ID_57504 0x1751 +#define BROADCOM_DEV_ID_57502 0x1752 +#define BROADCOM_DEV_ID_57508_MF1 0x1800 +#define BROADCOM_DEV_ID_57504_MF1 0x1801 +#define BROADCOM_DEV_ID_57502_MF1 0x1802 +#define BROADCOM_DEV_ID_57508_MF2 0x1803 +#define BROADCOM_DEV_ID_57504_MF2 0x1804 +#define BROADCOM_DEV_ID_57502_MF2 0x1805 +#define BROADCOM_DEV_ID_57500_VF1 0x1806 +#define BROADCOM_DEV_ID_57500_VF2 0x1807 +#define BROADCOM_DEV_ID_58802 0xd802 +#define BROADCOM_DEV_ID_58804 0xd804 +#define BROADCOM_DEV_ID_58808 0x16f0 +#define BROADCOM_DEV_ID_58802_VF 0xd800 + #define BNXT_MAX_MTU 9574 #define VLAN_TAG_SIZE 4 #define BNXT_NUM_VLANS 2 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ RTE_ETHER_CRC_LEN +\ (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) +/* FW adds extra 4 bytes for FCS */ +#define BNXT_VNIC_MRU(mtu)\ + ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) #define BNXT_VF_RSV_NUM_RSS_CTX 1 #define BNXT_VF_RSV_NUM_L2_CTX 4 /* TODO: For now, do not support VMDq/RFS on VFs. */ @@ -58,6 +117,17 @@ #define BNXT_NUM_ASYNC_CPR(bp) 1 #endif +/* In FreeBSD OS, nic_uio driver does not support interrupts */ +#ifdef RTE_EXEC_ENV_FREEBSD +#ifdef BNXT_NUM_ASYNC_CPR +#undef BNXT_NUM_ASYNC_CPR +#endif +#define BNXT_NUM_ASYNC_CPR(bp) 0 +#endif + +#define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET +#define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET + /* Chimp Communication Channel */ #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 @@ -118,13 +188,13 @@ enum bnxt_hw_context { struct bnxt_vlan_table_entry { uint16_t tpid; uint16_t vid; -} __attribute__((packed)); +} __rte_packed; struct bnxt_vlan_antispoof_table_entry { uint16_t tpid; uint16_t vid; uint16_t mask; -} __attribute__((packed)); +} __rte_packed; struct bnxt_child_vf_info { void *req_buf; @@ -169,9 +239,10 @@ struct bnxt_pf_info { uint8_t evb_mode; }; -/* Max wait time is 10 * 100ms = 1s */ -#define BNXT_LINK_WAIT_CNT 10 -#define BNXT_LINK_WAIT_INTERVAL 100 +/* Max wait time for link up is 10s and link down is 500ms */ +#define BNXT_LINK_UP_WAIT_CNT 200 +#define BNXT_LINK_DOWN_WAIT_CNT 10 +#define BNXT_LINK_WAIT_INTERVAL 50 struct bnxt_link_info { uint32_t phy_flags; uint8_t mac_type; @@ -399,6 +470,11 @@ struct bnxt_error_recovery_info { uint32_t last_reset_counter; }; +struct bnxt_mark_info { + uint32_t mark_id; + bool valid; +}; + /* address space location of register */ #define BNXT_FW_STATUS_REG_TYPE_MASK 3 /* register is located in PCIe config space */ @@ -445,19 +521,17 @@ struct bnxt { #define BNXT_FLAG_STINGRAY BIT(14) #define BNXT_FLAG_FW_RESET BIT(15) #define BNXT_FLAG_FATAL_ERROR BIT(16) -#define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17) -#define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18) -#define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19) -#define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20) -#define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21) -#define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22) -#define BNXT_FLAG_NEW_RM BIT(23) -#define BNXT_FLAG_INIT_DONE BIT(24) -#define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(25) -#define BNXT_FLAG_ADV_FLOW_MGMT BIT(26) +#define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) +#define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) +#define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) +#define BNXT_FLAG_NEW_RM BIT(20) +#define BNXT_FLAG_NPAR_PF BIT(21) +#define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) +#define BNXT_FLAG_ADV_FLOW_MGMT BIT(23) +#define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) -#define BNXT_NPAR(bp) ((bp)->port_partition_type) +#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. @@ -468,6 +542,12 @@ struct bnxt { #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) + uint32_t fw_cap; +#define BNXT_FW_CAP_HOT_RESET BIT(0) +#define BNXT_FW_CAP_IF_CHANGE BIT(1) +#define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) +#define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) + uint32_t flow_flags; #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0) pthread_mutex_t flow_lock; @@ -514,19 +594,22 @@ struct bnxt { uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; - uint16_t hwrm_cmd_seq; + uint16_t chimp_cmd_seq; uint16_t kong_cmd_seq; void *hwrm_cmd_resp_addr; rte_iova_t hwrm_cmd_resp_dma_addr; void *hwrm_short_cmd_req_addr; rte_iova_t hwrm_short_cmd_req_dma_addr; rte_spinlock_t hwrm_lock; + pthread_mutex_t def_cp_lock; uint16_t max_req_len; uint16_t max_resp_len; uint16_t hwrm_max_ext_req_len; - /* default command timeout value of 50ms */ -#define HWRM_CMD_TIMEOUT 50000 + /* default command timeout value of 500ms */ +#define DFLT_HWRM_CMD_TIMEOUT 500000 + /* short command timeout value of 50ms */ +#define SHORT_HWRM_CMD_TIMEOUT 50000 /* default HWRM request timeout value */ uint32_t hwrm_cmd_timeout; @@ -545,6 +628,20 @@ struct bnxt { uint16_t max_cp_rings; uint16_t max_tx_rings; uint16_t max_rx_rings; +#define MAX_STINGRAY_RINGS 128U +/* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */ +#define BNXT_MAX_RX_RINGS(bp) \ + (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \ + MAX_STINGRAY_RINGS), \ + bp->max_stat_ctx / 2U) : \ + RTE_MIN(bp->max_rx_rings, \ + bp->max_stat_ctx / 2U)) +#define BNXT_MAX_TX_RINGS(bp) \ + (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp))) + +#define BNXT_MAX_RINGS(bp) \ + (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ + BNXT_MAX_TX_RINGS(bp))) uint16_t max_nq_rings; uint16_t max_l2_ctx; uint16_t max_rx_em_flows; @@ -558,8 +655,6 @@ struct bnxt { #define BNXT_OUTER_TPID_BD_SHFT 16 uint32_t outer_tpid_bd; struct bnxt_pf_info pf; - uint8_t port_partition_type; - uint8_t dev_stopped; uint8_t vxlan_port_cnt; uint8_t geneve_port_cnt; uint16_t vxlan_port; @@ -580,12 +675,17 @@ struct bnxt { /* Struct to hold adapter error recovery related info */ struct bnxt_error_recovery_info *recovery_info; +#define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) +/* TCAM and EM should be 16-bit only. Other modes not supported. */ +#define BNXT_FLOW_ID_MASK 0x0000ffff + struct bnxt_mark_info *mark_table; }; -int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete); +int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); +int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, + bool exp_link_status); int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); int is_bnxt_in_error(struct bnxt *bp); -uint16_t bnxt_rss_ctxts(const struct bnxt *bp); int bnxt_map_fw_health_status_regs(struct bnxt *bp); uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); @@ -600,11 +700,23 @@ extern const struct rte_flow_ops bnxt_flow_ops; #define bnxt_release_flow_lock(bp) \ pthread_mutex_unlock(&(bp)->flow_lock) +#define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ + if ((vnic_id) >= (bp)->max_vnics) { \ + rte_flow_error_set(error, \ + EINVAL, \ + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ + NULL, \ + "Group id is invalid!"); \ + rc = -rte_errno; \ + goto ret; \ + } \ +} while (0) + extern int bnxt_logtype_driver; #define PMD_DRV_LOG_RAW(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ __func__, ## args) #define PMD_DRV_LOG(level, fmt, args...) \ - PMD_DRV_LOG_RAW(level, fmt, ## args) + PMD_DRV_LOG_RAW(level, fmt, ## args) #endif