X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt_ethdev.c;h=257e6b0d6a04541348f152efed476c0162f8bc82;hb=af397b3c93f82b0803c0890874d7ee3b5127522d;hp=0788d263d833a51664c07925c71eb9042da03976;hpb=dc241adc68127e63ff1e5dbc0f0db00e82a20dbe;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 0788d263d8..257e6b0d6a 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2018 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -7,8 +7,8 @@ #include #include -#include -#include +#include +#include #include #include #include @@ -80,10 +80,14 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, { .vendor_id = 0, /* sentinel */ }, }; -#define BNXT_DEVARG_TRUFLOW "host-based-truflow" +#define BNXT_DEVARG_ACCUM_STATS "accum-stats" #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" #define BNXT_DEVARG_REPRESENTOR "representor" @@ -93,10 +97,11 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" +#define BNXT_DEVARG_APP_ID "app-id" static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, - BNXT_DEVARG_TRUFLOW, + BNXT_DEVARG_ACCUM_STATS, BNXT_DEVARG_FLOW_XSTAT, BNXT_DEVARG_MAX_NUM_KFLOWS, BNXT_DEVARG_REP_BASED_PF, @@ -105,14 +110,20 @@ static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REP_Q_F2R, BNXT_DEVARG_REP_FC_R2F, BNXT_DEVARG_REP_FC_F2R, + BNXT_DEVARG_APP_ID, NULL }; /* - * truflow == false to disable the feature - * truflow == true to enable the feature + * accum-stats == false to disable flow counter accumulation + * accum-stats == true to enable flow counter accumulation */ -#define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) +#define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) + +/* + * app-id = an non-negative 8-bit number + */ +#define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) /* * flow_xstat == false to disable the feature @@ -215,16 +226,19 @@ uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) static void bnxt_free_parent_info(struct bnxt *bp) { rte_free(bp->parent); + bp->parent = NULL; } static void bnxt_free_pf_info(struct bnxt *bp) { rte_free(bp->pf); + bp->pf = NULL; } static void bnxt_free_link_info(struct bnxt *bp) { rte_free(bp->link_info); + bp->link_info = NULL; } static void bnxt_free_leds_info(struct bnxt *bp) @@ -245,7 +259,9 @@ static void bnxt_free_flow_stats_info(struct bnxt *bp) static void bnxt_free_cos_queues(struct bnxt *bp) { rte_free(bp->rx_cos_queue); + bp->rx_cos_queue = NULL; rte_free(bp->tx_cos_queue); + bp->tx_cos_queue = NULL; } static void bnxt_free_mem(struct bnxt *bp, bool reconfig) @@ -410,15 +426,16 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) goto err_out; /* Alloc RSS context only if RSS mode is enabled */ - if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { + if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) { int j, nr_ctxs = bnxt_rss_ctxts(bp); + /* RSS table size in Thor is 512. + * Cap max Rx rings to same value + */ if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); - PMD_DRV_LOG(ERR, - "Only queues 0-%d will be in RSS table\n", - BNXT_RSS_TBL_SIZE_P5 - 1); + goto err_out; } rc = 0; @@ -441,7 +458,7 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) * setting is not available at this time, it will not be * configured correctly in the CFA. */ - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) + if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) vnic->vlan_strip = true; else vnic->vlan_strip = false; @@ -475,10 +492,11 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); - if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) - bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); - else - bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); + rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, + (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ? + true : false); + if (rc) + goto err_out; return 0; err_out: @@ -562,13 +580,14 @@ static int bnxt_register_fc_ctx_mem(struct bnxt *bp) return rc; } -static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, +static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size, struct bnxt_ctx_mem_buf_info *ctx) { if (!ctx) return -EINVAL; - ctx->va = rte_zmalloc(type, size, 0); + ctx->va = rte_zmalloc_socket(type, size, 0, + bp->eth_dev->device->numa_node); if (ctx->va == NULL) return -ENOMEM; rte_mem_lock_page(ctx->va); @@ -592,7 +611,7 @@ static int bnxt_init_fc_ctx_mem(struct bnxt *bp) sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, pdev->addr.bus, pdev->addr.devid, pdev->addr.function); /* 4 bytes for each counter-id */ - rc = bnxt_alloc_ctx_mem_buf(type, + rc = bnxt_alloc_ctx_mem_buf(bp, type, max_fc * 4, &bp->flow_stat->rx_fc_in_tbl); if (rc) @@ -601,7 +620,7 @@ static int bnxt_init_fc_ctx_mem(struct bnxt *bp) sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, pdev->addr.bus, pdev->addr.devid, pdev->addr.function); /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ - rc = bnxt_alloc_ctx_mem_buf(type, + rc = bnxt_alloc_ctx_mem_buf(bp, type, max_fc * 16, &bp->flow_stat->rx_fc_out_tbl); if (rc) @@ -610,7 +629,7 @@ static int bnxt_init_fc_ctx_mem(struct bnxt *bp) sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, pdev->addr.bus, pdev->addr.devid, pdev->addr.function); /* 4 bytes for each counter-id */ - rc = bnxt_alloc_ctx_mem_buf(type, + rc = bnxt_alloc_ctx_mem_buf(bp, type, max_fc * 4, &bp->flow_stat->tx_fc_in_tbl); if (rc) @@ -619,7 +638,7 @@ static int bnxt_init_fc_ctx_mem(struct bnxt *bp) sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, pdev->addr.bus, pdev->addr.devid, pdev->addr.function); /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ - rc = bnxt_alloc_ctx_mem_buf(type, + rc = bnxt_alloc_ctx_mem_buf(bp, type, max_fc * 16, &bp->flow_stat->tx_fc_out_tbl); if (rc) @@ -675,25 +694,52 @@ static int bnxt_update_phy_setting(struct bnxt *bp) return rc; } -static int bnxt_init_chip(struct bnxt *bp) +static void bnxt_free_prev_ring_stats(struct bnxt *bp) +{ + rte_free(bp->prev_rx_ring_stats); + rte_free(bp->prev_tx_ring_stats); + + bp->prev_rx_ring_stats = NULL; + bp->prev_tx_ring_stats = NULL; +} + +static int bnxt_alloc_prev_ring_stats(struct bnxt *bp) +{ + bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats", + sizeof(struct bnxt_ring_stats) * + bp->rx_cp_nr_rings, + 0); + if (bp->prev_rx_ring_stats == NULL) + return -ENOMEM; + + bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats", + sizeof(struct bnxt_ring_stats) * + bp->tx_cp_nr_rings, + 0); + if (bp->prev_tx_ring_stats == NULL) + goto error; + + return 0; + +error: + bnxt_free_prev_ring_stats(bp); + return -ENOMEM; +} + +static int bnxt_start_nic(struct bnxt *bp) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; uint32_t intr_vector = 0; uint32_t queue_id, base = BNXT_MISC_VEC_ID; uint32_t vec = BNXT_MISC_VEC_ID; unsigned int i, j; int rc; - if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { - bp->eth_dev->data->dev_conf.rxmode.offloads |= - DEV_RX_OFFLOAD_JUMBO_FRAME; + if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) bp->flags |= BNXT_FLAG_JUMBO; - } else { - bp->eth_dev->data->dev_conf.rxmode.offloads &= - ~DEV_RX_OFFLOAD_JUMBO_FRAME; + else bp->flags &= ~BNXT_FLAG_JUMBO; - } /* THOR does not support ring groups. * But we will use the array to save RSS context IDs. @@ -701,12 +747,6 @@ static int bnxt_init_chip(struct bnxt *bp) if (BNXT_CHIP_P5(bp)) bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; - rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); - if (rc) { - PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); - goto err_out; - } - rc = bnxt_alloc_hwrm_rings(bp); if (rc) { PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); @@ -744,11 +784,37 @@ skip_cosq_cfg: goto err_out; } + for (j = 0; j < bp->rx_nr_rings; j++) { + struct bnxt_rx_queue *rxq = bp->rx_queues[j]; + + if (!rxq->rx_deferred_start) { + bp->eth_dev->data->rx_queue_state[j] = + RTE_ETH_QUEUE_STATE_STARTED; + rxq->rx_started = true; + } + } + + /* default vnic 0 */ + rc = bnxt_setup_one_vnic(bp, 0); + if (rc) + goto err_out; /* VNIC configuration */ - for (i = 0; i < bp->nr_vnics; i++) { - rc = bnxt_setup_one_vnic(bp, i); - if (rc) - goto err_out; + if (BNXT_RFS_NEEDS_VNIC(bp)) { + for (i = 1; i < bp->nr_vnics; i++) { + rc = bnxt_setup_one_vnic(bp, i); + if (rc) + goto err_out; + } + } + + for (j = 0; j < bp->tx_nr_rings; j++) { + struct bnxt_tx_queue *txq = bp->tx_queues[j]; + + if (!txq->tx_deferred_start) { + bp->eth_dev->data->tx_queue_state[j] = + RTE_ETH_QUEUE_STATE_STARTED; + txq->tx_started = true; + } } rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); @@ -774,26 +840,24 @@ skip_cosq_cfg: return rc; } - if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { - intr_handle->intr_vec = - rte_zmalloc("intr_vec", - bp->eth_dev->data->nb_rx_queues * - sizeof(int), 0); - if (intr_handle->intr_vec == NULL) { + if (rte_intr_dp_is_en(intr_handle)) { + if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", + bp->eth_dev->data->nb_rx_queues)) { PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" " intr_vec", bp->eth_dev->data->nb_rx_queues); rc = -ENOMEM; - goto err_disable; + goto err_out; } - PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " - "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", - intr_handle->intr_vec, intr_handle->nb_efd, - intr_handle->max_intr); + PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d " + "intr_handle->max_intr = %d\n", + rte_intr_nb_efd_get(intr_handle), + rte_intr_max_intr_get(intr_handle)); for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; queue_id++) { - intr_handle->intr_vec[queue_id] = - vec + BNXT_RX_VEC_START; - if (vec < base + intr_handle->nb_efd - 1) + rte_intr_vec_list_index_set(intr_handle, + queue_id, vec + BNXT_RX_VEC_START); + if (vec < base + rte_intr_nb_efd_get(intr_handle) + - 1) vec++; } } @@ -803,12 +867,12 @@ skip_cosq_cfg: #ifndef RTE_EXEC_ENV_FREEBSD /* In FreeBSD OS, nic_uio driver does not support interrupts */ if (rc) - goto err_free; + goto err_out; #endif rc = bnxt_update_phy_setting(bp); if (rc) - goto err_free; + goto err_out; bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); if (!bp->mark_table) @@ -816,10 +880,6 @@ skip_cosq_cfg: return 0; -err_free: - rte_free(intr_handle->intr_vec); -err_disable: - rte_intr_efd_disable(intr_handle); err_out: /* Some of the error status returned by FW may not be from errno.h */ if (rc > 0) @@ -842,45 +902,48 @@ static int bnxt_shutdown_nic(struct bnxt *bp) uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) { - uint32_t link_speed = bp->link_info->support_speeds; + uint32_t link_speed = 0; uint32_t speed_capa = 0; + if (bp->link_info == NULL) + return 0; + + link_speed = bp->link_info->support_speeds; + /* If PAM4 is configured, use PAM4 supported speed */ if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) link_speed = bp->link_info->support_pam4_speeds; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) - speed_capa |= ETH_LINK_SPEED_100M; + speed_capa |= RTE_ETH_LINK_SPEED_100M; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) - speed_capa |= ETH_LINK_SPEED_100M_HD; + speed_capa |= RTE_ETH_LINK_SPEED_100M_HD; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) - speed_capa |= ETH_LINK_SPEED_1G; + speed_capa |= RTE_ETH_LINK_SPEED_1G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) - speed_capa |= ETH_LINK_SPEED_2_5G; + speed_capa |= RTE_ETH_LINK_SPEED_2_5G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) - speed_capa |= ETH_LINK_SPEED_10G; + speed_capa |= RTE_ETH_LINK_SPEED_10G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) - speed_capa |= ETH_LINK_SPEED_20G; + speed_capa |= RTE_ETH_LINK_SPEED_20G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) - speed_capa |= ETH_LINK_SPEED_25G; + speed_capa |= RTE_ETH_LINK_SPEED_25G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) - speed_capa |= ETH_LINK_SPEED_40G; + speed_capa |= RTE_ETH_LINK_SPEED_40G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) - speed_capa |= ETH_LINK_SPEED_50G; + speed_capa |= RTE_ETH_LINK_SPEED_50G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) - speed_capa |= ETH_LINK_SPEED_100G; + speed_capa |= RTE_ETH_LINK_SPEED_100G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) - speed_capa |= ETH_LINK_SPEED_50G; + speed_capa |= RTE_ETH_LINK_SPEED_50G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) - speed_capa |= ETH_LINK_SPEED_100G; + speed_capa |= RTE_ETH_LINK_SPEED_100G; if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) - speed_capa |= ETH_LINK_SPEED_200G; + speed_capa |= RTE_ETH_LINK_SPEED_200G; if (bp->link_info->auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) - speed_capa |= ETH_LINK_SPEED_FIXED; - else - speed_capa |= ETH_LINK_SPEED_AUTONEG; + speed_capa |= RTE_ETH_LINK_SPEED_FIXED; return speed_capa; } @@ -911,7 +974,7 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, dev_info->max_rx_queues = max_rx_rings; dev_info->max_tx_queues = max_rx_rings; dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); - dev_info->hash_key_size = 40; + dev_info->hash_key_size = HW_HASH_KEY_SIZE; max_vnics = bp->max_vnics; /* MTU specifics */ @@ -924,15 +987,21 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) - dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; - dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; + dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) + dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | dev_info->tx_queue_offload_capa; + if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) + dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT; dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; dev_info->speed_capa = bnxt_get_speed_capabilities(bp); + dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | + RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; - /* *INDENT-OFF* */ dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_thresh = { .pthresh = 8, @@ -954,7 +1023,6 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, }; eth_dev->data->dev_conf.intr_conf.lsc = 1; - eth_dev->data->dev_conf.intr_conf.rxq = 1; dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; @@ -968,16 +1036,14 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, BNXT_SWITCH_PORT_ID_TRUSTED_VF; } - /* *INDENT-ON* */ - /* * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim * need further investigation. */ /* VMDq resources */ - vpool = 64; /* ETH_64_POOLS */ - vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ + vpool = 64; /* RTE_ETH_64_POOLS */ + vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */ for (i = 0; i < 4; vpool >>= 1, i++) { if (max_vnics > vpool) { for (j = 0; j < 5; vrxq >>= 1, j++) { @@ -1072,24 +1138,19 @@ static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) goto resource_error; - if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && + if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) && bp->max_vnics < eth_dev->data->nb_rx_queues) goto resource_error; bp->rx_cp_nr_rings = bp->rx_nr_rings; bp->tx_cp_nr_rings = bp->tx_nr_rings; - if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) - rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; + if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) + rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; - if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { - eth_dev->data->mtu = - eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * - BNXT_NUM_VLANS; - bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); - } + bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); + return 0; resource_error: @@ -1114,7 +1175,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, - (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? + (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? ("full-duplex") : ("half-duplex\n")); else PMD_DRV_LOG(INFO, "Port %d Link Down\n", @@ -1127,10 +1188,14 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) */ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) { + uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; uint16_t buf_size; int i; - if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) + if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) + return 1; + + if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) return 1; for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -1138,7 +1203,7 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM); - if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) + if (eth_dev->data->mtu + overhead > buf_size) return 1; } return 0; @@ -1149,32 +1214,62 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; -#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) -#ifndef RTE_LIBRTE_IEEE1588 + /* Disable vector mode RX for Stingray2 for now */ + if (BNXT_CHIP_SR2(bp)) { + bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; + return bnxt_recv_pkts; + } + +#if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \ + !defined(RTE_LIBRTE_IEEE1588) + + /* Vector mode receive cannot be enabled if scattered rx is in use. */ + if (eth_dev->data->scattered_rx) + goto use_scalar_rx; + + /* + * Vector mode receive cannot be enabled if Truflow is enabled or if + * asynchronous completions and receive completions can be placed in + * the same completion ring. + */ + if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp)) + goto use_scalar_rx; + /* - * Vector mode receive can be enabled only if scatter rx is not - * in use and rx offloads are limited to VLAN stripping and - * CRC stripping. + * Vector mode receive cannot be enabled if any receive offloads outside + * a limited subset have been enabled. */ - if (!eth_dev->data->scattered_rx && - !(eth_dev->data->dev_conf.rxmode.offloads & - ~(DEV_RX_OFFLOAD_VLAN_STRIP | - DEV_RX_OFFLOAD_KEEP_CRC | - DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM | - DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | - DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | - DEV_RX_OFFLOAD_RSS_HASH | - DEV_RX_OFFLOAD_VLAN_FILTER)) && - !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { - PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", + if (eth_dev->data->dev_conf.rxmode.offloads & + ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP | + RTE_ETH_RX_OFFLOAD_KEEP_CRC | + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | + RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | + RTE_ETH_RX_OFFLOAD_RSS_HASH | + RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) + goto use_scalar_rx; + +#if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { + PMD_DRV_LOG(INFO, + "Using AVX2 vector mode receive for port %d\n", + eth_dev->data->port_id); + bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; + return bnxt_recv_pkts_vec_avx2; + } + #endif + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { + PMD_DRV_LOG(INFO, + "Using SSE vector mode receive for port %d\n", eth_dev->data->port_id); bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; return bnxt_recv_pkts_vec; } + +use_scalar_rx: PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", eth_dev->data->port_id); PMD_DRV_LOG(INFO, @@ -1182,32 +1277,50 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) eth_dev->data->port_id, eth_dev->data->scattered_rx, eth_dev->data->dev_conf.rxmode.offloads); -#endif #endif bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; return bnxt_recv_pkts; } static eth_tx_burst_t -bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) +bnxt_transmit_function(struct rte_eth_dev *eth_dev) { -#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) -#ifndef RTE_LIBRTE_IEEE1588 - uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; struct bnxt *bp = eth_dev->data->dev_private; + /* Disable vector mode TX for Stingray2 for now */ + if (BNXT_CHIP_SR2(bp)) + return bnxt_xmit_pkts; + +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \ + !defined(RTE_LIBRTE_IEEE1588) + uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; + /* * Vector mode transmit can be enabled only if not using scatter rx * or tx offloads. */ - if (!eth_dev->data->scattered_rx && - !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && - !BNXT_TRUFLOW_EN(bp) && - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { - PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", + if (eth_dev->data->scattered_rx || + (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) || + BNXT_TRUFLOW_EN(bp)) + goto use_scalar_tx; + +#if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { + PMD_DRV_LOG(INFO, + "Using AVX2 vector mode transmit for port %d\n", + eth_dev->data->port_id); + return bnxt_xmit_pkts_vec_avx2; + } +#endif + if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { + PMD_DRV_LOG(INFO, + "Using SSE vector mode transmit for port %d\n", eth_dev->data->port_id); return bnxt_xmit_pkts_vec; } + +use_scalar_tx: PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", eth_dev->data->port_id); PMD_DRV_LOG(INFO, @@ -1215,7 +1328,6 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) eth_dev->data->port_id, eth_dev->data->scattered_rx, offloads); -#endif #endif return bnxt_xmit_pkts; } @@ -1239,128 +1351,126 @@ static int bnxt_handle_if_change_status(struct bnxt *bp) return rc; } -static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) +static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; - uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; - int vlan_mask = 0; - int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; - - if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); - return -EINVAL; - } + int rc = 0; - if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) - PMD_DRV_LOG(ERR, - "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", - bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); + if (!BNXT_SINGLE_PF(bp)) + return -ENOTSUP; - do { - rc = bnxt_hwrm_if_change(bp, true); - if (rc == 0 || rc != -EAGAIN) - break; + if (!bp->link_info->link_up) + rc = bnxt_set_hwrm_link_config(bp, true); + if (!rc) + eth_dev->data->dev_link.link_status = 1; - rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); - } while (retry_cnt--); + bnxt_print_link_info(eth_dev); + return rc; +} - if (rc) - return rc; +static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; - if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { - rc = bnxt_handle_if_change_status(bp); - if (rc) - return rc; - } + if (!BNXT_SINGLE_PF(bp)) + return -ENOTSUP; - bnxt_enable_int(bp); + eth_dev->data->dev_link.link_status = 0; + bnxt_set_hwrm_link_config(bp, false); + bp->link_info->link_up = 0; - rc = bnxt_init_chip(bp); - if (rc) - goto error; + return 0; +} - eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); - eth_dev->data->dev_started = 1; +static void bnxt_free_switch_domain(struct bnxt *bp) +{ + int rc = 0; - bnxt_link_update_op(eth_dev, 1); + if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) + return; - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) - vlan_mask |= ETH_VLAN_FILTER_MASK; - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) - vlan_mask |= ETH_VLAN_STRIP_MASK; - rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); + rc = rte_eth_switch_domain_free(bp->switch_domain_id); if (rc) - goto error; + PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", + bp->switch_domain_id, rc); +} - /* Initialize bnxt ULP port details */ - rc = bnxt_ulp_port_init(bp); - if (rc) - goto error; +static void bnxt_ptp_get_current_time(void *arg) +{ + struct bnxt *bp = arg; + struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; + int rc; - eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); - eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); + rc = is_bnxt_in_error(bp); + if (rc) + return; - bnxt_schedule_fw_health_check(bp); + if (!ptp) + return; - return 0; + bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, + &ptp->current_time); -error: - bnxt_shutdown_nic(bp); - bnxt_free_tx_mbufs(bp); - bnxt_free_rx_mbufs(bp); - bnxt_hwrm_if_change(bp, false); - eth_dev->data->dev_started = 0; - return rc; + rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); + if (rc != 0) { + PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); + bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; + } } -static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) +static int bnxt_schedule_ptp_alarm(struct bnxt *bp) { - struct bnxt *bp = eth_dev->data->dev_private; - int rc = 0; + struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; + int rc; - if (!bp->link_info->link_up) - rc = bnxt_set_hwrm_link_config(bp, true); - if (!rc) - eth_dev->data->dev_link.link_status = 1; + if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) + return 0; - bnxt_print_link_info(eth_dev); + bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, + &ptp->current_time); + + rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); return rc; } -static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) +static void bnxt_cancel_ptp_alarm(struct bnxt *bp) { - struct bnxt *bp = eth_dev->data->dev_private; - - eth_dev->data->dev_link.link_status = 0; - bnxt_set_hwrm_link_config(bp, false); - bp->link_info->link_up = 0; + if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { + rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); + bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; + } +} - return 0; +static void bnxt_ptp_stop(struct bnxt *bp) +{ + bnxt_cancel_ptp_alarm(bp); + bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; } -static void bnxt_free_switch_domain(struct bnxt *bp) +static int bnxt_ptp_start(struct bnxt *bp) { - int rc = 0; + int rc; - if (bp->switch_domain_id) { - rc = rte_eth_switch_domain_free(bp->switch_domain_id); - if (rc) - PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", - bp->switch_domain_id, rc); + rc = bnxt_schedule_ptp_alarm(bp); + if (rc != 0) { + PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); + } else { + bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; + bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; } + + return rc; } -/* Unload the driver, release resources */ -static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) +static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct rte_eth_link link; int ret; eth_dev->data->dev_started = 0; - eth_dev->data->scattered_rx = 0; /* Prevent crashes when queues are still in use */ eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; @@ -1381,6 +1491,9 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) bnxt_cancel_fw_health_check(bp); + if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) + bnxt_cancel_ptp_alarm(bp); + /* Do not bring link down during reset recovery */ if (!is_bnxt_in_error(bp)) { bnxt_dev_set_link_down_op(eth_dev); @@ -1394,10 +1507,7 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) /* Clean queue intr-vector mapping */ rte_intr_efd_disable(intr_handle); - if (intr_handle->intr_vec != NULL) { - rte_free(intr_handle->intr_vec); - intr_handle->intr_vec = NULL; - } + rte_intr_vec_list_free(intr_handle); bnxt_hwrm_port_clr_stats(bp); bnxt_free_tx_mbufs(bp); @@ -1407,6 +1517,7 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) bnxt_shutdown_nic(bp); bnxt_hwrm_if_change(bp, false); + bnxt_free_prev_ring_stats(bp); rte_free(bp->mark_table); bp->mark_table = NULL; @@ -1416,44 +1527,167 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) if (BNXT_FLOW_XSTATS_EN(bp)) bp->flow_stat->flow_count = 0; + eth_dev->data->scattered_rx = 0; + return 0; } -static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) +/* Unload the driver, release resources */ +static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; - int ret = 0; - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; + pthread_mutex_lock(&bp->err_recovery_lock); + if (bp->flags & BNXT_FLAG_FW_RESET) { + PMD_DRV_LOG(ERR, + "Adapter recovering from error..Please retry\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return -EAGAIN; + } + pthread_mutex_unlock(&bp->err_recovery_lock); - /* cancel the recovery handler before remove dev */ - rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); - rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); - bnxt_cancel_fc_thread(bp); + return bnxt_dev_stop(eth_dev); +} - if (eth_dev->data->dev_started) - ret = bnxt_dev_stop_op(eth_dev); +static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; + uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; + int vlan_mask = 0; + int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; - bnxt_free_switch_domain(bp); + if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); + return -EINVAL; + } - bnxt_uninit_resources(bp, false); + if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) + PMD_DRV_LOG(ERR, + "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", + bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); + + do { + rc = bnxt_hwrm_if_change(bp, true); + if (rc == 0 || rc != -EAGAIN) + break; + + rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); + } while (retry_cnt--); + + if (rc) + return rc; + + if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { + rc = bnxt_handle_if_change_status(bp); + if (rc) + return rc; + } + + bnxt_enable_int(bp); + + eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); + + rc = bnxt_start_nic(bp); + if (rc) + goto error; + + rc = bnxt_alloc_prev_ring_stats(bp); + if (rc) + goto error; + + eth_dev->data->dev_started = 1; + + bnxt_link_update_op(eth_dev, 1); + + if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) + vlan_mask |= RTE_ETH_VLAN_FILTER_MASK; + if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) + vlan_mask |= RTE_ETH_VLAN_STRIP_MASK; + rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); + if (rc) + goto error; + + /* Initialize bnxt ULP port details */ + rc = bnxt_ulp_port_init(bp); + if (rc) + goto error; + + eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); + eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); + + bnxt_schedule_fw_health_check(bp); + + if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) + bnxt_schedule_ptp_alarm(bp); + + return 0; + +error: + bnxt_dev_stop(eth_dev); + return rc; +} +static void +bnxt_uninit_locks(struct bnxt *bp) +{ + pthread_mutex_destroy(&bp->flow_lock); + pthread_mutex_destroy(&bp->def_cp_lock); + pthread_mutex_destroy(&bp->health_check_lock); + pthread_mutex_destroy(&bp->err_recovery_lock); + if (bp->rep_info) { + pthread_mutex_destroy(&bp->rep_info->vfr_lock); + pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); + } +} + +static void bnxt_drv_uninit(struct bnxt *bp) +{ bnxt_free_leds_info(bp); bnxt_free_cos_queues(bp); bnxt_free_link_info(bp); - bnxt_free_pf_info(bp); bnxt_free_parent_info(bp); + bnxt_uninit_locks(bp); rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); bp->tx_mem_zone = NULL; rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); bp->rx_mem_zone = NULL; - bnxt_hwrm_free_vf_info(bp); + bnxt_free_vf_info(bp); + bnxt_free_pf_info(bp); rte_free(bp->grp_info); bp->grp_info = NULL; +} + +static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; + int ret = 0; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + pthread_mutex_lock(&bp->err_recovery_lock); + if (bp->flags & BNXT_FLAG_FW_RESET) { + PMD_DRV_LOG(ERR, + "Adapter recovering from error...Please retry\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return -EAGAIN; + } + pthread_mutex_unlock(&bp->err_recovery_lock); + + /* cancel the recovery handler before remove dev */ + rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); + rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); + bnxt_cancel_fc_thread(bp); + + if (eth_dev->data->dev_started) + ret = bnxt_dev_stop(eth_dev); + + bnxt_uninit_resources(bp, false); + + bnxt_drv_uninit(bp); return ret; } @@ -1582,12 +1816,16 @@ int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) return rc; memset(&new, 0, sizeof(new)); + + if (bp->link_info == NULL) + goto out; + do { /* Retrieve link info from hardware */ rc = bnxt_get_hwrm_link_config(bp, &new); if (rc) { - new.link_speed = ETH_LINK_SPEED_100M; - new.link_duplex = ETH_LINK_FULL_DUPLEX; + new.link_speed = RTE_ETH_LINK_SPEED_100M; + new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; PMD_DRV_LOG(ERR, "Failed to retrieve link rc = 0x%x!\n", rc); goto out; @@ -1610,11 +1848,6 @@ out: if (new.link_status != eth_dev->data->dev_link.link_status || new.link_speed != eth_dev->data->dev_link.link_speed) { rte_eth_linkstatus_set(eth_dev, &new); - - rte_eth_dev_callback_process(eth_dev, - RTE_ETH_EVENT_INTR_LSC, - NULL); - bnxt_print_link_info(eth_dev); } @@ -1786,7 +2019,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, if (!vnic->rss_table) return -EINVAL; - if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) + if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) return -EINVAL; if (reta_size != tbl_size) { @@ -1799,8 +2032,8 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, for (i = 0; i < reta_size; i++) { struct bnxt_rx_queue *rxq; - idx = i / RTE_RETA_GROUP_SIZE; - sft = i % RTE_RETA_GROUP_SIZE; + idx = i / RTE_ETH_RETA_GROUP_SIZE; + sft = i % RTE_ETH_RETA_GROUP_SIZE; if (!(reta_conf[idx].mask & (1ULL << sft))) continue; @@ -1840,7 +2073,6 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, if (rc) return rc; - /* Retrieve from the default VNIC */ if (!vnic) return -EINVAL; if (!vnic->rss_table) @@ -1854,8 +2086,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, } for (idx = 0, i = 0; i < reta_size; i++) { - idx = i / RTE_RETA_GROUP_SIZE; - sft = i % RTE_RETA_GROUP_SIZE; + idx = i / RTE_ETH_RETA_GROUP_SIZE; + sft = i % RTE_ETH_RETA_GROUP_SIZE; if (reta_conf[idx].mask & (1ULL << sft)) { uint16_t qid; @@ -1893,7 +2125,7 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, * If RSS enablement were different than dev_configure, * then return -EINVAL */ - if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { + if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { if (!rss_conf->rss_hf) PMD_DRV_LOG(ERR, "Hash type NONE\n"); } else { @@ -1911,7 +2143,7 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); vnic->hash_mode = bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, - ETH_RSS_LEVEL(rss_conf->rss_hf)); + RTE_ETH_RSS_LEVEL(rss_conf->rss_hf)); /* * If hashkey is not specified, use the previously configured @@ -1922,7 +2154,8 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { PMD_DRV_LOG(ERR, - "Invalid hashkey length, should be 16 bytes\n"); + "Invalid hashkey length, should be %d bytes\n", + HW_HASH_KEY_SIZE); return -EINVAL; } memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); @@ -1955,30 +2188,30 @@ static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, hash_types = vnic->hash_type; rss_conf->rss_hf = 0; if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { - rss_conf->rss_hf |= ETH_RSS_IPV4; + rss_conf->rss_hf |= RTE_ETH_RSS_IPV4; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; } if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { - rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; + rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; } if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { - rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; + rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; } if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { - rss_conf->rss_hf |= ETH_RSS_IPV6; + rss_conf->rss_hf |= RTE_ETH_RSS_IPV6; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; } if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { - rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; + rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; } if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { - rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; + rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; } @@ -2018,17 +2251,17 @@ static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, fc_conf->autoneg = 1; switch (bp->link_info->pause) { case 0: - fc_conf->mode = RTE_FC_NONE; + fc_conf->mode = RTE_ETH_FC_NONE; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: - fc_conf->mode = RTE_FC_TX_PAUSE; + fc_conf->mode = RTE_ETH_FC_TX_PAUSE; break; case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: - fc_conf->mode = RTE_FC_RX_PAUSE; + fc_conf->mode = RTE_ETH_FC_RX_PAUSE; break; case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): - fc_conf->mode = RTE_FC_FULL; + fc_conf->mode = RTE_ETH_FC_FULL; break; } return 0; @@ -2044,17 +2277,18 @@ static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, if (rc) return rc; - if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { - PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); + if (!BNXT_SINGLE_PF(bp)) { + PMD_DRV_LOG(ERR, + "Flow Control Settings cannot be modified on VF or on shared PF\n"); return -ENOTSUP; } switch (fc_conf->mode) { - case RTE_FC_NONE: + case RTE_ETH_FC_NONE: bp->link_info->auto_pause = 0; bp->link_info->force_pause = 0; break; - case RTE_FC_RX_PAUSE: + case RTE_ETH_FC_RX_PAUSE: if (fc_conf->autoneg) { bp->link_info->auto_pause = HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; @@ -2065,7 +2299,7 @@ static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; } break; - case RTE_FC_TX_PAUSE: + case RTE_ETH_FC_TX_PAUSE: if (fc_conf->autoneg) { bp->link_info->auto_pause = HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; @@ -2076,7 +2310,7 @@ static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; } break; - case RTE_FC_FULL: + case RTE_ETH_FC_FULL: if (fc_conf->autoneg) { bp->link_info->auto_pause = HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | @@ -2107,7 +2341,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, return rc; switch (udp_tunnel->prot_type) { - case RTE_TUNNEL_TYPE_VXLAN: + case RTE_ETH_TUNNEL_TYPE_VXLAN: if (bp->vxlan_port_cnt) { PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", udp_tunnel->udp_port); @@ -2120,9 +2354,8 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, } tunnel_type = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; - bp->vxlan_port_cnt++; break; - case RTE_TUNNEL_TYPE_GENEVE: + case RTE_ETH_TUNNEL_TYPE_GENEVE: if (bp->geneve_port_cnt) { PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", udp_tunnel->udp_port); @@ -2135,7 +2368,6 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, } tunnel_type = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; - bp->geneve_port_cnt++; break; default: PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); @@ -2143,6 +2375,18 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, } rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, tunnel_type); + + if (rc != 0) + return rc; + + if (tunnel_type == + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN) + bp->vxlan_port_cnt++; + + if (tunnel_type == + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE) + bp->geneve_port_cnt++; + return rc; } @@ -2160,7 +2404,7 @@ bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, return rc; switch (udp_tunnel->prot_type) { - case RTE_TUNNEL_TYPE_VXLAN: + case RTE_ETH_TUNNEL_TYPE_VXLAN: if (!bp->vxlan_port_cnt) { PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); return -EINVAL; @@ -2177,7 +2421,7 @@ bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; port = bp->vxlan_fw_dst_port_id; break; - case RTE_TUNNEL_TYPE_GENEVE: + case RTE_ETH_TUNNEL_TYPE_GENEVE: if (!bp->geneve_port_cnt) { PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); return -EINVAL; @@ -2355,7 +2599,7 @@ bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) int rc; vnic = BNXT_GET_DEFAULT_VNIC(bp); - if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { + if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) { /* Remove any VLAN filters programmed */ for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) bnxt_del_vlan_filter(bp, i); @@ -2375,7 +2619,7 @@ bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) bnxt_add_vlan_filter(bp, 0); } PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", - !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); + !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)); return 0; } @@ -2388,12 +2632,16 @@ static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) /* Destroy vnic filters and vnic */ if (bp->eth_dev->data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_VLAN_FILTER) { + RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) bnxt_del_vlan_filter(bp, i); } bnxt_del_dflt_mac_filter(bp, vnic); + rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); + if (rc) + return rc; + rc = bnxt_hwrm_vnic_free(bp, vnic); if (rc) return rc; @@ -2423,7 +2671,7 @@ bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) return rc; if (bp->eth_dev->data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_VLAN_FILTER) { + RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { rc = bnxt_add_vlan_filter(bp, 0); if (rc) return rc; @@ -2441,7 +2689,7 @@ bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) return rc; PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", - !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); + !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)); return rc; } @@ -2461,22 +2709,22 @@ bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) if (!dev->data->dev_started) return 0; - if (mask & ETH_VLAN_FILTER_MASK) { + if (mask & RTE_ETH_VLAN_FILTER_MASK) { /* Enable or disable VLAN filtering */ rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); if (rc) return rc; } - if (mask & ETH_VLAN_STRIP_MASK) { + if (mask & RTE_ETH_VLAN_STRIP_MASK) { /* Enable or disable VLAN stripping */ rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); if (rc) return rc; } - if (mask & ETH_VLAN_EXTEND_MASK) { - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) + if (mask & RTE_ETH_VLAN_EXTEND_MASK) { + if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); else PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); @@ -2491,10 +2739,10 @@ bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, { struct bnxt *bp = dev->data->dev_private; int qinq = dev->data->dev_conf.rxmode.offloads & - DEV_RX_OFFLOAD_VLAN_EXTEND; + RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; - if (vlan_type != ETH_VLAN_TYPE_INNER && - vlan_type != ETH_VLAN_TYPE_OUTER) { + if (vlan_type != RTE_ETH_VLAN_TYPE_INNER && + vlan_type != RTE_ETH_VLAN_TYPE_OUTER) { PMD_DRV_LOG(ERR, "Unsupported vlan type."); return -EINVAL; @@ -2506,7 +2754,7 @@ bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, return -EINVAL; } - if (vlan_type == ETH_VLAN_TYPE_OUTER) { + if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { switch (tpid) { case RTE_ETHER_TYPE_QINQ: bp->outer_tpid_bd = @@ -2534,7 +2782,7 @@ bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, } bp->outer_tpid_bd |= tpid; PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); - } else if (vlan_type == ETH_VLAN_TYPE_INNER) { + } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) { PMD_DRV_LOG(ERR, "Can accelerate only outer vlan in QinQ\n"); return -EINVAL; @@ -2574,7 +2822,7 @@ bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, bnxt_del_dflt_mac_filter(bp, vnic); memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); - if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { /* This filter will allow only untagged packets */ rc = bnxt_add_vlan_filter(bp, 0); } else { @@ -2637,9 +2885,11 @@ bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", fw_major, fw_minor, fw_updt, fw_rsvd); + if (ret < 0) + return -EINVAL; ret += 1; /* add the size of '\0' */ - if (fw_size < (uint32_t)ret) + if (fw_size < (size_t)ret) return ret; else return 0; @@ -2695,11 +2945,15 @@ static const struct { eth_rx_burst_t pkt_burst; const char *info; } bnxt_rx_burst_info[] = { - {bnxt_recv_pkts, "Scalar"}, + {bnxt_recv_pkts, "Scalar"}, #if defined(RTE_ARCH_X86) - {bnxt_recv_pkts_vec, "Vector SSE"}, -#elif defined(RTE_ARCH_ARM64) - {bnxt_recv_pkts_vec, "Vector Neon"}, + {bnxt_recv_pkts_vec, "Vector SSE"}, +#endif +#if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) + {bnxt_recv_pkts_vec_avx2, "Vector AVX2"}, +#endif +#if defined(RTE_ARCH_ARM64) + {bnxt_recv_pkts_vec, "Vector Neon"}, #endif }; @@ -2725,11 +2979,15 @@ static const struct { eth_tx_burst_t pkt_burst; const char *info; } bnxt_tx_burst_info[] = { - {bnxt_xmit_pkts, "Scalar"}, + {bnxt_xmit_pkts, "Scalar"}, #if defined(RTE_ARCH_X86) - {bnxt_xmit_pkts_vec, "Vector SSE"}, -#elif defined(RTE_ARCH_ARM64) - {bnxt_xmit_pkts_vec, "Vector Neon"}, + {bnxt_xmit_pkts_vec, "Vector SSE"}, +#endif +#if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) + {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"}, +#endif +#if defined(RTE_ARCH_ARM64) + {bnxt_xmit_pkts_vec, "Vector Neon"}, #endif }; @@ -2753,9 +3011,10 @@ bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) { + uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; struct bnxt *bp = eth_dev->data->dev_private; uint32_t new_pkt_size; - uint32_t rc = 0; + uint32_t rc; uint32_t i; rc = is_bnxt_in_error(bp); @@ -2766,8 +3025,7 @@ int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) if (!eth_dev->data->nb_rx_queues) return rc; - new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + - VLAN_TAG_SIZE * BNXT_NUM_VLANS; + new_pkt_size = new_mtu + overhead; /* * Disallow any MTU change that would require scattered receive support @@ -2783,18 +3041,13 @@ int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) return -EINVAL; } - if (new_mtu > RTE_ETHER_MTU) { + if (new_mtu > RTE_ETHER_MTU) bp->flags |= BNXT_FLAG_JUMBO; - bp->eth_dev->data->dev_conf.rxmode.offloads |= - DEV_RX_OFFLOAD_JUMBO_FRAME; - } else { - bp->eth_dev->data->dev_conf.rxmode.offloads &= - ~DEV_RX_OFFLOAD_JUMBO_FRAME; + else bp->flags &= ~BNXT_FLAG_JUMBO; - } /* Is there a change in mtu setting? */ - if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) + if (eth_dev->data->mtu == new_mtu) return rc; for (i = 0; i < bp->nr_vnics; i++) { @@ -2816,8 +3069,8 @@ int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) } } - if (!rc) - eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; + if (bnxt_hwrm_config_host_mtu(bp)) + PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n"); PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); @@ -2835,9 +3088,8 @@ bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) if (rc) return rc; - if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { - PMD_DRV_LOG(ERR, - "PVID cannot be modified for this function\n"); + if (!BNXT_SINGLE_PF(bp)) { + PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n"); return -ENOTSUP; } bp->vlan = on ? pvid : 0; @@ -2875,33 +3127,64 @@ bnxt_dev_led_off_op(struct rte_eth_dev *dev) } static uint32_t -bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) +bnxt_rx_queue_count_op(void *rx_queue) { - struct bnxt *bp = (struct bnxt *)dev->data->dev_private; - uint32_t desc = 0, raw_cons = 0, cons; + struct bnxt *bp; struct bnxt_cp_ring_info *cpr; + uint32_t desc = 0, raw_cons, cp_ring_size; struct bnxt_rx_queue *rxq; struct rx_pkt_cmpl *rxcmp; int rc; + rxq = rx_queue; + bp = rxq->bp; + rc = is_bnxt_in_error(bp); if (rc) return rc; - rxq = dev->data->rx_queues[rx_queue_id]; cpr = rxq->cp_ring; raw_cons = cpr->cp_raw_cons; + cp_ring_size = cpr->cp_ring_struct->ring_size; while (1) { + uint32_t agg_cnt, cons, cmpl_type; + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); - rte_prefetch0(&cpr->cp_desc_ring[cons]); rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; - if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { + if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) break; - } else { - raw_cons++; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (BNXT_CHIP_P5(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); } } @@ -2911,42 +3194,110 @@ bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) static int bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) { - struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; - struct bnxt_rx_ring_info *rxr; + struct bnxt_rx_queue *rxq = rx_queue; struct bnxt_cp_ring_info *cpr; - struct rte_mbuf *rx_buf; + struct bnxt_rx_ring_info *rxr; + uint32_t desc, raw_cons, cp_ring_size; + struct bnxt *bp = rxq->bp; struct rx_pkt_cmpl *rxcmp; - uint32_t cons, cp_cons; int rc; - if (!rxq) - return -EINVAL; - - rc = is_bnxt_in_error(rxq->bp); + rc = is_bnxt_in_error(bp); if (rc) return rc; - cpr = rxq->cp_ring; - rxr = rxq->rx_ring; - if (offset >= rxq->nb_rx_desc) return -EINVAL; - cons = RING_CMP(cpr->cp_ring_struct, offset); - cp_cons = cpr->cp_raw_cons; - rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + rxr = rxq->rx_ring; + cpr = rxq->cp_ring; + cp_ring_size = cpr->cp_ring_struct->ring_size; + + /* + * For the vector receive case, the completion at the requested + * offset can be indexed directly. + */ +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) + if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { + struct rx_pkt_cmpl *rxcmp; + uint32_t cons; - if (cons > cp_cons) { - if (CMPL_VALID(rxcmp, cpr->valid)) - return RTE_ETH_RX_DESC_DONE; - } else { - if (CMPL_VALID(rxcmp, !cpr->valid)) + /* Check status of completion descriptor. */ + raw_cons = cpr->cp_raw_cons + + offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) return RTE_ETH_RX_DESC_DONE; + + /* Check whether rx desc has an mbuf attached. */ + cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); + if (cons >= rxq->rxrearm_start && + cons < rxq->rxrearm_start + rxq->rxrearm_nb) { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + return RTE_ETH_RX_DESC_AVAIL; } - rx_buf = rxr->rx_buf_ring[cons]; - if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) - return RTE_ETH_RX_DESC_UNAVAIL; +#endif + + /* + * For the non-vector receive case, scan the completion ring to + * locate the completion descriptor for the requested offset. + */ + raw_cons = cpr->cp_raw_cons; + desc = 0; + while (1) { + uint32_t agg_cnt, cons, cmpl_type; + + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) + break; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + if (desc == offset) { + cons = rxcmp->opaque; + if (rxr->rx_buf_ring[cons]) + return RTE_ETH_RX_DESC_DONE; + else + return RTE_ETH_RX_DESC_UNAVAIL; + } + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (desc == offset) + return RTE_ETH_RX_DESC_DONE; + + if (BNXT_CHIP_P5(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); + } + } return RTE_ETH_RX_DESC_AVAIL; } @@ -2955,48 +3306,53 @@ static int bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) { struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; - struct bnxt_tx_ring_info *txr; - struct bnxt_cp_ring_info *cpr; - struct bnxt_sw_tx_bd *tx_buf; - struct tx_pkt_cmpl *txcmp; - uint32_t cons, cp_cons; + struct bnxt_cp_ring_info *cpr = txq->cp_ring; + uint32_t ring_mask, raw_cons, nb_tx_pkts = 0; + struct cmpl_base *cp_desc_ring; int rc; - if (!txq) - return -EINVAL; - rc = is_bnxt_in_error(txq->bp); if (rc) return rc; - cpr = txq->cp_ring; - txr = txq->tx_ring; - if (offset >= txq->nb_tx_desc) return -EINVAL; - cons = RING_CMP(cpr->cp_ring_struct, offset); - txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; - cp_cons = cpr->cp_raw_cons; + /* Return "desc done" if descriptor is available for use. */ + if (bnxt_tx_bds_in_hw(txq) <= offset) + return RTE_ETH_TX_DESC_DONE; - if (cons > cp_cons) { - if (CMPL_VALID(txcmp, cpr->valid)) - return RTE_ETH_TX_DESC_UNAVAIL; - } else { - if (CMPL_VALID(txcmp, !cpr->valid)) - return RTE_ETH_TX_DESC_UNAVAIL; + raw_cons = cpr->cp_raw_cons; + cp_desc_ring = cpr->cp_desc_ring; + ring_mask = cpr->cp_ring_struct->ring_mask; + + /* Check to see if hw has posted a completion for the descriptor. */ + while (1) { + struct tx_cmpl *txcmp; + uint32_t cons; + + cons = RING_CMPL(ring_mask, raw_cons); + txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; + + if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) + break; + + if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) + nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque); + + if (nb_tx_pkts > offset) + return RTE_ETH_TX_DESC_DONE; + + raw_cons = NEXT_RAW_CMP(raw_cons); } - tx_buf = &txr->tx_buf_ring[cons]; - if (tx_buf->mbuf == NULL) - return RTE_ETH_TX_DESC_DONE; + /* Descriptor is pending transmit, not yet completed by hardware. */ return RTE_ETH_TX_DESC_FULL; } int -bnxt_filter_ctrl_op(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, void *arg) +bnxt_flow_ops_get_op(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops) { struct bnxt *bp = dev->data->dev_private; int ret = 0; @@ -3009,10 +3365,8 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev, bp = vfr->parent_dev->data->dev_private; /* parent is deleted while children are still valid */ if (!bp) { - PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n", - dev->data->port_id, - filter_type, - filter_op); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", + dev->data->port_id); return -EIO; } } @@ -3021,27 +3375,16 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev, if (ret) return ret; - switch (filter_type) { - case RTE_ETH_FILTER_GENERIC: - if (filter_op != RTE_ETH_FILTER_GET) - return -EINVAL; + /* PMD supports thread-safe flow operations. rte_flow API + * functions can avoid mutex for multi-thread safety. + */ + dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; - /* PMD supports thread-safe flow operations. rte_flow API - * functions can avoid mutex for multi-thread safety. - */ - dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; + if (BNXT_TRUFLOW_EN(bp)) + *ops = &bnxt_ulp_rte_flow_ops; + else + *ops = &bnxt_flow_ops; - if (BNXT_TRUFLOW_EN(bp)) - *(const void **)arg = &bnxt_ulp_rte_flow_ops; - else - *(const void **)arg = &bnxt_flow_ops; - break; - default: - PMD_DRV_LOG(ERR, - "Filter type (%d) not supported", filter_type); - ret = -EINVAL; - break; - } return ret; } @@ -3145,19 +3488,49 @@ static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; + rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); return 0; } -static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) +static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts) { struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; struct bnxt_pf_info *pf = bp->pf; uint16_t port_id; + int i = 0; uint32_t fifo; - if (!ptp) - return -ENODEV; + if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5)) + return -EINVAL; + + port_id = pf->port_id; + fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); + while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) { + rte_write32(1 << port_id, (uint8_t *)bp->bar0 + + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); + fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); + *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + + ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); + *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + + ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; + i++; + } + + if (i >= BNXT_PTP_RX_PND_CNT) + return -EBUSY; + + return 0; +} + +static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) +{ + struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; + struct bnxt_pf_info *pf = bp->pf; + uint16_t port_id; + uint32_t fifo; fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); @@ -3170,10 +3543,8 @@ static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); - if (fifo & BNXT_PTP_RX_FIFO_PENDING) { -/* bnxt_clr_rx_ts(bp); TBD */ - return -EBUSY; - } + if (fifo & BNXT_PTP_RX_FIFO_PENDING) + return bnxt_clr_rx_ts(bp, ts); *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); @@ -3191,11 +3562,13 @@ bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ns = rte_timespec_to_ns(ts); /* Set the timecounters to a new value. */ ptp->tc.nsec = ns; + ptp->tx_tstamp_tc.nsec = ns; + ptp->rx_tstamp_tc.nsec = ns; return 0; } @@ -3209,7 +3582,7 @@ bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) int rc = 0; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, @@ -3231,7 +3604,7 @@ bnxt_timesync_enable(struct rte_eth_dev *dev) int rc; if (!ptp) - return 0; + return -ENOTSUP; ptp->rx_filter = 1; ptp->tx_tstamp_en = 1; @@ -3259,8 +3632,10 @@ bnxt_timesync_enable(struct rte_eth_dev *dev) if (!BNXT_CHIP_P5(bp)) bnxt_map_ptp_regs(bp); + else + rc = bnxt_ptp_start(bp); - return 0; + return rc; } static int @@ -3270,7 +3645,7 @@ bnxt_timesync_disable(struct rte_eth_dev *dev) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ptp->rx_filter = 0; ptp->tx_tstamp_en = 0; @@ -3280,6 +3655,8 @@ bnxt_timesync_disable(struct rte_eth_dev *dev) if (!BNXT_CHIP_P5(bp)) bnxt_unmap_ptp_regs(bp); + else + bnxt_ptp_stop(bp); return 0; } @@ -3295,7 +3672,7 @@ bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, uint64_t ns; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rx_tstamp_cycles = ptp->rx_timestamp; @@ -3318,7 +3695,7 @@ bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, int rc = 0; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, @@ -3339,9 +3716,11 @@ bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ptp->tc.nsec += delta; + ptp->tx_tstamp_tc.nsec += delta; + ptp->rx_tstamp_tc.nsec += delta; return 0; } @@ -3496,6 +3875,149 @@ bnxt_set_eeprom_op(struct rte_eth_dev *dev, in_eeprom->data, in_eeprom->length); } +static int bnxt_get_module_info(struct rte_eth_dev *dev, + struct rte_eth_dev_module_info *modinfo) +{ + uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; + struct bnxt *bp = dev->data->dev_private; + int rc; + + /* No point in going further if phy status indicates + * module is not inserted or if it is powered down or + * if it is of type 10GBase-T + */ + if (bp->link_info->module_status > + HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) { + PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n", + dev->data->port_id); + return -ENOTSUP; + } + + /* This feature is not supported in older firmware versions */ + if (bp->hwrm_spec_code < 0x10202) { + PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n", + dev->data->port_id); + return -ENOTSUP; + } + + rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, + SFF_DIAG_SUPPORT_OFFSET + 1, + module_info); + + if (rc) + return rc; + + switch (module_info[0]) { + case SFF_MODULE_ID_SFP: + modinfo->type = RTE_ETH_MODULE_SFF_8472; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; + if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0) + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; + break; + case SFF_MODULE_ID_QSFP: + case SFF_MODULE_ID_QSFP_PLUS: + modinfo->type = RTE_ETH_MODULE_SFF_8436; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; + break; + case SFF_MODULE_ID_QSFP28: + modinfo->type = RTE_ETH_MODULE_SFF_8636; + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; + if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) + modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN; + break; + default: + PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id); + return -ENOTSUP; + } + + PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n", + dev->data->port_id, modinfo->type, modinfo->eeprom_len); + + return 0; +} + +static int bnxt_get_module_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *info) +{ + uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 }; + uint32_t offset = info->offset, length = info->length; + uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; + struct bnxt *bp = dev->data->dev_private; + uint8_t *data = info->data; + uint8_t page = offset >> 7; + uint8_t max_pages = 2; + uint8_t opt_pages; + int rc; + + rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, + SFF_DIAG_SUPPORT_OFFSET + 1, + module_info); + if (rc) + return rc; + + switch (module_info[0]) { + case SFF_MODULE_ID_SFP: + module_info[SFF_DIAG_SUPPORT_OFFSET] = 0; + if (module_info[SFF_DIAG_SUPPORT_OFFSET]) { + pg_addr[2] = I2C_DEV_ADDR_A2; + pg_addr[3] = I2C_DEV_ADDR_A2; + max_pages = 4; + } + break; + case SFF_MODULE_ID_QSFP28: + rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, + SFF8636_OPT_PAGES_OFFSET, + 1, &opt_pages); + if (rc) + return rc; + + if (opt_pages & SFF8636_PAGE1_MASK) { + pg_addr[2] = I2C_DEV_ADDR_A0; + max_pages = 3; + } + if (opt_pages & SFF8636_PAGE2_MASK) { + pg_addr[3] = I2C_DEV_ADDR_A0; + max_pages = 4; + } + if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) { + pg_addr[4] = I2C_DEV_ADDR_A0; + max_pages = 5; + } + break; + default: + break; + } + + memset(data, 0, length); + + offset &= 0xff; + while (length && page < max_pages) { + uint8_t raw_page = page ? page - 1 : 0; + uint16_t chunk; + + if (pg_addr[page] == I2C_DEV_ADDR_A2) + raw_page = 0; + else if (page) + offset |= 0x80; + chunk = RTE_MIN(length, 256 - offset); + + if (pg_addr[page]) { + rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page], + raw_page, offset, + chunk, data); + if (rc) + return rc; + } + + data += chunk; + length -= chunk; + offset = 0; + page += 1 + (chunk > 128); + } + + return length ? -EINVAL : 0; +} + /* * Initialization */ @@ -3552,11 +4074,13 @@ static const struct eth_dev_ops bnxt_dev_ops = { .rx_queue_stop = bnxt_rx_queue_stop, .tx_queue_start = bnxt_tx_queue_start, .tx_queue_stop = bnxt_tx_queue_stop, - .filter_ctrl = bnxt_filter_ctrl_op, + .flow_ops_get = bnxt_flow_ops_get_op, .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, .get_eeprom_length = bnxt_get_eeprom_length_op, .get_eeprom = bnxt_get_eeprom_op, .set_eeprom = bnxt_set_eeprom_op, + .get_module_info = bnxt_get_module_info, + .get_module_eeprom = bnxt_get_module_eeprom, .timesync_enable = bnxt_timesync_enable, .timesync_disable = bnxt_timesync_disable, .timesync_read_time = bnxt_timesync_read_time, @@ -3620,13 +4144,19 @@ static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) uint32_t val = info->reset_reg_val[index]; uint32_t reg = info->reset_reg[index]; uint32_t type, offset; + int ret; type = BNXT_FW_STATUS_REG_TYPE(reg); offset = BNXT_FW_STATUS_REG_OFF(reg); switch (type) { case BNXT_FW_STATUS_REG_TYPE_CFG: - rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); + ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", + val, offset); + return; + } break; case BNXT_FW_STATUS_REG_TYPE_GRC: offset = bnxt_map_reset_regs(bp, offset); @@ -3646,11 +4176,37 @@ static void bnxt_dev_cleanup(struct bnxt *bp) bp->eth_dev->data->dev_link.link_status = 0; bp->link_info->link_up = 0; if (bp->eth_dev->data->dev_started) - bnxt_dev_stop_op(bp->eth_dev); + bnxt_dev_stop(bp->eth_dev); bnxt_uninit_resources(bp, true); } +static int +bnxt_check_fw_reset_done(struct bnxt *bp) +{ + int timeout = bp->fw_reset_max_msecs; + uint16_t val = 0; + int rc; + + do { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return rc; + } + if (val != 0xffff) + break; + rte_delay_ms(1); + } while (timeout--); + + if (val == 0xffff) { + PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); + return -1; + } + + return 0; +} + static int bnxt_restore_vlan_filters(struct bnxt *bp) { struct rte_eth_dev *dev = bp->eth_dev; @@ -3681,7 +4237,7 @@ static int bnxt_restore_mac_filters(struct bnxt *bp) struct rte_ether_addr *addr; uint64_t pool_mask; uint32_t pool = 0; - uint16_t i; + uint32_t i; int rc; if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) @@ -3741,27 +4297,44 @@ static int bnxt_restore_filters(struct bnxt *bp) return ret; } -static void bnxt_dev_recover(void *arg) +static int bnxt_check_fw_ready(struct bnxt *bp) { - struct bnxt *bp = arg; int timeout = bp->fw_reset_max_msecs; int rc = 0; - /* Clear Error flag so that device re-init should happen */ - bp->flags &= ~BNXT_FLAG_FATAL_ERROR; - do { - rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); + rc = bnxt_hwrm_poll_ver_get(bp); if (rc == 0) break; rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); timeout -= BNXT_FW_READY_WAIT_INTERVAL; - } while (rc && timeout); + } while (rc && timeout > 0); + + if (rc) + PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); + + return rc; +} + +static void bnxt_dev_recover(void *arg) +{ + struct bnxt *bp = arg; + int rc = 0; + + pthread_mutex_lock(&bp->err_recovery_lock); + + if (!bp->fw_reset_min_msecs) { + rc = bnxt_check_fw_reset_done(bp); + if (rc) + goto err; + } - if (rc) { - PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); + /* Clear Error flag so that device re-init should happen */ + bp->flags &= ~BNXT_FLAG_FATAL_ERROR; + + rc = bnxt_check_fw_ready(bp); + if (rc) goto err; - } rc = bnxt_init_resources(bp, true); if (rc) { @@ -3783,26 +4356,52 @@ static void bnxt_dev_recover(void *arg) goto err_start; PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return; err_start: - bnxt_dev_stop_op(bp->eth_dev); + bnxt_dev_stop(bp->eth_dev); err: bp->flags |= BNXT_FLAG_FATAL_ERROR; bnxt_uninit_resources(bp, false); + if (bp->eth_dev->data->dev_conf.intr_conf.rmv) + rte_eth_dev_callback_process(bp->eth_dev, + RTE_ETH_EVENT_INTR_RMV, + NULL); + pthread_mutex_unlock(&bp->err_recovery_lock); PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); } void bnxt_dev_reset_and_resume(void *arg) { struct bnxt *bp = arg; + uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; + uint16_t val = 0; int rc; bnxt_dev_cleanup(bp); bnxt_wait_for_device_shutdown(bp); - rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, - bnxt_dev_recover, (void *)bp); + /* During some fatal firmware error conditions, the PCI config space + * register 0x2e which normally contains the subsystem ID will become + * 0xffff. This register will revert back to the normal value after + * the chip has completed core reset. If we detect this condition, + * we can poll this config register immediately for the value to revert. + */ + if (bp->flags & BNXT_FLAG_FATAL_ERROR) { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return; + } + if (val == 0xffff) { + bp->fw_reset_min_msecs = 0; + us = 1; + } + } + + rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); if (rc) PMD_DRV_LOG(ERR, "Error setting recovery alarm"); } @@ -3812,13 +4411,17 @@ uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) struct bnxt_error_recovery_info *info = bp->recovery_info; uint32_t reg = info->status_regs[index]; uint32_t type, offset, val = 0; + int ret = 0; type = BNXT_FW_STATUS_REG_TYPE(reg); offset = BNXT_FW_STATUS_REG_OFF(reg); switch (type) { case BNXT_FW_STATUS_REG_TYPE_CFG: - rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); + ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); + if (ret < 0) + PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", + offset); break; case BNXT_FW_STATUS_REG_TYPE_GRC: offset = info->mapped_status_regs[index]; @@ -3839,11 +4442,11 @@ static int bnxt_fw_reset_all(struct bnxt *bp) int rc = 0; if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { - /* Reset through master function driver */ + /* Reset through primary function driver */ for (i = 0; i < info->reg_array_cnt; i++) bnxt_write_fw_reset_reg(bp, i); /* Wait for time specified by FW after triggering reset */ - rte_delay_ms(info->master_func_wait_period_after_reset); + rte_delay_ms(info->primary_func_wait_period_after_reset); } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { /* Reset with the help of Kong processor */ rc = bnxt_hwrm_fw_reset(bp); @@ -3860,8 +4463,8 @@ static void bnxt_fw_reset_cb(void *arg) struct bnxt_error_recovery_info *info = bp->recovery_info; int rc = 0; - /* Only Master function can do FW reset */ - if (bnxt_is_master_func(bp) && + /* Only Primary function can do FW reset */ + if (bnxt_is_primary_func(bp) && bnxt_is_recovery_enabled(bp)) { rc = bnxt_fw_reset_all(bp); if (rc) { @@ -3889,8 +4492,8 @@ static void bnxt_fw_reset_cb(void *arg) * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. * When the driver detects heartbeat stop or change in reset_counter, * it has to trigger a reset to recover from the error condition. - * A “master PF” is the function who will have the privilege to - * initiate the chimp reset. The master PF will be elected by the + * A “primary function” is the function who will have the privilege to + * initiate the chimp reset. The primary function will be elected by the * firmware and will be notified through async message. */ static void bnxt_check_fw_health(void *arg) @@ -3924,10 +4527,12 @@ reset: bp->flags |= BNXT_FLAG_FATAL_ERROR; bp->flags |= BNXT_FLAG_FW_RESET; + bnxt_stop_rxtx(bp); + PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); - if (bnxt_is_master_func(bp)) - wait_msec = info->master_func_wait_period; + if (bnxt_is_primary_func(bp)) + wait_msec = info->primary_func_wait_period; else wait_msec = info->normal_func_wait_period; @@ -3959,9 +4564,6 @@ done: static void bnxt_cancel_fw_health_check(struct bnxt *bp) { - if (!bnxt_is_recovery_enabled(bp)) - return; - rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; } @@ -3979,6 +4581,7 @@ static bool bnxt_vf_pciid(uint16_t device_id) case BROADCOM_DEV_ID_58802_VF: case BROADCOM_DEV_ID_57500_VF1: case BROADCOM_DEV_ID_57500_VF2: + case BROADCOM_DEV_ID_58818_VF: /* FALLTHROUGH */ return true; default: @@ -4001,6 +4604,10 @@ static bool bnxt_p5_device(uint16_t device_id) case BROADCOM_DEV_ID_57502_MF2: case BROADCOM_DEV_ID_57500_VF1: case BROADCOM_DEV_ID_57500_VF2: + case BROADCOM_DEV_ID_58812: + case BROADCOM_DEV_ID_58814: + case BROADCOM_DEV_ID_58818: + case BROADCOM_DEV_ID_58818_VF: /* FALLTHROUGH */ return true; default: @@ -4023,7 +4630,7 @@ bool bnxt_stratus_device(struct bnxt *bp) } } -static int bnxt_init_board(struct rte_eth_dev *eth_dev) +static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); struct bnxt *bp = eth_dev->data->dev_private; @@ -4077,7 +4684,7 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, if (!mz) { mz = rte_memzone_reserve_aligned(mz_name, rmem->nr_pages * 8, - SOCKET_ID_ANY, + bp->eth_dev->device->numa_node, RTE_MEMZONE_2MB | RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_IOVA_CONTIG, @@ -4100,7 +4707,7 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, if (!mz) { mz = rte_memzone_reserve_aligned(mz_name, mem_size, - SOCKET_ID_ANY, + bp->eth_dev->device->numa_node, RTE_MEMZONE_1GB | RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_IOVA_CONTIG, @@ -4197,39 +4804,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp) ctx_pg = &ctx->qp_mem; ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; - mem_size = ctx->qp_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); - if (rc) - return rc; + if (ctx->qp_entry_size) { + mem_size = ctx->qp_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->srq_mem; ctx_pg->entries = ctx->srq_max_l2_entries; - mem_size = ctx->srq_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); - if (rc) - return rc; + if (ctx->srq_entry_size) { + mem_size = ctx->srq_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->cq_mem; ctx_pg->entries = ctx->cq_max_l2_entries; - mem_size = ctx->cq_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); - if (rc) - return rc; + if (ctx->cq_entry_size) { + mem_size = ctx->cq_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->vnic_mem; ctx_pg->entries = ctx->vnic_max_vnic_entries + ctx->vnic_max_ring_table_entries; - mem_size = ctx->vnic_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); - if (rc) - return rc; + if (ctx->vnic_entry_size) { + mem_size = ctx->vnic_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->stat_mem; ctx_pg->entries = ctx->stat_max_entries; - mem_size = ctx->stat_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); - if (rc) - return rc; + if (ctx->stat_entry_size) { + mem_size = ctx->stat_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); + if (rc) + return rc; + } min = ctx->tqm_min_entries_per_ring; @@ -4243,13 +4860,22 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp) entries = clamp_t(uint32_t, entries, min, ctx->tqm_max_entries_per_ring); for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { + /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. + * i > 8 is other ext rings. + */ ctx_pg = ctx->tqm_mem[i]; ctx_pg->entries = i ? entries : entries_sp; - mem_size = ctx->tqm_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); - if (rc) - return rc; - ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; + if (ctx->tqm_entry_size) { + mem_size = ctx->tqm_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, + "tqm_mem", i); + if (rc) + return rc; + } + if (i < BNXT_MAX_TQM_LEGACY_RINGS) + ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; + else + ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; } ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; @@ -4375,7 +5001,7 @@ static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); bnxt_eth_hw_addr_random(bp->mac_addr); PMD_DRV_LOG(INFO, - "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", + "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n", bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); @@ -4421,6 +5047,32 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } +struct bnxt * +bnxt_get_bp(uint16_t port) +{ + struct bnxt *bp; + struct rte_eth_dev *dev; + + if (!rte_eth_dev_is_valid_port(port)) { + PMD_DRV_LOG(ERR, "Invalid port %d\n", port); + return NULL; + } + + dev = &rte_eth_devices[port]; + if (!is_bnxt_supported(dev)) { + PMD_DRV_LOG(ERR, "Device %d not supported\n", port); + return NULL; + } + + bp = (struct bnxt *)dev->data->dev_private; + if (!BNXT_TRUFLOW_EN(bp)) { + PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); + return NULL; + } + + return bp; +} + uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, enum bnxt_ulp_intf_type type) @@ -4445,6 +5097,39 @@ bnxt_get_svif(uint16_t port_id, bool func_svif, return func_svif ? bp->func_svif : bp->port_svif; } +void +bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, + uint8_t *mac, uint8_t *parent_mac) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && + type != BNXT_ULP_INTF_TYPE_PF) + return; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); + + if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) + memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); +} + +uint16_t +bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) +{ + struct rte_eth_dev *eth_dev; + struct bnxt *bp; + + if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) + return 0; + + eth_dev = &rte_eth_devices[port]; + bp = eth_dev->data->dev_private; + + return bp->parent->vnic; +} uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) { @@ -4648,7 +5333,11 @@ static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) return 0; } -static int bnxt_init_fw(struct bnxt *bp) +/* This function gets the FW version along with the + * capabilities(MAX and current) of the function, vnic, + * error recovery, phy and other chip related info + */ +static int bnxt_get_config(struct bnxt *bp) { uint16_t mtu; int rc = 0; @@ -4689,6 +5378,10 @@ static int bnxt_init_fw(struct bnxt *bp) if (rc) return rc; + rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); + if (rc) + return rc; + bnxt_hwrm_port_mac_qcfg(bp); bnxt_hwrm_parent_pf_qcfg(bp); @@ -4724,8 +5417,15 @@ bnxt_init_locks(struct bnxt *bp) } err = pthread_mutex_init(&bp->health_check_lock, NULL); - if (err) + if (err) { PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); + return err; + } + + err = pthread_mutex_init(&bp->err_recovery_lock, NULL); + if (err) + PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); + return err; } @@ -4733,7 +5433,7 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) { int rc = 0; - rc = bnxt_init_fw(bp); + rc = bnxt_get_config(bp); if (rc) return rc; @@ -4790,47 +5490,43 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return rc; } - rc = bnxt_init_locks(bp); - if (rc) - return rc; - return 0; } static int -bnxt_parse_devarg_truflow(__rte_unused const char *key, - const char *value, void *opaque_arg) +bnxt_parse_devarg_accum_stats(__rte_unused const char *key, + const char *value, void *opaque_arg) { struct bnxt *bp = opaque_arg; - unsigned long truflow; + unsigned long accum_stats; char *end = NULL; if (!value || !opaque_arg) { PMD_DRV_LOG(ERR, - "Invalid parameter passed to truflow devargs.\n"); + "Invalid parameter passed to accum-stats devargs.\n"); return -EINVAL; } - truflow = strtoul(value, &end, 10); + accum_stats = strtoul(value, &end, 10); if (end == NULL || *end != '\0' || - (truflow == ULONG_MAX && errno == ERANGE)) { + (accum_stats == ULONG_MAX && errno == ERANGE)) { PMD_DRV_LOG(ERR, - "Invalid parameter passed to truflow devargs.\n"); + "Invalid parameter passed to accum-stats devargs.\n"); return -EINVAL; } - if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { + if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { PMD_DRV_LOG(ERR, - "Invalid value passed to truflow devargs.\n"); + "Invalid value passed to accum-stats devargs.\n"); return -EINVAL; } - if (truflow) { - bp->flags |= BNXT_FLAG_TRUFLOW_EN; - PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); + if (accum_stats) { + bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; + PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); } else { - bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; - PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); + bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; + PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); } return 0; @@ -4907,6 +5603,42 @@ bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, return 0; } +static int +bnxt_parse_devarg_app_id(__rte_unused const char *key, + const char *value, void *opaque_arg) +{ + struct bnxt *bp = opaque_arg; + unsigned long app_id; + char *end = NULL; + + if (!value || !opaque_arg) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to app-id " + "devargs.\n"); + return -EINVAL; + } + + app_id = strtoul(value, &end, 10); + if (end == NULL || *end != '\0' || + (app_id == ULONG_MAX && errno == ERANGE)) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to app_id " + "devargs.\n"); + return -EINVAL; + } + + if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { + PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", + (uint16_t)app_id); + return -EINVAL; + } + + bp->app_id = app_id; + PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); + + return 0; +} + static int bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -5130,40 +5862,53 @@ bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, return 0; } -static void +static int bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) { struct rte_kvargs *kvlist; + int ret; if (devargs == NULL) - return; + return 0; kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); if (kvlist == NULL) - return; - - /* - * Handler for "truflow" devarg. - * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" - */ - rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, - bnxt_parse_devarg_truflow, bp); + return -EINVAL; /* * Handler for "flow_xstat" devarg. * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" */ - rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, - bnxt_parse_devarg_flow_xstat, bp); + ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, + bnxt_parse_devarg_flow_xstat, bp); + if (ret) + goto err; + /* + * Handler for "accum-stats" devarg. + * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" + */ + rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, + bnxt_parse_devarg_accum_stats, bp); /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" */ - rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, - bnxt_parse_devarg_max_num_kflows, bp); + ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, + bnxt_parse_devarg_max_num_kflows, bp); + if (ret) + goto err; + +err: + /* + * Handler for "app-id" devarg. + * Invoked as for ex: "-a 000:00:0d.0,app-id=1" + */ + rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, + bnxt_parse_devarg_app_id, bp); rte_kvargs_free(kvlist); + return ret; } static int bnxt_alloc_switch_domain(struct bnxt *bp) @@ -5184,38 +5929,14 @@ static int bnxt_alloc_switch_domain(struct bnxt *bp) return rc; } -static int -bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) +/* Allocate and initialize various fields in bnxt struct that + * need to be allocated/destroyed only once in the lifetime of the driver + */ +static int bnxt_drv_init(struct rte_eth_dev *eth_dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - static int version_printed; - struct bnxt *bp; - int rc; - - if (version_printed++ == 0) - PMD_DRV_LOG(INFO, "%s\n", bnxt_version); - - eth_dev->dev_ops = &bnxt_dev_ops; - eth_dev->rx_queue_count = bnxt_rx_queue_count_op; - eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; - eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; - eth_dev->rx_pkt_burst = &bnxt_recv_pkts; - eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; - - /* - * For secondary processes, we don't initialise any further - * as primary has already done this work. - */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; - - rte_eth_copy_pci_info(eth_dev, pci_dev); - eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; - - bp = eth_dev->data->dev_private; - - /* Parse dev arguments passed on when starting the DPDK application. */ - bnxt_parse_dev_args(bp, pci_dev->device.devargs); + struct bnxt *bp = eth_dev->data->dev_private; + int rc = 0; bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -5247,7 +5968,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) } } - rc = bnxt_init_board(eth_dev); + rc = bnxt_map_pci_bars(eth_dev); if (rc) { PMD_DRV_LOG(ERR, "Failed to initialize board rc: %x\n", rc); @@ -5256,27 +5977,77 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) rc = bnxt_alloc_pf_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_link_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_parent_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_hwrm_resources(bp); if (rc) { PMD_DRV_LOG(ERR, - "Failed to allocate hwrm resource rc: %x\n", rc); - goto error_free; + "Failed to allocate response buffer rc: %x\n", rc); + return rc; } rc = bnxt_alloc_leds_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_cos_queues(bp); + if (rc) + return rc; + + rc = bnxt_init_locks(bp); + if (rc) + return rc; + + rc = bnxt_alloc_switch_domain(bp); + if (rc) + return rc; + + return rc; +} + +static int +bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + static int version_printed; + struct bnxt *bp; + int rc; + + if (version_printed++ == 0) + PMD_DRV_LOG(INFO, "%s\n", bnxt_version); + + eth_dev->dev_ops = &bnxt_dev_ops; + eth_dev->rx_queue_count = bnxt_rx_queue_count_op; + eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; + eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; + eth_dev->rx_pkt_burst = &bnxt_recv_pkts; + eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; + + /* + * For secondary processes, we don't initialise any further + * as primary has already done this work. + */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pci_dev); + eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + + bp = eth_dev->data->dev_private; + + /* Parse dev arguments passed on when starting the DPDK application. */ + rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); + if (rc) + goto error_free; + + rc = bnxt_drv_init(eth_dev); if (rc) goto error_free; @@ -5288,10 +6059,9 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) if (rc) goto error_free; - bnxt_alloc_switch_domain(bp); - PMD_DRV_LOG(INFO, - DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", + "Found %s device at mem %" PRIX64 ", node addr %pM\n", + DRV_MODULE_NAME, pci_dev->mem_resource[0].phys_addr, pci_dev->mem_resource[0].addr); @@ -5371,18 +6141,6 @@ bnxt_free_error_recovery_info(struct bnxt *bp) bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; } -static void -bnxt_uninit_locks(struct bnxt *bp) -{ - pthread_mutex_destroy(&bp->flow_lock); - pthread_mutex_destroy(&bp->def_cp_lock); - pthread_mutex_destroy(&bp->health_check_lock); - if (bp->rep_info) { - pthread_mutex_destroy(&bp->rep_info->vfr_lock); - pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); - } -} - static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) { @@ -5392,9 +6150,12 @@ bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) bnxt_free_mem(bp, reconfig_dev); bnxt_hwrm_func_buf_unrgtr(bp); - rte_free(bp->pf->vf_req_buf); + if (bp->pf != NULL) { + rte_free(bp->pf->vf_req_buf); + bp->pf->vf_req_buf = NULL; + } - rc = bnxt_hwrm_func_driver_unregister(bp, 0); + rc = bnxt_hwrm_func_driver_unregister(bp); bp->flags &= ~BNXT_FLAG_REGISTERED; bnxt_free_ctx_mem(bp); if (!reconfig_dev) { @@ -5404,8 +6165,9 @@ bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) bnxt_uninit_ctx_mem(bp); - bnxt_uninit_locks(bp); bnxt_free_flow_stats_info(bp); + if (bp->rep_info != NULL) + bnxt_free_switch_domain(bp); bnxt_free_rep_info(bp); rte_free(bp->ptp_cfg); bp->ptp_cfg = NULL; @@ -5513,6 +6275,13 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, int i, ret = 0; struct rte_kvargs *kvlist = NULL; + if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) + return 0; + if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { + PMD_DRV_LOG(ERR, "unsupported representor type %d\n", + eth_da->type); + return -ENOTSUP; + } num_rep = eth_da->nb_representor_ports; if (num_rep > BNXT_MAX_VF_REPS) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", @@ -5753,6 +6522,7 @@ static int bnxt_pci_remove(struct rte_pci_device *pci_dev) static struct rte_pci_driver bnxt_rte_pmd = { .id_table = bnxt_pci_id_map, .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | + RTE_PCI_DRV_INTR_RMV | RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs * and OVS-DPDK */ @@ -5774,7 +6544,7 @@ bool is_bnxt_supported(struct rte_eth_dev *dev) return is_device_supported(dev, &bnxt_rte_pmd); } -RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); +RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); -RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); +