X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt_ethdev.c;h=2bd889b15b531134bec57b2ff4ddcf9e282ed13b;hb=6a11a1eac0b6dcd52580eef99cf6f09e3361cc3b;hp=9d5c8aa0f87617e2b8f0676ad9a61c0d3cd7b94a;hpb=c50944609ec7b2e63c3a9b48599a1864e35ac794;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 9d5c8aa0f8..2bd889b15b 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2014-2018 Broadcom + * Copyright(c) 2014-2021 Broadcom * All rights reserved. */ @@ -7,8 +7,8 @@ #include #include -#include -#include +#include +#include #include #include #include @@ -47,27 +47,13 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, @@ -94,6 +80,10 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, { .vendor_id = 0, /* sentinel */ }, }; @@ -689,7 +679,7 @@ static int bnxt_update_phy_setting(struct bnxt *bp) return rc; } -static int bnxt_init_chip(struct bnxt *bp) +static int bnxt_start_nic(struct bnxt *bp) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; @@ -758,11 +748,17 @@ skip_cosq_cfg: goto err_out; } + /* default vnic 0 */ + rc = bnxt_setup_one_vnic(bp, 0); + if (rc) + goto err_out; /* VNIC configuration */ - for (i = 0; i < bp->nr_vnics; i++) { - rc = bnxt_setup_one_vnic(bp, i); - if (rc) - goto err_out; + if (BNXT_RFS_NEEDS_VNIC(bp)) { + for (i = 1; i < bp->nr_vnics; i++) { + rc = bnxt_setup_one_vnic(bp, i); + if (rc) + goto err_out; + } } rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); @@ -1147,6 +1143,9 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) return 1; + if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) + return 1; + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; @@ -1163,6 +1162,12 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; + /* Disable vector mode RX for Stingray2 for now */ + if (BNXT_CHIP_SR2(bp)) { + bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; + return bnxt_recv_pkts; + } + #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) #ifndef RTE_LIBRTE_IEEE1588 /* @@ -1179,6 +1184,7 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_VLAN_FILTER)) && !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && @@ -1202,12 +1208,17 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) } static eth_tx_burst_t -bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) +bnxt_transmit_function(struct rte_eth_dev *eth_dev) { + struct bnxt *bp = eth_dev->data->dev_private; + + /* Disable vector mode TX for Stingray2 for now */ + if (BNXT_CHIP_SR2(bp)) + return bnxt_xmit_pkts; + #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) #ifndef RTE_LIBRTE_IEEE1588 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; - struct bnxt *bp = eth_dev->data->dev_private; /* * Vector mode transmit can be enabled only if not using scatter rx @@ -1252,85 +1263,14 @@ static int bnxt_handle_if_change_status(struct bnxt *bp) return rc; } -static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) -{ - struct bnxt *bp = eth_dev->data->dev_private; - uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; - int vlan_mask = 0; - int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; - - if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); - return -EINVAL; - } - - if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) - PMD_DRV_LOG(ERR, - "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", - bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); - - do { - rc = bnxt_hwrm_if_change(bp, true); - if (rc == 0 || rc != -EAGAIN) - break; - - rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); - } while (retry_cnt--); - - if (rc) - return rc; - - if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { - rc = bnxt_handle_if_change_status(bp); - if (rc) - return rc; - } - - bnxt_enable_int(bp); - - rc = bnxt_init_chip(bp); - if (rc) - goto error; - - eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); - eth_dev->data->dev_started = 1; - - bnxt_link_update_op(eth_dev, 1); - - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) - vlan_mask |= ETH_VLAN_FILTER_MASK; - if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) - vlan_mask |= ETH_VLAN_STRIP_MASK; - rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); - if (rc) - goto error; - - /* Initialize bnxt ULP port details */ - rc = bnxt_ulp_port_init(bp); - if (rc) - goto error; - - eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); - eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); - - bnxt_schedule_fw_health_check(bp); - - return 0; - -error: - bnxt_shutdown_nic(bp); - bnxt_free_tx_mbufs(bp); - bnxt_free_rx_mbufs(bp); - bnxt_hwrm_if_change(bp, false); - eth_dev->data->dev_started = 0; - return rc; -} - static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; int rc = 0; + if (!BNXT_SINGLE_PF(bp)) + return -ENOTSUP; + if (!bp->link_info->link_up) rc = bnxt_set_hwrm_link_config(bp, true); if (!rc) @@ -1344,6 +1284,9 @@ static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; + if (!BNXT_SINGLE_PF(bp)) + return -ENOTSUP; + eth_dev->data->dev_link.link_status = 0; bnxt_set_hwrm_link_config(bp, false); bp->link_info->link_up = 0; @@ -1363,8 +1306,74 @@ static void bnxt_free_switch_domain(struct bnxt *bp) } } -/* Unload the driver, release resources */ -static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) +static void bnxt_ptp_get_current_time(void *arg) +{ + struct bnxt *bp = arg; + struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; + int rc; + + rc = is_bnxt_in_error(bp); + if (rc) + return; + + if (!ptp) + return; + + bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, + &ptp->current_time); + + rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); + if (rc != 0) { + PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); + bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; + } +} + +static int bnxt_schedule_ptp_alarm(struct bnxt *bp) +{ + struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; + int rc; + + if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) + return 0; + + bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, + &ptp->current_time); + + rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); + return rc; +} + +static void bnxt_cancel_ptp_alarm(struct bnxt *bp) +{ + if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { + rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); + bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; + } +} + +static void bnxt_ptp_stop(struct bnxt *bp) +{ + bnxt_cancel_ptp_alarm(bp); + bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; +} + +static int bnxt_ptp_start(struct bnxt *bp) +{ + int rc; + + rc = bnxt_schedule_ptp_alarm(bp); + if (rc != 0) { + PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); + } else { + bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; + bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; + } + + return rc; +} + +static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); @@ -1394,6 +1403,9 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) bnxt_cancel_fw_health_check(bp); + if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) + bnxt_cancel_ptp_alarm(bp); + /* Do not bring link down during reset recovery */ if (!is_bnxt_in_error(bp)) { bnxt_dev_set_link_down_op(eth_dev); @@ -1432,41 +1444,159 @@ static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) return 0; } -static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) +/* Unload the driver, release resources */ +static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; - int ret = 0; - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; + pthread_mutex_lock(&bp->err_recovery_lock); + if (bp->flags & BNXT_FLAG_FW_RESET) { + PMD_DRV_LOG(ERR, + "Adapter recovering from error..Please retry\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return -EAGAIN; + } + pthread_mutex_unlock(&bp->err_recovery_lock); - /* cancel the recovery handler before remove dev */ - rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); - rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); - bnxt_cancel_fc_thread(bp); + return bnxt_dev_stop(eth_dev); +} - if (eth_dev->data->dev_started) - ret = bnxt_dev_stop_op(eth_dev); +static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; + uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; + int vlan_mask = 0; + int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; - bnxt_free_switch_domain(bp); + if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); + return -EINVAL; + } - bnxt_uninit_resources(bp, false); + if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) + PMD_DRV_LOG(ERR, + "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", + bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); + do { + rc = bnxt_hwrm_if_change(bp, true); + if (rc == 0 || rc != -EAGAIN) + break; + + rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); + } while (retry_cnt--); + + if (rc) + return rc; + + if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { + rc = bnxt_handle_if_change_status(bp); + if (rc) + return rc; + } + + bnxt_enable_int(bp); + + eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); + + rc = bnxt_start_nic(bp); + if (rc) + goto error; + + eth_dev->data->dev_started = 1; + + bnxt_link_update_op(eth_dev, 1); + + if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) + vlan_mask |= ETH_VLAN_FILTER_MASK; + if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) + vlan_mask |= ETH_VLAN_STRIP_MASK; + rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); + if (rc) + goto error; + + /* Initialize bnxt ULP port details */ + rc = bnxt_ulp_port_init(bp); + if (rc) + goto error; + + eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); + eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); + + bnxt_schedule_fw_health_check(bp); + + if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) + bnxt_schedule_ptp_alarm(bp); + + return 0; + +error: + bnxt_dev_stop(eth_dev); + return rc; +} + +static void +bnxt_uninit_locks(struct bnxt *bp) +{ + pthread_mutex_destroy(&bp->flow_lock); + pthread_mutex_destroy(&bp->def_cp_lock); + pthread_mutex_destroy(&bp->health_check_lock); + pthread_mutex_destroy(&bp->err_recovery_lock); + if (bp->rep_info) { + pthread_mutex_destroy(&bp->rep_info->vfr_lock); + pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); + } +} + +static void bnxt_drv_uninit(struct bnxt *bp) +{ + bnxt_free_switch_domain(bp); bnxt_free_leds_info(bp); bnxt_free_cos_queues(bp); bnxt_free_link_info(bp); bnxt_free_pf_info(bp); bnxt_free_parent_info(bp); + bnxt_uninit_locks(bp); rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); bp->tx_mem_zone = NULL; rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); bp->rx_mem_zone = NULL; - bnxt_hwrm_free_vf_info(bp); + bnxt_free_vf_info(bp); rte_free(bp->grp_info); bp->grp_info = NULL; +} + +static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) +{ + struct bnxt *bp = eth_dev->data->dev_private; + int ret = 0; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + pthread_mutex_lock(&bp->err_recovery_lock); + if (bp->flags & BNXT_FLAG_FW_RESET) { + PMD_DRV_LOG(ERR, + "Adapter recovering from error...Please retry\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return -EAGAIN; + } + pthread_mutex_unlock(&bp->err_recovery_lock); + + /* cancel the recovery handler before remove dev */ + rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); + rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); + bnxt_cancel_fc_thread(bp); + + if (eth_dev->data->dev_started) + ret = bnxt_dev_stop(eth_dev); + + bnxt_uninit_resources(bp, false); + + bnxt_drv_uninit(bp); return ret; } @@ -2407,6 +2537,10 @@ static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) } bnxt_del_dflt_mac_filter(bp, vnic); + rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); + if (rc) + return rc; + rc = bnxt_hwrm_vnic_free(bp, vnic); if (rc) return rc; @@ -2891,8 +3025,8 @@ static uint32_t bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) { struct bnxt *bp = (struct bnxt *)dev->data->dev_private; - uint32_t desc = 0, raw_cons = 0, cons; struct bnxt_cp_ring_info *cpr; + uint32_t desc = 0, raw_cons; struct bnxt_rx_queue *rxq; struct rx_pkt_cmpl *rxcmp; int rc; @@ -2906,15 +3040,43 @@ bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) raw_cons = cpr->cp_raw_cons; while (1) { + uint32_t agg_cnt, cons, cmpl_type; + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); - rte_prefetch0(&cpr->cp_desc_ring[cons]); rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; - if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { + if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) break; - } else { - raw_cons++; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (BNXT_CHIP_P5(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); } } @@ -2924,42 +3086,109 @@ bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) static int bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) { - struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; - struct bnxt_rx_ring_info *rxr; + struct bnxt_rx_queue *rxq = rx_queue; struct bnxt_cp_ring_info *cpr; - struct rte_mbuf *rx_buf; + struct bnxt_rx_ring_info *rxr; + uint32_t desc, raw_cons; + struct bnxt *bp = rxq->bp; struct rx_pkt_cmpl *rxcmp; - uint32_t cons, cp_cons; int rc; - if (!rxq) - return -EINVAL; - - rc = is_bnxt_in_error(rxq->bp); + rc = is_bnxt_in_error(bp); if (rc) return rc; - cpr = rxq->cp_ring; - rxr = rxq->rx_ring; - if (offset >= rxq->nb_rx_desc) return -EINVAL; - cons = RING_CMP(cpr->cp_ring_struct, offset); - cp_cons = cpr->cp_raw_cons; - rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + rxr = rxq->rx_ring; + cpr = rxq->cp_ring; - if (cons > cp_cons) { - if (CMPL_VALID(rxcmp, cpr->valid)) - return RTE_ETH_RX_DESC_DONE; - } else { - if (CMPL_VALID(rxcmp, !cpr->valid)) + /* + * For the vector receive case, the completion at the requested + * offset can be indexed directly. + */ +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) + if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { + struct rx_pkt_cmpl *rxcmp; + uint32_t cons; + + /* Check status of completion descriptor. */ + raw_cons = cpr->cp_raw_cons + + offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) return RTE_ETH_RX_DESC_DONE; + + /* Check whether rx desc has an mbuf attached. */ + cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); + if (cons >= rxq->rxrearm_start && + cons < rxq->rxrearm_start + rxq->rxrearm_nb) { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + return RTE_ETH_RX_DESC_AVAIL; } - rx_buf = rxr->rx_buf_ring[cons]; - if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) - return RTE_ETH_RX_DESC_UNAVAIL; +#endif + + /* + * For the non-vector receive case, scan the completion ring to + * locate the completion descriptor for the requested offset. + */ + raw_cons = cpr->cp_raw_cons; + desc = 0; + while (1) { + uint32_t agg_cnt, cons, cmpl_type; + + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) + break; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + if (desc == offset) { + cons = rxcmp->opaque; + if (rxr->rx_buf_ring[cons]) + return RTE_ETH_RX_DESC_DONE; + else + return RTE_ETH_RX_DESC_UNAVAIL; + } + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (desc == offset) + return RTE_ETH_RX_DESC_DONE; + + if (BNXT_CHIP_P5(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); + } + } return RTE_ETH_RX_DESC_AVAIL; } @@ -2970,7 +3199,7 @@ bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; struct bnxt_tx_ring_info *txr; struct bnxt_cp_ring_info *cpr; - struct bnxt_sw_tx_bd *tx_buf; + struct rte_mbuf **tx_buf; struct tx_pkt_cmpl *txcmp; uint32_t cons, cp_cons; int rc; @@ -3000,16 +3229,15 @@ bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) return RTE_ETH_TX_DESC_UNAVAIL; } tx_buf = &txr->tx_buf_ring[cons]; - if (tx_buf->mbuf == NULL) + if (*tx_buf == NULL) return RTE_ETH_TX_DESC_DONE; return RTE_ETH_TX_DESC_FULL; } int -bnxt_filter_ctrl_op(struct rte_eth_dev *dev, - enum rte_filter_type filter_type, - enum rte_filter_op filter_op, void *arg) +bnxt_flow_ops_get_op(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops) { struct bnxt *bp = dev->data->dev_private; int ret = 0; @@ -3022,10 +3250,8 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev, bp = vfr->parent_dev->data->dev_private; /* parent is deleted while children are still valid */ if (!bp) { - PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n", - dev->data->port_id, - filter_type, - filter_op); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", + dev->data->port_id); return -EIO; } } @@ -3034,27 +3260,16 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev, if (ret) return ret; - switch (filter_type) { - case RTE_ETH_FILTER_GENERIC: - if (filter_op != RTE_ETH_FILTER_GET) - return -EINVAL; + /* PMD supports thread-safe flow operations. rte_flow API + * functions can avoid mutex for multi-thread safety. + */ + dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; - /* PMD supports thread-safe flow operations. rte_flow API - * functions can avoid mutex for multi-thread safety. - */ - dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; + if (BNXT_TRUFLOW_EN(bp)) + *ops = &bnxt_ulp_rte_flow_ops; + else + *ops = &bnxt_flow_ops; - if (BNXT_TRUFLOW_EN(bp)) - *(const void **)arg = &bnxt_ulp_rte_flow_ops; - else - *(const void **)arg = &bnxt_flow_ops; - break; - default: - PMD_DRV_LOG(ERR, - "Filter type (%d) not supported", filter_type); - ret = -EINVAL; - break; - } return ret; } @@ -3158,6 +3373,7 @@ static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; + rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); return 0; } @@ -3169,9 +3385,6 @@ static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) uint16_t port_id; uint32_t fifo; - if (!ptp) - return -ENODEV; - fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) @@ -3204,11 +3417,13 @@ bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ns = rte_timespec_to_ns(ts); /* Set the timecounters to a new value. */ ptp->tc.nsec = ns; + ptp->tx_tstamp_tc.nsec = ns; + ptp->rx_tstamp_tc.nsec = ns; return 0; } @@ -3222,7 +3437,7 @@ bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) int rc = 0; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, @@ -3244,7 +3459,7 @@ bnxt_timesync_enable(struct rte_eth_dev *dev) int rc; if (!ptp) - return 0; + return -ENOTSUP; ptp->rx_filter = 1; ptp->tx_tstamp_en = 1; @@ -3272,8 +3487,10 @@ bnxt_timesync_enable(struct rte_eth_dev *dev) if (!BNXT_CHIP_P5(bp)) bnxt_map_ptp_regs(bp); + else + rc = bnxt_ptp_start(bp); - return 0; + return rc; } static int @@ -3283,7 +3500,7 @@ bnxt_timesync_disable(struct rte_eth_dev *dev) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ptp->rx_filter = 0; ptp->tx_tstamp_en = 0; @@ -3293,6 +3510,8 @@ bnxt_timesync_disable(struct rte_eth_dev *dev) if (!BNXT_CHIP_P5(bp)) bnxt_unmap_ptp_regs(bp); + else + bnxt_ptp_stop(bp); return 0; } @@ -3308,7 +3527,7 @@ bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, uint64_t ns; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rx_tstamp_cycles = ptp->rx_timestamp; @@ -3331,7 +3550,7 @@ bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, int rc = 0; if (!ptp) - return 0; + return -ENOTSUP; if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, @@ -3352,9 +3571,11 @@ bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; if (!ptp) - return 0; + return -ENOTSUP; ptp->tc.nsec += delta; + ptp->tx_tstamp_tc.nsec += delta; + ptp->rx_tstamp_tc.nsec += delta; return 0; } @@ -3565,7 +3786,7 @@ static const struct eth_dev_ops bnxt_dev_ops = { .rx_queue_stop = bnxt_rx_queue_stop, .tx_queue_start = bnxt_tx_queue_start, .tx_queue_stop = bnxt_tx_queue_stop, - .filter_ctrl = bnxt_filter_ctrl_op, + .flow_ops_get = bnxt_flow_ops_get_op, .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, .get_eeprom_length = bnxt_get_eeprom_length_op, .get_eeprom = bnxt_get_eeprom_op, @@ -3633,13 +3854,19 @@ static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) uint32_t val = info->reset_reg_val[index]; uint32_t reg = info->reset_reg[index]; uint32_t type, offset; + int ret; type = BNXT_FW_STATUS_REG_TYPE(reg); offset = BNXT_FW_STATUS_REG_OFF(reg); switch (type) { case BNXT_FW_STATUS_REG_TYPE_CFG: - rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); + ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", + val, offset); + return; + } break; case BNXT_FW_STATUS_REG_TYPE_GRC: offset = bnxt_map_reset_regs(bp, offset); @@ -3659,11 +3886,37 @@ static void bnxt_dev_cleanup(struct bnxt *bp) bp->eth_dev->data->dev_link.link_status = 0; bp->link_info->link_up = 0; if (bp->eth_dev->data->dev_started) - bnxt_dev_stop_op(bp->eth_dev); + bnxt_dev_stop(bp->eth_dev); bnxt_uninit_resources(bp, true); } +static int +bnxt_check_fw_reset_done(struct bnxt *bp) +{ + int timeout = bp->fw_reset_max_msecs; + uint16_t val = 0; + int rc; + + do { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return rc; + } + if (val != 0xffff) + break; + rte_delay_ms(1); + } while (timeout--); + + if (val == 0xffff) { + PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); + return -1; + } + + return 0; +} + static int bnxt_restore_vlan_filters(struct bnxt *bp) { struct rte_eth_dev *dev = bp->eth_dev; @@ -3754,28 +4007,45 @@ static int bnxt_restore_filters(struct bnxt *bp) return ret; } -static void bnxt_dev_recover(void *arg) +static int bnxt_check_fw_ready(struct bnxt *bp) { - struct bnxt *bp = arg; int timeout = bp->fw_reset_max_msecs; int rc = 0; - /* Clear Error flag so that device re-init should happen */ - bp->flags &= ~BNXT_FLAG_FATAL_ERROR; - do { - rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); + rc = bnxt_hwrm_poll_ver_get(bp); if (rc == 0) break; rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); timeout -= BNXT_FW_READY_WAIT_INTERVAL; - } while (rc && timeout); + } while (rc && timeout > 0); - if (rc) { + if (rc) PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); - goto err; + + return rc; +} + +static void bnxt_dev_recover(void *arg) +{ + struct bnxt *bp = arg; + int rc = 0; + + pthread_mutex_lock(&bp->err_recovery_lock); + + if (!bp->fw_reset_min_msecs) { + rc = bnxt_check_fw_reset_done(bp); + if (rc) + goto err; } + /* Clear Error flag so that device re-init should happen */ + bp->flags &= ~BNXT_FLAG_FATAL_ERROR; + + rc = bnxt_check_fw_ready(bp); + if (rc) + goto err; + rc = bnxt_init_resources(bp, true); if (rc) { PMD_DRV_LOG(ERR, @@ -3796,26 +4066,48 @@ static void bnxt_dev_recover(void *arg) goto err_start; PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); + pthread_mutex_unlock(&bp->err_recovery_lock); + return; err_start: - bnxt_dev_stop_op(bp->eth_dev); + bnxt_dev_stop(bp->eth_dev); err: bp->flags |= BNXT_FLAG_FATAL_ERROR; bnxt_uninit_resources(bp, false); + pthread_mutex_unlock(&bp->err_recovery_lock); PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); } void bnxt_dev_reset_and_resume(void *arg) { struct bnxt *bp = arg; + uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; + uint16_t val = 0; int rc; bnxt_dev_cleanup(bp); bnxt_wait_for_device_shutdown(bp); - rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, - bnxt_dev_recover, (void *)bp); + /* During some fatal firmware error conditions, the PCI config space + * register 0x2e which normally contains the subsystem ID will become + * 0xffff. This register will revert back to the normal value after + * the chip has completed core reset. If we detect this condition, + * we can poll this config register immediately for the value to revert. + */ + if (bp->flags & BNXT_FLAG_FATAL_ERROR) { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return; + } + if (val == 0xffff) { + bp->fw_reset_min_msecs = 0; + us = 1; + } + } + + rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); if (rc) PMD_DRV_LOG(ERR, "Error setting recovery alarm"); } @@ -3992,6 +4284,7 @@ static bool bnxt_vf_pciid(uint16_t device_id) case BROADCOM_DEV_ID_58802_VF: case BROADCOM_DEV_ID_57500_VF1: case BROADCOM_DEV_ID_57500_VF2: + case BROADCOM_DEV_ID_58818_VF: /* FALLTHROUGH */ return true; default: @@ -4014,6 +4307,10 @@ static bool bnxt_p5_device(uint16_t device_id) case BROADCOM_DEV_ID_57502_MF2: case BROADCOM_DEV_ID_57500_VF1: case BROADCOM_DEV_ID_57500_VF2: + case BROADCOM_DEV_ID_58812: + case BROADCOM_DEV_ID_58814: + case BROADCOM_DEV_ID_58818: + case BROADCOM_DEV_ID_58818_VF: /* FALLTHROUGH */ return true; default: @@ -4036,7 +4333,7 @@ bool bnxt_stratus_device(struct bnxt *bp) } } -static int bnxt_init_board(struct rte_eth_dev *eth_dev) +static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); struct bnxt *bp = eth_dev->data->dev_private; @@ -4210,39 +4507,49 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp) ctx_pg = &ctx->qp_mem; ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; - mem_size = ctx->qp_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); - if (rc) - return rc; + if (ctx->qp_entry_size) { + mem_size = ctx->qp_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->srq_mem; ctx_pg->entries = ctx->srq_max_l2_entries; - mem_size = ctx->srq_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); - if (rc) - return rc; + if (ctx->srq_entry_size) { + mem_size = ctx->srq_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->cq_mem; ctx_pg->entries = ctx->cq_max_l2_entries; - mem_size = ctx->cq_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); - if (rc) - return rc; + if (ctx->cq_entry_size) { + mem_size = ctx->cq_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->vnic_mem; ctx_pg->entries = ctx->vnic_max_vnic_entries + ctx->vnic_max_ring_table_entries; - mem_size = ctx->vnic_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); - if (rc) - return rc; + if (ctx->vnic_entry_size) { + mem_size = ctx->vnic_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); + if (rc) + return rc; + } ctx_pg = &ctx->stat_mem; ctx_pg->entries = ctx->stat_max_entries; - mem_size = ctx->stat_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); - if (rc) - return rc; + if (ctx->stat_entry_size) { + mem_size = ctx->stat_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); + if (rc) + return rc; + } min = ctx->tqm_min_entries_per_ring; @@ -4256,13 +4563,22 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp) entries = clamp_t(uint32_t, entries, min, ctx->tqm_max_entries_per_ring); for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { + /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. + * i > 8 is other ext rings. + */ ctx_pg = ctx->tqm_mem[i]; ctx_pg->entries = i ? entries : entries_sp; - mem_size = ctx->tqm_entry_size * ctx_pg->entries; - rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); - if (rc) - return rc; - ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; + if (ctx->tqm_entry_size) { + mem_size = ctx->tqm_entry_size * ctx_pg->entries; + rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, + "tqm_mem", i); + if (rc) + return rc; + } + if (i < BNXT_MAX_TQM_LEGACY_RINGS) + ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; + else + ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; } ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; @@ -4661,7 +4977,11 @@ static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) return 0; } -static int bnxt_init_fw(struct bnxt *bp) +/* This function gets the FW version along with the + * capabilities(MAX and current) of the function, vnic, + * error recovery, phy and other chip related info + */ +static int bnxt_get_config(struct bnxt *bp) { uint16_t mtu; int rc = 0; @@ -4702,6 +5022,10 @@ static int bnxt_init_fw(struct bnxt *bp) if (rc) return rc; + rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); + if (rc) + return rc; + bnxt_hwrm_port_mac_qcfg(bp); bnxt_hwrm_parent_pf_qcfg(bp); @@ -4737,8 +5061,15 @@ bnxt_init_locks(struct bnxt *bp) } err = pthread_mutex_init(&bp->health_check_lock, NULL); - if (err) + if (err) { PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); + return err; + } + + err = pthread_mutex_init(&bp->err_recovery_lock, NULL); + if (err) + PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); + return err; } @@ -4746,7 +5077,7 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) { int rc = 0; - rc = bnxt_init_fw(bp); + rc = bnxt_get_config(bp); if (rc) return rc; @@ -4803,10 +5134,6 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) return rc; } - rc = bnxt_init_locks(bp); - if (rc) - return rc; - return 0; } @@ -5143,40 +5470,49 @@ bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, return 0; } -static void +static int bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) { struct rte_kvargs *kvlist; + int ret; if (devargs == NULL) - return; + return 0; kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); if (kvlist == NULL) - return; + return -EINVAL; /* * Handler for "truflow" devarg. * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" */ - rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, - bnxt_parse_devarg_truflow, bp); + ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, + bnxt_parse_devarg_truflow, bp); + if (ret) + goto err; /* * Handler for "flow_xstat" devarg. * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" */ - rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, - bnxt_parse_devarg_flow_xstat, bp); + ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, + bnxt_parse_devarg_flow_xstat, bp); + if (ret) + goto err; /* * Handler for "max_num_kflows" devarg. * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" */ - rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, - bnxt_parse_devarg_max_num_kflows, bp); + ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, + bnxt_parse_devarg_max_num_kflows, bp); + if (ret) + goto err; +err: rte_kvargs_free(kvlist); + return ret; } static int bnxt_alloc_switch_domain(struct bnxt *bp) @@ -5197,38 +5533,14 @@ static int bnxt_alloc_switch_domain(struct bnxt *bp) return rc; } -static int -bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) +/* Allocate and initialize various fields in bnxt struct that + * need to be allocated/destroyed only once in the lifetime of the driver + */ +static int bnxt_drv_init(struct rte_eth_dev *eth_dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - static int version_printed; - struct bnxt *bp; - int rc; - - if (version_printed++ == 0) - PMD_DRV_LOG(INFO, "%s\n", bnxt_version); - - eth_dev->dev_ops = &bnxt_dev_ops; - eth_dev->rx_queue_count = bnxt_rx_queue_count_op; - eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; - eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; - eth_dev->rx_pkt_burst = &bnxt_recv_pkts; - eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; - - /* - * For secondary processes, we don't initialise any further - * as primary has already done this work. - */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; - - rte_eth_copy_pci_info(eth_dev, pci_dev); - eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; - - bp = eth_dev->data->dev_private; - - /* Parse dev arguments passed on when starting the DPDK application. */ - bnxt_parse_dev_args(bp, pci_dev->device.devargs); + struct bnxt *bp = eth_dev->data->dev_private; + int rc = 0; bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -5260,7 +5572,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) } } - rc = bnxt_init_board(eth_dev); + rc = bnxt_map_pci_bars(eth_dev); if (rc) { PMD_DRV_LOG(ERR, "Failed to initialize board rc: %x\n", rc); @@ -5269,27 +5581,77 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) rc = bnxt_alloc_pf_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_link_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_parent_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_hwrm_resources(bp); if (rc) { PMD_DRV_LOG(ERR, - "Failed to allocate hwrm resource rc: %x\n", rc); - goto error_free; + "Failed to allocate response buffer rc: %x\n", rc); + return rc; } rc = bnxt_alloc_leds_info(bp); if (rc) - goto error_free; + return rc; rc = bnxt_alloc_cos_queues(bp); + if (rc) + return rc; + + rc = bnxt_init_locks(bp); + if (rc) + return rc; + + rc = bnxt_alloc_switch_domain(bp); + if (rc) + return rc; + + return rc; +} + +static int +bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + static int version_printed; + struct bnxt *bp; + int rc; + + if (version_printed++ == 0) + PMD_DRV_LOG(INFO, "%s\n", bnxt_version); + + eth_dev->dev_ops = &bnxt_dev_ops; + eth_dev->rx_queue_count = bnxt_rx_queue_count_op; + eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; + eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; + eth_dev->rx_pkt_burst = &bnxt_recv_pkts; + eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; + + /* + * For secondary processes, we don't initialise any further + * as primary has already done this work. + */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pci_dev); + eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + + bp = eth_dev->data->dev_private; + + /* Parse dev arguments passed on when starting the DPDK application. */ + rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); + if (rc) + goto error_free; + + rc = bnxt_drv_init(eth_dev); if (rc) goto error_free; @@ -5301,8 +5663,6 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) if (rc) goto error_free; - bnxt_alloc_switch_domain(bp); - PMD_DRV_LOG(INFO, DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", pci_dev->mem_resource[0].phys_addr, @@ -5384,18 +5744,6 @@ bnxt_free_error_recovery_info(struct bnxt *bp) bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; } -static void -bnxt_uninit_locks(struct bnxt *bp) -{ - pthread_mutex_destroy(&bp->flow_lock); - pthread_mutex_destroy(&bp->def_cp_lock); - pthread_mutex_destroy(&bp->health_check_lock); - if (bp->rep_info) { - pthread_mutex_destroy(&bp->rep_info->vfr_lock); - pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); - } -} - static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) { @@ -5417,7 +5765,6 @@ bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) bnxt_uninit_ctx_mem(bp); - bnxt_uninit_locks(bp); bnxt_free_flow_stats_info(bp); bnxt_free_rep_info(bp); rte_free(bp->ptp_cfg); @@ -5526,6 +5873,13 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, int i, ret = 0; struct rte_kvargs *kvlist = NULL; + if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) + return 0; + if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { + PMD_DRV_LOG(ERR, "unsupported representor type %d\n", + eth_da->type); + return -ENOTSUP; + } num_rep = eth_da->nb_representor_ports; if (num_rep > BNXT_MAX_VF_REPS) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",