X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt_hwrm.c;h=82e89b7c8af7d4b091a984e8b49a71663a1d348f;hb=586e6028371764452b7dbae3b1f50adde87be80e;hp=d583839cb0ead0926291ca33db4729bae8212872;hpb=8fd709a10b25d6d3fe293b3f8343c179d85631df;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index d583839cb0..82e89b7c8a 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -628,7 +628,7 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp, uint16_t j = dst_id - 1; //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ - if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) && + if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) && conf->pool_map[j].pools & (1UL << j)) { PMD_DRV_LOG(DEBUG, "Add vlan %u to vmdq pool %u\n", @@ -941,6 +941,10 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED) bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN; + if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) { + bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; + PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n"); + } unlock: HWRM_UNLOCK(); @@ -1001,6 +1005,11 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP) bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2; + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) { + bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP; + PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n"); + } + bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported); HWRM_UNLOCK(); @@ -1050,9 +1059,9 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp) HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER | HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD); - req.ver_maj = RTE_VER_YEAR; - req.ver_min = RTE_VER_MONTH; - req.ver_upd = RTE_VER_MINOR; + req.ver_maj_8b = RTE_VER_YEAR; + req.ver_min_8b = RTE_VER_MONTH; + req.ver_upd_8b = RTE_VER_MINOR; if (BNXT_PF(bp)) { req.enables |= rte_cpu_to_le_32( @@ -1085,7 +1094,8 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp) rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE); req.async_event_fwd[2] |= - rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST); + rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST | + ASYNC_CMPL_EVENT_ID_ERROR_REPORT); rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); @@ -1360,7 +1370,7 @@ error: return rc; } -int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags) +int bnxt_hwrm_func_driver_unregister(struct bnxt *bp) { int rc; struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 }; @@ -1370,7 +1380,6 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags) return 0; HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB); - req.flags = flags; rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); @@ -1863,6 +1872,10 @@ int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx) struct hwrm_ring_grp_alloc_input req = {.req_type = 0 }; struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr; + /* Don't attempt to re-create the ring group if it is already created */ + if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID) + return 0; + HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB); req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id); @@ -1887,6 +1900,9 @@ int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx) struct hwrm_ring_grp_free_input req = {.req_type = 0 }; struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr; + if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) + return 0; + HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB); req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id); @@ -2716,12 +2732,23 @@ void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index) struct bnxt_ring *ring = rxr->rx_ring_struct; struct bnxt_cp_ring_info *cpr = rxq->cp_ring; + if (BNXT_HAS_RING_GRPS(bp)) + bnxt_hwrm_ring_grp_free(bp, queue_index); + bnxt_hwrm_ring_free(bp, ring, HWRM_RING_FREE_INPUT_RING_TYPE_RX, cpr->cp_ring_struct->fw_ring_id); if (BNXT_HAS_RING_GRPS(bp)) bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID; + /* Check agg ring struct explicitly. + * bnxt_need_agg_ring() returns the current state of offload flags, + * but we may have to deal with agg ring struct before the offload + * flags are updated. + */ + if (!bnxt_need_agg_ring(bp->eth_dev) || rxr->ag_ring_struct == NULL) + goto no_agg; + ring = rxr->ag_ring_struct; bnxt_hwrm_ring_free(bp, ring, BNXT_CHIP_P5(bp) ? @@ -2731,6 +2758,7 @@ void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index) if (BNXT_HAS_RING_GRPS(bp)) bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID; +no_agg: bnxt_hwrm_stat_ctx_free(bp, cpr); bnxt_free_cp_ring(bp, cpr); @@ -2951,12 +2979,12 @@ static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed) { uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH; - if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG) + if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG) return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH; switch (conf_link_speed) { - case ETH_LINK_SPEED_10M_HD: - case ETH_LINK_SPEED_100M_HD: + case RTE_ETH_LINK_SPEED_10M_HD: + case RTE_ETH_LINK_SPEED_100M_HD: /* FALLTHROUGH */ return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF; } @@ -2973,51 +3001,51 @@ static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed, { uint16_t eth_link_speed = 0; - if (conf_link_speed == ETH_LINK_SPEED_AUTONEG) - return ETH_LINK_SPEED_AUTONEG; + if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG) + return RTE_ETH_LINK_SPEED_AUTONEG; - switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) { - case ETH_LINK_SPEED_100M: - case ETH_LINK_SPEED_100M_HD: + switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) { + case RTE_ETH_LINK_SPEED_100M: + case RTE_ETH_LINK_SPEED_100M_HD: /* FALLTHROUGH */ eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB; break; - case ETH_LINK_SPEED_1G: + case RTE_ETH_LINK_SPEED_1G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB; break; - case ETH_LINK_SPEED_2_5G: + case RTE_ETH_LINK_SPEED_2_5G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB; break; - case ETH_LINK_SPEED_10G: + case RTE_ETH_LINK_SPEED_10G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB; break; - case ETH_LINK_SPEED_20G: + case RTE_ETH_LINK_SPEED_20G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB; break; - case ETH_LINK_SPEED_25G: + case RTE_ETH_LINK_SPEED_25G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB; break; - case ETH_LINK_SPEED_40G: + case RTE_ETH_LINK_SPEED_40G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB; break; - case ETH_LINK_SPEED_50G: + case RTE_ETH_LINK_SPEED_50G: eth_link_speed = pam4_link ? HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB : HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB; break; - case ETH_LINK_SPEED_100G: + case RTE_ETH_LINK_SPEED_100G: eth_link_speed = pam4_link ? HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB : HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB; break; - case ETH_LINK_SPEED_200G: + case RTE_ETH_LINK_SPEED_200G: eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB; break; @@ -3030,11 +3058,11 @@ static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed, return eth_link_speed; } -#define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \ - ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \ - ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \ - ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \ - ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G) +#define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \ + RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \ + RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \ + RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \ + RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G) static int bnxt_validate_link_speed(struct bnxt *bp) { @@ -3043,13 +3071,13 @@ static int bnxt_validate_link_speed(struct bnxt *bp) uint32_t link_speed_capa; uint32_t one_speed; - if (link_speed == ETH_LINK_SPEED_AUTONEG) + if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) return 0; link_speed_capa = bnxt_get_speed_capabilities(bp); - if (link_speed & ETH_LINK_SPEED_FIXED) { - one_speed = link_speed & ~ETH_LINK_SPEED_FIXED; + if (link_speed & RTE_ETH_LINK_SPEED_FIXED) { + one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED; if (one_speed & (one_speed - 1)) { PMD_DRV_LOG(ERR, @@ -3079,71 +3107,71 @@ bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed) { uint16_t ret = 0; - if (link_speed == ETH_LINK_SPEED_AUTONEG) { + if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) { if (bp->link_info->support_speeds) return bp->link_info->support_speeds; link_speed = BNXT_SUPPORTED_SPEEDS; } - if (link_speed & ETH_LINK_SPEED_100M) + if (link_speed & RTE_ETH_LINK_SPEED_100M) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB; - if (link_speed & ETH_LINK_SPEED_100M_HD) + if (link_speed & RTE_ETH_LINK_SPEED_100M_HD) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB; - if (link_speed & ETH_LINK_SPEED_1G) + if (link_speed & RTE_ETH_LINK_SPEED_1G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB; - if (link_speed & ETH_LINK_SPEED_2_5G) + if (link_speed & RTE_ETH_LINK_SPEED_2_5G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB; - if (link_speed & ETH_LINK_SPEED_10G) + if (link_speed & RTE_ETH_LINK_SPEED_10G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB; - if (link_speed & ETH_LINK_SPEED_20G) + if (link_speed & RTE_ETH_LINK_SPEED_20G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB; - if (link_speed & ETH_LINK_SPEED_25G) + if (link_speed & RTE_ETH_LINK_SPEED_25G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB; - if (link_speed & ETH_LINK_SPEED_40G) + if (link_speed & RTE_ETH_LINK_SPEED_40G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB; - if (link_speed & ETH_LINK_SPEED_50G) + if (link_speed & RTE_ETH_LINK_SPEED_50G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB; - if (link_speed & ETH_LINK_SPEED_100G) + if (link_speed & RTE_ETH_LINK_SPEED_100G) ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB; - if (link_speed & ETH_LINK_SPEED_200G) + if (link_speed & RTE_ETH_LINK_SPEED_200G) ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB; return ret; } static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed) { - uint32_t eth_link_speed = ETH_SPEED_NUM_NONE; + uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE; switch (hw_link_speed) { case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB: - eth_link_speed = ETH_SPEED_NUM_100M; + eth_link_speed = RTE_ETH_SPEED_NUM_100M; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: - eth_link_speed = ETH_SPEED_NUM_1G; + eth_link_speed = RTE_ETH_SPEED_NUM_1G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB: - eth_link_speed = ETH_SPEED_NUM_2_5G; + eth_link_speed = RTE_ETH_SPEED_NUM_2_5G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: - eth_link_speed = ETH_SPEED_NUM_10G; + eth_link_speed = RTE_ETH_SPEED_NUM_10G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: - eth_link_speed = ETH_SPEED_NUM_20G; + eth_link_speed = RTE_ETH_SPEED_NUM_20G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: - eth_link_speed = ETH_SPEED_NUM_25G; + eth_link_speed = RTE_ETH_SPEED_NUM_25G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: - eth_link_speed = ETH_SPEED_NUM_40G; + eth_link_speed = RTE_ETH_SPEED_NUM_40G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: - eth_link_speed = ETH_SPEED_NUM_50G; + eth_link_speed = RTE_ETH_SPEED_NUM_50G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: - eth_link_speed = ETH_SPEED_NUM_100G; + eth_link_speed = RTE_ETH_SPEED_NUM_100G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB: - eth_link_speed = ETH_SPEED_NUM_200G; + eth_link_speed = RTE_ETH_SPEED_NUM_200G; break; case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB: default: @@ -3156,16 +3184,16 @@ static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed) static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex) { - uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX; + uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX; switch (hw_link_duplex) { case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH: case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL: /* FALLTHROUGH */ - eth_link_duplex = ETH_LINK_FULL_DUPLEX; + eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX; break; case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF: - eth_link_duplex = ETH_LINK_HALF_DUPLEX; + eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX; break; default: PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n", @@ -3194,12 +3222,12 @@ int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link) link->link_speed = bnxt_parse_hw_link_speed(link_info->link_speed); else - link->link_speed = ETH_SPEED_NUM_NONE; + link->link_speed = RTE_ETH_SPEED_NUM_NONE; link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex); link->link_status = link_info->link_up; link->link_autoneg = link_info->auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ? - ETH_LINK_FIXED : ETH_LINK_AUTONEG; + RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG; exit: return rc; } @@ -3225,7 +3253,7 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up) autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds); if (BNXT_CHIP_P5(bp) && - dev_conf->link_speeds == ETH_LINK_SPEED_40G) { + dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) { /* 40G is not supported as part of media auto detect. * The speed should be forced and autoneg disabled * to configure 40G speed. @@ -3316,7 +3344,7 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu) HWRM_CHECK_RESULT(); - bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX; + bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX; svif_info = rte_le_to_cpu_16(resp->svif_info); if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID) @@ -3389,16 +3417,6 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); - /* FIXME: Temporary workaround - remove when firmware issue is fixed. */ - if (bp->parent->vnic == 0) { - PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n"); - /* Use hard-coded values appropriate for current Wh+ fw. */ - if (bp->parent->fid == 2) - bp->parent->vnic = 0x100; - else - bp->parent->vnic = 1; - } - HWRM_UNLOCK(); return 0; @@ -5084,6 +5102,7 @@ static int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) { struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr; + uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state; struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 }; struct bnxt_rx_queue **rxqs = bp->rx_queues; uint16_t *ring_tbl = vnic->rss_table; @@ -5117,7 +5136,7 @@ bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) /* Find next active ring. */ for (cnt = 0; cnt < max_rings; cnt++) { - if (rxqs[k]->rx_started) + if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED) break; if (++k == max_rings) k = 0; @@ -5706,11 +5725,11 @@ int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) /* FW returned values are in units of 100msec */ info->driver_polling_freq = rte_le_to_cpu_32(resp->driver_polling_freq) * 100; - info->master_func_wait_period = + info->primary_func_wait_period = rte_le_to_cpu_32(resp->master_func_wait_period) * 100; info->normal_func_wait_period = rte_le_to_cpu_32(resp->normal_func_wait_period) * 100; - info->master_func_wait_period_after_reset = + info->primary_func_wait_period_after_reset = rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100; info->max_bailout_time_after_reset = rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;