X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=380dec4d3ed1b6f12606968e16e3fca278788f83;hb=447a0721ff9acfc14f5c64c031be7da956e9344a;hp=598da7153d69cf231934c655daf169f071e13bb1;hpb=c689d42de54b57efc1cee512ef548beba7ba8d92;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 598da7153d..380dec4d3e 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2020 Broadcom Inc. + * Copyright (c) 2014-2022 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -269,6 +269,7 @@ struct cmd_nums { */ uint16_t req_type; #define HWRM_VER_GET UINT32_C(0x0) + #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb) #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc) #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd) #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe) @@ -336,14 +337,16 @@ struct cmd_nums { #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48) #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49) #define HWRM_VNIC_QCAPS UINT32_C(0x4a) + /* Updates specific fields in RX VNIC structure */ + #define HWRM_VNIC_UPDATE UINT32_C(0x4b) #define HWRM_RING_ALLOC UINT32_C(0x50) #define HWRM_RING_FREE UINT32_C(0x51) #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53) #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54) - #define HWRM_RING_SQ_ALLOC UINT32_C(0x55) - #define HWRM_RING_SQ_CFG UINT32_C(0x56) - #define HWRM_RING_SQ_FREE UINT32_C(0x57) + #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55) + #define HWRM_RING_SCHQ_CFG UINT32_C(0x56) + #define HWRM_RING_SCHQ_FREE UINT32_C(0x57) #define HWRM_RING_RESET UINT32_C(0x5e) #define HWRM_RING_GRP_ALLOC UINT32_C(0x60) #define HWRM_RING_GRP_FREE UINT32_C(0x61) @@ -358,6 +361,11 @@ struct cmd_nums { #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) + #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83) + #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84) + #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) + #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) + #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -392,7 +400,13 @@ struct cmd_nums { #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) - #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba) + /* Reserved. */ + #define HWRM_RESERVED7 UINT32_C(0xba) + #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb) + #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc) + #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd) + #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe) + #define HWRM_FW_LIVEPATCH UINT32_C(0xbf) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) @@ -413,6 +427,7 @@ struct cmd_nums { #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) #define HWRM_FW_ECN_CFG UINT32_C(0xcd) #define HWRM_FW_ECN_QCFG UINT32_C(0xce) + #define HWRM_FW_SECURE_CFG UINT32_C(0xcf) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -425,6 +440,8 @@ struct cmd_nums { #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) /* Tells the fw to collect dsc dump on a given port and lane. */ #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) + #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda) + #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -522,6 +539,14 @@ struct cmd_nums { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127) + /* Experimental */ + #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128) + /* Experimental */ + #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ @@ -620,6 +645,39 @@ struct cmd_nums { #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198) /* Queries extended statistics context */ #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199) + /* Configure SoC packet DMA settings */ + #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a) + /* Query SoC packet DMA settings */ + #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b) + /* PTP - Queries configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c) + /* PTP - Configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d) + /* PTP - Configuration for disciplining PHC. */ + #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e) + /* PTP - Queries for PHC timestamps. */ + #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f) + /* PTP - Extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) + /* PTP - Query extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS or QUIC key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) + /* The is the new API to configure backing stores. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3) + /* The is the new API to query backing store configurations. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4) + /* To support doorbell pacing configuration. */ + #define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5) + /* To query doorbell pacing configuration. */ + #define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6) + /* + * To broadcast the doorbell event to the drivers to + * initiate pacing of doorbells. + */ + #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7) + /* The is the new API to query backing store capabilities. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -647,6 +705,48 @@ struct cmd_nums { #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) /* Tells the fw to read the fru memory */ #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Used to provision SoC software images */ + #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) + /* Retrieves the SoC status and image provisioning information */ + #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) + /* Tells the fw to program the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) + /* Tells the fw to read the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) + /* Tells the fw to get the health of seeprom data */ + #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* + * The command is used for certificate provisioning to export a + * Certificate Signing Request (CSR) from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211) + /* + * The command is used for certificate provisioning to import a + * CA-signed certificate chain to the device. + */ + #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212) + /* + * The command is used for certificate provisioning to query the + * provisioned state. + */ + #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213) + /* + * The command is used to get the hash of the NVM configuration that is + * calculated during firmware boot. + */ + #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214) + /* Retrieves the PSOC status and provisioning information. */ + #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215) + /* + * This command allows manufacturing tool to determine which selftests + * are available to be run. + */ + #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216) + /* + * This command allows manufacturing tool to request which selftests + * to run. + */ + #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -672,10 +772,18 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) /* Experimental */ + #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) /* Experimental */ + #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3) + /* Experimental */ #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) /* Experimental */ #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) @@ -692,6 +800,10 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) /* Experimental */ + #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec) + /* Experimental */ + #define HWRM_TF_EM_MOVE UINT32_C(0x2ed) + /* Experimental */ #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) /* Experimental */ #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) @@ -704,6 +816,10 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd) /* Experimental */ + #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) + /* Experimental */ + #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* Experimental */ #define HWRM_SV UINT32_C(0x400) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) @@ -742,6 +858,25 @@ struct cmd_nums { #define HWRM_DBG_QCFG UINT32_C(0xff21) /* Set destination parameters for crashdump medium */ #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + /* Experimental */ + #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23) + /* Experimental */ + #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24) + /* Experimental */ + #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25) + /* Experimental */ + #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26) + /* Experimental */ + #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27) + /* Experimental */ + #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28) + /* Experimental */ + #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29) + /* Experimental */ + #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) + /* Experimental */ + #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) @@ -855,6 +990,18 @@ struct ret_codes { * may try again later. */ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) + /* + * This error code is reported by Firmware when an operation requested + * by the host is not allowed due to a secure lock violation. + */ + #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11) + /* + * This error code is reported by Firmware when an operation requested + * by a VF cannot be forwarded to the parent PF as required, either + * because the PF is down or otherwise doesn't have an appropriate + * async completion ring or associated forwarding buffers configured. + */ + #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -940,10 +1087,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 1 +#define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 48 -#define HWRM_VERSION_STR "1.10.1.48" +#define HWRM_VERSION_RSVD 83 +#define HWRM_VERSION_STR "1.10.2.83" /**************** * hwrm_ver_get * @@ -1243,6 +1390,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1330,18 +1483,34 @@ struct hwrm_ver_get_output { * If set to 1, it will indicate to host drivers that firmware is * not ready to start full blown HWRM commands. Host drivers should * re-try HWRM_VER_GET with some timeout period. The timeout period - * can be selected up to 5 seconds. + * can be selected up to 5 seconds. Host drivers should also check + * for dev_not_rdy_backing_store to identify if flag is set due to + * backing store not been available. * For Example, PCIe hot-plug: * Hot plug timing is system dependent. It generally takes up to - * 600 miliseconds for firmware to clear DEV_NOT_RDY flag. + * 600 milliseconds for firmware to clear DEV_NOT_RDY flag. * If set to 0, device is ready to accept all HWRM commands. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1) + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \ + UINT32_C(0x1) /* * If set to 1, external version present. * If set to 0, external version not present. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2) + #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \ + UINT32_C(0x2) + /* + * Firmware sets this flag along with dev_not_rdy flag to indicate + * host drivers that it has not completed resource initialization + * required for data path operations. Host drivers should not send + * any HWRM command that requires data path resources. Firmware will + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry + * those commands once both the flags are cleared. + * If this flag and dev_not_rdy flag are set to 0, device is ready + * to accept all HWRM commands. + */ + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \ + UINT32_C(0x4) uint8_t unused_0[2]; /* * For backward compatibility this field must be set to 1. @@ -1483,7 +1652,18 @@ struct hwrm_ver_get_output { * used with the short cmd request format. */ uint16_t max_ext_req_len; - uint8_t unused_1[5]; + /* + * This field returns the maximum request timeout value in seconds. + * For backward compatibility, a value of zero should be interpreted + * as the default value of 40 seconds. Drivers should always honor the + * maximum timeout, but are permitted to warn if a longer duration than + * this default is advertised. Values larger than 40 seconds should + * only be used as a stopgap measure to address a device limitation or + * for the purposes of test and debugging. The long term goal is for + * firmware to significantly reduce this value in the passage of time. + */ + uint16_t max_req_timeout; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -1494,6 +1674,678 @@ struct hwrm_ver_get_output { uint8_t valid; } __rte_packed; +/* cfa_bds_read_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_read_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is read command. From 32 to 128B can be read from a table + * using this command. + */ + #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0) + #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + * this command is read from. The bottom two bits of this value must be + * zero. The size of the write is controlled by the data_size field. + */ + uint64_t host_address; +} __rte_packed; + +/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */ +struct cfa_bds_write_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is write command. From 32 to 128B can be written to a table + * using this command. + */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1) + #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE + /* This value selects the table type to be acted upon. */ + uint8_t write_thru_table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + uint32_t unused0; + uint32_t unused1; + /* + * This is the data to be written. Data length is determined by the + * data_size field. The bd_cnt in the encapsulating BD must also be set + * correctly to ensure that the BD is processed correctly and the full + * WRITE_CMD message is extracted from the BD. + */ + uint32_t dta[32]; +} __rte_packed; + +/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */ +struct cfa_bds_read_clr_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is read-clear command. 32B can be read from a table and + * a 16b mask can be used to clear specific 16b units after the + * read as an atomic operation. + */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. + * Always set the value to 1. + */ + uint8_t data_size; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + * this command is read from. The bottom two bits of this value must be + * zero. The size of the write is controlled by the data_size field. + */ + uint64_t host_address; + /* + * This is active high clear mask for the 32B of data that this command + * can read. Bit 0 of the field will clear bits 15:0 of the first word + * of data read when set to '1'. + */ + uint16_t clear_mask; + uint16_t unused0[3]; + uint16_t unused1[4]; +} __rte_packed; + +/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */ +struct cfa_bds_em_insert_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * An exact match table insert will be attempted into the table. + * If there is a free location in the bucket, the payload will + * be written to the bucket. + */ + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + uint8_t write_thru; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0 + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; + /* + * This is the Exact Match Lookup Record. Data length is determined by + * the data_size field. The bd_cnt in the encapsulating BD must also be + */ + uint32_t dta[32]; +} __rte_packed; + +/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */ +struct cfa_bds_em_delete_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* An exact match table delete will be attempted. */ + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + uint8_t write_thru; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0 + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + uint32_t unused0; + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; + /* + * This is the Exact Match Lookup Record. Data length is determined by + * the data_size field. The bd_cnt in the encapsulating BD must also be + */ + uint64_t dta; + uint32_t unused1[2]; +} __rte_packed; + +/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_invalidate_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * The specified table area will be invalidated. If it is needed. + * again, it will be read from the backing store. + */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \ + UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \ + UINT32_C(0x1) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* This value specifies the number of cache lines to invalidate. */ + uint8_t data_size; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + uint32_t unused[2]; +} __rte_packed; + +/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_event_collect_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* Reads notification messages from the Host Notification Queue. */ + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \ + UINT32_C(0x6) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT + uint8_t unused0; + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \ + UINT32_C(0x1f) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0 + uint32_t unused1; + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; +} __rte_packed; + +/* ce_bds_add_data_msg (size:512b/64B) */ +struct ce_bds_add_data_msg { + uint32_t version_algorithm_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0 + /* + * This is the add command. Using this opcode, Host Driver can add + * information required for kTLS processing. The information is + * updated in the CFCK context. + */ + #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1) + #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \ + CE_BDS_ADD_DATA_MSG_OPCODE_ADD + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_ADD_DATA_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_ADD_DATA_MSG_KID_SFT 4 + /* + * Currently only two algorithms are supported, AES_GCM_128 and + * AES_GCM_256. Additional bits for future growth. + */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \ + UINT32_C(0xf000000) + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24 + /* AES_GCM_128 Algorithm */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \ + UINT32_C(0x1000000) + /* AES_GCM_256 Algorithm */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \ + UINT32_C(0x2000000) + /* + * Version number of TLS connection. HW will provide registers that + * converts the 4b encoded version number to 16b of actual version + * number in the TLS Header. This field is initialized/updated by + * this "KTLS crypto add" mid-path command. + */ + #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \ + UINT32_C(0xf0000000) + #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28 + /* TLS1.2 Version */ + #define CE_BDS_ADD_DATA_MSG__TLS1_2 \ + (UINT32_C(0x0) << 28) + /* TLS1.3 Version */ + #define CE_BDS_ADD_DATA_MSG__TLS1_3 \ + (UINT32_C(0x1) << 28) + #define CE_BDS_ADD_DATA_MSG__LAST \ + CE_BDS_ADD_DATA_MSG__TLS1_3 + uint8_t cmd_type_ctx_kind; + /* + * Command Type in the TLS header. HW will provide registers that + * converts the 3b encoded command type to 8b of actual command + * type in the TLS Header. This field is initialized/updated by + * this "KTLS crypto add" mid-path command. + */ + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7) + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 + /* Application */ + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \ + CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP + /* This field selects the context kind for the request. */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3 + /* Crypto key transmit context */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3) + /* Crypto key receive context */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX + uint8_t unused0[3]; + /* + * Salt is part of the nonce that is used as the Initial Vector (IV) in + * AES-GCM cipher suites. These are exchanged as part of the handshake + * process and is either the client_write_iv (when the client is + * sending) or server_write_iv (when the server is sending). In + * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to + * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number + * is zero padded to 12B and then xor'ed with the 4B of salt to generate + * the 12B of IV. This value is initialized by this mid-path command. + */ + uint32_t salt; + uint32_t unused1; + /* + * This field keeps track of the TCP sequence number that is expected as + * the first byte in the next TCP packet. This field is calculated by HW + * using the output of the parser. The field is initialized as part of + * the Mid-path BD download/update of a kTLS connection. For every TCP + * packet processed, TCE HW will update the value to Current packet TCP + * sequence number + Current packet TCP Payload Length. + */ + uint32_t pkt_tcp_seq_num; + /* + * This field maintains the TCP sequence number of the first byte in the + * header of the active TLS record. This field is initialized as part of + * the Mid-path BD download/update of a kTLS connection. For every + * record that is processed, TCE HW copies the value from the + * next_tls_header_tcp_seq_num field. + */ + uint32_t tls_header_tcp_seq_num; + /* + * This is sequence number for the TLS record in a particular session. + * In TLS1.2, record sequence number is part of the Associated Data (AD) + * in the AEAD algorithm. In TLS1.3, record sequence number is part of + * the Initial Vector (IV). The field is initialized as part of the + * mid-path BD download/update of a kTLS connection. TCE HW increments + * the field after that for every record processed as it parses the TCP + * packet. + */ + uint32_t record_seq_num[2]; + /* + * Key used for encrypting or decrypting TLS records. The Key is + * exchanged during the hand-shake protocol by the client-server and + * provided to HW through this mid-path BD. + */ + uint32_t session_key[8]; +} __rte_packed; + +/* ce_bds_delete_data_msg (size:64b/8B) */ +struct ce_bds_delete_data_msg { + uint32_t kid_opcode_ctx_kind; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0 + /* + * This is the delete command. Using this opcode, the host Driver + * can remove a key context from the CFCK. If context is deleted + * and packets with the same KID come through the pipeline, the + * following actions are taken. For transmit packets, no crypto + * operation will be performed, payload will be zero'ed out. For + * receive packets, no crypto operation will be performed, + * payload will be unmodified. + */ + #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \ + CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0) + #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4 + /* This field selects the context kind for the request. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000) + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_SFT 24 + /* Crypto Key Transmit Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24) + /* Crypto Key Receive Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24) + /* QUIC Key Transmit Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24) + /* QUIC Key Receive Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24) + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX + uint32_t unused0; +} __rte_packed; + +/* ce_bds_resync_resp_ack_msg (size:128b/16B) */ +struct ce_bds_resync_resp_ack_msg { + uint32_t resync_status_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0 + /* + * This command is used by the driver as a response to the resync + * request sent by the crypto engine. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3) + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \ + CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0) + #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4 + /* + * This field indicates if the resync request resulted in a success or + * a failure. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \ + UINT32_C(0x1000000) + /* + * An ACK indicates that the driver was able to find the TLS record + * associated with TCP sequence number provided by the HW + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \ + (UINT32_C(0x0) << 24) + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \ + CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK + /* + * This field is the echo of the TCP sequence number provided in the + * resync request by the HW. If HW sent multiple resync requests, it + * only tracks the latest TCP sequence number. When the response from + * the Driver doesn't match the latest request, HW will drop the resync + * response. + */ + uint32_t resync_record_tcp_seq_num; + /* + * This field indicates the TLS record sequence number associated with + * the resync request. HW will take this number and add the delta records + * it has found since sending the resync request, update the context and + * resume decrypting records. + */ + uint32_t resync_record_seq_num[2]; +} __rte_packed; + +/* ce_bds_resync_resp_nack_msg (size:64b/8B) */ +struct ce_bds_resync_resp_nack_msg { + uint32_t resync_status_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0 + /* + * This command is used by the driver as a response to the resync + * request sent by the crypto engine. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3) + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \ + CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4 + /* + * This field indicates if the resync request resulted in a success or + * a failure. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \ + UINT32_C(0x1000000) + /* + * An NAK indicates that the driver wasn't able to find the TLS + * record associated with TCP sequence number provided by the HW + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \ + (UINT32_C(0x1) << 24) + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \ + CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK + /* + * This field is the echo of the TCP sequence number provided in the + * resync request by the HW. If HW sent multiple resync requests, it + * only tracks the latest TCP sequence number. When the response from + * the Driver doesn't match the latest request, HW will drop the resync + * response. + */ + uint32_t resync_record_tcp_seq_num; +} __rte_packed; + +/* crypto_presync_bd_cmd (size:256b/32B) */ +struct crypto_presync_bd_cmd { + uint8_t flags; + /* + * Typically, presync BDs are used for packet retransmissions. Source + * port sends all the packets in order over the network to destination + * port and packets get dropped in the network. The destination port + * will request retranmission of dropped packets and source port driver + * will send presync BD to setup the transmitter appropriately. It will + * provide the start and end TCP sequence number of the data to be + * transmitted. HW keeps two sets of context variable, one for in order + * traffic and one for retransmission traffic. HW is designed to + * transmit everything posted in the presync BD and return to in order + * mode after that. No inorder context variables are updated in the + * process. There is a special case where packets can be dropped + * between the TCP stack and Device Driver (Berkeley Packet Filter for + * ex) and HW still needs to transmit rest of the traffic. In this + * mode, driver will send a presync BD as if it is a retransmission but + * at the end of the transmission, the in order variables need to be + * updated. This flag is used by driver to indicate that in order + * variables needs to be updated at the end of completing the task + * associated with the presync BD. + */ + #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \ + UINT32_C(0x1) + uint8_t unused0; + uint16_t unused1; + /* + * This field maintains the TCP sequence number of the first byte in the + * Header of the active TLS record. This field is set to 0 during + * mid-path BD updates, but is set to correct value when a presync BD is + * detected. For every record that is processed, the value from the + * next_tls_header_tcp_seq_num field is copied. + */ + uint32_t header_tcp_seq_num; + /* + * When a retransmitted packet has a TLS authentication TAG present and + * the data spans multiple TCP Packets, HW is required to read the entire + * record to recalculate the TAG but only transmit what is required. This + * field is the start TCP sequence number of the packet(s) that need to + * be re-transmitted. This field is initialized to 0 during Mid-path BD + * add command and initialized to value provided by the driver when + * Pre-sync BD is detected. This field is never updated unless another + * Pre-sync BD signaling a new retransmission is scheduled. + */ + uint32_t start_tcp_seq_num; + /* + * When a retransmitted packet has a TLS authentication TAG present and + * the data spans multiple TCP Packets, HW is required to read the + * entire record to recalculate the TAG but only transmit what is + * required. This field is the end TCP sequence number of the packet(s) + * that need to be re-transmitted. This field is initialized to 0 during + * Mid-path BD add command and initialized to value provided by the + * driver when Pre-sync BD is detected. This field is never updated + * unless another Pre-sync BD signaling a new retransmission is + * scheduled. + */ + uint32_t end_tcp_seq_num; + /* + * For TLS1.2, an explicit nonce is used as part of the IV (concatenated + * with the SALT). For retrans packets, this field is extracted from the + * TLS record, field right after the TLS Header and stored in the + * context. This field needs to be stored in context as TCP segmentation + * could have split the field into multiple TCP packets. This value is + * initialized to 0 when presync BD is detected by taking the value from + * the first TLS header. When subsequent TLS Headers are detected, the + * value is extracted from packet. + */ + uint32_t explicit_nonce[2]; + /* + * This is sequence number for the TLS record in a particular session. In + * TLS1.2, record sequence number is part of the Associated Data (AD) in + * the AEAD algorithm. In TLS1.3, record sequence number is part of the + * Initial Vector (IV). The field is initialized to 0 during Mid-path BD + * download. Is initialized to correct value when a pre-sync BD is + * detected. TCE HW increments the field after that for every record + * processed as it parses the TCP packet. Subsequent pre-sync BDs + * delivering more retransmission instruction will also update this + * field. + */ + uint32_t record_seq_num[2]; +} __rte_packed; + /* bd_base (size:64b/8B) */ struct bd_base { uint8_t type; @@ -1525,6 +2377,22 @@ struct bd_base { * RX Producer Assembly Buffer Descriptor. */ #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6) + /* + * Indicates that this BD is used to issue a command to one of + * the mid-path destinations. + */ + #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8) + /* + * Indicates that this BD is used to issue a cryptographic pre- + * sync command through the fast path and destined for TCE. + */ + #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9) + /* + * Indicates a timed transmit BD. This is a 16b BD that is inserted + * into a packet BD chain immediately after the first BD. It is used + * to control the flow in a timed transmit operation. + */ + #define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa) /* * Indicates that this BD is 32B long and is used for * normal L2 packet transmission. @@ -1637,7 +2505,12 @@ struct tx_bd_short { * used for any data that the driver wants to associate with the * transmit BD. * - * This field must be valid on the first BD of a packet. + * This field must be valid on the first BD of a packet. If completion + * coalescing is enabled on the TX ring, it is suggested that the driver + * populate the opaque field to indicate the specific TX ring with which + * the completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. */ uint32_t opaque; /* @@ -1740,11 +2613,16 @@ struct tx_bd_long { */ uint16_t len; /* - * The opaque data field is pass through to the completion and can be + * The opaque data field is passed through to the completion and can be * used for any data that the driver wants to associate with the * transmit BD. * - * This field must be valid on the first BD of a packet. + * This field must be valid on the first BD of a packet. If completion + * coalescing is enabled on the TX ring, it is suggested that the driver + * populate the opaque field to indicate the specific TX ring with which + * the completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. */ uint32_t opaque; /* @@ -1796,10 +2674,22 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) /* - * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. + * This bit, in conjunction with the stamp_1step bit, controls whether + * a TX packet timestamp is collected and the type of timestamp that + * is collected. * * This bit must be valid on the first BD of a packet. + * + * Enumerations of the concatenation { stamp, stamp_1step } are + * as follows: + * + * - 2'b00: ts_none - no timestamp + * - 2'b01: ts_ptp_1step - 1-step PTP + * - 2'b10: ts_2cmpl - 2-step PTP timestamp or PA timestamp + * - 2'b11: ts_rsvd - reserved, same behavior as ts_none + * For the ts_2cmpl enumeration, an additional completion is returned. + * This additional completion may carry a 2-step PTP timestamp or a PA + * timestamp, depending on parsing of the transmitted packet. */ #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8) /* @@ -1808,15 +2698,15 @@ struct tx_bd_long_hi { * of the packet associated with this descriptor. * * For outer UDP checksum, global outer UDP checksum TE_NIC register - * needs to be enabled. If the global outer UDP checksum TE_NIC register - * bit is set, outer UDP checksum will be calculated for the following - * cases: - * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner - * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for - * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP - * checksum will not be calculated. - * 2. Packets with lso flag set which implies inner TCP checksum calculation - * as part of LSO operation. + * needs to be enabled. If the global outer UDP checksum TE_NIC + * register bit is set, outer UDP checksum will be calculated for + * the following cases: + * 1. Packets with tcp_udp_chksum flag set to offload checksum for + * inner packet AND the inner packet is TCP/UDP. If the inner packet + * is ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is + * set, the outer UDP checksum will not be calculated. + * 2. Packets with lso flag set which implies inner TCP checksum + * calculation as part of LSO operation. */ #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* @@ -1824,9 +2714,9 @@ struct tx_bd_long_hi { * Send Offload) processing for both normal or encapsulated * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver - * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum - * flags since the controller will replace the appropriate - * checksum fields for segmented packets. + * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and + * tcp_udp_chksum flags since the controller will replace the + * appropriate checksum fields for segmented packets. * * When this bit is 1, the hdr_size and mss fields must be valid. */ @@ -1863,7 +2753,53 @@ struct tx_bd_long_hi { * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) - uint16_t hdr_size; + /* + * If set to '1', then the timestamp from the BD is used. If cleared + * to 0, then TWE provides the timestamp. + */ + #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400) + /* + * If set to '1', this operation will cause a trace capture in each + * block it passes through. + */ + #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800) + /* + * This bit, in conjunction with the stamp bit, controls whether a + * TX packet timestamp is collected and the type of timestamp that + * is collected. + * + * See the stamp field for a description of the valid combinations of + * stamp and stamp_1step. + * + * This bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000) + /* + * If set to '1', the controller replaces the Outer-tunnel IP checksum + * field with hardware calculated IP checksum for the IP header of the + * packet associated with this descriptor. For outer UDP checksum, it + * will be the following behavior for all cases independent of + * settings of inner LSO and checksum offload BD flags. + * If outer UDP checksum is 0, then do not update it. + * If outer UDP checksum is non zero, then the hardware should + * compute and update it. + */ + #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) + /* + * If set to zero when LSO is '1', then the IPID of the Outer-tunnel + * IP header will not be modified during LSO operations. If set to one + * when LSO is '1', then the IPID of the Outer-tunnel IP header will + * be incremented for each subsequent segment of an LSO operation. The + * flag is ignored if the LSO packet is a normal (non-tunneled) TCP + * packet. + */ + #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000) + /* + * If set to '1', When set to 1, KTLS encryption will be enabled for + * the packet. + */ + #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000) + uint16_t kid_or_ts_low_hdr_size; /* * When LSO is '1', this field must contain the offset of the * TCP payload from the beginning of the packet in as @@ -1873,9 +2809,16 @@ struct tx_bd_long_hi { * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff) - #define TX_BD_LONG_HDR_SIZE_SFT 0 - uint32_t mss; + #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff) + #define TX_BD_LONG_HDR_SIZE_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of + * the 20-bit KID. + */ + #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00) + #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9 + uint32_t kid_or_ts_high_mss; /* * This is the MSS value that will be used to do the LSO processing. * The value is the length in bytes of the TCP payload for each @@ -1883,9 +2826,22 @@ struct tx_bd_long_hi { * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff) - #define TX_BD_LONG_MSS_SFT 0 - uint16_t unused2; + #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff) + #define TX_BD_LONG_MSS_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, the least significant 13 bits + * of this field contain the upper 13 bits of the 20-bit KID. + */ + #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000) + #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15 + /* + * This value selects bits 25:16 of the CFA action to perform on the + * packet. See the cfa_action field for more information. + */ + uint16_t cfa_action_high; + #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0 /* * This value selects a CFA action to perform on the packet. * Set this value to zero if no CFA action is desired. @@ -1899,59 +2855,77 @@ struct tx_bd_long_hi { */ uint32_t cfa_meta; /* When key=1, This is the VLAN tag VID value. */ - #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 /* When key=1, This is the VLAN tag DE value. */ - #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) /* When key=1, This is the VLAN tag PRI value. */ - #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \ + (UINT32_C(0x0) << 16) /* 0x8100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \ + (UINT32_C(0x1) << 16) /* 0x9100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \ + (UINT32_C(0x2) << 16) /* 0x9200 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \ + (UINT32_C(0x3) << 16) /* 0x9300 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \ + (UINT32_C(0x4) << 16) /* Value programmed in CFA VLANTPID register. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \ + (UINT32_C(0x5) << 16) #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \ TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) - #define TX_BD_LONG_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define TX_BD_LONG_CFA_META_KEY_SFT 28 /* No editing */ - #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + #define TX_BD_LONG_CFA_META_KEY_NONE \ + (UINT32_C(0x0) << 28) /* * - meta[17:16] - TPID select value (0 = 0x8100). * - meta[15:12] - PRI/DE value. * - meta[11:0] - VID value. */ - #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \ + (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ - TX_BD_LONG_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* - * This structure is used to inform the NIC of packet data that needs to be - * transmitted with additional processing that requires extra data such as - * VLAN insertion plus attached inline data. This BD type may be used to - * improve latency for small packets needing the additional extended features - * supported by long BDs. + * This structure is used to inform the NIC of packet data that needs to + * be transmitted with additional processing that requires extra data + * such as VLAN insertion plus attached inline data. + * This BD type may be used to improve latency for small packets needing + * the additional extended features supported by long BDs. */ /* tx_bd_long_inline (size:256b/32B) */ struct tx_bd_long_inline { @@ -2019,8 +2993,13 @@ struct tx_bd_long_inline { uint16_t len; /* * The opaque data field is passed through to the completion and can be - * used for any data that the driver wants to associate with the transmit - * BD. + * used for any data that the driver wants to associate with the + * transmit BD. This field must be valid on the first BD of a packet. + * If completion coalescing is enabled on the TX ring, it is suggested + * that the driver populate the opaque field to indicate the specific + * TX ring with which the completion is associated, then utilize the + * opaque and sq_cons_idx fields in the coalesced completion record to + * determine the specific packets that are to be completed on that ring. * * This field must be valid on the first BD of a packet. */ @@ -2058,7 +3037,8 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4) /* * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. + * was actually transmitted at the TX MAC for 2-step time sync. This + * bit must be valid on the first BD of a packet. */ #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8) /* @@ -2087,9 +3067,73 @@ struct tx_bd_long_inline { * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) - uint16_t unused2; - uint32_t unused3; - uint16_t unused4; + /* + * If set to '1', then the timestamp from the BD is used. If cleared + * to 0, then TWE provides the timestamp. + */ + #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400) + /* + * If set to '1', this operation will cause a trace capture in each + * block it passes through. + */ + #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800) + /* + * If set to '1', the device will record the time at which the packet + * was actually transmitted at the TX MAC for 1-step time sync. This + * bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000) + /* + * If set to '1', the controller replaces the Outer-tunnel IP checksum + * field with hardware calculated IP checksum for the IP header of the + * packet associated with this descriptor. For outer UDP checksum, it + * will be the following behavior for all cases independent of settings + * of inner LSO and checksum offload BD flags. If outer UDP checksum + * is 0, then do not update it. If outer UDP checksum is non zero, then + * the hardware should compute and update it. + */ + #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) + /* + * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP + * header will not be modified during LSO operations. If set to one + * when LSO is '1', then the IPID of the Outer-tunnel IP header will be + * incremented for each subsequent segment of an LSO operation. The + * flag is ignored if the LSO packet is a normal (non-tunneled) TCP + * packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000) + /* + * If set to '1', When set to 1, KTLS encryption will be enabled for + * the packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000) + uint8_t unused2; + uint8_t kid_or_ts_low; + #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1) + /* + * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of + * the 20-bit KID. + */ + #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe) + #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1 + uint32_t kid_or_ts_high; + #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff) + #define TX_BD_LONG_INLINE_UNUSED_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, the least significant 13 bits + * of this field contain the upper 13 bits of the 20-bit KID. + */ + #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000) + #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15 + /* + * This value selects bits 25:16 of the CFA action to perform on the + * packet. See the cfa_action field for more information. + */ + uint16_t cfa_action_high; + #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0 /* * This value selects a CFA action to perform on the packet. * Set this value to zero if no CFA action is desired. @@ -2103,16 +3147,19 @@ struct tx_bd_long_inline { */ uint32_t cfa_meta; /* When key = 1, this is the VLAN tag VID value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 /* When key = 1, this is the VLAN tag DE value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \ + UINT32_C(0x1000) /* When key = 1, this is the VLAN tag PRI value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \ + UINT32_C(0xe000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 /* When key = 1, this is the VLAN tag TPID select value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \ + UINT32_C(0x70000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \ (UINT32_C(0x0) << 16) @@ -2135,7 +3182,7 @@ struct tx_bd_long_inline { TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \ UINT32_C(0xff80000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. @@ -2144,7 +3191,7 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \ UINT32_C(0xf0000000) - #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 /* No editing */ #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \ (UINT32_C(0x0) << 28) @@ -2155,8 +3202,18 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \ (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ - TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* tx_bd_empty (size:128b/16B) */ @@ -2177,6 +3234,97 @@ struct tx_bd_empty { uint8_t unused_4[8]; } __rte_packed; +/* tx_bd_mp_cmd (size:128b/16B) */ +struct tx_bd_mp_cmd { + /* Unless otherwise stated, sub-fields of this field are always valid. */ + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_MP_CMD_TYPE_SFT 0 + /* + * Indicates that this BD is used to issue a command to one of + * the mid-path destinations. + */ + #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8) + #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD + #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_MP_CMD_FLAGS_SFT 6 + /* */ + #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0) + #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6 + /* + * This value indicates the number of 16B BD locations (slots) + * consumed in the ring by this mid-path command BD, including the + * BD header and the command field. + */ + #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8 + /* + * This value defines the length of command field in bytes. The maximum + * value shall be 496. + */ + uint16_t len; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with this + * Tx mid-path command. + */ + uint32_t opaque; + uint64_t unused1; +} __rte_packed; + +/* tx_bd_presync_cmd (size:128b/16B) */ +struct tx_bd_presync_cmd { + /* Unless otherwise stated, sub-fields of this field are always valid. */ + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_PRESYNC_CMD_TYPE_SFT 0 + /* + * Indicates that this BD is used to issue a cryptographic pre- + * sync command through the fast path and destined for TCE. + */ + #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9) + #define TX_BD_PRESYNC_CMD_TYPE_LAST \ + TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD + #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6 + /* */ + #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0) + #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6 + /* + * This value indicates the number of 16B BD locations (slots) + * consumed in the ring by this pre-sync command BD, including the + * BD header and the command field. + */ + #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8 + /* + * This value defines the length of command field in bytes. The maximum + * value shall be 496. + */ + uint16_t len; + /* + * The opaque data field is pass through to TCE and can be used for + * debug. + */ + uint32_t opaque; + /* + * This field is the Crypto Context ID to which the retransmit packet is + * applied. The KID references the context fields used by the + * associated kTLS offloaded connection. + */ + uint32_t kid; + /* + * The KID value of all-ones is reserved for non-KTLS packets, which + * only implies that this value must not be used when filling this + * field for crypto packets. + */ + #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff) + #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0 + uint32_t unused_1; +} __rte_packed; + /* rx_prod_pkt_bd (size:128b/16B) */ struct rx_prod_pkt_bd { /* This value identifies the type of buffer descriptor. */ @@ -2204,16 +3352,18 @@ struct rx_prod_pkt_bd { */ #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* + * This field has been deprecated. There can be no additional + * BDs for this packet from this ring. + * + * Old definition: * This value is the number of additional buffers in the ring that * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same - * network packet. - * - * Even if the packet to be placed does not need all the - * additional buffers, they will be consumed anyway. + * network packet. Even if the packet to be placed does not need + * all the additional buffers, they will be consumed anyway. */ #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300) #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8 @@ -2303,6 +3453,309 @@ struct rx_prod_agg_bd { uint64_t address; } __rte_packed; +/* cfa_cmpls_cmp_data_msg (size:128b/16B) */ +struct cfa_cmpls_cmp_data_msg { + uint32_t mp_client_dma_length_opcode_status_type; + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f) + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0 + /* Mid Path Short Completion with length = 16B. */ + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \ + UINT32_C(0x1e) + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + /* This value indicates the status for the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0) + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6 + /* Completed without error. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \ + (UINT32_C(0x0) << 6) + /* Indicates an unsupported CFA opcode in the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \ + (UINT32_C(0x1) << 6) + /* + * Indicates a CFA command formatting error. This error can occur on + * any of the supported CFA commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \ + (UINT32_C(0x2) << 6) + /* + * Indicates an SVIF-Table scope error. This error can occur on any + * of the supported CFA commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \ + (UINT32_C(0x3) << 6) + /* + * Indicates that the table_index is either outside of the + * table_scope range set by its EM_SIZE or, for EM Insert, it is in + * the static bucket range. This error can occur on EM Insert + * commands. It can also occur on Read, Read Clear, Write, and + * Invalidate commands if the table_type is EM. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \ + (UINT32_C(0x4) << 6) + /* + * Cache operation responded with an error. This error can occur on + * Read, Read Clear, Write, EM Insert, and EM Delete commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \ + (UINT32_C(0x5) << 6) + /* + * Indicates failure on EM Insert or EM Delete Command. Hash index + * and hash msb are returned in table_index and hash_msb fields. + * Dma_length is set to 1 if the bucket is also returned (as dma + * data). + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \ + (UINT32_C(0x6) << 6) + /* + * Indicates no notifications were available on an Event Collection + * command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \ + (UINT32_C(0x7) << 6) + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \ + CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10 + /* This is the opcode from the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \ + UINT32_C(0xff000) + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12 + /* + * This is read command. From 32 to 128B can be read from a table + * using this command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \ + (UINT32_C(0x0) << 12) + /* + * This is write command. From 32 to 128B can be written to a table + * using this command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \ + (UINT32_C(0x1) << 12) + /* + * This is read-clear command. 32B can be read from a table and a 16b + * mask can be used to clear specific 16b units after the read as an + * atomic operation. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \ + (UINT32_C(0x2) << 12) + /* + * An exact match table insert will be attempted into the table. If + * there is a free location in the bucket, the payload will be + * written to the bucket. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \ + (UINT32_C(0x3) << 12) + /* An exact match table delete will be attempted. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \ + (UINT32_C(0x4) << 12) + /* + * The specified table area will be invalidated. If it is needed + * again, it will be read from the backing store. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \ + (UINT32_C(0x5) << 12) + /* Reads notification messages from the Host Notification Queue. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \ + (UINT32_C(0x6) << 12) + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT + /* + * This field indicates the length of the DMA that accompanies the + * completion. Specified in units of DWords (32b). Valid values are + * between 0 and 128. A value of zero indicates that there is no DMA + * that accompanies the completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \ + UINT32_C(0xff00000) + #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \ + UINT32_C(0xf0000000) + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28 + /* TX configurable flow processing block. */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \ + (UINT32_C(0x2) << 28) + /* RX configurable flow processing block. */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \ + (UINT32_C(0x3) << 28) + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ + CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque; + uint16_t hash_msb_v; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1 + /* + * This is the upper 12b of the hash, returned on Exact Match + * Insertion/Deletion Commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0) + #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4 + /* This is the table type from the command. */ + uint8_t table_type; + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0 + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4 + /* This command acts on the action table of the specified scope. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM + uint8_t table_scope; + /* This is the table scope from the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0 + uint32_t table_index; + /* + * This is the table index from the command (if it exists). However, if + * an Exact Match Insertion/Deletion command failed, then this is the + * table index of the calculated static hash bucket. + */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0 +} __rte_packed; + +/* CFA Mid-Path 32B DMA Message */ +/* cfa_dma32b_data_msg (size:256b/32B) */ +struct cfa_dma32b_data_msg { + /* DMA data value. */ + uint32_t dta[8]; +} __rte_packed; + +/* CFA Mid-Path 64B DMA Message */ +/* cfa_dma64b_data_msg (size:512b/64B) */ +struct cfa_dma64b_data_msg { + /* DMA data value. */ + uint32_t dta[16]; +} __rte_packed; + +/* CFA Mid-Path 96B DMA Message */ +/* cfa_dma96b_data_msg (size:768b/96B) */ +struct cfa_dma96b_data_msg { + /* DMA data value. */ + uint32_t dta[24]; +} __rte_packed; + +/* CFA Mid-Path 128B DMA Message */ +/* cfa_dma128b_data_msg (size:1024b/128B) */ +struct cfa_dma128b_data_msg { + /* DMA data value. */ + uint32_t dta[32]; +} __rte_packed; + +/* ce_cmpls_cmp_data_msg (size:128b/16B) */ +struct ce_cmpls_cmp_data_msg { + uint16_t status_subtype_type; + /* + * This field indicates the exact type of the completion. By + * convention, the LSB identifies the length of the record in 16B + * units. Even values indicate 16B records. Odd values indicate 32B + * records. + */ + #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f) + #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0 + /* Completion of a Mid Path Command. Length = 16B */ + #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e) + #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \ + CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + /* + * This value indicates the CE sub-type operation that is being + * completed. + */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6 + /* Completion Response for a Solicited Command. */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6) + /* Error Completion (Unsolicited). */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6) + /* Re-Sync Completion (Unsolicited) */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \ + CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC + /* This value indicates the status for the command. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10 + /* Completed without error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \ + (UINT32_C(0x0) << 10) + /* CFCK load error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \ + (UINT32_C(0x1) << 10) + /* FID check error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \ + (UINT32_C(0x2) << 10) + /* Context kind / MP version mismatch error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \ + (UINT32_C(0x3) << 10) + /* Unsupported Destination Connection ID Length. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \ + (UINT32_C(0x4) << 10) + /* + * Invalid MP Command [anything other than ADD or DELETE + * triggers this for QUIC]. + */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \ + (UINT32_C(0x5) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \ + CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR + uint8_t unused0; + uint8_t mp_clients; + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4 + /* TX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4) + /* RX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \ + CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque; + /* */ + uint32_t kid_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe) + #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1 + uint32_t unused2; +} __rte_packed; + /* cmpl_base (size:128b/16B) */ struct cmpl_base { uint16_t type; @@ -2335,6 +3788,11 @@ struct cmpl_base { * Completion of PTP TX packet. Length = 32B */ #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) + /* + * TX L2 Packet Timestamp completion: + * Completion of an L2 Packet Timestamp Packet. Length = 16B + */ + #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4) /* * RX L2 TPA Start V2 Completion: * Completion of and L2 RX packet. Length = 32B @@ -2349,13 +3807,19 @@ struct cmpl_base { * and later chips. */ #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf) + /* + * RX L2 completion: + * This is the compressed version of Rx Completion for performance + * applications. Length = 16B + */ + #define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10) /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B */ #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11) /* - * RX Aggregation Buffer completion : + * RX Aggregation Buffer completion: * Completion of an L2 aggregation buffer in support of * TPA, HDS, or Jumbo packet completion. Length = 16B */ @@ -2372,6 +3836,24 @@ struct cmpl_base { * Length = 32B */ #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15) + /* + * RX TPA Aggregation Buffer Completion: + * Completion of an L2 aggregation buffer in support of TPA packet + * completion. + * Length = 16B + */ + #define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16) + /* + * RX L2 completion: Completion of and L2 RX packet. + * Length = 32B + */ + #define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17) + /* + * RX L2 TPA Start completion: Completion at the beginning of a TPA + * operation. + * Length = 32B + */ + #define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19) /* * Statistics Ejection Completion: * Completion of statistics data ejection buffer. @@ -2539,7 +4021,7 @@ struct tx_cmpl { */ #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200) /* - * When this bit is '1', it was not possible to collect a a timestamp + * When this bit is '1', it was not possible to collect a timestamp * for a PTP completion, in which case the timestamp_hi and * timestamp_lo fields are invalid. When this bit is '0' for a PTP * completion, the timestamp_hi and timestamp_lo fields are valid. @@ -2824,8 +4306,9 @@ struct tx_cmpl_ptp_hi { uint64_t v2; /* * This value is written by the NIC such that it will be different for - * each pass through the completion queue.The even passes will write 1. - * The odd passes will write 0 + * each pass through the completion queue. + * The even passes will write 1. + * The odd passes will write 0. */ #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) } __rte_packed; @@ -2840,53 +4323,60 @@ struct rx_pkt_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_PKT_CMPL_TYPE_SFT 0 + #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_CMPL_TYPE_SFT 0 /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B */ - #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11) - #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2 - #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_PKT_CMPL_FLAGS_SFT 6 + #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11) + #define RX_PKT_CMPL_TYPE_LAST \ + RX_PKT_CMPL_TYPE_RX_L2 + #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an * error of some type. Type of error is indicated in * error_flags. */ - #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Normal: * Packet was placed using normal algorithm. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: * Packet was placed using jumbo algorithm. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \ RX_PKT_CMPL_FLAGS_PLACEMENT_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. + */ + #define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12 /* * Not Known: * Indicates that the packet type was not known. @@ -2936,15 +4426,15 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \ (UINT32_C(0x7) << 12) /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP * packet. */ #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ (UINT32_C(0x8) << 12) /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP * packet and that a timestamp was taken for the packet. */ #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ @@ -2984,37 +4474,49 @@ struct rx_pkt_cmpl { /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of inner * IP and TCP or UDP headers. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0) + /* + * The RSS hash was computed over source IP address and destination * IP address of inner IP header. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3) + #define RX_PKT_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. * * A value of zero indicates that header is 256B into the packet. */ @@ -3501,15 +5003,15 @@ struct rx_pkt_v2_cmpl { #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \ (UINT32_C(0x7) << 12) /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP * packet. */ #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ (UINT32_C(0x8) << 12) /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP * packet and that a timestamp was taken for the packet. */ #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ @@ -3549,33 +5051,45 @@ struct rx_pkt_v2_cmpl { /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of inner * IP and TCP or UDP headers. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0) + /* + * The RSS hash was computed over source IP address and destination * IP address of inner IP header. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3) + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 uint16_t metadata1_payload_offset; /* * This is data from the CFA as indicated by the meta_format field. @@ -3585,16 +5099,36 @@ struct rx_pkt_v2_cmpl { * truncation placement is used, this value represents the placed * (truncated) length of the packet. */ - #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) - #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0 + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0 /* This is data from the CFA as indicated by the meta_format field. */ - #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) - #define RX_PKT_V2_CMPL_METADATA1_SFT 12 + #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_METADATA1_SFT 12 /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) - #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12 - /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) /* * This value is the RSS hash value calculated for the packet * based on the mode bits and key value in the VNIC. When vee_cmpl_mode @@ -3647,7 +5181,7 @@ struct rx_pkt_v2_cmpl_hi { * information: * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i + * value, justified to LSB. * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier * - NVGRE = TNI[23:0] -> Tenant Network ID @@ -4007,12 +5541,8 @@ struct rx_pkt_v2_cmpl_hi { uint32_t timestamp; } __rte_packed; -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +/* rx_pkt_v3_cmpl (size:128b/16B) */ +struct rx_pkt_v3_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -4021,84 +5551,145 @@ struct rx_tpa_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_START_CMPL_TYPE_SFT 0 + #define RX_PKT_V3_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_V3_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B + * RX L2 V3 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in Thor2 + * and later chips. */ - #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) - #define RX_TPA_START_CMPL_TYPE_LAST \ - RX_TPA_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_START_CMPL_FLAGS_SFT 6 - /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 UINT32_C(0x17) + #define RX_PKT_V3_CMPL_TYPE_LAST \ + RX_PKT_V3_CMPL_TYPE_RX_L2_V3 + #define RX_PKT_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_V3_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_V3_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Normal: + * Packet was placed using normal algorithm. + */ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Packet was placed using jumbo algorithm. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Truncation: + * Packet was placed using truncation algorithm. The + * placed (truncated) length is indicated in the payload_offset + * field. The original length is indicated in the len field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION \ + (UINT32_C(0x3) << 7) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_LAST \ + RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* * TCP Packet: * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP + * packet. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP + * packet and that a timestamp was taken for the packet. + * The 4b sub-nanosecond portion of the timestamp is in + * the payload_offset field. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -4106,879 +5697,955 @@ struct rx_tpa_start_cmpl { * corresponds to. */ uint32_t opaque; + uint16_t rss_hash_type_agg_bufs_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t v1; + #define RX_PKT_V3_CMPL_V1 UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + #define RX_PKT_V3_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_V3_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 1 b */ + #define RX_PKT_V3_CMPL_UNUSED1 UINT32_C(0x40) /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, - * destination IP address, source port, and destination port of inner - * IP and TCP or UDP headers. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination - * IP address of inner IP header. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the + * hardware, HWRM firmware, and drivers. For example, if RSS hash + * is supported and enabled for TCP traffic only, then the values of + * tuple_extract_op corresponding to 4-tuples are only valid for + * TCP traffic. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_SFT 7 + /* + * The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * inner IP and TCP or UDP headers. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (UINT32_C(0x0) << 7) + /* + * The RSS hash was computed over source IP address and + * destination IP address of inner IP header. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (UINT32_C(0x1) << 7) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2 (UINT32_C(0x2) << 7) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (UINT32_C(0x3) << 7) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * The RSS hash was computed over source IP address of the inner + * IP header. */ - uint16_t agg_id; - /* unused2 is 9 b */ - #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (UINT32_C(0x4) << 7) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * The RSS hash was computed over destination IP address of the + * inner IP header. */ - #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) - #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (UINT32_C(0x5) << 7) + /* + * The RSS hash was computed over source IP address of the outer + * IP header. + * Note: For non-tunneled packets, this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (UINT32_C(0x6) << 7) + /* + * The RSS hash was computed over destination IP address of the + * outer IP header. + * Note: For non-tunneled packets, this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (UINT32_C(0x7) << 7) + /* + * The RSS hash was computed over source IP address, destination + * IP address, and flow label of the inner IP header. + * Note: For packets without an inner IPv6 header, this value is not + * this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (UINT32_C(0x8) << 7) + /* + * The RSS hash was computed over the flow label of the inner + * IP header. + * Note: For packets without an inner IPv6 header, this value + * is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (UINT32_C(0x9) << 7) + /* + * The RSS hash was computed over source IP address, destination + * IP address, and flow label of the outer IP header. + * Note: For packets without an outer IPv6 header, this value is not + * applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (UINT32_C(0xa) << 7) + /* + * The RSS hash was computed over the flow label of the outer + * IP header. + * Note: For packets without an outer IPv6 header, this value + * is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 + uint16_t metadata1_payload_offset; + /* + * If truncation placement is not used, this value indicates the offset + * in bytes from the beginning of the packet where the inner payload + * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. + * For PTP packets with timestamp (as indicated by the flags_itype + * field), this field contains the 4b sub-nanosecond portion of the + * timestamp. + * + * If truncation placement is used, this value represents the placed + * (truncated) length of the packet. + */ + #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_V3_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V3_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_V3_CMPL_METADATA1_VALID UINT32_C(0x8000) /* * This value is the RSS hash value calculated for the packet - * based on the mode bits and key value in the VNIC. + * based on the mode bits and key value in the VNIC. When hairpin_en + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. */ uint32_t rss_hash; } __rte_packed; -/* - * Last 16 bytes of rx_tpa_start_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_cmpl_hi { +/* Last 16 bytes of RX Packet V3 Completion Record */ +/* rx_pkt_v3_cmpl_hi (size:128b/16B) */ +struct rx_pkt_v3_cmpl_hi { uint32_t flags2; /* - * This indicates that the ip checksum was calculated for the - * inner packet and that the sum passed for all segments - * included in the aggregation. + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * This indicates that the TCP, UDP or ICMP checksum was - * calculated for the inner packet and that the sum passed - * for all segments included in the aggregation. + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. */ - #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * This indicates that the ip checksum was calculated for the - * tunnel header and that the sum passed for all segments - * included in the aggregation. + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the sum passed for - * all segments included in the aggregation. + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) /* This value indicates what format the metadata field is. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* - * The metadata field contains the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. - * - metadata[31:16] contains the vlan TPID value. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \ (UINT32_C(0x1) << 4) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_LAST \ + RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE \ + UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 10) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_LAST \ + RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] */ - uint32_t metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 - uint16_t v2; + uint32_t metadata2; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_V2 \ + UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_PKT_V3_CMPL_HI_ERRORS_SFT 1 /* - * This field identifies the CFA action rule that was used for this - * packet. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - uint16_t cfa_code; + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 8 physical buffers. */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. For regular placement, this error is + * not valid. For HDS and jumbo placement, this means that not + * enough agg BDs were posted to place the packet. */ - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. + * Bad Format: + * BDs were not formatted correctly. */ - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. + * Flush: + * There was a bad_format error on the previous operation */ - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH + /* This indicates that there was an error in the IP header checksum. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR \ + UINT32_C(0x10) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * This indicates that there was an error in the TCP, UDP or ICMP + * checksum. */ - #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 -} __rte_packed; - -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte - * struct) - */ -/* rx_tpa_start_v2_cmpl (size:128b/16B) */ -struct rx_tpa_start_v2_cmpl { - uint16_t flags_type; + #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR \ + UINT32_C(0x20) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates that there was an error in the tunnel IP header + * checksum. */ - #define RX_TPA_START_V2_CMPL_TYPE_MASK \ - UINT32_C(0x3f) - #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 + #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR \ + UINT32_C(0x40) + /* This indicates that there was an error in the tunnel UDP checksum. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR \ + UINT32_C(0x80) /* - * RX L2 TPA Start V2 Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B - * This is the new version of the RX_TPA_START completion used - * in SR2 and later chips. + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ - UINT32_C(0xd) - #define RX_TPA_START_V2_CMPL_TYPE_LAST \ - RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 - #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ - UINT32_C(0xffc0) - #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 + #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR \ + UINT32_C(0x100) /* - * When this bit is '1', it indicates a packet that has an error - * of some type. Type of error is indicated in error_flags. + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ - UINT32_C(0x40) - /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ - UINT32_C(0x380) - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe00) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9 /* - * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ - (UINT32_C(0x1) << 7) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 9) /* - * Header/Data Separation: - * Packet was placed using Header/Data separation algorithm. - * The separation location is indicated by the itype field. + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ - (UINT32_C(0x2) << 7) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 9) /* - * IOC/Jumbo: - * Packet will be placed using In-Order Completion/Jumbo where - * the first packet of the aggregation is placed using Jumbo - * Placement. Subsequent packets will be placed such that each - * packet starts at the beginning of an aggregation buffer. + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ - (UINT32_C(0x4) << 7) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 9) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 9) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 9) /* - * IOC/Header-Data Separation: - * Packet will be placed using In-Order Completion/HDS where - * the header is in the first packet buffer. Payload of each - * packet will be placed such that each packet starts at the - * beginning of an aggregation buffer. + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ - (UINT32_C(0x7) << 7) - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ - UINT32_C(0x400) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 9) /* - * This bit is '1' if metadata has been added to the end of the - * packet in host memory. Metadata starts at the first 32B boundary - * after the end of the packet for regular and jumbo placement. It - * starts at the first 32B boundary after the end of the header for - * HDS placement. The length of the metadata is indicated in the - * metadata itself. + * Indicates that the IP checksum failed its check in the tunnel + * header. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ - UINT32_C(0x800) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 9) /* - * This value indicates what the inner packet determined for the - * packet was. + * Indicates that the L4 checksum failed its check in the tunnel + * header. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 9) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK \ UINT32_C(0xf000) - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_SFT 12 /* - * TCP Packet: - * Indicates that the packet was IP and TCP. + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 */ - uint16_t len; + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 12) /* - * This is a copy of the opaque field from the RX BD this completion - * corresponds to. If the VNIC is configured to not use an Rx BD for - * the TPA Start completion, then this is a copy of the opaque field - * from the first BD used to place the TPA Start packet. + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. */ - uint32_t opaque; + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 12) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. */ - uint8_t v1; + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 12) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. */ - #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 12) /* - * This is the RSS hash type for the packet. The value is packed - * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * - * The value of tuple_extrac_op provides the information about - * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, - * destination IP address, source port, and destination port of inner - * IP and TCP or UDP headers. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination - * IP address of inner IP header. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, - * destination IP address, source port, and destination port of - * IP and TCP or UDP headers of outer tunnel headers. - * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and - * destination IP address of IP header of outer tunnel headers. - * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. */ - uint8_t rss_hash_type; + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 12) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * Indicates that the IP checksum failed its check in the + * inner header. */ - uint16_t agg_id; + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \ + (UINT32_C(0x9) << 12) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * Indicates that the L4 checksum failed its check in the + * inner header. */ - #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff) - #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0 - #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) - #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12 - /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) - #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12 - /* When meta_format != 0, this value is the VLAN valid. */ - #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \ + (UINT32_C(0xa) << 12) + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR /* - * This value is the RSS hash value calculated for the packet - * based on the mode bits and key value in the VNIC. - * When vee_cmpl_mode is set in VNIC context, this is the lower - * 32b of the host address from the first BD used to place the packet. + * This is data from the CFA block as indicated by the meta_format + * field. */ - uint32_t rss_hash; -} __rte_packed; - -/* - * Last 16 bytes of RX L2 TPA Start V2 Completion Record - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_v2_cmpl_hi { - uint32_t flags2; - /* This indicates that the aggregation was done using GRO rules. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ - UINT32_C(0x4) + uint16_t metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_SFT 13 /* - * When this bit is '0', the cs_ok field has the following definition:- - * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum - * in the delivered packet, counted from the outer-most header group to - * the inner-most header group, stopping at the first error. - - * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum - * in the delivered packet, counted from the outer-most header group to - * the inner-most header group, stopping at the first error. When this - * bit is '1', the cs_ok field has the following definition: - - * hdr_cnt[2:0] = The number of header groups that were parsed by the - * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit - * will be '1' if all the parsed header groups with an IP checksum are - * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed - * header groups with an L4 checksum are valid. + * The timestamp field contains the 32b timestamp for the packet from + * the MAC. + * + * When hairpin_en is set in VNIC context, this is the upper 32b of the + * host address from the first BD used to place the packet. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \ - UINT32_C(0x8) - /* This value indicates what format the metadata field is. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \ - UINT32_C(0xf0) - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* There is no metadata information. Values are zero. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \ - (UINT32_C(0x0) << 4) + uint32_t timestamp; +} __rte_packed; + +/* rx_pkt_compress_cmpl (size:128b/16B) */ +struct rx_pkt_compress_cmpl { + uint16_t flags_type; /* - * The {metadata1, metadata0} fields contain the vtag - * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], - * de, vid[11:0]} The metadata2 field contains the table scope - * and action record pointer. - metadata2[25:0] contains the - * action record pointer. - metadata2[31:26] contains the table - * scope. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ - (UINT32_C(0x1) << 4) + #define RX_PKT_COMPRESS_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_COMPRESS_CMPL_TYPE_SFT 0 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} - * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 - * - IPv4 = 0 (not populated) - * - IPv6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * RX L2 completion: + * This is the compressed version of Rx Completion for performance + * applications. Length = 16B + * This version of the completion record is used in Thor2 and later + * chips. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ - (UINT32_C(0x2) << 4) + #define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS \ + UINT32_C(0x10) + #define RX_PKT_COMPRESS_CMPL_TYPE_LAST \ + RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS + #define RX_PKT_COMPRESS_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_PKT_COMPRESS_CMPL_FLAGS_SFT 6 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} - * The metadata2 field contains the 32b metadata from the prepended - * header (chdr_data). + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ - (UINT32_C(0x3) << 4) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} - * The metadata2 field contains the outer_l3_offset, - * inner_l2_offset, inner_l3_offset, and inner_l4_size. - * - metadata2[8:0] contains the outer_l3_offset. - * - metadata2[17:9] contains the inner_l2_offset. - * - metadata2[26:18] contains the inner_l3_offset. - * - metadata2[31:27] contains the inner_l4_size. + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ - (UINT32_C(0x4) << 4) - #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE \ + UINT32_C(0x100) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 8) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 8) + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_LAST \ + RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \ - UINT32_C(0x100) - /* - * This indicates that the complete 1's complement checksum was - * calculated for the packet in the affregation. - */ - #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + #define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE \ UINT32_C(0x200) + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) /* - * This field indicates the status of IP and L4 CS calculations done - * by the chip. The format of this field is indicated by the - * cs_all_ok_mode bit. - * CS status for TPA packets is always valid. This means that "all_ok" - * status will always be set. The ok count status will be set - * appropriately for the packet header, such that all existing CS - * values are ok. + * This value indicates what the inner packet determined for the + * packet was. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \ - UINT32_C(0xfc00) - #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10 + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_SFT 12 /* - * This value is the complete 1's complement checksum calculated from - * the start of the outer L3 header to the end of the packet (not - * including the ethernet crc). It is valid when the - * 'complete_checksum_calc' flag is set. For TPA Start completions, - * the complete checksum is calculated for the first packet in the - * aggregation only. + * Not Known: + * Indicates that the packet type was not known. */ - #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ - UINT32_C(0xffff0000) - #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) /* - * This is data from the CFA block as indicated by the meta_format - * field. - * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped - * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], - * act_rec_ptr[25:0]} - * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] - * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] - * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] - * When vee_cmpl_mode is set in VNIC context, this is the upper 32b - * of the host address from the first BD used to place the packet. + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. */ - uint32_t metadata2; - uint16_t errors_v2; + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_V2_CMPL_V2 \ - UINT32_C(0x1) - #define RX_TPA_START_V2_CMPL_ERRORS_MASK \ - UINT32_C(0xfffe) - #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1 + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) /* - * This error indicates that there was some sort of problem with - * the BDs for the packetThe packet should be treated as - * invalid. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \ - UINT32_C(0xe) - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1 - /* No buffer error */ - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ - (UINT32_C(0x0) << 1) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) /* - * Did Not Fit: - * Packet did not fit into packet buffer provided. This means - * that the TPA Start packet was too big to be placed into the - * per-packet maximum number of physical buffers configured for - * the VNIC, or that it was too big to be placed into the - * per-aggregation maximum number of physical buffers configured - * for the VNIC. This error only occurs when the VNIC is - * configured for variable size receive buffers. + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ - (UINT32_C(0x1) << 1) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) /* - * Bad Format: - * BDs were not formatted correctly. + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ - (UINT32_C(0x3) << 1) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) /* - * Flush: - * There was a bad_format error on the previous operation + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ - (UINT32_C(0x5) << 1) - #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) /* - * This is data from the CFA block as indicated by the meta_format - * field. + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP + * packet. */ - uint16_t metadata0; - /* When meta_format != 0, this value is the VLAN VID. */ - #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) - #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0 - /* When meta_format != 0, this value is the VLAN DE. */ - #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000) - /* When meta_format != 0, this value is the VLAN PRI. */ - #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13 + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) /* - * This field contains the outer_l3_offset, inner_l2_offset, - * inner_l3_offset, and inner_l4_size. - * - * hdr_offsets[8:0] contains the outer_l3_offset. - * hdr_offsets[17:9] contains the inner_l2_offset. - * hdr_offsets[26:18] contains the inner_l3_offset. - * hdr_offsets[31:27] contains the inner_l4_size. + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP + * packet and that a timestamp was taken for the packet. + * The 4b sub-nanosecond portion of the timestamp is in + * the payload_offset field. */ - uint32_t hdr_offsets; -} __rte_packed; - -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { - uint16_t flags_type; + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ - #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_END_CMPL_TYPE_SFT 0 + uint16_t len; /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. - * Length = 32B + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. When hairpin_en + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. */ - #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_END_CMPL_TYPE_LAST \ - RX_TPA_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_END_CMPL_FLAGS_SFT 6 + uint32_t rss_hash; + uint16_t metadata1_cs_error_calc_v1; /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) - /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_COMPRESS_CMPL_V1 \ + UINT32_C(0x1) + /* unused is 3 b */ + #define RX_PKT_COMPRESS_CMPL_UNUSED_MASK \ + UINT32_C(0xe) + #define RX_PKT_COMPRESS_CMPL_UNUSED_SFT 1 + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK \ + UINT32_C(0xff0) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_SFT 4 + /* This indicates that there was an error in the IP header checksum. */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR \ + UINT32_C(0x10) /* - * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * This indicates that there was an error in the TCP, UDP or ICMP + * checksum. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ - (UINT32_C(0x1) << 7) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR \ + UINT32_C(0x20) /* - * Header/Data Separation: - * Packet was placed using Header/Data separation algorithm. - * The separation location is indicated by the itype field. + * This indicates that there was an error in the tunnel IP header + * checksum. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ - (UINT32_C(0x2) << 7) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR \ + UINT32_C(0x40) + /* This indicates that there was an error in the tunnel UDP checksum. */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR \ + UINT32_C(0x80) /* - * IOC/Jumbo: - * Packet will be placed using In-Order Completion/Jumbo where - * the first packet of the aggregation is placed using Jumbo - * Placement. Subsequent packets will be placed such that each - * packet starts at the beginning of an aggregation buffer. + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ - (UINT32_C(0x4) << 7) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC \ + UINT32_C(0x100) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC \ + UINT32_C(0x200) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC \ + UINT32_C(0x400) /* - * IOC/Header-Data Separation: - * Packet will be placed using In-Order Completion/HDS where - * the header is in the first packet buffer. Payload of each - * packet will be placed such that each packet starts at the - * beginning of an aggregation buffer. + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ - (UINT32_C(0x7) << 7) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS - /* unused is 1 b */ - #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC \ + UINT32_C(0x800) + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_PKT_COMPRESS_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t vlanc_tcid; + /* When meta_format!=0, this value is the VLAN VID. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff) + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_SFT 0 + /* When meta_format!=0, this value is the VLAN DE. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE UINT32_C(0x1000) + /* When meta_format!=0, this value is the VLAN PRI. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_SFT 13 + uint32_t errors_agg_bufs_opaque; + /* Lower 16bits of the Opaque field provided in the Rx BD. */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK \ + UINT32_C(0xffff) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_SFT \ + 0 /* - * This bit is '1' if metadata has been added to the end of the - * packet in host memory. Metadata starts at the first 32B boundary - * after the end of the packet for regular and jumbo placement. - * It starts at the first 32B boundary after the end of the header - * for HDS placement. The length of the metadata is indicated in the - * metadata itself. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK \ + UINT32_C(0x1f0000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_SFT \ + 16 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK \ + UINT32_C(0x1fe00000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_SFT \ + 21 /* - * This value indicates what the inner packet determined for the - * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. */ - #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ - UINT32_C(0xf000) - #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0x1e00000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_SFT \ + 21 /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. */ - uint16_t len; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 21) /* - * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. */ - uint32_t opaque; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 21) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * indicates that header length is out of range. Valid for + * IPv4 and RoCE */ - uint8_t agg_bufs_v1; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 21) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 */ - #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 21) /* - * This value is the number of aggregation buffers that follow this - * entry in the completion ring that are a part of this aggregation - * packet. - * If the value is zero, then the packet is completely contained - * in the buffer space provided in the aggregation start completion. + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. */ - #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) - #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 21) /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * - * A value of zero indicates an offset of 256 bytes. + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. */ - uint8_t payload_offset; - uint8_t agg_id; - /* unused2 is 1 b */ - #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 21) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. */ - #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) - #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 21) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 21) /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. */ - uint32_t tsdelta; -} __rte_packed; - -/* - * Last 16 bytes of rx_tpa_end_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { - uint32_t tpa_dup_acks; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 21) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_LAST \ + RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. */ - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe000000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_SFT \ + 25 /* - * This value is the valid when TPA completion is active. It - * indicates the length of the longest segment of the TPA operation - * for LRO mode and the length of the first segment in GRO mode. - * - * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used - * to indicate MSS size to the stack. + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. */ - uint16_t tpa_seg_len; - /* unused4 is 16 b */ - uint16_t unused3; - uint16_t errors_v2; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 25) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. */ - #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define RX_TPA_END_CMPL_ERRORS_SFT 1 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 25) /* - * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as - * invalid. + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 25) /* - * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not - * BDs on chip but that there was adequate reservation. - * provided by the TPA block. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ - (UINT32_C(0x2) << 1) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 25) /* - * This error occurs when TPA block was not configured to - * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. - * - * This error can also be generated when the number of - * segments is not programmed correctly in TPA and the - * 33 total aggregation buffers allowed for the TPA - * operation has been exceeded. + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ - (UINT32_C(0x4) << 1) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR - /* unused5 is 16 b */ - uint16_t unused_4; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 25) /* - * This is the opaque value that was completed for the TPA start - * completion that corresponds to this TPA end completion. + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. */ - uint32_t start_opaque; + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 25) + /* + * Indicates that the IP checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 25) + /* + * Indicates that the L4 checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 25) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + /* + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR \ + UINT32_C(0x10000000) + /* unused1 is 3 b */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK \ + UINT32_C(0xe0000000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_SFT \ + 29 } __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl { +/* rx_tpa_start_cmpl (size:128b/16B) */ +struct rx_tpa_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -4987,28 +6654,23 @@ struct rx_tpa_v2_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_START_CMPL_TYPE_MASK \ - UINT32_C(0x3f) - #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 /* * RX L2 TPA Start Completion: * Completion at the beginning of a TPA operation. * Length = 32B */ - #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ - UINT32_C(0x13) - #define RX_TPA_V2_START_CMPL_TYPE_LAST \ - RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ - UINT32_C(0xffc0) - #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + #define RX_TPA_START_CMPL_TYPE_LAST \ + RX_TPA_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ - UINT32_C(0x40) + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ - UINT32_C(0x380) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -5017,14 +6679,14 @@ struct rx_tpa_v2_start_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* * GRO/Jumbo: @@ -5034,7 +6696,7 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -5045,39 +6707,28 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ - UINT32_C(0x400) - /* - * For devices that support timestamps, when this bit is cleared the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the 32b timestamp for - * the packet from the MAC. When this bit is set, the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the outer_l3_offset, inner_l2_offset, - * inner_l3_offset, and inner_l4_size. - */ - #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ - UINT32_C(0x800) + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ - UINT32_C(0xf000) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 /* * TCP Packet: * Indicates that the packet was IP and TCP. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* * This value indicates the amount of packet data written to the * buffer the opaque field in this completion corresponds to. @@ -5099,8 +6750,8 @@ struct rx_tpa_v2_start_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. @@ -5137,6 +6788,16 @@ struct rx_tpa_v2_start_cmpl { * with the TPA end completion. */ uint16_t agg_id; + /* unused2 is 9 b */ + #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) + #define RX_TPA_START_CMPL_AGG_ID_SFT 9 /* * This value is the RSS hash value calculated for the packet * based on the mode bits and key value in the VNIC. @@ -5145,48 +6806,43 @@ struct rx_tpa_v2_start_cmpl { } __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_start_cmpl. + * Last 16 bytes of rx_tpa_start_cmpl. * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl_hi { +/* rx_tpa_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the * inner packet and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ - UINT32_C(0x1) + #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) /* * This indicates that the TCP, UDP or ICMP checksum was * calculated for the inner packet and that the sum passed * for all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ - UINT32_C(0x2) + #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* * This indicates that the ip checksum was calculated for the * tunnel header and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ - UINT32_C(0x4) + #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* * This indicates that the UDP checksum was * calculated for the tunnel packet and that the sum passed for * all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ - UINT32_C(0x8) + #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) /* This value indicates what format the metadata field is. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ - UINT32_C(0xf0) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Value is zero. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* * The metadata field contains the VLAN tag and TPID value. @@ -5195,140 +6851,47 @@ struct rx_tpa_v2_start_cmpl_hi { * - metadata[15:13] contains the vlan PRI value. * - metadata[31:16] contains the vlan TPID value. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ (UINT32_C(0x1) << 4) - /* - * If ext_meta_format is equal to 1, the metadata field - * contains the lower 16b of the tunnel ID value, justified - * to LSB - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ - (UINT32_C(0x2) << 4) - /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ - (UINT32_C(0x3) << 4) - /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset, inner_l2_offset, inner_l3_offset and - * inner_l4_size. - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[17:9] contains the inner_l2_offset. - * - metadata[26:18] contains the inner_l3_offset. - * - metadata[31:27] contains the inner_l4_size. - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ - (UINT32_C(0x4) << 4) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ - UINT32_C(0x100) - /* - * This indicates that the complete 1's complement checksum was - * calculated for the packet. - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ - UINT32_C(0x200) - /* - * The combination of this value and meta_format indicated what - * format the metadata field is. - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ - UINT32_C(0xc00) - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 - /* - * This value is the complete 1's complement checksum calculated from - * the start of the outer L3 header to the end of the packet (not - * including the ethernet crc). It is valid when the - * 'complete_checksum_calc' flag is set. For TPA Start completions, - * the complete checksum is calculated for the first packet in the - * aggregation only. - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ - UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* * This is data from the CFA block as indicated by the meta_format * field. */ uint32_t metadata; - /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ - #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ - #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ - #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ - #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 - uint16_t errors_v2; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 + uint16_t v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V2 \ - UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ - UINT32_C(0xfffe) - #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 - /* - * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as - * invalid. - */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ - UINT32_C(0xe) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 - /* No buffer error */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ - (UINT32_C(0x0) << 1) - /* - * Bad Format: - * BDs were not formatted correctly. - */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ - (UINT32_C(0x3) << 1) - /* - * Flush: - * There was a bad_format error on the previous operation - */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ - (UINT32_C(0x5) << 1) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH + #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) /* * This field identifies the CFA action rule that was used for this * packet. */ uint16_t cfa_code; /* - * For devices that support timestamps this field is overridden - * with the timestamp value. When `flags.timestamp_fld_format` is - * cleared, this field contains the 32b timestamp for the packet from the - * MAC. - * - * When `flags.timestamp_fld_format` is set, this field contains the - * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size - * as defined below. + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. */ uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* @@ -5336,35 +6899,37 @@ struct rx_tpa_v2_start_cmpl_hi { * the outer L3 header. If there is no outer L3 header, then this * value is zero. */ - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 /* * This is the offset from the beginning of the packet in bytes for * the inner most L2 header. */ - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 /* * This is the offset from the beginning of the packet in bytes for * the inner most L3 header. */ - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 /* * This is the size in bytes of the inner most L4 header. * This can be subtracted from the payload_offset to determine * the start of the inner most L4 header. */ - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 + #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 } __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte + * struct) */ -/* rx_tpa_v2_end_cmpl (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl { +/* rx_tpa_start_v2_cmpl (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -5373,27 +6938,33 @@ struct rx_tpa_v2_end_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V2_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. + * RX L2 TPA Start V2 Completion: + * Completion at the beginning of a TPA operation. * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. */ - #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_V2_END_CMPL_TYPE_LAST \ - RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ + UINT32_C(0xd) + #define RX_TPA_START_V2_CMPL_TYPE_LAST \ + RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 + #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -5402,15 +6973,24 @@ struct rx_tpa_v2_end_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* * GRO/Jumbo: * Packet will be placed using GRO/Jumbo where the first @@ -5419,7 +6999,7 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -5430,44 +7010,102 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10 + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. */ uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated * with. Use this number to correlate the TPA start completion @@ -5475,138 +7113,271 @@ struct rx_tpa_v2_end_cmpl { */ uint16_t agg_id; /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - uint32_t tsdelta; + #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V2_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V2_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. + */ + uint32_t rss_hash; } __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_end_cmpl. + * Last 16 bytes of RX L2 TPA Start V2 Completion Record * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl_hi { +/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl_hi { + uint32_t flags2; + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x4) /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. */ - uint16_t tpa_dup_acks; + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) /* - * This value indicated the offset in bytes from the beginning of - * the packet where the inner payload starts. This value is valid - * for TCP, UDP, FCoE and RoCE packets + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - uint8_t payload_offset; + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) /* - * The value is the total number of aggregation buffers that were - * used in the TPA operation. All TPA aggregation buffer completions - * precede the TPA End completion. If the value is zero, then the - * aggregation is completely contained in the buffer space provided - * in the aggregation start completion. - * Note that the field is simply provided as a cross check. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). */ - uint8_t tpa_agg_bufs; + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) /* - * This value is the valid when TPA completion is active. It - * indicates the length of the longest segment of the TPA operation - * for LRO mode and the length of the first segment in GRO mode. - * - * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used - * to indicate MSS size to the stack. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. */ - uint16_t tpa_seg_len; - uint16_t unused_1; + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet in the affregation. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + * CS status for TPA packets is always valid. This means that "all_ok" + * status will always be set. The ok count status will be set + * appropriately for the packet header, such that all existing CS + * values are ok. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ + #define RX_TPA_START_V2_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_ERRORS_MASK \ UINT32_C(0xfffe) - #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * the BDs for the packetThe packet should be treated as * invalid. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \ UINT32_C(0xe) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) /* - * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not - * BDs on chip but that there was adequate reservation. - * provided by the TPA block. + * Did Not Fit: + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ - (UINT32_C(0x2) << 1) + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) - /* - * This error occurs when TPA block was not configured to - * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. - * - * This error can also be generated when the number of - * segments is not programmed correctly in TPA and the - * 33 total aggregation buffers allowed for the TPA - * operation has been exceeded. - */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ - (UINT32_C(0x4) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH - uint16_t unused_2; + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * This is the opaque value that was completed for the TPA start - * completion that corresponds to this TPA end completion. + * This is data from the CFA block as indicated by the meta_format + * field. */ - uint32_t start_opaque; + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13 + /* + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. + * + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. + */ + uint32_t hdr_offsets; } __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V3 Completion Record (32 bytes split to 2 16-byte + * struct) */ -/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ -struct rx_tpa_v2_abuf_cmpl { - uint16_t type; +/* rx_tpa_start_v3_cmpl (size:128b/16B) */ +struct rx_tpa_start_v3_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -5614,253 +7385,478 @@ struct rx_tpa_v2_abuf_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V3_CMPL_TYPE_SFT 0 /* - * RX TPA Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA packet completion. Length = 16B + * RX L2 TPA Start V3 completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in Thor2 and later chips. */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) - #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ - RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + #define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 \ + UINT32_C(0x19) + #define RX_TPA_START_V3_CMPL_TYPE_LAST \ + RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 + #define RX_TPA_START_V3_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V3_CMPL_FLAGS_SFT 6 /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - uint16_t len; + #define RX_TPA_START_V3_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - uint32_t opaque; - uint16_t v; + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * This is the aggregation ID that the completion is associated with. Use - * this number to correlate the TPA agg completion with the TPA start - * completion and the TPA end completion. + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. */ - uint16_t agg_id; - uint32_t unused_1; -} __rte_packed; - -/* rx_abuf_cmpl (size:128b/16B) */ -struct rx_abuf_cmpl { - uint16_t type; + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) /* - * RX Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) - #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. */ uint32_t opaque; - uint32_t v; + uint16_t rss_hash_type_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_ABUF_CMPL_V UINT32_C(0x1) - /* unused3 is 32 b */ - uint32_t unused_2; -} __rte_packed; - -/* VEE FLUSH Completion Record (16 bytes) */ -/* vee_flush (size:128b/16B) */ -struct vee_flush { - uint32_t downstream_path_type; + #define RX_TPA_START_V3_CMPL_V1 UINT32_C(0x1) + /* unused1 is 6 b. */ + #define RX_TPA_START_V3_CMPL_UNUSED1_MASK UINT32_C(0x7e) + #define RX_TPA_START_V3_CMPL_UNUSED1_SFT 1 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. + * * 1: The RSS hash was computed over source IP address and + * destination IP address of inner IP header. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 4: The RSS hash was computed over source IP address of the inner + * IP header. + * * 5: The RSS hash was computed over destination IP address of the + * inner IP header. + * * 6: The RSS hash was computed over source IP address of the outer + * IP header. Note: For non-tunneled packets, this value is not + * applicable + * * 7: The RSS hash was computed over destination IP address of the + * outer IP header. + * Note: For non-tunneled packets, this value is not applicable. + * * 8: The RSS hash was computed over source IP address, destination + * IP address, and flow label of the inner IP header. + * Note: For packets without an inner IPv6 header, this value is not + * applicable. + * * 9: The RSS hash was computed over the flow label of the inner + * IP header. + * Note: For packets without an inner IPv6 header, this value + * is not applicable. + * * 10: The RSS hash was computed over source IP address, destination + * IP address, and flow label of the outer IP header. + * Note: For packets without an outer IPv6 header, this value is not + * applicable. + * * 11: The RSS hash was computed over the flow label of the outer + * IP header. Note: For packets without an outer IPv6 header, this + * value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported + * and enabled for TCP traffic only, then the values of + * tuple_extract_op corresponding to 4-tuples are only valid for TCP + * traffic */ - #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f) - #define VEE_FLUSH_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80) + #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_SFT 7 /* - * VEE Flush Completion: - * This completion is inserted manually by the Primate and processed - * by the VEE hardware to ensure that all completions on a VEE - * function have been processed by the VEE hardware before FLR - * process is completed. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c) - #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH - /* downstream_path is 1 b */ - #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40) - /* This completion is associated with VEE Transmit */ - #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6) - /* This completion is associated with VEE Receive */ - #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6) - #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX + uint16_t agg_id; /* - * This is an opaque value that is passed through the completion - * to the VEE handler SW and is used to indicate what VEE VQ or - * function has completed FLR processing. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - uint32_t opaque; - uint32_t v; + #define RX_TPA_START_V3_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V3_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V3_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V3_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_LAST \ + RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V3_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes will - * write 1. The odd passes will write 0. + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. */ - #define VEE_FLUSH_V UINT32_C(0x1) - /* unused3 is 32 b */ - uint32_t unused_3; + uint32_t rss_hash; } __rte_packed; -/* eject_cmpl (size:128b/16B) */ -struct eject_cmpl { - uint16_t type; +/* + * Last 16 bytes of RX L2 TPA Start V3 Completion Record + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_start_v3_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v3_cmpl_hi { + uint32_t flags2; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. */ - #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define EJECT_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * Statistics Ejection Completion: - * Completion of statistics data ejection buffer. - * Length = 16B + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. */ - #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) - #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT - #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define EJECT_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. */ - #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This is the length of the statistics data stored in this - * buffer. + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. */ - uint16_t len; + #define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * This is a copy of the opaque field from the RX BD this ejection - * buffer corresponds to. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - uint32_t opaque; - uint16_t v; + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE \ + UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 10) + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_LAST \ + RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x800) + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define EJECT_CMPL_V UINT32_C(0x1) - #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define EJECT_CMPL_ERRORS_SFT 1 + #define RX_TPA_START_V3_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_START_V3_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_START_V3_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for statistics ejection. The statistics ejection should - * be treated as invalid + * the BDs for the packetThe packet should be treated as + * invalid. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) /* * Did Not Fit: - * Statistics did not fit into aggregation buffer provided. + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ - EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH - /* reserved16 is 16 b */ - uint16_t reserved16; - /* unused3 is 32 b */ - uint32_t unused_2; -} __rte_packed; - -/* hwrm_cmpl (size:128b/16B) */ -struct hwrm_cmpl { - uint16_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * HWRM Command Completion: - * Completion of an HWRM command. + * This is data from the CFA block as indicated by the meta_format + * field. */ - #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) - #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE - /* This is the sequence_id of the HWRM command that has completed. */ - uint16_t sequence_id; - /* unused2 is 32 b */ - uint32_t unused_1; - uint32_t v; + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V3_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V3_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V3_CMPL_METADATA0_PRI_SFT 13 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. + * + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. */ - #define HWRM_CMPL_V UINT32_C(0x1) - /* unused4 is 32 b */ - uint32_t unused_3; + uint32_t hdr_offsets; } __rte_packed; -/* hwrm_fwd_req_cmpl (size:128b/16B) */ -struct hwrm_fwd_req_cmpl { +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl (size:128b/16B) */ +struct rx_tpa_end_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -5868,408 +7864,265 @@ struct hwrm_fwd_req_cmpl { * records. Odd values indicate 32B * records. */ - uint16_t req_len_type; + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B */ - #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Request */ - #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) - #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ - HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ - /* Length of forwarded request in bytes. */ - #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) - #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_END_CMPL_TYPE_LAST \ + RX_TPA_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 /* - * Source ID of this request. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. */ - uint16_t source_id; - /* unused1 is 32 b */ - uint32_t unused0; - /* Address of forwarded request. */ - uint32_t req_buf_addr_v[2]; + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 -} __rte_packed; - -/* hwrm_fwd_resp_cmpl (size:128b/16B) */ -struct hwrm_fwd_resp_cmpl { - uint16_t type; + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Response */ - #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) - #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ - HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * Source ID of this response. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. */ - uint16_t source_id; - /* Length of forwarded response in bytes. */ - uint16_t resp_len; - /* unused2 is 16 b */ - uint16_t unused_1; - /* Address of forwarded request. */ - uint32_t resp_buf_addr_v[2]; + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 -} __rte_packed; - -/* hwrm_async_event_cmpl (size:128b/16B) */ -struct hwrm_async_event_cmpl { - uint16_t type; + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ - UINT32_C(0x0) - /* Link MTU changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \ - UINT32_C(0x1) - /* Link speed changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \ - UINT32_C(0x2) - /* DCB Configuration changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \ - UINT32_C(0x3) - /* Port connection not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \ - UINT32_C(0x4) - /* Link speed configuration was not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ - UINT32_C(0x5) - /* Link speed configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \ - UINT32_C(0x6) - /* Port PHY configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \ - UINT32_C(0x7) - /* Reset notification to clients */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \ - UINT32_C(0x8) - /* Master function selection event */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \ - UINT32_C(0x9) - /* Function driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \ - UINT32_C(0x10) - /* Function driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \ - UINT32_C(0x11) - /* Function FLR related processing has completed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \ - UINT32_C(0x12) - /* PF driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \ - UINT32_C(0x20) - /* PF driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \ - UINT32_C(0x21) - /* VF Function Level Reset (FLR) */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \ - UINT32_C(0x30) - /* VF MAC Address Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \ - UINT32_C(0x31) - /* PF-VF communication channel status change. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ - UINT32_C(0x32) - /* VF Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \ - UINT32_C(0x33) - /* LLFC/PFC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \ - UINT32_C(0x34) - /* Default VNIC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \ - UINT32_C(0x35) - /* HW flow aged */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \ - UINT32_C(0x36) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) /* - * A debug notification being posted to the driver. These - * notifications are purely for diagnostic purpose and should not be - * used for functional purpose. The driver is not supposed to act - * on these messages except to log/record it. + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \ - UINT32_C(0x37) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* When set, this bit indicates that the timestamp field is valid. */ + #define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID UINT32_C(0x400) /* - * An EEM flow cached memory flush for all flows request event being - * posted to the PF driver. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \ - UINT32_C(0x38) + #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* - * An EEM flow cache memory flush completion event being posted to the - * firmware by the PF driver. This is indication that host EEM flush - * has completed by the PF. + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \ - UINT32_C(0x39) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 /* - * A tcp flag action change event being posted to the PF or trusted VF - * driver by the firmware. The PF or trusted VF driver should query - * the firmware for the new TCP flag action update after receiving - * this async event. + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ - UINT32_C(0x3a) + uint16_t len; /* - * An EEM flow active event being posted to the PF or trusted VF driver - * by the firmware. The PF or trusted VF driver should update the - * flow's aging timer after receiving this async event. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \ - UINT32_C(0x3b) + uint32_t opaque; /* - * A eem cfg change event being posted to the trusted VF driver by the - * firmware if the parent PF EEM configuration changed. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ - UINT32_C(0x3c) + uint8_t agg_bufs_v1; /* - * Deprecated. - * TFLIB unique default VNIC Configuration Change + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ - UINT32_C(0x3d) + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) /* - * Deprecated. - * TFLIB unique link status changed + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ - UINT32_C(0x3e) + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; /* - * An event signifying completion for HWRM_FW_STATE_QUIESCE - * (completion, timeout, or error) + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ - UINT32_C(0x3f) + uint8_t payload_offset; + uint8_t agg_id; + /* unused2 is 1 b */ + #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) /* - * An event signifying a HWRM command is in progress and its - * response will be deferred. This event is used on crypto controllers - * only. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ - UINT32_C(0x40) + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 /* - * An event signifying that a PFC WatchDog configuration - * has changed on any port / cos. + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ - UINT32_C(0x41) + uint32_t tsdelta; +} __rte_packed; + +/* + * Last 16 bytes of rx_tpa_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; /* - * A trace log message. This contains firmware trace logs string - * embedded in the asynchronous message. This is an experimental - * event, not meant for production use at this time. + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \ - UINT32_C(0xfe) - /* HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the valid when TPA completion is active. It + * indicates the length of the longest segment of the TPA operation + * for LRO mode and the length of the first segment in GRO mode. + * + * This value may be used by GRO software to re-construct the original + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used + * to indicate MSS size to the stack. */ - #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; -} __rte_packed; - -/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_status_change { - uint16_t type; + uint16_t tpa_seg_len; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The lower 16b of the timestamp of the last packet added to the + * aggregation. Only valid when flags.timestamp_valid is set. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \ - UINT32_C(0x0) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint16_t timestamp_lower; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates link status change */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \ - UINT32_C(0x1) + #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_TPA_END_CMPL_ERRORS_SFT 1 /* - * If this bit set to 0, then it indicates that the link - * was up and it went down. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \ - UINT32_C(0x0) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* - * If this bit is set to 1, then it indicates that the link - * was down and it went up. + * This error occurs when there is a fatal HW problem in + * the chip only. It indicates that there were not + * BDs on chip but that there was adequate reservation. + * provided by the TPA block. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP - /* Indicates the physical port this link status change occur */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \ - UINT32_C(0xe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \ - 1 - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff0) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 4 - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0xff00000) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ - 20 -} __rte_packed; - -/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_mtu_change { - uint16_t type; + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This error occurs when TPA block was not configured to + * reserve adequate BDs for TPA operations on this RX + * ring. All data for the TPA operation was not placed. + * + * This error can also be generated when the number of + * segments is not programmed correctly in TPA and the + * 33 total aggregation buffers allowed for the TPA + * operation has been exceeded. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link MTU changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + (UINT32_C(0x4) << 1) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The upper 16b of the timestamp of the last packet added to the + * aggregation. Only valid when flags.timestamp_valid is set. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* The new MTU of the link in bytes. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 + uint16_t timestamp_upper; + /* + * This is the opaque value that was completed for the TPA start + * completion that corresponds to this TPA end completion. + */ + uint32_t start_opaque; } __rte_packed; -/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_change { - uint16_t type; +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_start_cmpl (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -6277,877 +8130,385 @@ struct hwrm_async_event_cmpl_link_speed_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ + #define RX_TPA_V2_START_CMPL_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * RX L2 TPA Start Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; + #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ + UINT32_C(0x13) + #define RX_TPA_V2_START_CMPL_TYPE_LAST \ + RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * When this bit is '1', the link was forced to the - * force_link_speed value. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \ - UINT32_C(0x1) - /* The new link speed in 100 Mbps units. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \ - UINT32_C(0xfffe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \ - 1 - /* 100Mb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \ - (UINT32_C(0x1) << 1) - /* 1Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \ - (UINT32_C(0xa) << 1) - /* 2Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \ - (UINT32_C(0x14) << 1) - /* 25Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \ - (UINT32_C(0x19) << 1) - /* 10Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \ - (UINT32_C(0x64) << 1) - /* 20Mb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \ - (UINT32_C(0xc8) << 1) - /* 25Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \ - (UINT32_C(0xfa) << 1) - /* 40Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \ - (UINT32_C(0x190) << 1) - /* 50Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \ - (UINT32_C(0x1f4) << 1) - /* 100Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \ - (UINT32_C(0x3e8) << 1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff0000) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 16 -} __rte_packed; - -/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_dcb_config_change { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* DCB Configuration changed */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE - /* Event specific data */ - uint32_t event_data2; - /* ETS configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \ - UINT32_C(0x1) - /* PFC configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \ - UINT32_C(0x2) - /* APP configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ - UINT32_C(0x4) - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 - /* Priority recommended for RoCE traffic */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \ - 16 - /* none is 255 */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \ - (UINT32_C(0xff) << 16) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE - /* Priority recommended for L2 traffic */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \ - 24 - /* none is 255 */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \ - (UINT32_C(0xff) << 24) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE -} __rte_packed; - -/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_conn_not_allowed { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Port connection not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \ - UINT32_C(0x4) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * For devices that support timestamps, when this bit is cleared the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the 32b timestamp for + * the packet from the MAC. When this bit is set, the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ - 0 + #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ + UINT32_C(0x800) /* - * This value indicates the current port level enforcement policy - * for the optics module when there is an optical module mismatch - * and port is not connected. + * This value indicates what the inner packet determined for the + * packet was. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \ - 16 - /* No enforcement */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \ - (UINT32_C(0x0) << 16) - /* Disable Transmit side Laser. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \ - (UINT32_C(0x1) << 16) - /* Raise a warning message. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \ - (UINT32_C(0x2) << 16) - /* Power down the module. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \ - (UINT32_C(0x3) << 16) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN -} __rte_packed; - -/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * TCP Packet: + * Indicates that the packet was IP and TCP. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed configuration was not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ - UINT32_C(0x5) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ - 0 -} __rte_packed; - -/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_change { - uint16_t type; + uint16_t len; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \ - UINT32_C(0x6) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint32_t opaque; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 - /* - * If set to 1, it indicates that the supported link speeds - * configuration on the port has changed. - * If set to 0, then there is no change in supported link speeds - * configuration. - */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \ - UINT32_C(0x10000) - /* - * If set to 1, it indicates that the link speed configuration - * on the port has become illegal or invalid. - * If set to 0, then the link speed configuration on the port is - * legal or valid. - */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ - UINT32_C(0x20000) -} __rte_packed; - -/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_phy_cfg_change { - uint16_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Port PHY configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \ - UINT32_C(0x7) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 + #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 /* - * If set to 1, it indicates that the FEC - * configuration on the port has changed. - * If set to 0, then there is no change in FEC configuration. + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \ - UINT32_C(0x10000) + uint8_t rss_hash_type; /* - * If set to 1, it indicates that the EEE configuration - * on the port has changed. - * If set to 0, then there is no change in EEE configuration - * on the port. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \ - UINT32_C(0x20000) + uint16_t agg_id; /* - * If set to 1, it indicates that the pause configuration - * on the PHY has changed. - * If set to 0, then there is no change in the pause - * configuration on the PHY. + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ - UINT32_C(0x40000) + uint32_t rss_hash; } __rte_packed; -/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ -struct hwrm_async_event_cmpl_reset_notify { - uint16_t type; +/* + * Last 16 bytes of rx_tpa_v2_start_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl_hi { + uint32_t flags2; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates that the ip checksum was calculated for the + * inner packet and that the sum passed for all segments + * included in the aggregation. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notify clients of imminent reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \ - UINT32_C(0x8) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the sum passed + * for all segments included in the aggregation. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 + #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * 8-lsb timestamp (100-msec resolution) - * The Minimum time required for the Firmware readiness after sending this - * notification to the driver instances. + * This indicates that the ip checksum was calculated for the + * tunnel header and that the sum passed for all segments + * included in the aggregation. */ - uint8_t timestamp_lo; + #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * 16-lsb timestamp (100-msec resolution) - * The Maximum Firmware Reset bail out value in the order of 100 - * milli seconds. The driver instances will use this value to re-initiate the - * registration process again if the core firmware didn’t set the ready - * state bit. + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the sum passed for + * all segments included in the aggregation. */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates driver action requested */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \ - 0 + #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata informtaion. Value is zero. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * If set to 1, it indicates that the l2 client should - * stop sending in band traffic to Nitro. - * if set to 0, there is no change in L2 client behavior. + * The metadata field contains the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. + * - metadata[31:16] contains the vlan TPID value. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \ - UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + (UINT32_C(0x1) << 4) /* - * If set to 1, it indicates that the L2 client should - * bring down the interface. - * If set to 0, then there is no change in L2 client behavior. + * If ext_meta_format is equal to 1, the metadata field + * contains the lower 16b of the tunnel ID value, justified + * to LSB + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN - /* Indicates reason for reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \ - 8 - /* A management client has requested reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \ - (UINT32_C(0x1) << 8) - /* A fatal firmware exception has occurred. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \ - (UINT32_C(0x2) << 8) - /* A non-fatal firmware exception has occurred. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ - (UINT32_C(0x3) << 8) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) /* - * Minimum time before driver should attempt access - units 100ms ticks. - * Range 0-65535 + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ - UINT32_C(0xffff0000) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ - 16 -} __rte_packed; - -/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_recovery { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset, inner_l2_offset, inner_l3_offset and + * inner_l4_size. + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[17:9] contains the inner_l2_offset. + * - metadata[26:18] contains the inner_l3_offset. + * - metadata[31:27] contains the inner_l4_size. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* - * This async notification message can be used for selecting or - * deselecting master function for error recovery, - * and to communicate to all the functions whether error recovery - * was enabled/disabled. + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \ - UINT32_C(0x9) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This indicates that the complete 1's complement checksum was + * calculated for the packet. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 - /* 8-lsb timestamp (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates driver action requested */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \ - 0 + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) /* - * If set to 1, this function is selected as Master function. - * This function has responsibility to do 'chip reset' when it - * detects a fatal error. If set to 0, master function functionality - * is disabled on this function. + * The combination of this value and meta_format indicated what + * format the metadata field is. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \ - UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ + UINT32_C(0xc00) + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 /* - * If set to 1, error recovery is enabled. - * If set to 0, error recovery is disabled. + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ - UINT32_C(0x2) -} __rte_packed; - -/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_unload { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is data from the CFA block as indicated by the meta_format + * field. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Function driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \ - UINT32_C(0x10) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint32_t metadata; + /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ + #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ + #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ + #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ + #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ - 0 -} __rte_packed; - -/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_load { - uint16_t type; + #define RX_TPA_V2_START_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Function driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \ - UINT32_C(0x11) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Bad Format: + * BDs were not formatted correctly. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 -} __rte_packed; - -/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_flr_proc_cmplt { - uint16_t type; + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Flush: + * There was a bad_format error on the previous operation */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Function FLR related processing has completed */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \ - UINT32_C(0x12) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field identifies the CFA action rule that was used for this + * packet. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ - 0 -} __rte_packed; - -/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_unload { - uint16_t type; + uint16_t cfa_code; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * For devices that support timestamps this field is overridden + * with the timestamp value. When `flags.timestamp_fld_format` is + * cleared, this field contains the 32b timestamp for the packet from the + * MAC. + * + * When `flags.timestamp_fld_format` is set, this field contains the + * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size + * as defined below. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* PF driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \ - UINT32_C(0x20) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PF ID */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 - /* Indicates the physical port this pf belongs to */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x70000) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 -} __rte_packed; - -/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_load { - uint16_t type; + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* PF driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \ - UINT32_C(0x21) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PF ID */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 - /* Indicates the physical port this pf belongs to */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x70000) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 } __rte_packed; -/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_flr { - uint16_t type; +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -7155,243 +8516,264 @@ struct hwrm_async_event_cmpl_vf_flr { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ + #define RX_TPA_V2_END_CMPL_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* VF Function Level Reset (FLR) */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* VF ID */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 -} __rte_packed; - -/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_mac_addr_change { - uint16_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \ + UINT32_C(0x15) + #define RX_TPA_V2_END_CMPL_TYPE_LAST \ + RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_V2_END_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* VF MAC Address Change */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \ - UINT32_C(0x31) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* VF ID */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ - 0 -} __rte_packed; - -/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_vf_comm_status_change { - uint16_t type; + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* PF-VF communication channel status change. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ - UINT32_C(0x32) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* unused is 1 b */ + #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 + /* + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint32_t opaque; + uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; + #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; /* - * If this bit is set to 1, then it indicates that the PF-VF - * communication was lost and it is established. - * If this bit set to 0, then it indicates that the PF-VF - * communication was established and it is lost. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ - UINT32_C(0x1) + uint16_t agg_id; + /* + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. + */ + uint32_t tsdelta; } __rte_packed; -/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_cfg_change { - uint16_t type; +/* + * Last 16 bytes of rx_tpa_v2_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl_hi { /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* VF Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \ - UINT32_C(0x33) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint16_t tpa_dup_acks; + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 + /* + * This value indicated the offset in bytes from the beginning of + * the packet where the inner payload starts. This value is valid + * for TCP, UDP, FCoE and RoCE packets + */ + uint8_t payload_offset; + /* + * The value is the total number of aggregation buffers that were + * used in the TPA operation. All TPA aggregation buffer completions + * precede the TPA End completion. If the value is zero, then the + * aggregation is completely contained in the buffer space provided + * in the aggregation start completion. + * Note that the field is simply provided as a cross check. + */ + uint8_t tpa_agg_bufs; + /* + * This value is the valid when TPA completion is active. It + * indicates the length of the longest segment of the TPA operation + * for LRO mode and the length of the first segment in GRO mode. + * + * This value may be used by GRO software to re-construct the original + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used + * to indicate MSS size to the stack. + */ + uint16_t tpa_seg_len; + uint16_t unused_1; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; + #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 /* - * Each flag provided in this field indicates a specific VF - * configuration change. At least one of these flags shall be set to 1 - * when an asynchronous event completion of this type is provided - * by the HWRM. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - uint32_t event_data1; + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * If this bit is set to 1, then the value of MTU - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * This error occurs when there is a fatal HW problem in + * the chip only. It indicates that there were not + * BDs on chip but that there was adequate reservation. + * provided by the TPA block. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \ - UINT32_C(0x1) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * If this bit is set to 1, then the value of MRU - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * Bad Format: + * BDs were not formatted correctly. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \ - UINT32_C(0x2) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * If this bit is set to 1, then the value of default MAC - * address was changed on this VF. - * If set to 0, then this bit should be ignored. + * This error occurs when TPA block was not configured to + * reserve adequate BDs for TPA operations on this RX + * ring. All data for the TPA operation was not placed. + * + * This error can also be generated when the number of + * segments is not programmed correctly in TPA and the + * 33 total aggregation buffers allowed for the TPA + * operation has been exceeded. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \ - UINT32_C(0x4) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + (UINT32_C(0x4) << 1) /* - * If this bit is set to 1, then the value of default VLAN - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * Flush: + * There was a bad_format error on the previous operation */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ - UINT32_C(0x8) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH + uint16_t unused_2; /* - * If this bit is set to 1, then the value of trusted VF enable - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * This is the opaque value that was completed for the TPA start + * completion that corresponds to this TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ - UINT32_C(0x10) + uint32_t start_opaque; } __rte_packed; -/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_llfc_pfc_change { +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ +struct rx_tpa_v2_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7400,77 +8782,48 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* unused1 is 10 b */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \ - UINT32_C(0xffc0) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6 - /* Identifiers of events. */ - uint16_t event_id; - /* LLFC/PFC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \ - UINT32_C(0x34) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + /* + * RX TPA Aggregation Buffer completion: + * Completion of an L2 aggregation buffer in support of + * TPA packet completion. Length = 16B + */ + #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) + #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ + RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates llfc pfc status change */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \ - 0 - /* - * If this field set to 1, then it indicates that llfc is - * enabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \ - UINT32_C(0x1) + #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) /* - * If this field is set to 2, then it indicates that pfc - * is enabled. + * This is the aggregation ID that the completion is associated with. Use + * this number to correlate the TPA agg completion with the TPA start + * completion and the TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC - /* Indicates the physical port this llfc pfc change occur */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x1c) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \ - 2 - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0x1fffe0) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 5 + uint16_t agg_id; + uint32_t unused_1; } __rte_packed; -/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_default_vnic_change { +/* rx_abuf_cmpl (size:128b/16B) */ +struct rx_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7479,81 +8832,44 @@ struct hwrm_async_event_cmpl_default_vnic_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* unused1 is 10 b */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \ - UINT32_C(0xffc0) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \ - 6 - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of a default vnic allocation or free */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ - UINT32_C(0x35) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_ABUF_CMPL_TYPE_SFT 0 + /* + * RX Aggregation Buffer completion: + * Completion of an L2 aggregation buffer in support of + * TPA, HDS, or Jumbo packet completion. Length = 16B + */ + #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) + #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates default vnic configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \ - 0 - /* - * If this field is set to 1, then it indicates that - * a default VNIC has been allocate. - */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \ - UINT32_C(0x1) - /* - * If this field is set to 2, then it indicates that - * a default VNIC has been freed. - */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0x3fc) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \ - 2 - /* Indicates the virtual function this event occurred on */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \ - UINT32_C(0x3fffc00) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ - 10 + #define RX_ABUF_CMPL_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_2; } __rte_packed; -/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ -struct hwrm_async_event_cmpl_hw_flow_aged { - uint16_t type; +/* VEE FLUSH Completion Record (16 bytes) */ +/* vee_flush (size:128b/16B) */ +struct vee_flush { + uint32_t downstream_path_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -7561,65 +8877,43 @@ struct hwrm_async_event_cmpl_hw_flow_aged { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of a hw flow aged */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \ - UINT32_C(0x36) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f) + #define VEE_FLUSH_TYPE_SFT 0 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * VEE Flush Completion: + * This completion is inserted manually by the Primate and processed + * by the VEE hardware to ensure that all completions on a VEE + * function have been processed by the VEE hardware before FLR + * process is completed. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates flow ID this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \ - UINT32_C(0x7fffffff) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \ - 0 - /* Indicates flow direction this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \ - UINT32_C(0x80000000) + #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c) + #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH + /* downstream_path is 1 b */ + #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40) + /* This completion is associated with VEE Transmit */ + #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6) + /* This completion is associated with VEE Receive */ + #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6) + #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX /* - * If this bit set to 0, then it indicates that the aged - * event was rx flow. + * This is an opaque value that is passed through the completion + * to the VEE handler SW and is used to indicate what VEE VQ or + * function has completed FLR processing. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 31) + uint32_t opaque; + uint32_t v; /* - * If this bit is set to 1, then it indicates that the aged - * event was tx flow. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX + #define VEE_FLUSH_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_3; } __rte_packed; -/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_req { +/* eject_cmpl (size:128b/16B) */ +struct eject_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7628,46 +8922,80 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of a eem_cache_flush request */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \ - UINT32_C(0x38) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define EJECT_CMPL_TYPE_SFT 0 + /* + * Statistics Ejection Completion: + * Completion of statistics data ejection buffer. + * Length = 16B + */ + #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) + #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT + #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define EJECT_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* + * This is the length of the statistics data stored in this + * buffer. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this ejection + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; + #define EJECT_CMPL_V UINT32_C(0x1) + #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define EJECT_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for statistics ejection. The statistics ejection should + * be treated as invalid + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Statistics did not fit into aggregation buffer provided. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ + EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH + /* reserved16 is 16 b */ + uint16_t reserved16; + /* unused3 is 32 b */ + uint32_t unused_2; } __rte_packed; -/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_done { +/* hwrm_cmpl (size:128b/16B) */ +struct hwrm_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7676,55 +9004,31 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; + #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_CMPL_TYPE_SFT 0 /* - * Notification of a host eem_cache_flush has completed. This event - * is generated by the host driver. + * HWRM Command Completion: + * Completion of an HWRM command. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \ - UINT32_C(0x39) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) + #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE + /* This is the sequence_id of the HWRM command that has completed. */ + uint16_t sequence_id; + /* unused2 is 32 b */ + uint32_t unused_1; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates function ID that this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ - 0 + #define HWRM_CMPL_V UINT32_C(0x1) + /* unused4 is 32 b */ + uint32_t unused_3; } __rte_packed; -/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_tcp_flag_action_change { - uint16_t type; +/* hwrm_fwd_req_cmpl (size:128b/16B) */ +struct hwrm_fwd_req_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -7732,47 +9036,7 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of tcp flag action change */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ - UINT32_C(0x3a) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; - /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. - */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; -} __rte_packed; - -/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_flow_active { - uint16_t type; + uint16_t req_len_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -7780,98 +9044,40 @@ struct hwrm_async_event_cmpl_eem_flow_active { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of an active eem flow */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \ - UINT32_C(0x3b) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE - /* Event specific data */ - uint32_t event_data2; - /* Indicates the 2nd global id this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \ - 0 + #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Request */ + #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) + #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ + HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ + /* Length of forwarded request in bytes. */ + #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) + #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 /* - * Indicates flow direction of the flow identified by - * the global_id_2. + * Source ID of this request. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \ - UINT32_C(0x40000000) - /* If this bit is set to 0, then it indicates that this rx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 30) - /* If this bit is set to 1, then it indicates that this tx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 30) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX - uint8_t opaque_v; + uint16_t source_id; + /* unused1 is 32 b */ + uint32_t unused0; + /* Address of forwarded request. */ + uint32_t req_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates the 1st global id this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \ - 0 - /* - * Indicates flow direction of the flow identified by the - * global_id_1. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \ - UINT32_C(0x40000000) - /* If this bit is set to 0, then it indicates that this is rx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 30) - /* If this bit is set to 1, then it indicates that this is tx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 30) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX - /* - * Indicates EEM flow aging mode this event occurred on. If - * this bit is set to 0, the event_data1 is the EEM global - * ID. If this bit is set to 1, the event_data1 is the number - * of global ID in the context memory. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \ - UINT32_C(0x80000000) - /* EEM flow aging mode 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \ - (UINT32_C(0x0) << 31) - /* EEM flow aging mode 1. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \ - (UINT32_C(0x1) << 31) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 + #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 } __rte_packed; -/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cfg_change { +/* hwrm_fwd_resp_cmpl (size:128b/16B) */ +struct hwrm_fwd_resp_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7880,55 +9086,39 @@ struct hwrm_async_event_cmpl_eem_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Notification of EEM configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \ - UINT32_C(0x3c) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Response */ + #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) + #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ + HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + /* + * Source ID of this response. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t source_id; + /* Length of forwarded response in bytes. */ + uint16_t resp_len; + /* unused2 is 16 b */ + uint16_t unused_1; + /* Address of forwarded request. */ + uint32_t resp_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* - * Value of 1 to indicate EEM TX configuration is enabled. Value of - * 0 to indicate the EEM TX configuration is disabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \ - UINT32_C(0x1) - /* - * Value of 1 to indicate EEM RX configuration is enabled. Value of 0 - * to indicate the EEM RX configuration is disabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ - UINT32_C(0x2) + #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 } __rte_packed; -/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_quiesce_done { +/* hwrm_async_event_cmpl (size:128b/16B) */ +struct hwrm_async_event_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -7937,162 +9127,230 @@ struct hwrm_async_event_cmpl_quiesce_done { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE - /* Event specific data */ - uint32_t event_data2; - /* Status of HWRM_FW_STATE_QUIESCE completion */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ - 0 + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ + UINT32_C(0x0) + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \ + UINT32_C(0x1) + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \ + UINT32_C(0x2) + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \ + UINT32_C(0x3) + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \ + UINT32_C(0x4) + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ + UINT32_C(0x5) + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \ + UINT32_C(0x6) + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \ + UINT32_C(0x7) + /* Reset notification to clients */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) + /* Master function selection event */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \ + UINT32_C(0x9) /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE - * completed successfully. + * An event signifying that a ring has been disabled by + * hw due to error. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ - UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \ + UINT32_C(0xa) + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \ + UINT32_C(0x10) + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \ + UINT32_C(0x11) + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \ + UINT32_C(0x12) + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \ + UINT32_C(0x20) + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \ + UINT32_C(0x21) + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \ + UINT32_C(0x30) + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \ + UINT32_C(0x31) + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ + UINT32_C(0x32) + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \ + UINT32_C(0x33) + /* LLFC/PFC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \ + UINT32_C(0x34) + /* Default VNIC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \ + UINT32_C(0x35) + /* HW flow aged */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \ + UINT32_C(0x36) /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed - * out. + * A debug notification being posted to the driver. These + * notifications are purely for diagnostic purpose and should not be + * used for functional purpose. The driver is not supposed to act + * on these messages except to log/record it. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \ + UINT32_C(0x37) /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE - * encountered an error. + * An EEM flow cached memory flush for all flows request event being + * posted to the PF driver. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR - /* opaque is 8 b */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ - 8 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \ + UINT32_C(0x38) /* - * Additional information about internal hardware state related to - * idle/quiesce state. QUIESCE may succeed per quiesce_status - * regardless of idle_state_flags. If QUIESCE fails, the host may - * inspect idle_state_flags to determine whether a retry is warranted. + * An EEM flow cache memory flush completion event being posted to the + * firmware by the PF driver. This is indication that host EEM flush + * has completed by the PF. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ - 16 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \ + UINT32_C(0x39) /* - * Failure to quiesce is caused by host not updating the NQ consumer - * index. + * A tcp flag action change event being posted to the PF or trusted VF + * driver by the firmware. The PF or trusted VF driver should query + * the firmware for the new TCP flag action update after receiving + * this async event. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ - UINT32_C(0x10000) - /* Flag 1 indicating partial non-idle state. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ - UINT32_C(0x20000) - /* Flag 2 indicating partial non-idle state. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ - UINT32_C(0x40000) - /* Flag 3 indicating partial non-idle state. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ - UINT32_C(0x80000) - uint8_t opaque_v; + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ + UINT32_C(0x3a) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * An EEM flow active event being posted to the PF or trusted VF driver + * by the firmware. The PF or trusted VF driver should update the + * flow's aging timer after receiving this async event. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Time stamp for error event */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ - UINT32_C(0x1) -} __rte_packed; - -/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ -struct hwrm_async_event_cmpl_deferred_response { - uint16_t type; + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \ + UINT32_C(0x3b) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * A eem cfg change event being posted to the trusted VF driver by the + * firmware if the parent PF EEM configuration changed. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ + UINT32_C(0x3c) + /* + * Deprecated. + * TFLIB unique default VNIC Configuration Change + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ + UINT32_C(0x3d) + /* + * Deprecated. + * TFLIB unique link status changed + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ + UINT32_C(0x3e) + /* + * An event signifying completion for HWRM_FW_STATE_QUIESCE + * (completion, timeout, or error) + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; /* * An event signifying a HWRM command is in progress and its - * response will be deferred + * response will be deferred. This event is used on crypto controllers + * only. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ UINT32_C(0x40) - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE - /* Event specific data */ - uint32_t event_data2; /* - * The PF's mailbox is clear to issue another command. - * A command with this seq_id is still in progress - * and will return a regular HWRM completion when done. - * 'event_data1' field, if non-zero, contains the estimated - * execution time for the command. + * An event signifying that a PFC WatchDog configuration + * has changed on any port / cos. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + /* + * An echo request from the firmware. An echo response is expected by + * the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + /* + * An event from firmware indicating who has been selected as the + * PHC Master or secondary. Also indicates the last time a failover + * happens. Event will also be sent when PHC rolls over. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE \ + UINT32_C(0x43) + /* + * An event from firmware showing the last PPS timestamp that has been + * latched. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + /* + * An event from firmware indicating that an error has occurred. + * The driver should log the event so that an administrator can be + * aware that a problem has occurred that may need attention. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + /* + * An event from firmware indicating that the programmed pacing + * threshold for the doorbell global FIFO has been crossed. The driver + * needs to take appropriate action to pace the doorbells when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \ + UINT32_C(0x46) + /* Maximum Registrable event id. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ + UINT32_C(0x47) + /* + * A trace log message. This contains firmware trace logs string + * embedded in the asynchronous message. This is an experimental + * event, not meant for production use at this time. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \ + UINT32_C(0xfe) + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR + /* Event specific data */ + uint32_t event_data2; uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; - /* Estimated remaining time of command execution in ms (if not zero) */ + /* Event specific data */ uint32_t event_data1; } __rte_packed; -/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { +/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_status_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -8101,22 +9359,21 @@ struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* PFC watchdog configuration change for given port/cos */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ - UINT32_C(0x41) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \ + UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -8125,59 +9382,54 @@ struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; + /* Indicates link status change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \ + UINT32_C(0x1) /* - * 1 in bit position X indicates PFC watchdog should - * be on for COSX + * If this bit set to 0, then it indicates that the link + * was up and it went down. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ - 0 - /* 1 means PFC WD for COS0 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \ + UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates that the link + * was down and it went up. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \ UINT32_C(0x1) - /* 1 means PFC WD for COS1 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ - UINT32_C(0x2) - /* 1 means PFC WD for COS2 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ - UINT32_C(0x4) - /* 1 means PFC WD for COS3 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ - UINT32_C(0x8) - /* 1 means PFC WD for COS4 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ - UINT32_C(0x10) - /* 1 means PFC WD for COS5 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ - UINT32_C(0x20) - /* 1 means PFC WD for COS6 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ - UINT32_C(0x40) - /* 1 means PFC WD for COS7 is on, 0 - off. */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP + /* Indicates the physical port this link status change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \ + UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \ + 1 /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff00) - #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 8 + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 4 + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0xff00000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ + 20 } __rte_packed; -/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ -struct hwrm_async_event_cmpl_fw_trace_msg { +/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_mtu_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -8186,105 +9438,48 @@ struct hwrm_async_event_cmpl_fw_trace_msg { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Firmware trace log message */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG - /* Trace byte 0 to 3 */ + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE + /* Event specific data */ uint32_t event_data2; - /* Trace byte0 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0 - /* Trace byte1 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8 - /* Trace byte2 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16 - /* Trace byte3 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1 - /* Trace flags */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; - /* Indicates if the string is partial or complete. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \ - UINT32_C(0x1) - /* Complete string */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \ - UINT32_C(0x0) - /* Partial string */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL - /* Indicates the firmware that sent the trace message. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \ - UINT32_C(0x2) - /* Primary firmware */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \ - (UINT32_C(0x0) << 1) - /* Secondary firmware */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \ - (UINT32_C(0x1) << 1) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY - /* Trace byte 4 to 5 */ + /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; - /* Trace byte4 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0 - /* Trace byte5 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8 - /* Trace byte 6 to 9 */ + /* Event specific data */ uint32_t event_data1; - /* Trace byte6 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0 - /* Trace byte7 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8 - /* Trace byte8 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16 - /* Trace byte9 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 + /* The new MTU of the link in bytes. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 } __rte_packed; -/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ -struct hwrm_async_event_cmpl_hwrm_error { +/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -8293,2294 +9488,3491 @@ struct hwrm_async_event_cmpl_hwrm_error { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE /* Event specific data */ uint32_t event_data2; - /* Severity of HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 - /* Warning */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \ - UINT32_C(0x0) - /* Non-fatal Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \ - UINT32_C(0x1) - /* Fatal Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Time stamp for error event */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ - UINT32_C(0x1) -} __rte_packed; - -/******************* - * hwrm_func_reset * - *******************/ - - -/* hwrm_func_reset_input (size:192b/24B) */ -struct hwrm_func_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * When this bit is '1', the link was forced to the + * force_link_speed value. */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \ + UINT32_C(0x1) + /* The new link speed in 100 Mbps units. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \ + UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \ + 1 + /* 100Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \ + (UINT32_C(0x1) << 1) + /* 1Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \ + (UINT32_C(0xa) << 1) + /* 2Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \ + (UINT32_C(0x14) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \ + (UINT32_C(0x19) << 1) + /* 10Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \ + (UINT32_C(0x64) << 1) + /* 20Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \ + (UINT32_C(0xc8) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \ + (UINT32_C(0xfa) << 1) + /* 40Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \ + (UINT32_C(0x190) << 1) + /* 50Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \ + (UINT32_C(0x1f4) << 1) + /* 100Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \ + (UINT32_C(0x3e8) << 1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 16 +} __rte_packed; + +/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_dcb_config_change { + uint16_t type; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE + /* Event specific data */ + uint32_t event_data2; + /* ETS configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \ + UINT32_C(0x1) + /* PFC configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \ + UINT32_C(0x2) + /* APP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ + UINT32_C(0x4) + /* DSCP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \ + UINT32_C(0x8) + uint8_t opaque_v; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 + /* Priority recommended for RoCE traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \ + 16 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \ + (UINT32_C(0xff) << 16) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE + /* Priority recommended for L2 traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \ + 24 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \ + (UINT32_C(0xff) << 24) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE +} __rte_packed; + +/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_conn_not_allowed { + uint16_t type; /* - * This bit must be '1' for the vf_id_valid field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The ID of the VF that this PF is trying to reset. - * Only the parent PF shall be allowed to reset a child VF. - * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t vf_id; - /* This value indicates the level of a function reset. */ - uint8_t func_reset_level; + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * Reset the caller function and its children VFs (if any). If no - * children functions exist, then reset the caller function only. + * This value indicates the current port level enforcement policy + * for the optics module when there is an optical module mismatch + * and port is not connected. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ - UINT32_C(0x0) - /* Reset the caller function only */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \ + 16 + /* No enforcement */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \ + (UINT32_C(0x0) << 16) + /* Disable Transmit side Laser. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \ + (UINT32_C(0x1) << 16) + /* Raise a warning message. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \ + (UINT32_C(0x2) << 16) + /* Power down the module. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \ + (UINT32_C(0x3) << 16) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN +} __rte_packed; + +/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { + uint16_t type; /* - * Reset all children VFs of the caller function driver if the - * caller is a PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver with - * no children VFs. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * Reset a specific VF of the caller function driver if the caller - * is the parent PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver that is not - * the parent of the VF that is being requested to reset. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ - UINT32_C(0x3) - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ - HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF - uint8_t unused_0; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 } __rte_packed; -/* hwrm_func_reset_output (size:128b/16B) */ -struct hwrm_func_reset_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_change { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __rte_packed; - -/******************** - * hwrm_func_getfid * - ********************/ - - -/* hwrm_func_getfid_input (size:192b/24B) */ -struct hwrm_func_getfid_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \ + UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If set to 1, it indicates that the supported link speeds + * configuration on the port has changed. + * If set to 0, then there is no change in supported link speeds + * configuration. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \ + UINT32_C(0x10000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If set to 1, it indicates that the link speed configuration + * on the port has become illegal or invalid. + * If set to 0, then the link speed configuration on the port is + * legal or valid. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ + UINT32_C(0x20000) +} __rte_packed; + +/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_phy_cfg_change { + uint16_t type; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \ + UINT32_C(0x7) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the pci_id field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * This value is the PCI ID of the queried function. - * If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (5b):Function Number(3b). + * If set to 1, it indicates that the FEC + * configuration on the port has changed. + * If set to 0, then there is no change in FEC configuration. */ - uint16_t pci_id; - uint8_t unused_0[2]; -} __rte_packed; - -/* hwrm_func_getfid_output (size:128b/16B) */ -struct hwrm_func_getfid_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \ + UINT32_C(0x10000) /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * If set to 1, it indicates that the EEE configuration + * on the port has changed. + * If set to 0, then there is no change in EEE configuration + * on the port. */ - uint16_t fid; - uint8_t unused_0[5]; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \ + UINT32_C(0x20000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If set to 1, it indicates that the pause configuration + * on the PHY has changed. + * If set to 0, then there is no change in the pause + * configuration on the PHY. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ + UINT32_C(0x40000) } __rte_packed; -/********************** - * hwrm_func_vf_alloc * - **********************/ - - -/* hwrm_func_vf_alloc_input (size:192b/24B) */ -struct hwrm_func_vf_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ +struct hwrm_async_event_cmpl_reset_notify { + uint16_t type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the first_vf_id field to be - * configured. - */ - #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) - /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t first_vf_id; - /* The number of virtual functions requested. */ - uint16_t num_vfs; -} __rte_packed; - -/* hwrm_func_vf_alloc_output (size:128b/16B) */ -struct hwrm_func_vf_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The ID of the first VF allocated. */ - uint16_t first_vf_id; - uint8_t unused_0[5]; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notify clients of imminent reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY + /* Event specific data. The data is for internal debug use only. */ + uint32_t event_data2; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * These bits indicate the status as being reported by the firmware. + * This value is exactly the same as status code in fw_status register. + * If the status code is equal to 0x8000, then the reset is initiated + * by the Host using the FW_RESET command when the FW is in a healthy + * state. If the status code is not equal to 0x8000, then the reset is + * initiated by the FW to recover from the error or FATAL state. */ - uint8_t valid; -} __rte_packed; - -/********************* - * hwrm_func_vf_free * - *********************/ - - -/* hwrm_func_vf_free_input (size:192b/24B) */ -struct hwrm_func_vf_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \ + 0 + uint8_t opaque_v; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * 8-lsb timestamp (100-msec resolution) + * The Minimum time required for the Firmware readiness after sending + * this notification to the driver instances. */ - uint16_t seq_id; + uint8_t timestamp_lo; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * 16-lsb timestamp (100-msec resolution) + * The Maximum Firmware Reset bail out value in the order of 100 + * milliseconds. The driver instances will use this value to reinitiate + * the registration process again if the core firmware didn’t set the + * state bit. */ - uint16_t target_id; + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates driver action requested */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \ + 0 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1, it indicates that the l2 client should + * stop sending in band traffic to Nitro. + * if set to 0, there is no change in L2 client behavior. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \ + UINT32_C(0x1) /* - * This bit must be '1' for the first_vf_id field to be - * configured. + * If set to 1, it indicates that the L2 client should + * bring down the interface. + * If set to 0, then there is no change in L2 client behavior. */ - #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN + /* Indicates reason for reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \ + 8 + /* A management client has requested reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \ + (UINT32_C(0x1) << 8) + /* A fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \ + (UINT32_C(0x2) << 8) + /* A non-fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ + (UINT32_C(0x3) << 8) + /* Fast reset */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ + (UINT32_C(0x4) << 8) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. */ - uint16_t first_vf_id; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* - * The number of virtual functions requested. - * 0xFFFF - Cleanup all children of this PF. + * Minimum time before driver should attempt access - units 100ms + * ticks. + * Range 0-65535 */ - uint16_t num_vfs; + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ + 16 } __rte_packed; -/* hwrm_func_vf_free_output (size:128b/16B) */ -struct hwrm_func_vf_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_recovery { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __rte_packed; - -/******************** - * hwrm_func_vf_cfg * - ********************/ - - -/* hwrm_func_vf_cfg_input (size:448b/56B) */ -struct hwrm_func_vf_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This async notification message can be used for selecting or + * deselecting master function for error recovery, + * and to communicate to all the functions whether error recovery + * was enabled/disabled. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \ + UINT32_C(0x9) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates driver action requested */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \ + 0 /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If set to 1, this function is selected as Master function. + * This function has responsibility to do 'chip reset' when it + * detects a fatal error. If set to 0, master function functionality + * is disabled on this function. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \ + UINT32_C(0x1) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1, error recovery is enabled. + * If set to 0, error recovery is disabled. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ + UINT32_C(0x2) +} __rte_packed; + +/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ +struct hwrm_async_event_cmpl_ring_monitor_msg { + uint16_t type; /* - * This bit must be '1' for the mtu field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Ring Monitor Message. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \ + UINT32_C(0xa) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG + /* Event specific data */ + uint32_t event_data2; + /* Type of Ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \ + 0 + /* tx ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \ + UINT32_C(0x0) + /* rx ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \ UINT32_C(0x1) - /* - * This bit must be '1' for the guest_vlan field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ + /* cmpl ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \ UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL + uint8_t opaque_v; /* - * This bit must be '1' for the async_event_cr field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ - UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. + * Event specific data. If ring_type_disabled indicates a tx, rx or cmpl + * then this field will indicate the ring id. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ - UINT32_C(0x8) + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_unload { + uint16_t type; /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \ UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the num_cmpl_rings field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ - UINT32_C(0x20) - /* - * This bit must be '1' for the num_tx_rings field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ - UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_load { + uint16_t type; /* - * This bit must be '1' for the num_rx_rings field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \ + UINT32_C(0x11) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ - UINT32_C(0x100) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_flr_proc_cmplt { + uint16_t type; /* - * This bit must be '1' for the num_vnics field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ - UINT32_C(0x200) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \ + UINT32_C(0x12) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ - UINT32_C(0x400) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_unload { + uint16_t type; /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x800) - /* - * The maximum transmission unit requested on the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to requesting mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. - */ - uint16_t mtu; - /* - * The guest VLAN for the function being configured. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). - */ - uint16_t guest_vlan; - /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. - */ - uint16_t async_event_cr; - /* - * This value is the current MAC address requested by the VF - * driver to be configured on this VF. A value of - * 00-00-00-00-00-00 indicates no MAC address configuration - * is requested by the VF driver. - * The parent PF driver may reject or overwrite this - * MAC address. - */ - uint8_t dflt_mac_addr[6]; - uint32_t flags; - /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. - */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ - UINT32_C(0x1) - /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. - */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \ + UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ - UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 +} __rte_packed; + +/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_load { + uint16_t type; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ - UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \ + UINT32_C(0x21) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ - UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 +} __rte_packed; + +/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_flr { + uint16_t type; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ - UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ - UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 +} __rte_packed; + +/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_mac_addr_change { + uint16_t type; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \ + UINT32_C(0x31) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If this bit is set to 1, the VF driver is requesting FW to enable - * PPP TX PUSH feature on all the TX rings specified in the - * num_tx_rings field. By default, the PPP TX push feature is - * disabled for all the TX rings of the VF. This flag is ignored if - * the num_tx_rings field is not specified or the VF doesn't support - * PPP tx push feature. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ - UINT32_C(0x100) - /* The number of RSS/COS contexts requested for the VF. */ - uint16_t num_rsscos_ctxs; - /* The number of completion rings requested for the VF. */ - uint16_t num_cmpl_rings; - /* The number of transmit rings requested for the VF. */ - uint16_t num_tx_rings; - /* The number of receive rings requested for the VF. */ - uint16_t num_rx_rings; - /* The number of L2 contexts requested for the VF. */ - uint16_t num_l2_ctxs; - /* The number of vnics requested for the VF. */ - uint16_t num_vnics; - /* The number of statistic contexts requested for the VF. */ - uint16_t num_stat_ctxs; - /* The number of HW ring groups requested for the VF. */ - uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ + 0 } __rte_packed; -/* hwrm_func_vf_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_vf_comm_status_change { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __rte_packed; - -/******************* - * hwrm_func_qcaps * - *******************/ - - -/* hwrm_func_qcaps_input (size:192b/24B) */ -struct hwrm_func_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ + UINT32_C(0x32) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If this bit is set to 1, then it indicates that the PF-VF + * communication was lost and it is established. + * If this bit set to 0, then it indicates that the PF-VF + * communication was established and it is lost. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_cfg_change { + uint16_t type; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \ + UINT32_C(0x33) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value indicates the VF ID of the VF whose configuration + * is changing if this async. event is sent to the parent PF. + * The firmware supports sending this to the parent PF if the + * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1. + * This value is undefined when the async. event is sent to the + * VF. */ - uint64_t resp_addr; + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 + uint8_t opaque_v; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. - * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID - * to be used by a trusted VF to query its parent PF. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_qcaps_output (size:704b/88B) */ -struct hwrm_func_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * Each flag provided in this field indicates a specific VF + * configuration change. At least one of these flags shall be set to 1 + * when an asynchronous event completion of this type is provided + * by the HWRM. */ - uint16_t fid; + uint32_t event_data1; /* - * Port ID of port that this function is associated with. - * Valid only for the PF. - * 0xFF... (All Fs) if this function is not associated with - * any port. - * 0xFF... (All Fs) if this function is called from a VF. + * If this bit is set to 1, then the value of MTU + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - uint16_t port_id; - uint32_t flags; - /* If 1, then Push mode is supported on this function. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \ UINT32_C(0x1) /* - * If 1, then the global MSI-X auto-masking is enabled for the - * device. + * If this bit is set to 1, then the value of MRU + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \ UINT32_C(0x2) /* - * If 1, then the Precision Time Protocol (PTP) processing - * is supported on this function. - * The HWRM should enable PTP on only a single Physical - * Function (PF) per port. + * If this bit is set to 1, then the value of default MAC + * address was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \ UINT32_C(0x4) /* - * If 1, then RDMA over Converged Ethernet (RoCE) v1 - * is supported on this function. + * If this bit is set to 1, then the value of default VLAN + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ UINT32_C(0x8) /* - * If 1, then RDMA over Converged Ethernet (RoCE) v2 - * is supported on this function. + * If this bit is set to 1, then the value of trusted VF enable + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ UINT32_C(0x10) +} __rte_packed; + +/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_llfc_pfc_change { + uint16_t type; /* - * If 1, then control and configuration of WoL magic packet - * are supported on this function. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ - UINT32_C(0x20) - /* - * If 1, then control and configuration of bitmap pattern - * packet are supported on this function. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ - UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* unused1 is 10 b */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \ + UINT32_C(0xffc0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6 + /* Identifiers of events. */ + uint16_t event_id; + /* LLFC/PFC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \ + UINT32_C(0x34) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If set to 1, then the control and configuration of rate limit - * of an allocated TX ring on the queried function is supported. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates llfc pfc status change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \ + 0 /* - * If 1, then control and configuration of minimum and - * maximum bandwidths are supported on the queried function. + * If this field set to 1, then it indicates that llfc is + * enabled. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ - UINT32_C(0x100) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \ + UINT32_C(0x1) /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the rate limits - * on the TX rings of its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the rate limits - * on the TX rings of its children VFs. + * If this field is set to 2, then it indicates that pfc + * is enabled. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ - UINT32_C(0x200) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC + /* Indicates the physical port this llfc pfc change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x1c) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \ + 2 + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0x1fffe0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 5 +} __rte_packed; + +/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_default_vnic_change { + uint16_t type; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the minimum and/or - * maximum bandwidths for its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the minimum or - * maximum bandwidths for its children VFs. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ - UINT32_C(0x400) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* unused1 is 10 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \ + UINT32_C(0xffc0) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \ + 6 + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of a default vnic allocation or free */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ + UINT32_C(0x35) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is supported - * on the queried function. - * If set to 0, then standard TX ring mode is not available - * on the queried function. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ - UINT32_C(0x800) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates default vnic configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \ + 0 /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GENEVE tunnel - * flags. + * If this field is set to 1, then it indicates that + * a default VNIC has been allocate. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x1000) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \ + UINT32_C(0x1) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect NVGRE tunnel - * flags. + * If this field is set to 2, then it indicates that + * a default VNIC has been freed. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x2000) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0x3fc) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \ + 2 + /* Indicates the virtual function this event occurred on */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0x3fffc00) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ + 10 +} __rte_packed; + +/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ +struct hwrm_async_event_cmpl_hw_flow_aged { + uint16_t type; /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GRE tunnel - * flags. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x4000) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of a hw flow aged */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \ + UINT32_C(0x36) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect MPLS tunnel - * flags. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x8000) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates flow ID this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \ + UINT32_C(0x7fffffff) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \ + 0 + /* Indicates flow direction this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \ + UINT32_C(0x80000000) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to support pcie stats. + * If this bit set to 0, then it indicates that the aged + * event was rx flow. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ - UINT32_C(0x10000) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 31) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to adopt the VF's belonging - * to another PF. + * If this bit is set to 1, then it indicates that the aged + * event was tx flow. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \ - UINT32_C(0x20000) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cache_flush_req { + uint16_t type; /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the administrative privilege to configure another PF + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ - UINT32_C(0x40000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of a eem_cache_flush request */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \ + UINT32_C(0x38) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then - * the PF will know that the firmware has the capability to track - * the virtual link status. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \ - UINT32_C(0x80000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cache_flush_done { + uint16_t type; /* - * If 1, then this function supports the push mode that uses - * write combine buffers and the long inline tx buffer descriptor. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \ - UINT32_C(0x100000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * If 1, then FW has capability to allocate TX rings dynamically - * in ring alloc even if PF reserved pool is zero. - * This bit will be used only for PFs. + * Notification of a host eem_cache_flush has completed. This event + * is generated by the host driver. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ - UINT32_C(0x200000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \ + UINT32_C(0x39) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * When this bit is '1', it indicates that core firmware is - * capable of Hot Reset. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \ - UINT32_C(0x400000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates function ID that this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_tcp_flag_action_change { + uint16_t type; /* - * This flag will be set to 1 by the FW if FW supports adapter error - * recovery. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \ - UINT32_C(0x800000) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of tcp flag action change */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ + UINT32_C(0x3a) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then - * the PF has the capability to support extended stats. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \ - UINT32_C(0x1000000) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_flow_active { + uint16_t type; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then host - * must initiate reset or reload (or fastboot) the firmware image - * upon detection of device shutdown state. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ - UINT32_C(0x2000000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of an active eem flow */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \ + UINT32_C(0x3b) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE + /* Event specific data */ + uint32_t event_data2; + /* Indicates the 2nd global id this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \ + 0 /* - * If the query is for a VF, then this flag (always set to 0) shall - * be ignored. If this query is for a PF and this flag is set to 1, - * host, when registered for the default vnic change async event, - * receives async notification whenever a default vnic state is - * changed for any of child or adopted VFs. + * Indicates flow direction of the flow identified by + * the global_id_2. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ - UINT32_C(0x4000000) - /* If set to 1, then the vlan acceleration for TX is disabled. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ - UINT32_C(0x8000000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \ + UINT32_C(0x40000000) + /* If this bit is set to 0, then it indicates that this rx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 30) + /* If this bit is set to 1, then it indicates that this tx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 30) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX + uint8_t opaque_v; /* - * When this bit is '1', it indicates that core firmware supports - * DBG_COREDUMP_XXX commands. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ - UINT32_C(0x10000000) - /* - * When this bit is '1', it indicates that core firmware supports - * DBG_CRASHDUMP_XXX commands. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ - UINT32_C(0x20000000) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the 1st global id this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \ + 0 /* - * If the query is for a VF, then this flag should be ignored. - * If the query is for a PF and this flag is set to 1, then - * the PF has the capability to support retrieval of - * rx_port_stats_ext_pfc_wd statistics (supported by the PFC - * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. - * If this flag is set to 1, only that (supported) command should - * be used for retrieval of PFC related statistics (rather than - * hwrm_port_qstats_ext command, which could previously be used). + * Indicates flow direction of the flow identified by the + * global_id_1. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \ UINT32_C(0x40000000) + /* If this bit is set to 0, then it indicates that this is rx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 30) + /* If this bit is set to 1, then it indicates that this is tx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 30) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX /* - * When this bit is '1', it indicates that core firmware supports - * DBG_QCAPS command + * Indicates EEM flow aging mode this event occurred on. If + * this bit is set to 0, the event_data1 is the EEM global + * ID. If this bit is set to 1, the event_data1 is the number + * of global ID in the context memory. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \ UINT32_C(0x80000000) + /* EEM flow aging mode 0. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \ + (UINT32_C(0x0) << 31) + /* EEM flow aging mode 1. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \ + (UINT32_C(0x1) << 31) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cfg_change { + uint16_t type; /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t mac_address[6]; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of EEM configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \ + UINT32_C(0x3c) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The maximum number of RSS/COS contexts that can be - * allocated to the function. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t max_rsscos_ctx; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * The maximum number of completion rings that can be - * allocated to the function. + * Value of 1 to indicate EEM TX configuration is enabled. Value of + * 0 to indicate the EEM TX configuration is disabled. */ - uint16_t max_cmpl_rings; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \ + UINT32_C(0x1) /* - * The maximum number of transmit rings that can be - * allocated to the function. + * Value of 1 to indicate EEM RX configuration is enabled. Value of 0 + * to indicate the EEM RX configuration is disabled. */ - uint16_t max_tx_rings; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ + UINT32_C(0x2) +} __rte_packed; + +/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_quiesce_done { + uint16_t type; /* - * The maximum number of receive rings that can be - * allocated to the function. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t max_rx_rings; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* Event specific data */ + uint32_t event_data2; + /* Status of HWRM_FW_STATE_QUIESCE completion */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ + 0 /* - * The maximum number of L2 contexts that can be - * allocated to the function. + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * completed successfully. */ - uint16_t max_l2_ctxs; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ + UINT32_C(0x0) /* - * The maximum number of VNICs that can be - * allocated to the function. + * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed + * out. */ - uint16_t max_vnics; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + UINT32_C(0x1) /* - * The identifier for the first VF enabled on a PF. This - * is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * encountered an error. */ - uint16_t first_vf_id; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + /* opaque is 8 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ + 8 /* - * The maximum number of VFs that can be - * allocated to the function. This is valid only on the - * PF with SR-IOV enabled. 0xFF... (All Fs) if this - * command is called on a PF with SR-IOV disabled or - * on a VF. + * Additional information about internal hardware state related to + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may + * inspect idle_state_flags to determine whether a retry is warranted. */ - uint16_t max_vfs; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ + 16 /* - * The maximum number of statistic contexts that can be - * allocated to the function. + * Failure to quiesce is caused by host not updating the NQ consumer + * index. */ - uint16_t max_stat_ctx; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ + UINT32_C(0x10000) + /* Flag 1 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ + UINT32_C(0x20000) + /* Flag 2 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ + UINT32_C(0x40000) + /* Flag 3 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ + UINT32_C(0x80000) + uint8_t opaque_v; /* - * The maximum number of Encapsulation records that can be - * offloaded by this function. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint32_t max_encap_records; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ +struct hwrm_async_event_cmpl_deferred_response { + uint16_t type; /* - * The maximum number of decapsulation records that can - * be offloaded by this function. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint32_t max_decap_records; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the TX side. + * An event signifying a HWRM command is in progress and its + * response will be deferred */ - uint32_t max_tx_em_flows; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE + /* Event specific data */ + uint32_t event_data2; /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the TX side. + * The PF's mailbox is clear to issue another command. + * A command with this seq_id is still in progress + * and will return a regular HWRM completion when done. + * 'event_data1' field, if non-zero, contains the estimated + * execution time for the command. */ - uint32_t max_tx_wm_flows; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ + 0 + uint8_t opaque_v; /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the RX side. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint32_t max_rx_em_flows; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Estimated remaining time of command execution in ms (if not zero) */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { + uint16_t type; /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the RX side. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint32_t max_rx_wm_flows; + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PFC watchdog configuration change for given port/cos */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The maximum number of multicast filters that can - * be supported by this function on the RX side. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint32_t max_mcast_filters; + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * The maximum value of flow_id that can be supported - * in completion records. + * 1 in bit position X indicates PFC watchdog should + * be on for COSX */ - uint32_t max_flow_id; + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ + 0 + /* 1 means PFC WD for COS0 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + UINT32_C(0x1) + /* 1 means PFC WD for COS1 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ + UINT32_C(0x2) + /* 1 means PFC WD for COS2 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ + UINT32_C(0x4) + /* 1 means PFC WD for COS3 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ + UINT32_C(0x8) + /* 1 means PFC WD for COS4 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ + UINT32_C(0x10) + /* 1 means PFC WD for COS5 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ + UINT32_C(0x20) + /* 1 means PFC WD for COS6 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ + UINT32_C(0x40) + /* 1 means PFC WD for COS7 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ + UINT32_C(0x80) + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff00) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 8 +} __rte_packed; + +/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ +struct hwrm_async_event_cmpl_echo_request { + uint16_t type; /* - * The maximum number of HW ring groups that can be - * supported on this function. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint32_t max_hw_ring_grps; + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The maximum number of strict priority transmit rings - * that can be allocated to the function. - * This number indicates the maximum number of TX rings - * that can be assigned strict priorities out of the - * maximum number of TX rings that can be allocated - * (max_tx_rings) to the function. + * An echo request from the firmware. An echo response is expected by + * the firmware. */ - uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; - uint32_t flags_ext; + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST + /* Event specific data that should be provided in the echo response */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If 1, the device can be configured to set the ECN bits in the - * IP header of received packets if the receive queue length - * exceeds a given threshold. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data that should be provided in the echo response */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ +struct hwrm_async_event_cmpl_phc_update { + uint16_t type; /* - * If 1, the device can report the number of received packets - * that it marked as having experienced congestion. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * If 1, the device can report extended hw statistics (including - * additional tpa statistics). + * This async event is used to notify driver of changes + * in PHC master. Only one master function can configure + * PHC. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \ - UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE \ + UINT32_C(0x43) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE + /* Event specific data */ + uint32_t event_data2; + /* This field provides the current master function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT \ + 0 + /* This field provides the current secondary function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT \ + 16 + uint8_t opaque_v; /* - * If set to 1, then the core firmware has support to enable/ - * disable hot reset support for interface dynamically through - * HWRM_FUNC_CFG. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \ - UINT32_C(0x8) - /* If 1, the proxy mode is supported on this function */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \ - UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates to the driver the type of PHC event. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK \ + UINT32_C(0xf) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT \ + 0 /* - * If 1, the tx rings source interface override feature is supported - * on this function. + * Indicates PHC Master selection event. The master fid is + * specified in event_data2.phc_master_fid. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \ - UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER \ + UINT32_C(0x1) /* - * If 1, the device supports scheduler queues. SQs can be managed - * using RING_SQ_ALLOC/CFG/FREE commands. + * Indicates PHC Secondary selection event. The secondary fid is + * specified in event_data2.phc_sec_fid. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \ - UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY \ + UINT32_C(0x2) /* - * If set to 1, then this function supports the TX push mode that - * uses ping-pong buffers from the push pages. + * Indicates PHC failover event. Failover happens from + * event_data2.phc_master_fid to event_data2.phc_sec_fid. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ - UINT32_C(0x80) - /* The maximum number of SQs supported by this device. */ - uint8_t max_sqs; - uint8_t unused_1[2]; + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER \ + UINT32_C(0x3) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Indicates that the 64bit Real time clock upper 16bits + * have been updated due to PHC rollover. The updated + * upper 16bits is in event_data1.phc_time_msb */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE + /* + * This field provides the upper 16bits of the 64bit real + * time clock. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT \ + 4 } __rte_packed; -/****************** - * hwrm_func_qcfg * - ******************/ - - -/* hwrm_func_qcfg_input (size:192b/24B) */ -struct hwrm_func_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ +struct hwrm_async_event_cmpl_pps_timestamp { + uint16_t type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This async notification message can be used to inform + * driver of the latest PPS timestamp that has been latched. + * When driver enables PPS event, Firmware will generate + * PPS timestamps every second, Firmware informs driver + * of this timestamp through the async event. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP + /* Event specific data */ + uint32_t event_data2; + /* Indicates the PPS event type */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \ + UINT32_C(0x1) + /* This is an internal event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \ + UINT32_C(0x0) + /* This is an external event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Indicates the pin number on which the event is + * received. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \ + UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \ + 1 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Contains bits[47:32] of the upper PPS timestamp. + * Lower 32 bits are in event_data1. Together they + * provide the 48 bit PPS timestamp. */ - uint64_t resp_addr; + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \ + 4 + uint8_t opaque_v; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. - * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID - * to be used by a trusted VF to query its parent PF. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t fid; - uint8_t unused_0[6]; + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Contains the lower 32 bits of the PPS timestamp. */ + uint32_t event_data1; + /* Contains the lower 32 bit PPS timestamp */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \ + 0 } __rte_packed; -/* hwrm_func_qcfg_output (size:768b/96B) */ -struct hwrm_func_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. - */ - uint16_t fid; +/* hwrm_async_event_cmpl_error_report (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report { + uint16_t type; /* - * Port ID of port that this function is associated with. - * 0xFF... (All Fs) if this function is not associated with - * any port. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t port_id; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * This value is the current VLAN setting for this - * function. The value of 0 for this field indicates - * no priority tagging or VLAN is used. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - uint16_t vlan; - uint16_t flags; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If 1, then magic packet based Out-Of-Box WoL is enabled on - * the port associated with this function. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled - * on the port associated with this function. + * Indicates the type of error being reported. See section on Error + * Report event error_types for details on each error. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_doorbell_pacing_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_doorbell_pacing_threshold { + uint16_t type; /* - * If set to 1, then FW based DCBX agent is enabled and running on - * the port associated with this function. - * If set to 0, then DCBX agent is not running in the firmware. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ - UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is enabled - * on the queried function. - * If set to 0, then the standard TX ring mode is disabled - * on the queried function. In this extended TX ring resource - * mode, the minimum and maximum bandwidth settings are not - * supported to allow the allocation of TX rings to span multiple - * scheduler nodes. + * This async notification message is used to inform the driver + * that the programmable pacing threshold for the doorbell FIFO is + * reached. The driver will take appropriate action to pace the + * doorbells when this async event is received from the firmware. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ - UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD \ + UINT32_C(0x46) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; /* - * If set to 1 then FW based LLDP agent is enabled and running on - * the port associated with this function. - * If set to 0 then the LLDP agent is not running in the firmware. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ - UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ +struct hwrm_async_event_cmpl_fw_trace_msg { + uint16_t type; /* - * If set to 1, then multi-host mode is active for this function. - * If set to 0, then multi-host mode is inactive for this function - * or not applicable for this device. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ - UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Firmware trace log message */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG + /* Trace byte 0 to 3 */ + uint32_t event_data2; + /* Trace byte0 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0 + /* Trace byte1 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8 + /* Trace byte2 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16 + /* Trace byte3 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24 + uint8_t opaque_v; /* - * If the function that is being queried is a PF, then the HWRM shall - * set this field to 0 and the HWRM client shall ignore this field. - * If the function that is being queried is a VF, then the HWRM shall - * set this field to 1 if the queried VF is trusted, otherwise the HWRM - * shall set this field to 0. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ - UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1 + /* Trace flags */ + uint8_t timestamp_lo; + /* Indicates if the string is partial or complete. */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \ + UINT32_C(0x1) + /* Complete string */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \ + UINT32_C(0x0) + /* Partial string */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL + /* Indicates the firmware that sent the trace message. */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \ + UINT32_C(0x2) + /* Primary firmware */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \ + (UINT32_C(0x0) << 1) + /* Secondary firmware */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \ + (UINT32_C(0x1) << 1) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY + /* Trace byte 4 to 5 */ + uint16_t timestamp_hi; + /* Trace byte4 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0 + /* Trace byte5 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8 + /* Trace byte 6 to 9 */ + uint32_t event_data1; + /* Trace byte6 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0 + /* Trace byte7 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8 + /* Trace byte8 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16 + /* Trace byte9 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 +} __rte_packed; + +/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_hwrm_error { + uint16_t type; /* - * If set to 1, then secure mode is enabled for this function or device. - * If set to 0, then secure mode is disabled (or normal mode) for this - * function or device. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Severity of HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 + /* Warning */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \ + UINT32_C(0x0) + /* Non-fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \ + UINT32_C(0x1) + /* Fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL + uint8_t opaque_v; /* - * If set to 1, then this PF is enabled with a preboot driver that - * requires access to the legacy L2 ring model and legacy 32b - * doorbells. If set to 0, then this PF is not allowed to use - * the legacy L2 rings. This feature is not allowed on VFs and - * is only relevant for devices that require a context backing - * store. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ - UINT32_C(0x100) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_base { + uint16_t type; /* - * If set to 1, then the firmware and all currently registered driver - * instances support hot reset. The hot reset support will be updated - * dynamically based on the driver interface advertisement. - * If set to 0, then the adapter is not currently able to initiate - * hot reset. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \ - UINT32_C(0x200) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * If set to 1, then the PPP tx push mode is enabled for all the - * reserved TX rings of this function. If set to 0, then PPP tx push - * mode is disabled for all the reserved TX rings of this function. + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \ - UINT32_C(0x400) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint8_t mac_address[6]; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* Reserved */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \ + UINT32_C(0x0) /* - * This value is current PCI ID of this - * function. If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (4b):Function Number(4b). - * If multi-host mode is active, the 4 lsb will indicate - * the PF index for this function. + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. */ - uint16_t pci_id; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) /* - * The number of RSS/COS contexts currently - * allocated to the function. + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. */ - uint16_t alloc_rsscos_ctx; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) /* - * The number of completion rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. */ - uint16_t alloc_cmpl_rings; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) /* - * The number of transmit rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. */ - uint16_t alloc_tx_rings; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) /* - * The number of receive rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * Indicates the NIC's temperature has crossed one of the thermal + * thresholds. */ - uint16_t alloc_rx_rings; - /* The allocated number of L2 contexts to the function. */ - uint16_t alloc_l2_ctx; - /* The allocated number of vnics to the function. */ - uint16_t alloc_vnics; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_pause_storm { + uint16_t type; /* - * The maximum transmission unit of the function. - * If the reported mtu value is non-zero then it will used for the - * rings allocated on this function. otherwise the default - * value is used if ring MTU is not specified. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t mtu; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The maximum receive unit of the function. - * For vnics allocated on this function, this default - * value is used if vnic MRU is not specified. + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - uint16_t mru; - /* The statistics context assigned to a function. */ - uint16_t stat_ctx_id; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The HWRM shall return Unknown value for this field - * when this command is used to query VF's configuration. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint8_t port_partition_type; - /* Single physical function */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) - /* Multiple physical functions */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) - /* Network Partitioning 1.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) - /* Network Partitioning 1.5 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) - /* Network Partitioning 2.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) - /* Unknown */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \ UINT32_C(0xff) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. */ - uint8_t port_pf_cnt; - /* number of PFs is not available */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_invalid_signal { + uint16_t type; /* - * The default VNIC ID assigned to a function that is - * being queried. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t dflt_vnic_id; - uint16_t max_mtu_configured; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates the minimum bandwidth is not - * configured. + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - uint32_t min_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the TSIO pin on which invalid signal is detected. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \ + 0 + uint8_t opaque_v; /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates that the maximum bandwidth is not - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 /* - * This value indicates the Edge virtual bridge mode for the - * domain that this function belongs to. + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. */ - uint8_t evb_mode; - /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) - /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) - /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA - uint8_t options; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; /* - * This value indicates the PCIE device cache line size. - * The cache line size allows the DMA writes to terminate and - * start at the cache boundary. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ UINT32_C(0x3) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 - /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ - UINT32_C(0x0) - /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ - UINT32_C(0x1) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 - /* This value is the virtual link admin state setting. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ - UINT32_C(0xc) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 - /* Admin link state is in forced down mode. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ - (UINT32_C(0x0) << 2) - /* Admin link state is in forced up mode. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ - (UINT32_C(0x1) << 2) - /* Admin link state is in auto mode - follows the physical link state. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ - (UINT32_C(0x2) << 2) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO - /* Reserved for future. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4 + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 /* - * The number of VFs that are allocated to the function. - * This is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. */ - uint16_t alloc_vfs; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) /* - * The number of allocated multicast filters for this - * function on the RX side. + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. */ - uint32_t alloc_mcast_filters; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; /* - * The number of allocated HW ring groups for this - * function. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint32_t alloc_hw_ring_grps; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The number of strict priority transmit rings out of - * currently allocated TX rings to the function - * (alloc_tx_rings). + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - uint16_t alloc_sp_tx_rings; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The number of statistics contexts - * currently reserved for the function. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t alloc_stat_ctx; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 /* - * This field specifies how many NQs are reserved for the PF. - * Remaining NQs that belong to the PF are available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. */ - uint16_t alloc_msix; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_thermal { + uint16_t type; /* - * The number of registered VF’s associated with the PF. This field - * should be ignored when the request received on the VF interface. - * This field will be updated on the PF interface to initiate - * the unregister request on PF in the HOT Reset Process. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t registered_vfs; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The size of the doorbell BAR in KBytes reserved for L2 including - * any area that is shared between L2 and RoCE. The L2 driver - * should only map the L2 portion of the doorbell BAR. Any rounding - * of the BAR size to the native CPU page size should be performed - * by the driver. If the value is zero, no special partitioning - * of the doorbell BAR between L2 and RoCE is required. + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. */ - uint16_t l2_doorbell_bar_size_kb; - uint8_t unused_1; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Current temperature. In Celsius */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT \ + 0 /* - * For backward compatibility this field must be set to 1. - * Older drivers might look for this field to be 1 before - * processing the message. + * The temperature setting of the threshold that was just crossed. + * In Celsius */ - uint8_t always_1; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT \ + 8 + uint8_t opaque_v; /* - * This GRC address location is used by the Host driver interfaces to poll - * the adapter ready state to re-initiate the registration process again - * after receiving the RESET Notify event. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint32_t reset_addr_poll; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 /* - * This field specifies legacy L2 doorbell size in KBytes. Drivers should use - * this value to find out the doorbell page offset from the BAR. + * There was thermal event. The type will be specified in the + * field threshold_type. event_data2 will contain the current + * temperature and the configured value for the threshold that + * was just crossed. The threshold values are lower thresholds, + * so the event will trigger with an active flag when the + * temperature is on an increasing trajectory. */ - uint16_t legacy_l2_db_size_kb; - uint16_t svif_info; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT + /* The specific type of thermal threshold error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK \ + UINT32_C(0x700) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT \ + 8 + /* Warning thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN \ + (UINT32_C(0x0) << 8) + /* Critical thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL \ + (UINT32_C(0x1) << 8) + /* Fatal thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL \ + (UINT32_C(0x2) << 8) /* - * This field specifies the source virtual interface of the function being - * queried. Drivers can use this to program svif field in the L2 context - * table + * Thermal shutdown threshold was crossed and a shutdown is + * imminent. This event will not occur if self shutdown + * is disabled. */ - #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) - #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 - /* This field specifies whether svif is valid or not */ - #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) - uint8_t unused_2[7]; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN \ + (UINT32_C(0x3) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Indicates if the thermal crossing occurs while the temperature is + * increasing or decreasing. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR \ + UINT32_C(0x800) + /* Threshold is crossed while the temperature is falling. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING \ + (UINT32_C(0x0) << 11) + /* Threshold is crossed while the temperature is rising. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING \ + (UINT32_C(0x1) << 11) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING +} __rte_packed; + +/* metadata_base_msg (size:64b/8B) */ +struct metadata_base_msg { + uint16_t md_type_link; + /* This field classifies the data present in the meta-data. */ + #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f) + #define METADATA_BASE_MSG_MD_TYPE_SFT 0 + /* Meta data fields are not valid */ + #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0) + /* + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. + */ + #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1) + /* + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. + */ + #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2) + #define METADATA_BASE_MSG_MD_TYPE_LAST \ + METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC + /* + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. + */ + #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0) + #define METADATA_BASE_MSG_LINK_SFT 5 + uint16_t unused0; + uint32_t unused1; } __rte_packed; -/***************** - * hwrm_func_cfg * - *****************/ - - -/* hwrm_func_cfg_input (size:768b/96B) */ -struct hwrm_func_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* tls_metadata_base_msg (size:64b/8B) */ +struct tls_metadata_base_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0 /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. */ - uint16_t cmpl_ring; + #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \ + UINT32_C(0x1) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. */ - uint16_t seq_id; + #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \ + UINT32_C(0x2) + #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \ + TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - uint16_t target_id; + #define TLS_METADATA_BASE_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_BASE_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_BASE_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - uint64_t resp_addr; + #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \ + UINT32_C(0x200) /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the the configuration is - * for the requesting function. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - uint16_t fid; + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10 /* - * This field specifies how many NQs will be reserved for the PF. - * Remaining NQs that belong to the PF become available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * This enumeration states that the ghash is not valid in the + * meta-data. */ - uint16_t num_msix; - uint32_t flags; + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) /* - * When this bit is '1', the function is disabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to disallow - * transmission of frames with the source MAC address that - * is configured for this function. + * This enumeration indicates that this pkt contains the record's + * tag and this pkt was received ooo, the partial_ghash field + * contains the ghash. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ - UINT32_C(0x1) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \ + (UINT32_C(0x1) << 10) /* - * When this bit is '1', the function is enabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to allow - * transmission of frames with the source MAC address that - * is configured for this function. + * This enumeration indicates that the current record's tag wasn't + * seen and the chip is moving on to the next record, the + * partial_ghash field contains the ghash. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ - UINT32_C(0x1fc) - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \ + (UINT32_C(0x2) << 10) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is requested to be - * enabled on the function being configured. + * This enumeration is set when there is no tags present in the + * packet. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ - UINT32_C(0x200) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then the standard TX ring mode is requested to - * be disabled on the function being configured. In this extended - * TX ring resource mode, the minimum and maximum bandwidth settings - * are not supported to allow the allocation of TX rings to - * span multiple scheduler nodes. + * This enumeration states that there is at least one tag in the + * packet and every tag is valid. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ - UINT32_C(0x400) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \ + (UINT32_C(0x1) << 12) /* - * If this bit is set, virtual mac address configured - * in this command will be persistent over warm boot. + * This enumeration states that there is at least one tag in the + * packet and at least one of the tag is invalid. The entire packet + * is sent decrypted to the host. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ - UINT32_C(0x800) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \ + (UINT32_C(0x2) << 12) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE /* - * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ - UINT32_C(0x1000) + #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \ + UINT32_C(0x4000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ - UINT32_C(0x2000) + #define TLS_METADATA_BASE_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ - UINT32_C(0x4000) + #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0 + uint16_t unused0; +} __rte_packed; + +/* tls_metadata_insync_msg (size:192b/24B) */ +struct tls_metadata_insync_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0 /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ - UINT32_C(0x8000) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \ + UINT32_C(0x1) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \ + TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ - UINT32_C(0x10000) + #define TLS_METADATA_INSYNC_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9 /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ - UINT32_C(0x20000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \ + UINT32_C(0x200) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ - UINT32_C(0x40000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10 /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This enumeration states that the ghash is not valid in the + * meta-data. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ - UINT32_C(0x80000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This enumeration indicates that this pkt contains the record's + * tag and this pkt was received ooo, the partial_ghash field + * contains the ghash. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ - UINT32_C(0x100000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \ + (UINT32_C(0x1) << 10) /* - * This configuration change can be initiated by a PF driver. This - * configuration request shall be targeted to a VF. From local host - * resident HWRM clients, only the parent PF driver shall be allowed - * to initiate this change on one of its children VFs. If this bit is - * set to 1, then the VF that is being configured is requested to be - * trusted. + * This enumeration indicates that the current record's tag wasn't + * seen and the chip is moving on to the next record, the + * partial_ghash field contains the ghash. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \ - UINT32_C(0x200000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \ + (UINT32_C(0x2) << 10) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * When this bit it set, even if PF reserved pool size is zero, - * FW will allow driver to create TX rings in ring alloc, - * by reserving TX ring, S3 node dynamically. + * This enumeration is set when there is no tags present in the + * packet. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ - UINT32_C(0x400000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of NQ rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This enumeration states that there is at least one tag in the + * packet and every tag is valid. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ - UINT32_C(0x800000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \ + (UINT32_C(0x1) << 12) /* - * This configuration change can be initiated by a PF driver. This - * configuration request shall be targeted to a VF. From local host - * resident HWRM clients, only the parent PF driver shall be allowed - * to initiate this change on one of its children VFs. If this bit is - * set to 1, then the VF that is being configured is requested to be - * untrusted. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \ - UINT32_C(0x1000000) - /* - * This bit is used by preboot drivers on a PF that require access - * to the legacy L2 ring model and legacy 32b doorbells. This - * feature is not allowed on VFs and is only relevant for devices - * that require a context backing store. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ - UINT32_C(0x2000000) - /* - * If this bit is set to 0, then the interface does not support hot - * reset capability which it advertised with the hot_reset_support - * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this - * flag to 0, adapter cannot do the hot reset. In this state, if the - * firmware receives a hot reset request, firmware must fail the - * request. If this bit is set to 1, then interface is renabling the - * hot reset capability. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \ - UINT32_C(0x4000000) - /* - * If this bit is set to 1, the PF driver is requesting FW - * to enable PPP TX PUSH feature on all the TX rings specified in - * the num_tx_rings field. By default, the PPP TX push feature is - * disabled for all the TX rings of the function. This flag is - * ignored if num_tx_rings field is not specified or the function - * doesn't support PPP tx push feature. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ - UINT32_C(0x8000000) - uint32_t enables; - /* - * This bit must be '1' for the mtu field to be - * configured. + * This enumeration states that there is at least one tag in the + * packet and at least one of the tag is invalid. The entire packet + * is sent decrypted to the host. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ - UINT32_C(0x1) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \ + (UINT32_C(0x2) << 12) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE /* - * This bit must be '1' for the mru field to be - * configured. + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ - UINT32_C(0x2) + #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \ + UINT32_C(0x4000) /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ - UINT32_C(0x4) + #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * This bit must be '1' for the num_cmpl_rings field to be - * configured. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ - UINT32_C(0x8) + #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0 /* - * This bit must be '1' for the num_tx_rings field to be - * configured. + * This field is only valid when md_type is set to tls_insync. This field + * indicates the offset within the current TCP packet where the TLS header + * starts. If there are multiple TLS headers in the packet, this provides + * the offset of the last TLS header. + * + * The field is calculated by subtracting TCP sequence number of the first + * byte of the TCP payload of the packet from the TCP sequence number of + * the last TLS header in the packet. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ - UINT32_C(0x10) + uint16_t tls_header_offset; /* - * This bit must be '1' for the num_rx_rings field to be - * configured. + * This is the sequence Number of the record that was processed by the HW. + * If there are multiple records in a packet, this would be the sequence + * number of the last record. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ - UINT32_C(0x20) + uint64_t record_seq_num; /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. + * This field contains cumulative partial GHASH value of all the packets + * decrypted by the HW associated with a TLS record. This field is valid + * on when packets belonging to have arrived out-of-order and HW could + * not decrypt every packet and authenticate the record. Partial GHASH is + * only sent out with packet having the TAG field. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ - UINT32_C(0x40) + uint64_t partial_ghash; +} __rte_packed; + +/* tls_metadata_resync_msg (size:256b/32B) */ +struct tls_metadata_resync_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0 /* - * This bit must be '1' for the num_vnics field to be - * configured. + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ - UINT32_C(0x80) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \ + UINT32_C(0x2) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \ + TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ - UINT32_C(0x100) + #define TLS_METADATA_RESYNC_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9 /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \ UINT32_C(0x200) /* - * This bit must be '1' for the dflt_vlan field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ - UINT32_C(0x400) - /* - * This bit must be '1' for the dflt_ip_addr field to be - * configured. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ - UINT32_C(0x800) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10 /* - * This bit must be '1' for the min_bw field to be - * configured. + * This enumeration states that the ghash is not valid in the + * meta-data. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ - UINT32_C(0x1000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * This bit must be '1' for the max_bw field to be - * configured. + * This enumeration is set when there is no tags present in the + * packet. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ - UINT32_C(0x2000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE /* - * This bit must be '1' for the async_event_cr field to be - * configured. + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) /* - * This bit must be '1' for the vlan_antispoof_mode field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the allowed_vlan_pris field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the evb_mode field to be - * configured. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ - UINT32_C(0x20000) + #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * This bit must be '1' for the num_mcast_filters field to be - * configured. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ - UINT32_C(0x40000) + #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0 + /* This field is unused in this context. */ + uint16_t metadata_0; /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. + * This field indicates the TCP sequence number of the TLS record that HW + * is requesting a resync on from the Driver. HW will keep a count of the + * TLS records it found after this record (delta_records). Driver will + * provide the TLS Record Sequence Number associated with the record. HW + * will add the delta_records to the Record Sequence Number provided by + * the driver and get back on sync. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x80000) + uint32_t resync_record_tcp_seq_num; + uint32_t unused0; + /* This field is unused in this context. */ + uint64_t metadata_2; + /* This field is unused in this context. */ + uint64_t metadata_3; +} __rte_packed; + +/******************* + * hwrm_func_reset * + *******************/ + + +/* hwrm_func_reset_input (size:192b/24B) */ +struct hwrm_func_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the cache_linesize field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ - UINT32_C(0x100000) + uint16_t cmpl_ring; /* - * This bit must be '1' for the num_msix field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ - UINT32_C(0x200000) + uint16_t seq_id; /* - * This bit must be '1' for the link admin state field to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ - UINT32_C(0x400000) + uint16_t target_id; /* - * This bit must be '1' for the hot_reset_if_en_dis field to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \ - UINT32_C(0x800000) + uint64_t resp_addr; + uint32_t enables; /* - * This bit must be '1' for the sq_id field to be + * This bit must be '1' for the vf_id_valid field to be * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \ - UINT32_C(0x1000000) - /* - * The maximum transmission unit of the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to configuring mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. - */ - uint16_t mtu; + #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) /* - * The maximum receive unit of the function. - * The HWRM should make sure that the mru of - * the function does not exceed the mru of the physical - * port that this function is associated with. + * The ID of the VF that this PF is trying to reset. + * Only the parent PF shall be allowed to reset a child VF. * - * In addition to configuring mru per function, it is - * possible to configure mru per vnic. - * By default, the mru of each vnic associated - * with a function is equal to the mru of the function. - * The HWRM should make sure that the mru of each vnic - * that is assigned to a function has a valid mru. - */ - uint16_t mru; - /* - * The number of RSS/COS contexts requested for the - * function. - */ - uint16_t num_rsscos_ctxs; - /* - * The number of completion rings requested for the - * function. This does not include the rings allocated - * to any children functions if any. - */ - uint16_t num_cmpl_rings; - /* - * The number of transmit rings requested for the function. - * This does not include the rings allocated to any - * children functions if any. - */ - uint16_t num_tx_rings; - /* - * The number of receive rings requested for the function. - * This does not include the rings allocated - * to any children functions if any. - */ - uint16_t num_rx_rings; - /* The requested number of L2 contexts for the function. */ - uint16_t num_l2_ctxs; - /* The requested number of vnics for the function. */ - uint16_t num_vnics; - /* The requested number of statistic contexts for the function. */ - uint16_t num_stat_ctxs; - /* - * The number of HW ring groups that should - * be reserved for this function. - */ - uint16_t num_hw_ring_grps; - /* The default MAC address for the function being configured. */ - uint8_t dflt_mac_addr[6]; - /* - * The default VLAN for the function being configured. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). - */ - uint16_t dflt_vlan; - /* - * The default IP address for the function being configured. - * This address is only used in enabling source property check. - */ - uint32_t dflt_ip_addr[4]; - /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - */ - uint32_t min_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID - /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * A parent PF driver shall use this field only when a specific child VF + * is requested to be reset. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + uint16_t vf_id; + /* This value indicates the level of a function reset. */ + uint8_t func_reset_level; /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. + * Reset the caller function and its children VFs (if any). If no + * children functions exist, then reset the caller function only. */ - uint16_t async_event_cr; - /* VLAN Anti-spoofing mode. */ - uint8_t vlan_antispoof_mode; - /* No VLAN anti-spoofing checks are enabled */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ UINT32_C(0x0) - /* Validate VLAN against the configured VLAN(s) */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ + /* Reset the caller function only */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ UINT32_C(0x1) - /* Insert VLAN if it does not exist, otherwise discard */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ - UINT32_C(0x2) - /* Insert VLAN if it does not exist, override VLAN if it exists */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ - UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN - /* - * This bit field defines VLAN PRIs that are allowed on - * this function. - * If nth bit is set, then VLAN PRI n is allowed on this - * function. - */ - uint8_t allowed_vlan_pris; /* - * The HWRM shall allow a PF driver to change EVB mode for the - * partition it belongs to. - * The HWRM shall not allow a VF driver to change the EVB mode. - * The HWRM shall take into account the switching of EVB mode - * from one to another and reconfigure hardware resources as - * appropriately. - * The switching from VEB to VEPA mode requires - * the disabling of the loopback traffic. Additionally, - * source knock outs are handled differently in VEB and VEPA - * modes. + * Reset all children VFs of the caller function driver if the + * caller is a PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver with + * no children VFs. */ - uint8_t evb_mode; - /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) - /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) - /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA - uint8_t options; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ + UINT32_C(0x2) /* - * This value indicates the PCIE device cache line size. - * The cache line size allows the DMA writes to terminate and - * start at the cache boundary. + * Reset a specific VF of the caller function driver if the caller + * is the parent PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver that is not + * the parent of the VF that is being requested to reset. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 - /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ - UINT32_C(0x0) - /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ - UINT32_C(0x1) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 - /* This value is the virtual link admin state setting. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ - UINT32_C(0xc) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 - /* Admin state is forced down. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ - (UINT32_C(0x0) << 2) - /* Admin state is forced up. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ - (UINT32_C(0x1) << 2) - /* Admin state is in auto mode - is to follow the physical link state. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ - (UINT32_C(0x2) << 2) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ - HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO - /* Reserved for future. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4 - /* - * The number of multicast filters that should - * be reserved for this function on the RX side. - */ - uint16_t num_mcast_filters; - /* Used by a PF driver to associate a SQ with a VF. */ - uint16_t sq_id; - uint8_t unused_0[6]; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ + HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF + uint8_t unused_0; } __rte_packed; -/* hwrm_func_cfg_output (size:128b/16B) */ -struct hwrm_func_cfg_output { +/* hwrm_func_reset_output (size:128b/16B) */ +struct hwrm_func_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10601,12 +12993,12 @@ struct hwrm_func_cfg_output { } __rte_packed; /******************** - * hwrm_func_qstats * + * hwrm_func_getfid * ********************/ -/* hwrm_func_qstats_input (size:192b/24B) */ -struct hwrm_func_qstats_input { +/* hwrm_func_getfid_input (size:192b/24B) */ +struct hwrm_func_getfid_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10635,36 +13027,24 @@ struct hwrm_func_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. - * A privileged PF can query for other function's statistics. - */ - uint16_t fid; - /* This flags indicates the type of statistics request. */ - uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) - /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This bit must be '1' for the pci_id field to be + * configured. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) /* - * flags should be set to 2 when request is for the counter mask, - * representing the width of each of the stats counters, rather - * than counters themselves. + * This value is the PCI ID of the queried function. + * If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (5b):Function Number(3b). */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK - uint8_t unused_0[5]; + uint16_t pci_id; + uint8_t unused_0[2]; } __rte_packed; -/* hwrm_func_qstats_output (size:1408b/176B) */ -struct hwrm_func_qstats_output { +/* hwrm_func_getfid_output (size:128b/16B) */ +struct hwrm_func_getfid_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10673,68 +13053,12 @@ struct hwrm_func_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast packets on the function. */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets on the function. */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets on the function. */ - uint64_t tx_bcast_pkts; /* - * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this - * can only happen if TMP is configured to allow dropping - * in HOL blocking conditions, which is not a normal - * configuration. + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint64_t tx_discard_pkts; - /* - * Number of dropped packets on transmit path on the function. - * These are packets that have been marked for drop by - * the TE CFA block or are packets that exceeded the - * transmit MTU limit for the function. - */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic on the function. */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic on the function. */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic on the function. */ - uint64_t tx_bcast_bytes; - /* Number of received unicast packets on the function. */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets on the function. */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets on the function. */ - uint64_t rx_bcast_pkts; - /* - * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. - * # The BD used for the packet has a bad format. - * # There were no BDs available in the ring for the packet. - * # There were no BDs available on-chip for the packet. - */ - uint64_t rx_discard_pkts; - /* - * Number of dropped packets on received path on the function. - * These are packets that have been marked for drop by the - * RE CFA. - */ - uint64_t rx_drop_pkts; - /* Number of received bytes for unicast traffic on the function. */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic on the function. */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic on the function. */ - uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets on the function. */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes on the function. */ - uint64_t rx_agg_bytes; - /* Number of aggregation events on the function. */ - uint64_t rx_agg_events; - /* Number of aborted aggregations on the function. */ - uint64_t rx_agg_aborts; - uint8_t unused_0[7]; + uint16_t fid; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10745,13 +13069,13 @@ struct hwrm_func_qstats_output { uint8_t valid; } __rte_packed; -/************************ - * hwrm_func_qstats_ext * - ************************/ +/********************** + * hwrm_func_vf_alloc * + **********************/ -/* hwrm_func_qstats_ext_input (size:256b/32B) */ -struct hwrm_func_qstats_ext_input { +/* hwrm_func_vf_alloc_input (size:192b/24B) */ +struct hwrm_func_vf_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10780,51 +13104,23 @@ struct hwrm_func_qstats_ext_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. - * A privileged PF can query for other function's statistics. - */ - uint16_t fid; - /* This flags indicates the type of statistics request. */ - uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) - /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. - */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) - /* - * flags should be set to 2 when request is for the counter mask - * representing the width of each of the stats counters, rather - * than counters themselves. - */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK - uint8_t unused_0[1]; uint32_t enables; /* - * This bit must be '1' for the sq_id and traffic_class fields to be + * This bit must be '1' for the first_vf_id field to be * configured. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID UINT32_C(0x1) - /* Specifies the SQ for which to gather statistics */ - uint16_t sq_id; + #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) /* - * Specifies the traffic class for which to gather statistics. Valid - * values are 0 through (max_configurable_queues - 1), where - * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - uint16_t traffic_class; - uint8_t unused_1[4]; + uint16_t first_vf_id; + /* The number of virtual functions requested. */ + uint16_t num_vfs; } __rte_packed; -/* hwrm_func_qstats_ext_output (size:1472b/184B) */ -struct hwrm_func_qstats_ext_output { +/* hwrm_func_vf_alloc_output (size:128b/16B) */ +struct hwrm_func_vf_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10833,49 +13129,9 @@ struct hwrm_func_qstats_ext_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ - uint64_t rx_discard_pkts; - /* Number of packets on receive path with error */ - uint64_t rx_error_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of packets on transmit path with error */ - uint64_t tx_error_pkts; - /* Number of discarded packets on transmit path */ - uint64_t tx_discard_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of TPA eligible packets */ - uint64_t rx_tpa_eligible_pkt; - /* Number of TPA eligible bytes */ - uint64_t rx_tpa_eligible_bytes; - /* Number of TPA packets */ - uint64_t rx_tpa_pkt; - /* Number of TPA bytes */ - uint64_t rx_tpa_bytes; - /* Number of TPA errors */ - uint64_t rx_tpa_errors; - uint8_t unused_0[7]; + /* The ID of the first VF allocated. */ + uint16_t first_vf_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10886,13 +13142,13 @@ struct hwrm_func_qstats_ext_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_clr_stats * - ***********************/ +/********************* + * hwrm_func_vf_free * + *********************/ -/* hwrm_func_clr_stats_input (size:192b/24B) */ -struct hwrm_func_clr_stats_input { +/* hwrm_func_vf_free_input (size:192b/24B) */ +struct hwrm_func_vf_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10921,17 +13177,26 @@ struct hwrm_func_clr_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * Function ID of the function. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit must be '1' for the first_vf_id field to be + * configured. */ - uint16_t fid; - uint8_t unused_0[6]; + #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t first_vf_id; + /* + * The number of virtual functions requested. + * 0xFFFF - Cleanup all children of this PF. + */ + uint16_t num_vfs; } __rte_packed; -/* hwrm_func_clr_stats_output (size:128b/16B) */ -struct hwrm_func_clr_stats_output { +/* hwrm_func_vf_free_output (size:128b/16B) */ +struct hwrm_func_vf_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10951,13 +13216,13 @@ struct hwrm_func_clr_stats_output { uint8_t valid; } __rte_packed; -/************************** - * hwrm_func_vf_resc_free * - **************************/ +/******************** + * hwrm_func_vf_cfg * + ********************/ -/* hwrm_func_vf_resc_free_input (size:192b/24B) */ -struct hwrm_func_vf_resc_free_input { +/* hwrm_func_vf_cfg_input (size:448b/56B) */ +struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10986,16 +13251,248 @@ struct hwrm_func_vf_resc_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This bit must be '1' for the mtu field to be + * configured. */ - uint16_t vf_id; - uint8_t unused_0[6]; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + UINT32_C(0x1) + /* + * This bit must be '1' for the guest_vlan field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ + UINT32_C(0x2) + /* + * This bit must be '1' for the async_event_cr field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4) + /* + * This bit must be '1' for the dflt_mac_addr field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the num_rsscos_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + UINT32_C(0x10) + /* + * This bit must be '1' for the num_cmpl_rings field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + UINT32_C(0x20) + /* + * This bit must be '1' for the num_tx_rings field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + UINT32_C(0x40) + /* + * This bit must be '1' for the num_rx_rings field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + UINT32_C(0x80) + /* + * This bit must be '1' for the num_l2_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + UINT32_C(0x100) + /* + * This bit must be '1' for the num_vnics field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x200) + /* + * This bit must be '1' for the num_stat_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x400) + /* + * This bit must be '1' for the num_hw_ring_grps field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) + /* + * The maximum transmission unit requested on the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to requesting mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t mtu; + /* + * The guest VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). + */ + uint16_t guest_vlan; + /* + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. + */ + uint16_t async_event_cr; + /* + * This value is the current MAC address requested by the VF + * driver to be configured on this VF. A value of + * 00-00-00-00-00-00 indicates no MAC address configuration + * is requested by the VF driver. + * The parent PF driver may reject or overwrite this + * MAC address. + */ + uint8_t dflt_mac_addr[6]; + uint32_t flags; + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x1) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x2) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x4) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x8) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x10) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x20) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x40) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x80) + /* + * If this bit is set to 1, the VF driver is requesting FW to enable + * PPP TX PUSH feature on all the TX rings specified in the + * num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the VF. This flag is ignored if + * the num_tx_rings field is not specified or the VF doesn't support + * PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x100) + /* + * If this bit is set to 1, the VF driver is requesting FW to disable + * PPP TX PUSH feature on all the TX rings of the VF. This flag is + * ignored if the VF doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x200) + /* The number of RSS/COS contexts requested for the VF. */ + uint16_t num_rsscos_ctxs; + /* The number of completion rings requested for the VF. */ + uint16_t num_cmpl_rings; + /* The number of transmit rings requested for the VF. */ + uint16_t num_tx_rings; + /* The number of receive rings requested for the VF. */ + uint16_t num_rx_rings; + /* The number of L2 contexts requested for the VF. */ + uint16_t num_l2_ctxs; + /* The number of vnics requested for the VF. */ + uint16_t num_vnics; + /* The number of statistic contexts requested for the VF. */ + uint16_t num_stat_ctxs; + /* The number of HW ring groups requested for the VF. */ + uint16_t num_hw_ring_grps; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; -/* hwrm_func_vf_resc_free_output (size:128b/16B) */ -struct hwrm_func_vf_resc_free_output { +/* hwrm_func_vf_cfg_output (size:128b/16B) */ +struct hwrm_func_vf_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11015,13 +13512,13 @@ struct hwrm_func_vf_resc_free_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_drv_rgtr * - **********************/ +/******************* + * hwrm_func_qcaps * + *******************/ -/* hwrm_func_drv_rgtr_input (size:896b/112B) */ -struct hwrm_func_drv_rgtr_input { +/* hwrm_func_qcaps_input (size:192b/24B) */ +struct hwrm_func_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11050,739 +13547,703 @@ struct hwrm_func_drv_rgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When this bit is '1', the function driver is requesting - * all requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_qcaps_output (size:768b/96B) */ +struct hwrm_func_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. + */ + uint16_t fid; + /* + * Port ID of port that this function is associated with. + * Valid only for the PF. + * 0xFF... (All Fs) if this function is not associated with + * any port. + * 0xFF... (All Fs) if this function is called from a VF. + */ + uint16_t port_id; + uint32_t flags; + /* If 1, then Push mode is supported on this function. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ UINT32_C(0x1) /* - * When this bit is '1', the function is requesting none of - * the requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * If 1, then the global MSI-X auto-masking is enabled for the + * device. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ UINT32_C(0x2) /* - * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be ignored and ver_maj, ver_min, ver_upd - * and ver_patch shall be used for the driver version information. - * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be used for the driver version information and - * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. + * If 1, then the Precision Time Protocol (PTP) processing + * is supported on this function. + * The HWRM should enable PTP on only a single Physical + * Function (PF) per port. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ UINT32_C(0x4) /* - * When this bit is '1', the function is indicating support of - * 64bit flow handle. The firmware that only supports 64bit flow - * handle should check this bit before allowing processing of - * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware - * with 64bit flow handle support can only be compatible with drivers - * that support 64bit flow handle. The legacy drivers that don't support - * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when - * running with new firmware that only supports 64bit flow handle. The new - * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED - * status to the legacy driver when encounters these commands. + * If 1, then RDMA over Converged Ethernet (RoCE) v1 + * is supported on this function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ UINT32_C(0x8) /* - * When this bit is '1', the function is indicating support of - * Hot Reset. The driver interface will destroy the resources, - * unregister the function and register again up on receiving - * the RESET_NOTIFY Async notification from the core firmware. - * The core firmware will this use flag and trigger the Hot Reset - * process only if all the registered driver instances are capable - * of this support. + * If 1, then RDMA over Converged Ethernet (RoCE) v2 + * is supported on this function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ UINT32_C(0x10) /* - * When this bit is 1, the function is indicating the support of the - * error recovery capability. Error recovery support will be used by - * firmware only if all the driver instances support error recovery - * process. By setting this bit, driver is indicating support for - * corresponding async event completion message. These will be - * delivered to the driver even if they did not register for it. - * If supported, after receiving reset notify async event with fatal - * flag set in event data1, then all the drivers have to tear down - * their resources without sending any HWRM commands to FW. + * If 1, then control and configuration of WoL magic packet + * are supported on this function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ UINT32_C(0x20) /* - * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select the - * Master function. The master function will be used to initiate - * designated functionality like error recovery etc… If none of the - * registered PF’s or trusted VF’s indicate this support, then - * firmware will select the 1st registered PF as Master capable instance. + * If 1, then control and configuration of bitmap pattern + * packet are supported on this function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ UINT32_C(0x40) - uint32_t enables; /* - * This bit must be '1' for the os_type field to be - * configured. + * If set to 1, then the control and configuration of rate limit + * of an allocated TX ring on the queried function is supported. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ - UINT32_C(0x1) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ + UINT32_C(0x80) /* - * This bit must be '1' for the ver field to be - * configured. + * If 1, then control and configuration of minimum and + * maximum bandwidths are supported on the queried function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ - UINT32_C(0x2) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ + UINT32_C(0x100) /* - * This bit must be '1' for the timestamp field to be - * configured. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the rate limits + * on the TX rings of its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the rate limits + * on the TX rings of its children VFs. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ - UINT32_C(0x4) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ + UINT32_C(0x200) /* - * This bit must be '1' for the vf_req_fwd field to be - * configured. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the minimum and/or + * maximum bandwidths for its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the minimum or + * maximum bandwidths for its children VFs. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ - UINT32_C(0x8) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ + UINT32_C(0x400) /* - * This bit must be '1' for the async_event_fwd field to be - * configured. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is supported + * on the queried function. + * If set to 0, then standard TX ring mode is not available + * on the queried function. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ - UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ - uint16_t os_type; - /* Unknown */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) - /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) - /* MSDOS OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) - /* Windows OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) - /* Solaris OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) - /* Linux OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) - /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) - /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) - /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) - /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) - /* UEFI driver. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI - /* This is the 8bit major version of the driver. */ - uint8_t ver_maj_8b; - /* This is the 8bit minor version of the driver. */ - uint8_t ver_min_8b; - /* This is the 8bit update version of the driver. */ - uint8_t ver_upd_8b; - uint8_t unused_0[3]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ + UINT32_C(0x800) /* - * This is a 32-bit timestamp provided by the driver for - * keep alive. - * The timestamp is in multiples of 1ms. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GENEVE tunnel + * flags. */ - uint32_t timestamp; - uint8_t unused_1[4]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x1000) /* - * This is a 256-bit bit mask provided by the PF driver for - * letting the HWRM know what commands issued by the VF driver - * to the HWRM should be forwarded to the PF driver. - * Nth bit refers to the Nth req_type. - * - * Setting Nth bit to 1 indicates that requests from the - * VF driver with req_type equal to N shall be forwarded to - * the parent PF driver. - * - * This field is not valid for the VF driver. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect NVGRE tunnel + * flags. */ - uint32_t vf_req_fwd[8]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x2000) /* - * This is a 256-bit bit mask provided by the function driver - * (PF or VF driver) to indicate the list of asynchronous event - * completions to be forwarded. - * - * Nth bit refers to the Nth event_id. - * - * Setting Nth bit to 1 by the function driver shall result in - * the HWRM forwarding asynchronous event completion with - * event_id equal to N. - * - * If all bits are set to 0 (value of 0), then the HWRM shall - * not forward any asynchronous event completion to this - * function driver. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GRE tunnel + * flags. */ - uint32_t async_event_fwd[8]; - /* This is the 16bit major version of the driver. */ - uint16_t ver_maj; - /* This is the 16bit minor version of the driver. */ - uint16_t ver_min; - /* This is the 16bit update version of the driver. */ - uint16_t ver_upd; - /* This is the 16bit patch version of the driver. */ - uint16_t ver_patch; -} __rte_packed; - -/* hwrm_func_drv_rgtr_output (size:128b/16B) */ -struct hwrm_func_drv_rgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x4000) /* - * When this bit is '1', it indicates that the - * HWRM_FUNC_DRV_IF_CHANGE call is supported. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect MPLS tunnel + * flags. */ - #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \ - UINT32_C(0x1) - uint8_t unused_0[3]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x8000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to support pcie stats. */ - uint8_t valid; -} __rte_packed; - -/************************ - * hwrm_func_drv_unrgtr * - ************************/ - - -/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ -struct hwrm_func_drv_unrgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ + UINT32_C(0x10000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to adopt the VF's belonging + * to another PF. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \ + UINT32_C(0x20000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the administrative privilege to configure another PF */ - uint16_t seq_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ + UINT32_C(0x40000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then + * the PF will know that the firmware has the capability to track + * the virtual link status. */ - uint16_t target_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \ + UINT32_C(0x80000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If 1, then this function supports the push mode that uses + * write combine buffers and the long inline tx buffer descriptor. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \ + UINT32_C(0x100000) /* - * When this bit is '1', the function driver is notifying - * the HWRM to prepare for the shutdown. + * If 1, then FW has capability to allocate TX rings dynamically + * in ring alloc even if PF reserved pool is zero. + * This bit will be used only for PFs. */ - #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ - UINT32_C(0x1) - uint8_t unused_0[4]; -} __rte_packed; - -/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ -struct hwrm_func_drv_unrgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ + UINT32_C(0x200000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When this bit is '1', it indicates that core firmware is + * capable of Hot Reset. */ - uint8_t valid; -} __rte_packed; - -/********************** - * hwrm_func_buf_rgtr * - **********************/ - - -/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ -struct hwrm_func_buf_rgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \ + UINT32_C(0x400000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This flag will be set to 1 by the FW if FW supports adapter error + * recovery. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \ + UINT32_C(0x800000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then + * the PF has the capability to support extended stats. */ - uint16_t seq_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \ + UINT32_C(0x1000000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then host + * must initiate reset or reload (or fastboot) the firmware image + * upon detection of device shutdown state. */ - uint16_t target_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ + UINT32_C(0x2000000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If the query is for a VF, then this flag (always set to 0) shall + * be ignored. If this query is for a PF and this flag is set to 1, + * host, when registered for the default vnic change async event, + * receives async notification whenever a default vnic state is + * changed for any of child or adopted VFs. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ + UINT32_C(0x4000000) + /* If set to 1, then the vlan acceleration for TX is disabled. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ + UINT32_C(0x8000000) /* - * This bit must be '1' for the vf_id field to be - * configured. + * When this bit is '1', it indicates that core firmware supports + * DBG_COREDUMP_XXX commands. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ + UINT32_C(0x10000000) /* - * This bit must be '1' for the err_buf_addr field to be - * configured. + * When this bit is '1', it indicates that core firmware supports + * DBG_CRASHDUMP_XXX commands. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ + UINT32_C(0x20000000) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * If the query is for a VF, then this flag should be ignored. + * If the query is for a PF and this flag is set to 1, then + * the PF has the capability to support retrieval of + * rx_port_stats_ext_pfc_wd statistics (supported by the PFC + * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. + * If this flag is set to 1, only that (supported) command should + * be used for retrieval of PFC related statistics (rather than + * hwrm_port_qstats_ext command, which could previously be used). */ - uint16_t vf_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + UINT32_C(0x40000000) /* - * This field represents the number of pages used for request - * buffer(s). + * When this bit is '1', it indicates that core firmware supports + * DBG_QCAPS command */ - uint16_t req_buf_num_pages; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \ + UINT32_C(0x80000000) /* - * This field represents the page size used for request - * buffer(s). + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. */ - uint16_t req_buf_page_size; - /* 16 bytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) - /* 4 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) - /* 8 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) - /* 64 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) - /* 2 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) - /* 4 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) - /* 1 Gbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ - HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G - /* The length of the request buffer per VF in bytes. */ - uint16_t req_buf_len; - /* The length of the response buffer in bytes. */ - uint16_t resp_buf_len; - uint8_t unused_0[2]; - /* This field represents the page address of page #0. */ - uint64_t req_buf_page_addr0; - /* This field represents the page address of page #1. */ - uint64_t req_buf_page_addr1; - /* This field represents the page address of page #2. */ - uint64_t req_buf_page_addr2; - /* This field represents the page address of page #3. */ - uint64_t req_buf_page_addr3; - /* This field represents the page address of page #4. */ - uint64_t req_buf_page_addr4; - /* This field represents the page address of page #5. */ - uint64_t req_buf_page_addr5; - /* This field represents the page address of page #6. */ - uint64_t req_buf_page_addr6; - /* This field represents the page address of page #7. */ - uint64_t req_buf_page_addr7; - /* This field represents the page address of page #8. */ - uint64_t req_buf_page_addr8; - /* This field represents the page address of page #9. */ - uint64_t req_buf_page_addr9; + uint8_t mac_address[6]; /* - * This field is used to receive the error reporting from - * the chipset. Only applicable for PFs. + * The maximum number of RSS/COS contexts that can be + * allocated to the function. */ - uint64_t error_buf_addr; + uint16_t max_rsscos_ctx; /* - * This field is used to receive the response forwarded by the - * HWRM. + * The maximum number of completion rings that can be + * allocated to the function. */ - uint64_t resp_buf_addr; -} __rte_packed; - -/* hwrm_func_buf_rgtr_output (size:128b/16B) */ -struct hwrm_func_buf_rgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t max_cmpl_rings; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * The maximum number of transmit rings that can be + * allocated to the function. */ - uint8_t valid; -} __rte_packed; - -/************************ - * hwrm_func_buf_unrgtr * - ************************/ - - -/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ -struct hwrm_func_buf_unrgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t max_tx_rings; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The maximum number of receive rings that can be + * allocated to the function. */ - uint16_t cmpl_ring; + uint16_t max_rx_rings; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The maximum number of L2 contexts that can be + * allocated to the function. */ - uint16_t seq_id; + uint16_t max_l2_ctxs; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The maximum number of VNICs that can be + * allocated to the function. */ - uint16_t target_id; + uint16_t max_vnics; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The identifier for the first VF enabled on a PF. This + * is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. */ - uint64_t resp_addr; - uint32_t enables; + uint16_t first_vf_id; /* - * This bit must be '1' for the vf_id field to be - * configured. + * The maximum number of VFs that can be + * allocated to the function. This is valid only on the + * PF with SR-IOV enabled. 0xFF... (All Fs) if this + * command is called on a PF with SR-IOV disabled or + * on a VF. */ - #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + uint16_t max_vfs; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * The maximum number of statistic contexts that can be + * allocated to the function. */ - uint16_t vf_id; - uint8_t unused_0[2]; -} __rte_packed; - -/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ -struct hwrm_func_buf_unrgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t max_stat_ctx; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * The maximum number of Encapsulation records that can be + * offloaded by this function. */ - uint8_t valid; -} __rte_packed; - -/********************** - * hwrm_func_drv_qver * - **********************/ - - -/* hwrm_func_drv_qver_input (size:192b/24B) */ -struct hwrm_func_drv_qver_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t max_encap_records; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The maximum number of decapsulation records that can + * be offloaded by this function. */ - uint16_t cmpl_ring; + uint32_t max_decap_records; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the TX side. */ - uint16_t seq_id; + uint32_t max_tx_em_flows; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the TX side. */ - uint16_t target_id; + uint32_t max_tx_wm_flows; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the RX side. */ - uint64_t resp_addr; - /* Reserved for future use. */ - uint32_t reserved; + uint32_t max_rx_em_flows; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the RX side. */ - uint16_t fid; - uint8_t unused_0[2]; -} __rte_packed; - -/* hwrm_func_drv_qver_output (size:256b/32B) */ -struct hwrm_func_drv_qver_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ - uint16_t os_type; - /* Unknown */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) - /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) - /* MSDOS OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) - /* Windows OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) - /* Solaris OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) - /* Linux OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) - /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) - /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) - /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) - /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) - /* UEFI driver. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI - /* This is the 8bit major version of the driver. */ - uint8_t ver_maj_8b; - /* This is the 8bit minor version of the driver. */ - uint8_t ver_min_8b; - /* This is the 8bit update version of the driver. */ - uint8_t ver_upd_8b; - uint8_t unused_0[3]; - /* This is the 16bit major version of the driver. */ - uint16_t ver_maj; - /* This is the 16bit minor version of the driver. */ - uint16_t ver_min; - /* This is the 16bit update version of the driver. */ - uint16_t ver_upd; - /* This is the 16bit patch version of the driver. */ - uint16_t ver_patch; - uint8_t unused_1[7]; + uint32_t max_rx_wm_flows; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * The maximum number of multicast filters that can + * be supported by this function on the RX side. */ - uint8_t valid; -} __rte_packed; - -/**************************** - * hwrm_func_resource_qcaps * - ****************************/ - - -/* hwrm_func_resource_qcaps_input (size:192b/24B) */ -struct hwrm_func_resource_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t max_mcast_filters; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The maximum value of flow_id that can be supported + * in completion records. */ - uint16_t cmpl_ring; + uint32_t max_flow_id; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The maximum number of HW ring groups that can be + * supported on this function. */ - uint16_t seq_id; + uint32_t max_hw_ring_grps; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The maximum number of strict priority transmit rings + * that can be allocated to the function. + * This number indicates the maximum number of TX rings + * that can be assigned strict priorities out of the + * maximum number of TX rings that can be allocated + * (max_tx_rings) to the function. */ - uint16_t target_id; + uint16_t max_sp_tx_rings; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. */ - uint64_t resp_addr; + uint16_t max_msix_vfs; + uint32_t flags_ext; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * If 1, the device can be configured to set the ECN bits in the + * IP header of received packets if the receive queue length + * exceeds a given threshold. */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ -struct hwrm_func_resource_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ - uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ - uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ - uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ - UINT32_C(0x0) - /* The PF driver should only reserve minimal resources for each VF. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ UINT32_C(0x1) /* - * The PF driver should not reserve any resources for each VF until the - * the VF interface is brought up. + * If 1, the device can report the number of received packets + * that it marked as having experienced congestion. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ - HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ - uint16_t min_rsscos_ctx; - /* Maximum non-guaranteed number of RSS/COS contexts */ - uint16_t max_rsscos_ctx; - /* Minimum guaranteed number of completion rings */ - uint16_t min_cmpl_rings; - /* Maximum non-guaranteed number of completion rings */ - uint16_t max_cmpl_rings; - /* Minimum guaranteed number of transmit rings */ - uint16_t min_tx_rings; - /* Maximum non-guaranteed number of transmit rings */ - uint16_t max_tx_rings; - /* Minimum guaranteed number of receive rings */ - uint16_t min_rx_rings; - /* Maximum non-guaranteed number of receive rings */ - uint16_t max_rx_rings; - /* Minimum guaranteed number of L2 contexts */ - uint16_t min_l2_ctxs; - /* Maximum non-guaranteed number of L2 contexts */ - uint16_t max_l2_ctxs; - /* Minimum guaranteed number of VNICs */ - uint16_t min_vnics; - /* Maximum non-guaranteed number of VNICs */ - uint16_t max_vnics; - /* Minimum guaranteed number of statistic contexts */ - uint16_t min_stat_ctx; - /* Maximum non-guaranteed number of statistic contexts */ - uint16_t max_stat_ctx; - /* Minimum guaranteed number of ring groups */ - uint16_t min_hw_ring_grps; - /* Maximum non-guaranteed number of ring groups */ - uint16_t max_hw_ring_grps; /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. + * If 1, the device can report extended hw statistics (including + * additional tpa statistics). */ - uint16_t max_tx_scheduler_inputs; - uint16_t flags; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \ + UINT32_C(0x4) /* - * When this bit is '1', it indicates that VF_RESOURCE_CFG supports - * feature to reserve all minimum resources when minimum >= 1, otherwise - * returns an error. + * If set to 1, then the core firmware has support to enable/ + * disable hot reset support for interface dynamically through + * HWRM_FUNC_CFG. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x8) + /* If 1, the proxy mode is supported on this function */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \ + UINT32_C(0x10) + /* + * If 1, the tx rings source interface override feature is supported + * on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \ + UINT32_C(0x20) + /* + * If 1, the device supports scheduler queues. SCHQs can be managed + * using RING_SCHQ_ALLOC/CFG/FREE commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \ + UINT32_C(0x40) + /* + * If set to 1, then this function supports the TX push mode that + * uses ping-pong buffers from the push pages. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ + UINT32_C(0x80) + /* + * If set to 1, then this function doesn't have the privilege to + * configure the EVB mode of the port it uses. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \ + UINT32_C(0x100) + /* + * If set to 1, then the HW and FW support the SoC packet DMA + * datapath between SoC and NIC. This function can act as the + * HWRM communication transport agent on behalf of the SoC SPD + * software module. This capability is only advertised to the + * SoC PFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \ + UINT32_C(0x200) + /* + * If set to 1, then this function supports FW_LIVEPATCH for + * firmware livepatch commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates that core firmware is + * capable of fast Reset. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \ + UINT32_C(0x800) + /* + * When this bit is '1', it indicates that firmware and hardware + * are capable of updating tx_metadata via hwrm_ring_cfg command. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \ + UINT32_C(0x1000) + /* + * If set to 1, then the device can report the action + * needed to activate set nvm options. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \ + UINT32_C(0x2000) + /* + * When this bit is '1', it indicates that the BD metadata feature + * is supported for this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that the echo request feature + * is supported for this function. If the driver registers for the + * echo request asynchronous event, then the firmware can send an + * unsolicited echo request to the driver and expect an echo + * response. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that core firmware supports + * NPAR 1.2 on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \ + UINT32_C(0x10000) + /* When this bit is '1', it indicates that PTM feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \ + UINT32_C(0x20000) + /* When this bit is '1', it indicates that PPS feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \ + UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that VF config. change + * async event is supported on the parent PF if the async. + * event is registered by the PF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \ + UINT32_C(0x80000) + /* + * When this bit is '1', the NIC supports configuration of + * partition_min_bw and partition_max_bw. Configuration of a + * minimum guaranteed bandwidth is only supported if the + * min_bw_supported flag is also set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \ + UINT32_C(0x100000) + /* + * When this bit is '1', the FW supports configuration of + * PCP and TPID values of the default VLAN. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \ + UINT32_C(0x200000) + /* When this bit is '1', it indicates that HW and FW support KTLS. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \ + UINT32_C(0x400000) + /* + * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG + * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions + * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive + * rate control. Configuration of a minimum guaranteed bandwidth + * is only supported if the min_bw_supported flag is also set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \ + UINT32_C(0x800000) + /* + * When this bit is '1', the firmware supports enforcement of + * minimum guaranteed bandwidth. A minimum guaranteed bandwidth + * could be configured for a partition or for an endpoint. Firmware + * only sets this flag if one or both of the ep_rate_control and + * partition_bw_supported flags are set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \ + UINT32_C(0x1000000) + /* + * When this bit is '1', HW supports TX coalesced completion + * records. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1', it indicates the FW has full support + * for all backing store types with the BACKING_STORE_CFG/QCFG + * V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates the FW forces to use the + * BACKING_STORE_CFG/QCFG V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that FW will support a single + * 64bit real time clock for PTP. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting Doorbell Pacing. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED \ + UINT32_C(0x20000000) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting HW based doorbell drop recovery. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED \ + UINT32_C(0x40000000) + /* + * When this bit is '1', it indicates the driver can disable the CQ + * overflow detection and can also skip the index updates for CQ. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED \ + UINT32_C(0x80000000) + /* The maximum number of SCHQs supported by this device. */ + uint8_t max_schqs; + uint8_t mpc_chnls_cap; + /* + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the TX crypto engine block. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1) + /* + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the RX crypto engine block. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2) + /* + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the TX configurable flow processing block. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4) + /* + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the RX configurable flow processing block. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8) + /* + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the primate processor block. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint32_t flags_ext2; + /* + * When this bit is '1', it indicates that FW will support + * timestamping on all RX packets, not just PTP type packets. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED \ UINT32_C(0x1) - uint8_t unused_0[5]; + /* When this bit is '1', it indicates that HW and FW support QUIC. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \ + UINT32_C(0x2) + uint16_t tunnel_disable_flag; + /* + * When this bit is '1', it indicates that the VXLAN parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the NGE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates that the NVGRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates that the L2GRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that the GRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the IPINIP parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates that the MPLS parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the PPPOE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \ + UINT32_C(0x80) + uint8_t unused_1; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************************* - * hwrm_func_backing_store_qcaps * - *********************************/ +/****************** + * hwrm_func_qcfg * + ******************/ -/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcaps_input { +/* hwrm_func_qcfg_input (size:192b/24B) */ +struct hwrm_func_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11811,10 +14272,19 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. + */ + uint16_t fid; + uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ -struct hwrm_func_backing_store_qcaps_output { +/* hwrm_func_qcfg_output (size:896b/112B) */ +struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11823,1146 +14293,6564 @@ struct hwrm_func_backing_store_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum number of QP context entries supported for this function. */ - uint32_t qp_max_entries; /* - * Minimum number of QP context entries that are needed to be reserved - * for QP1 for the PF and its VFs. PF drivers must allocate at least - * this many QP context entries, even if RoCE will not be used. + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ - uint16_t qp_max_l2_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t qp_entry_size; - /* Maximum number of SRQ context entries that can be used for L2. */ - uint16_t srq_max_l2_entries; - /* Maximum number of SRQ context entries supported for this function. */ - uint32_t srq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t srq_entry_size; - /* Maximum number of CQ context entries that can be used for L2. */ - uint16_t cq_max_l2_entries; - /* Maximum number of CQ context entries supported for this function. */ - uint32_t cq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t cq_entry_size; - /* Maximum number of VNIC context entries supported for this function. */ - uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ - uint16_t vnic_max_ring_table_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ - uint32_t stat_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t stat_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tqm_entry_size; - /* Minimum number of TQM context entries required per ring. */ - uint32_t tqm_min_entries_per_ring; + uint16_t fid; /* - * Maximum number of TQM context entries supported per ring. This is - * actually a recommended TQM queue size based on worst case usage of - * the TQM queue. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * TQM slowpath rings should be sized as follows: - * - * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size - * - * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * Port ID of port that this function is associated with. + * 0xFF... (All Fs) if this function is not associated with + * any port. */ - uint32_t tqm_max_entries_per_ring; + uint16_t port_id; /* - * Maximum number of MR plus AV context entries supported for this - * function. + * This value is the current VLAN setting for this + * function. The value of 0 for this field indicates + * no priority tagging or VLAN is used. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). */ - uint32_t mrav_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t mrav_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tim_entry_size; - /* Maximum number of Timer context entries supported for this function. */ - uint32_t tim_max_entries; - /* - * When this field is zero, the 32b `mrav_num_entries` field in the - * `backing_store_cfg` and `backing_store_qcfg` commands represents - * the total number of MR plus AV entries allowed in the MR/AV backing - * store PBL. - * - * When this field is non-zero, the 32b `mrav_num_entries` field in - * the `backing_store_cfg` and `backing_store_qcfg` commands is - * logically divided into two 16b fields. Bits `[31:16]` represents - * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`. - * Both of these values are represented in a unit granularity - * specified by this field. For example, if this field is 16 and - * `mrav_num_entries` is `0x02000100`, then the number of MR entries - * is 8192 and the number of AV entries is 4096. + uint16_t vlan; + uint16_t flags; + /* + * If 1, then magic packet based Out-Of-Box WoL is enabled on + * the port associated with this function. */ - uint16_t mrav_num_entries_units; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ + UINT32_C(0x1) /* - * The number of entries specified for any TQM ring must be a - * multiple of this value to prevent any resource allocation - * limitations. + * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled + * on the port associated with this function. */ - uint8_t tqm_entries_multiple; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ + UINT32_C(0x2) /* - * Initializer to be used by drivers - * to initialize context memory to ensure - * context subsystem flags an error for an attack - * before the first time context load. + * If set to 1, then FW based DCBX agent is enabled and running on + * the port associated with this function. + * If set to 0, then DCBX agent is not running in the firmware. */ - uint8_t ctx_kind_initializer; - /* Reserved for future. */ - uint32_t rsvd; - /* Reserved for future. */ - uint16_t rsvd1; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ + UINT32_C(0x4) /* - * Count of TQM fastpath rings to be used for allocating backing store. - * Backing store configuration must be specified for each TQM ring from - * this count in `backing_store_cfg`. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is enabled + * on the queried function. + * If set to 0, then the standard TX ring mode is disabled + * on the queried function. In this extended TX ring resource + * mode, the minimum and maximum bandwidth settings are not + * supported to allow the allocation of TX rings to span multiple + * scheduler nodes. */ - uint8_t tqm_fp_rings_count; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ + UINT32_C(0x8) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If set to 1 then FW based LLDP agent is enabled and running on + * the port associated with this function. + * If set to 0 then the LLDP agent is not running in the firmware. */ - uint8_t valid; -} __rte_packed; - -/******************************* - * hwrm_func_backing_store_cfg * - *******************************/ - - -/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ -struct hwrm_func_backing_store_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ + UINT32_C(0x10) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * If set to 1, then multi-host mode is active for this function. + * The NIC is attached to two or more independent host systems + * through two or more PCIe endpoints. + * If set to 0, then multi-host mode is inactive for this function + * or not applicable for this device. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ + UINT32_C(0x20) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If the function that is being queried is a PF, then the HWRM shall + * set this field to 0 and the HWRM client shall ignore this field. + * If the function that is being queried is a VF, then the HWRM shall + * set this field to 1 if the queried VF is trusted, otherwise the HWRM + * shall set this field to 0. */ - uint16_t seq_id; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ + UINT32_C(0x40) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If set to 1, then secure mode is enabled for this function or device. + * If set to 0, then secure mode is disabled (or normal mode) for this + * function or device. */ - uint16_t target_id; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \ + UINT32_C(0x80) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1, then this PF is enabled with a preboot driver that + * requires access to the legacy L2 ring model and legacy 32b + * doorbells. If set to 0, then this PF is not allowed to use + * the legacy L2 rings. This feature is not allowed on VFs and + * is only relevant for devices that require a context backing + * store. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ + UINT32_C(0x100) /* - * When set, the firmware only uses on-chip resources and does not - * expect any backing store to be provided by the host driver. This - * mode provides minimal L2 functionality (e.g. limited L2 resources, - * no RoCE). + * If set to 1, then the firmware and all currently registered driver + * instances support hot reset. The hot reset support will be updated + * dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * hot reset. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ - UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \ + UINT32_C(0x200) /* - * When set, the 32b `mrav_num_entries` field is logically divided - * into two 16b fields, `mr_num_entries` and `av_num_entries`. + * If set to 1, then the PPP tx push mode is enabled for all the + * reserved TX rings of this function. If set to 0, then PPP tx push + * mode is disabled for all the reserved TX rings of this function. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \ - UINT32_C(0x2) - uint32_t enables; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \ + UINT32_C(0x400) /* - * This bit must be '1' for the qp fields to be - * configured. + * If set to 1, then the firmware will notify driver using async + * event when a ring is disabled due to a Hardware error. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ - UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \ + UINT32_C(0x800) /* - * This bit must be '1' for the srq fields to be - * configured. + * If set to 1, then the firmware and all currently registered driver + * instances support fast reset. The fast reset support will be + * updated dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * fast reset. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ - UINT32_C(0x2) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \ + UINT32_C(0x1000) /* - * This bit must be '1' for the cq fields to be - * configured. + * If set to 1, then multi-root mode is active for this function. + * The NIC is attached to a single host with a single operating + * system, but through two or more PCIe endpoints. + * If set to 0, then multi-root mode is inactive for this function + * or not applicable for this device. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ - UINT32_C(0x4) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \ + UINT32_C(0x2000) /* - * This bit must be '1' for the vnic fields to be - * configured. + * This flag indicates RDMA support for child VFS of + * a physical function. + * If set to 1, RoCE is supported on all child VFs. + * If set to 0, RoCE is disabled on all child VFs. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ - UINT32_C(0x8) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \ + UINT32_C(0x4000) /* - * This bit must be '1' for the stat fields to be - * configured. + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ - UINT32_C(0x10) + uint8_t mac_address[6]; /* - * This bit must be '1' for the tqm_sp fields to be - * configured. + * This value is current PCI ID of this + * function. If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (4b):Function Number(4b). + * If multi-host mode is active, the 4 lsb will indicate + * the PF index for this function. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ - UINT32_C(0x20) + uint16_t pci_id; /* - * This bit must be '1' for the tqm_ring0 fields to be - * configured. + * The number of RSS/COS contexts currently + * allocated to the function. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ - UINT32_C(0x40) + uint16_t alloc_rsscos_ctx; /* - * This bit must be '1' for the tqm_ring1 fields to be - * configured. + * The number of completion rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ - UINT32_C(0x80) + uint16_t alloc_cmpl_rings; /* - * This bit must be '1' for the tqm_ring2 fields to be - * configured. + * The number of transmit rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ - UINT32_C(0x100) + uint16_t alloc_tx_rings; /* - * This bit must be '1' for the tqm_ring3 fields to be - * configured. + * The number of receive rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ - UINT32_C(0x200) + uint16_t alloc_rx_rings; + /* The allocated number of L2 contexts to the function. */ + uint16_t alloc_l2_ctx; + /* The allocated number of vnics to the function. */ + uint16_t alloc_vnics; /* - * This bit must be '1' for the tqm_ring4 fields to be - * configured. + * The maximum transmission unit of the function + * configured by the admin pf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default + * value is used if ring MTU is not specified. + * The driver cannot use any MTU bigger than this value + * if it is non-zero. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ - UINT32_C(0x400) + uint16_t admin_mtu; /* - * This bit must be '1' for the tqm_ring5 fields to be - * configured. + * The maximum receive unit of the function. + * For vnics allocated on this function, this default + * value is used if vnic MRU is not specified. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ - UINT32_C(0x800) + uint16_t mru; + /* The statistics context assigned to a function. */ + uint16_t stat_ctx_id; /* - * This bit must be '1' for the tqm_ring6 fields to be - * configured. + * The HWRM shall return Unknown value for this field + * when this command is used to query VF's configuration. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ - UINT32_C(0x1000) + uint8_t port_partition_type; + /* Single physical function */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) + /* Multiple physical functions */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) + /* Network Partitioning 1.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) + /* Network Partitioning 1.5 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) + /* Network Partitioning 2.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Network Partitioning 1.2 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5) + /* Unknown */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN /* - * This bit must be '1' for the tqm_ring7 fields to be - * configured. + * This field will indicate number of physical functions on this port_partition. + * HWRM shall return unavail (i.e. value of 0) for this field + * when this command is used to query VF's configuration or + * from older firmware that doesn't support this field. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ - UINT32_C(0x2000) + uint8_t port_pf_cnt; + /* number of PFs is not available */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL /* - * This bit must be '1' for the mrav fields to be - * configured. + * The default VNIC ID assigned to a function that is + * being queried. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ - UINT32_C(0x4000) + uint16_t dflt_vnic_id; + uint16_t max_mtu_configured; /* - * This bit must be '1' for the tim fields to be - * configured. + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ - UINT32_C(0x8000) - /* QPC page size and level. */ - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 - /* QPC page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G - /* SRQ page size and level. */ - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G - /* CQ page size and level. */ - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ + uint32_t min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. + */ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * This value indicates the Edge virtual bridge mode for the + * domain that this function belongs to. + */ + uint8_t evb_mode; + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA + uint8_t options; + /* + * This value indicates the PCIE device cache line size. + * The cache line size allows the DMA writes to terminate and + * start at the cache boundary. + */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ + UINT32_C(0x3) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + /* Cache Line Size 64 bytes */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ + /* Cache Line Size 128 bytes */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 - /* CQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* This value is the virtual link admin state setting. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + UINT32_C(0xc) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin link state is in forced down mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + (UINT32_C(0x0) << 2) + /* Admin link state is in forced up mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + (UINT32_C(0x1) << 2) + /* Admin link state is in auto mode - follows the physical link state. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + (UINT32_C(0x2) << 2) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO + /* Reserved for future. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4 + /* + * The number of VFs that are allocated to the function. + * This is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t alloc_vfs; + /* + * The number of allocated multicast filters for this + * function on the RX side. + */ + uint32_t alloc_mcast_filters; + /* + * The number of allocated HW ring groups for this + * function. + */ + uint32_t alloc_hw_ring_grps; + /* + * The number of strict priority transmit rings out of + * currently allocated TX rings to the function + * (alloc_tx_rings). + */ + uint16_t alloc_sp_tx_rings; + /* + * The number of statistics contexts + * currently reserved for the function. + */ + uint16_t alloc_stat_ctx; + /* + * This field specifies how many NQs are reserved for the PF. + * Remaining NQs that belong to the PF are available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). + */ + uint16_t alloc_msix; + /* + * The number of registered VF’s associated with the PF. This field + * should be ignored when the request received on the VF interface. + * This field will be updated on the PF interface to initiate + * the unregister request on PF in the HOT Reset Process. + */ + uint16_t registered_vfs; + /* + * The size of the doorbell BAR in KBytes reserved for L2 including + * any area that is shared between L2 and RoCE. The L2 driver + * should only map the L2 portion of the doorbell BAR. Any rounding + * of the BAR size to the native CPU page size should be performed + * by the driver. If the value is zero, no special partitioning + * of the doorbell BAR between L2 and RoCE is required. + */ + uint16_t l2_doorbell_bar_size_kb; + uint8_t unused_1; + /* + * For backward compatibility this field must be set to 1. + * Older drivers might look for this field to be 1 before + * processing the message. + */ + uint8_t always_1; + /* + * This GRC address location is used by the Host driver interfaces to poll + * the adapter ready state to re-initiate the registration process again + * after receiving the RESET Notify event. + */ + uint32_t reset_addr_poll; + /* + * This field specifies legacy L2 doorbell size in KBytes. Drivers should use + * this value to find out the doorbell page offset from the BAR. + */ + uint16_t legacy_l2_db_size_kb; + uint16_t svif_info; + /* + * This field specifies the source virtual interface of the function being + * queried. Drivers can use this to program svif field in the L2 context + * table + */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 + /* This field specifies whether svif is valid or not */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) + uint8_t mpc_chnls; + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the TX crypto engine block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the RX crypto engine block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the TX configurable flow processing block is + * enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the RX configurable flow processing block is + * enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the primate processor block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ + UINT32_C(0x10) + uint8_t unused_2[3]; + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. + * The format of this field is defined to match min_bw, even though + * the partition minimum rate is always specified as a percentage. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Always percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Bandwidth value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though + * the partition bandwidth must be specified as a percentage. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Always a percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum transmission unit of the function + * configured by the host pf/vf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default + * value is used if ring MTU is not specified. + */ + uint16_t host_mtu; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_func_cfg * + *****************/ + + +/* hwrm_func_cfg_input (size:896b/112B) */ +struct hwrm_func_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + /* + * This field specifies how many NQs will be reserved for the PF. + * Remaining NQs that belong to the PF become available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). + */ + uint16_t num_msix; + uint32_t flags; + /* + * When this bit is '1', the function is disabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to disallow + * transmission of frames with the source MAC address that + * is configured for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ + UINT32_C(0x1) + /* + * When this bit is '1', the function is enabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to allow + * transmission of frames with the source MAC address that + * is configured for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ + UINT32_C(0x1fc) + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 + /* + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is requested to be + * enabled on the function being configured. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ + UINT32_C(0x200) + /* + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then the standard TX ring mode is requested to + * be disabled on the function being configured. In this extended + * TX ring resource mode, the minimum and maximum bandwidth settings + * are not supported to allow the allocation of TX rings to + * span multiple scheduler nodes. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ + UINT32_C(0x400) + /* + * If this bit is set, virtual mac address configured + * in this command will be persistent over warm boot. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ + UINT32_C(0x800) + /* + * This bit only applies to the VF. If this bit is set, the statistic + * context counters will not be cleared when the statistic context is freed + * or a function reset is called on VF. This bit will be cleared when the PF + * is unloaded or a function reset is called on the PF. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ + UINT32_C(0x1000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x2000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x4000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x8000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x10000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x20000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x40000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x80000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x100000) + /* + * This configuration change can be initiated by a PF driver. This + * configuration request shall be targeted to a VF. From local host + * resident HWRM clients, only the parent PF driver shall be allowed + * to initiate this change on one of its children VFs. If this bit is + * set to 1, then the VF that is being configured is requested to be + * trusted. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \ + UINT32_C(0x200000) + /* + * When this bit it set, even if PF reserved pool size is zero, + * FW will allow driver to create TX rings in ring alloc, + * by reserving TX ring, S3 node dynamically. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ + UINT32_C(0x400000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of NQ rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ + UINT32_C(0x800000) + /* + * This configuration change can be initiated by a PF driver. This + * configuration request shall be targeted to a VF. From local host + * resident HWRM clients, only the parent PF driver shall be allowed + * to initiate this change on one of its children VFs. If this bit is + * set to 1, then the VF that is being configured is requested to be + * untrusted. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \ + UINT32_C(0x1000000) + /* + * This bit is used by preboot drivers on a PF that require access + * to the legacy L2 ring model and legacy 32b doorbells. This + * feature is not allowed on VFs and is only relevant for devices + * that require a context backing store. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ + UINT32_C(0x2000000) + /* + * If this bit is set to 0, then the interface does not support hot + * reset capability which it advertised with the hot_reset_support + * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this + * flag to 0, adapter cannot do the hot reset. In this state, if the + * firmware receives a hot reset request, firmware must fail the + * request. If this bit is set to 1, then interface is renabling the + * hot reset capability. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \ + UINT32_C(0x4000000) + /* + * If this bit is set to 1, the PF driver is requesting FW + * to enable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the function. This flag is + * ignored if num_tx_rings field is not specified or the function + * doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x8000000) + /* + * If this bit is set to 1, the PF driver is requesting FW + * to disable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. This flag is ignored if num_tx_rings + * field is not specified or the function doesn't support PPP tx + * push feature. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x10000000) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \ + UINT32_C(0x20000000) + /* + * If this bit is set to 1, the driver is requesting FW to disable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \ + UINT32_C(0x40000000) + uint32_t enables; + /* + * This bit must be '1' for the admin_mtu field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ + UINT32_C(0x2) + /* + * This bit must be '1' for the num_rsscos_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + UINT32_C(0x4) + /* + * This bit must be '1' for the num_cmpl_rings field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + UINT32_C(0x8) + /* + * This bit must be '1' for the num_tx_rings field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + UINT32_C(0x10) + /* + * This bit must be '1' for the num_rx_rings field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + UINT32_C(0x20) + /* + * This bit must be '1' for the num_l2_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + UINT32_C(0x40) + /* + * This bit must be '1' for the num_vnics field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x80) + /* + * This bit must be '1' for the num_stat_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dflt_mac_addr field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x200) + /* + * This bit must be '1' for the dflt_vlan field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ + UINT32_C(0x400) + /* + * This bit must be '1' for the dflt_ip_addr field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ + UINT32_C(0x800) + /* + * This bit must be '1' for the min_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the max_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the async_event_cr field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the vlan_antispoof_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the allowed_vlan_pris field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the evb_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the num_mcast_filters field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the num_hw_ring_grps field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the cache_linesize field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ + UINT32_C(0x100000) + /* + * This bit must be '1' for the num_msix field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ + UINT32_C(0x200000) + /* + * This bit must be '1' for the link admin state field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ + UINT32_C(0x400000) + /* + * This bit must be '1' for the hot_reset_if_en_dis field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x800000) + /* + * This bit must be '1' for the schq_id field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x1000000) + /* + * This bit must be '1' for the mpc_chnls field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \ + UINT32_C(0x2000000) + /* + * This bit must be '1' for the partition_min_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \ + UINT32_C(0x4000000) + /* + * This bit must be '1' for the partition_max_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \ + UINT32_C(0x8000000) + /* + * This bit must be '1' for the tpid field to be + * configured. This bit is only valid when dflt_vlan enable + * bit is set. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \ + UINT32_C(0x10000000) + /* + * This bit must be '1' for the host_mtu field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ + UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) + /* + * This field can be used by the admin PF to configure + * mtu of foster PFs. + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t admin_mtu; + /* + * The maximum receive unit of the function. + * The HWRM should make sure that the mru of + * the function does not exceed the mru of the physical + * port that this function is associated with. + * + * In addition to configuring mru per function, it is + * possible to configure mru per vnic. + * By default, the mru of each vnic associated + * with a function is equal to the mru of the function. + * The HWRM should make sure that the mru of each vnic + * that is assigned to a function has a valid mru. + */ + uint16_t mru; + /* + * The number of RSS/COS contexts requested for the + * function. + */ + uint16_t num_rsscos_ctxs; + /* + * The number of completion rings requested for the + * function. This does not include the rings allocated + * to any children functions if any. + */ + uint16_t num_cmpl_rings; + /* + * The number of transmit rings requested for the function. + * This does not include the rings allocated to any + * children functions if any. + */ + uint16_t num_tx_rings; + /* + * The number of receive rings requested for the function. + * This does not include the rings allocated + * to any children functions if any. + */ + uint16_t num_rx_rings; + /* The requested number of L2 contexts for the function. */ + uint16_t num_l2_ctxs; + /* The requested number of vnics for the function. */ + uint16_t num_vnics; + /* The requested number of statistic contexts for the function. */ + uint16_t num_stat_ctxs; + /* + * The number of HW ring groups that should + * be reserved for this function. + */ + uint16_t num_hw_ring_grps; + /* The default MAC address for the function being configured. */ + uint8_t dflt_mac_addr[6]; + /* + * The default VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). + */ + uint16_t dflt_vlan; + /* + * The default IP address for the function being configured. + * This address is only used in enabling source property check. + */ + uint32_t dflt_ip_addr[4]; + /* + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. + */ + uint32_t min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. + */ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. + */ + uint16_t async_event_cr; + /* VLAN Anti-spoofing mode. */ + uint8_t vlan_antispoof_mode; + /* No VLAN anti-spoofing checks are enabled */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ + UINT32_C(0x0) + /* Validate VLAN against the configured VLAN(s) */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ + UINT32_C(0x1) + /* Insert VLAN if it does not exist, otherwise discard */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ + UINT32_C(0x2) + /* Insert VLAN if it does not exist, override VLAN if it exists */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN + /* + * This bit field defines VLAN PRIs that are allowed on + * this function. + * If nth bit is set, then VLAN PRI n is allowed on this + * function. + */ + uint8_t allowed_vlan_pris; + /* + * The evb_mode is configured on a per port basis. The default evb_mode + * is configured based on the NVM EVB mode setting upon firmware + * initialization. The HWRM allows a PF driver to change EVB mode for a + * port used by the PF only when one of the following conditions is + * satisfied. + * 1. The current operating mode is single function mode. + * (ie. one PF per port) + * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the + * EVB mode of the port used by the PAXC PF. None of the X86 PFs + * should have privileges. + * The HWRM doesn't permit any PFs to change the underlying EVB mode + * when running as MHB or NPAR mode in performance NIC configuration. + * The HWRM doesn't permit a VF driver to change the EVB mode. + * Once the HWRM determines a function doesn't meet the conditions + * to configure the EVB mode, it sets the evb_mode_cfg_not_supported + * flag in HWRM_FUNC_QCAPS command response for the function. + * The HWRM takes into account the switching of EVB mode from one to + * another and reconfigure hardware resources as reqiured. The + * switching from VEB to VEPA mode requires the disabling of the + * loopback traffic. Additionally, source knockouts are handled + * differently in VEB and VEPA modes. + */ + uint8_t evb_mode; + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA + uint8_t options; + /* + * This value indicates the PCIE device cache line size. + * The cache line size allows the DMA writes to terminate and + * start at the cache boundary. + */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + /* Cache Line Size 64 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ + UINT32_C(0x0) + /* Cache Line Size 128 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ + UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* This value is the virtual link admin state setting. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + UINT32_C(0xc) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin state is forced down. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + (UINT32_C(0x0) << 2) + /* Admin state is forced up. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + (UINT32_C(0x1) << 2) + /* Admin state is in auto mode - is to follow the physical link state. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + (UINT32_C(0x2) << 2) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO + /* Reserved for future. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4 + /* + * The number of multicast filters that should + * be reserved for this function on the RX side. + */ + uint16_t num_mcast_filters; + /* Used by a PF driver to associate a SCHQ with a VF. */ + uint16_t schq_id; + uint16_t mpc_chnls; + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the TX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the TX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the RX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the RX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the TX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \ + UINT32_C(0x10) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the TX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ + UINT32_C(0x20) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the RX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \ + UINT32_C(0x40) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the RX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ + UINT32_C(0x80) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the primate processor block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \ + UINT32_C(0x100) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the primate processor block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \ + UINT32_C(0x200) + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. The sum of the + * minimum bandwidths for all partitions on a link must not exceed + * 100%. + * The format of this field is defined to match min_bw, even though + * it does not allow all the options for min_bw at this time. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though it + * does not allow all the options for max_bw at this time. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The TPID for the function for which default VLAN + * is configured. If the dflt_vlan is not specified + * with the TPID, FW returns error. If the TPID is + * not specified with dflt_vlan, the default TPID of + * 0x8100 will be used. This field is specified in + * network byte order. + */ + uint16_t tpid; + /* + * This field can be used by the host PF to configure + * mtu value. + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_cfg_output (size:128b/16B) */ +struct hwrm_func_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_func_cfg_cmd_err (size:64b/8B) */ +struct hwrm_func_cfg_cmd_err { + /* command specific error codes for the cmd_err field in hwrm_err_output */ + uint8_t code; + /* Unknown error. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The partition minimum bandwidth is out of range. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \ + UINT32_C(0x1) + /* The minimum bandwidth is more than the maximum bandwidth. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \ + UINT32_C(0x2) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for a partition. + */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \ + UINT32_C(0x3) + /* Partition bandwidths must be specified as a percentage. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \ + UINT32_C(0x4) + #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \ + HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT + uint8_t unused_0[7]; +} __rte_packed; + +/******************** + * hwrm_func_qstats * + ********************/ + + +/* hwrm_func_qstats_input (size:192b/24B) */ +struct hwrm_func_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * A privileged PF can query for other function's statistics. + */ + uint16_t fid; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_func_qstats_output (size:1408b/176B) */ +struct hwrm_func_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of transmitted unicast packets on the function. */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets on the function. */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets on the function. */ + uint64_t tx_bcast_pkts; + /* + * Number of transmitted packets that were discarded due to + * internal NIC resource problems. For transmit, this + * can only happen if TMP is configured to allow dropping + * in HOL blocking conditions, which is not a normal + * configuration. + */ + uint64_t tx_discard_pkts; + /* + * Number of dropped packets on transmit path on the function. + * These are packets that have been marked for drop by + * the TE CFA block or are packets that exceeded the + * transmit MTU limit for the function. + */ + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic on the function. */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic on the function. */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic on the function. */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets on the function. */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets on the function. */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets on the function. */ + uint64_t rx_bcast_pkts; + /* + * Number of received packets that were discarded on the function + * due to resource limitations. This can happen for 3 reasons. + * # The BD used for the packet has a bad format. + * # There were no BDs available in the ring for the packet. + * # There were no BDs available on-chip for the packet. + */ + uint64_t rx_discard_pkts; + /* + * Number of dropped packets on received path on the function. + * These are packets that have been marked for drop by the + * RE CFA. + */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic on the function. */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic on the function. */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic on the function. */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets on the function. */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes on the function. */ + uint64_t rx_agg_bytes; + /* Number of aggregation events on the function. */ + uint64_t rx_agg_events; + /* Number of aborted aggregations on the function. */ + uint64_t rx_agg_aborts; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_func_qstats_ext * + ************************/ + + +/* hwrm_func_qstats_ext_input (size:256b/32B) */ +struct hwrm_func_qstats_ext_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * A privileged PF can query for other function's statistics. + */ + uint16_t fid; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[1]; + uint32_t enables; + /* + * This bit must be '1' for the schq_id and traffic_class fields to + * be configured. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1) + /* Specifies the SCHQ for which to gather statistics */ + uint16_t schq_id; + /* + * Specifies the traffic class for which to gather statistics. Valid + * values are 0 through (max_configurable_queues - 1), where + * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG + */ + uint16_t traffic_class; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_qstats_ext_output (size:1536b/192B) */ +struct hwrm_func_qstats_ext_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on received path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + /* Number of TPA errors */ + uint64_t rx_tpa_events; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_clr_stats * + ***********************/ + + +/* hwrm_func_clr_stats_input (size:192b/24B) */ +struct hwrm_func_clr_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_clr_stats_output (size:128b/16B) */ +struct hwrm_func_clr_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_vf_resc_free * + **************************/ + + +/* hwrm_func_vf_resc_free_input (size:192b/24B) */ +struct hwrm_func_vf_resc_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vf_resc_free_output (size:128b/16B) */ +struct hwrm_func_vf_resc_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_drv_rgtr * + **********************/ + + +/* hwrm_func_drv_rgtr_input (size:896b/112B) */ +struct hwrm_func_drv_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the function driver is requesting + * all requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \ + UINT32_C(0x1) + /* + * When this bit is '1', the function is requesting none of + * the requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \ + UINT32_C(0x2) + /* + * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be ignored and ver_maj, ver_min, ver_upd + * and ver_patch shall be used for the driver version information. + * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be used for the driver version information and + * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the function is indicating support of + * 64bit flow handle. The firmware that only supports 64bit flow + * handle should check this bit before allowing processing of + * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware + * with 64bit flow handle support can only be compatible with drivers + * that support 64bit flow handle. The legacy drivers that don't support + * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when + * running with new firmware that only supports 64bit flow handle. The new + * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * status to the legacy driver when encounters these commands. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ + UINT32_C(0x8) + /* + * When this bit is '1', the function is indicating support of + * Hot Reset. The driver interface will destroy the resources, + * unregister the function and register again up on receiving + * the RESET_NOTIFY Async notification from the core firmware. + * The core firmware will this use flag and trigger the Hot Reset + * process only if all the registered driver instances are capable + * of this support. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \ + UINT32_C(0x10) + /* + * When this bit is 1, the function is indicating the support of the + * error recovery capability. Error recovery support will be used by + * firmware only if all the driver instances support error recovery + * process. By setting this bit, driver is indicating support for + * corresponding async event completion message. These will be + * delivered to the driver even if they did not register for it. + * If supported, after receiving reset notify async event with fatal + * flag set in event data1, then all the drivers have to tear down + * their resources without sending any HWRM commands to FW. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \ + UINT32_C(0x20) + /* + * When this bit is 1, the function is indicating the support of the + * Master capability. The Firmware will use this capability to select the + * Master function. The master function will be used to initiate + * designated functionality like error recovery etc… If none of the + * registered PF’s or trusted VF’s indicate this support, then + * firmware will select the 1st registered PF as Master capable instance. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ + UINT32_C(0x40) + /* + * When this bit is 1, the function is indicating the support of the + * fast reset capability. Fast reset support will be used by + * firmware only if all the driver instances support fast reset + * process. By setting this bit, driver is indicating support for + * corresponding async event completion message. These will be + * delivered to the driver even if they did not register for it. + * If supported, after receiving reset notify async event with fast + * reset flag set in event data1, then all the drivers have to tear + * down their resources without sending any HWRM commands to FW. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \ + UINT32_C(0x80) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the vnic_rss_cfg's INVALID_PARAM error + * returned by firmware. Firmware returns error, if host driver + * configures the invalid hash_types bit combination for a given + * IP version. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ + UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) + uint32_t enables; + /* + * This bit must be '1' for the os_type field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ver field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ + UINT32_C(0x2) + /* + * This bit must be '1' for the timestamp field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vf_req_fwd field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the async_event_fwd field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ + UINT32_C(0x10) + /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + uint16_t os_type; + /* Unknown */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + /* UEFI driver. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI + /* This is the 8bit major version of the driver. */ + uint8_t ver_maj_8b; + /* This is the 8bit minor version of the driver. */ + uint8_t ver_min_8b; + /* This is the 8bit update version of the driver. */ + uint8_t ver_upd_8b; + uint8_t unused_0[3]; + /* + * This is a 32-bit timestamp provided by the driver for + * keep alive. + * The timestamp is in multiples of 1ms. + */ + uint32_t timestamp; + uint8_t unused_1[4]; + /* + * This is a 256-bit bit mask provided by the PF driver for + * letting the HWRM know what commands issued by the VF driver + * to the HWRM should be forwarded to the PF driver. + * Nth bit refers to the Nth req_type. + * + * Setting Nth bit to 1 indicates that requests from the + * VF driver with req_type equal to N shall be forwarded to + * the parent PF driver. + * + * This field is not valid for the VF driver. + */ + uint32_t vf_req_fwd[8]; + /* + * This is a 256-bit bit mask provided by the function driver + * (PF or VF driver) to indicate the list of asynchronous event + * completions to be forwarded. + * + * Nth bit refers to the Nth event_id. + * + * Setting Nth bit to 1 by the function driver shall result in + * the HWRM forwarding asynchronous event completion with + * event_id equal to N. + * + * If all bits are set to 0 (value of 0), then the HWRM shall + * not forward any asynchronous event completion to this + * function driver. + */ + uint32_t async_event_fwd[8]; + /* This is the 16bit major version of the driver. */ + uint16_t ver_maj; + /* This is the 16bit minor version of the driver. */ + uint16_t ver_min; + /* This is the 16bit update version of the driver. */ + uint16_t ver_upd; + /* This is the 16bit patch version of the driver. */ + uint16_t ver_patch; +} __rte_packed; + +/* hwrm_func_drv_rgtr_output (size:128b/16B) */ +struct hwrm_func_drv_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', it indicates that the + * HWRM_FUNC_DRV_IF_CHANGE call is supported. + */ + #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \ + UINT32_C(0x1) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_func_drv_unrgtr * + ************************/ + + +/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ +struct hwrm_func_drv_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the function driver is notifying + * the HWRM to prepare for the shutdown. + */ + #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ + UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ +struct hwrm_func_drv_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_buf_rgtr * + **********************/ + + +/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ +struct hwrm_func_buf_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id field to be + * configured. + */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + /* + * This bit must be '1' for the err_buf_addr field to be + * configured. + */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + /* + * This field represents the number of pages used for request + * buffer(s). + */ + uint16_t req_buf_num_pages; + /* + * This field represents the page size used for request + * buffer(s). + */ + uint16_t req_buf_page_size; + /* 16 bytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) + /* 4 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) + /* 8 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) + /* 64 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) + /* 2 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) + /* 4 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) + /* 1 Gbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ + HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G + /* The length of the request buffer per VF in bytes. */ + uint16_t req_buf_len; + /* The length of the response buffer in bytes. */ + uint16_t resp_buf_len; + uint8_t unused_0[2]; + /* This field represents the page address of page #0. */ + uint64_t req_buf_page_addr0; + /* This field represents the page address of page #1. */ + uint64_t req_buf_page_addr1; + /* This field represents the page address of page #2. */ + uint64_t req_buf_page_addr2; + /* This field represents the page address of page #3. */ + uint64_t req_buf_page_addr3; + /* This field represents the page address of page #4. */ + uint64_t req_buf_page_addr4; + /* This field represents the page address of page #5. */ + uint64_t req_buf_page_addr5; + /* This field represents the page address of page #6. */ + uint64_t req_buf_page_addr6; + /* This field represents the page address of page #7. */ + uint64_t req_buf_page_addr7; + /* This field represents the page address of page #8. */ + uint64_t req_buf_page_addr8; + /* This field represents the page address of page #9. */ + uint64_t req_buf_page_addr9; + /* + * This field is used to receive the error reporting from + * the chipset. Only applicable for PFs. + */ + uint64_t error_buf_addr; + /* + * This field is used to receive the response forwarded by the + * HWRM. + */ + uint64_t resp_buf_addr; +} __rte_packed; + +/* hwrm_func_buf_rgtr_output (size:128b/16B) */ +struct hwrm_func_buf_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_func_buf_unrgtr * + ************************/ + + +/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ +struct hwrm_func_buf_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id field to be + * configured. + */ + #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ +struct hwrm_func_buf_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_drv_qver * + **********************/ + + +/* hwrm_func_drv_qver_input (size:192b/24B) */ +struct hwrm_func_drv_qver_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Reserved for future use. */ + uint32_t reserved; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_drv_qver_output (size:256b/32B) */ +struct hwrm_func_drv_qver_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + uint16_t os_type; + /* Unknown */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + /* UEFI driver. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI + /* This is the 8bit major version of the driver. */ + uint8_t ver_maj_8b; + /* This is the 8bit minor version of the driver. */ + uint8_t ver_min_8b; + /* This is the 8bit update version of the driver. */ + uint8_t ver_upd_8b; + uint8_t unused_0[3]; + /* This is the 16bit major version of the driver. */ + uint16_t ver_maj; + /* This is the 16bit minor version of the driver. */ + uint16_t ver_min; + /* This is the 16bit update version of the driver. */ + uint16_t ver_upd; + /* This is the 16bit patch version of the driver. */ + uint16_t ver_patch; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_func_resource_qcaps * + ****************************/ + + +/* hwrm_func_resource_qcaps_input (size:192b/24B) */ +struct hwrm_func_resource_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ +struct hwrm_func_resource_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + uint16_t max_vfs; + /* Maximum guaranteed number of MSI-X vectors supported by function */ + uint16_t max_msix; + /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + uint16_t vf_reservation_strategy; + /* The PF driver should evenly divide its remaining resources among all VFs. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ + UINT32_C(0x0) + /* The PF driver should only reserve minimal resources for each VF. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ + UINT32_C(0x1) + /* + * The PF driver should not reserve any resources for each VF until + * the VF interface is brought up. + */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ + UINT32_C(0x2) + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; + /* + * Maximum number of inputs into the transmit scheduler for this function. + * The number of TX rings assigned to the function cannot exceed this value. + */ + uint16_t max_tx_scheduler_inputs; + uint16_t flags; + /* + * When this bit is '1', it indicates that VF_RESOURCE_CFG supports + * feature to reserve all minimum resources when minimum >= 1, otherwise + * returns an error. + */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ + UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_func_vf_resource_cfg * + *****************************/ + + +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ +struct hwrm_func_vf_resource_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF ID that is being configured by PF */ + uint16_t vf_id; + /* Maximum guaranteed number of MSI-X vectors for the function */ + uint16_t max_msix; + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; + uint16_t flags; + /* + * If this bit is set, all minimum resources requested should be + * reserved if minimum >= 1, otherwise return error. In case of + * error, keep all existing reservations before the call. + */ + #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ + UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ +struct hwrm_func_vf_resource_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved number of RSS/COS contexts */ + uint16_t reserved_rsscos_ctx; + /* Reserved number of completion rings */ + uint16_t reserved_cmpl_rings; + /* Reserved number of transmit rings */ + uint16_t reserved_tx_rings; + /* Reserved number of receive rings */ + uint16_t reserved_rx_rings; + /* Reserved number of L2 contexts */ + uint16_t reserved_l2_ctxs; + /* Reserved number of VNICs */ + uint16_t reserved_vnics; + /* Reserved number of statistic contexts */ + uint16_t reserved_stat_ctx; + /* Reserved number of ring groups */ + uint16_t reserved_hw_ring_grps; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_func_backing_store_qcaps * + *********************************/ + + +/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ +struct hwrm_func_backing_store_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ +struct hwrm_func_backing_store_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum number of QP context entries supported for this function. */ + uint32_t qp_max_entries; + /* + * Minimum number of QP context entries that are needed to be reserved + * for QP1 for the PF and its VFs. PF drivers must allocate at least + * this many QP context entries, even if RoCE will not be used. + */ + uint16_t qp_min_qp1_entries; + /* + * Maximum number of QP context entries that can be used for L2 and + * mid-path. + */ + uint16_t qp_max_l2_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t qp_entry_size; + /* Maximum number of SRQ context entries that can be used for L2. */ + uint16_t srq_max_l2_entries; + /* Maximum number of SRQ context entries supported for this function. */ + uint32_t srq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t srq_entry_size; + /* Maximum number of CQ context entries that can be used for L2. */ + uint16_t cq_max_l2_entries; + /* Maximum number of CQ context entries supported for this function. */ + uint32_t cq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t cq_entry_size; + /* Maximum number of VNIC context entries supported for this function. */ + uint16_t vnic_max_vnic_entries; + /* Maximum number of Ring table context entries supported for this function. */ + uint16_t vnic_max_ring_table_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t vnic_entry_size; + /* Maximum number of statistic context entries supported for this function. */ + uint32_t stat_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t stat_entry_size; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tqm_entry_size; + /* Minimum number of TQM context entries required per ring. */ + uint32_t tqm_min_entries_per_ring; + /* + * Maximum number of TQM context entries supported per ring. This is + * actually a recommended TQM queue size based on worst case usage of + * the TQM queue. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * TQM slowpath rings should be sized as follows: + * + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size + * + * Where: + * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_l2_tx_rings is the number of L2 rings in the QP backing store + * num_roce_qps is the number of RoCE QPs in the QP backing store + * tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_max_entries_per_ring; + /* + * Maximum number of MR plus AV context entries supported for this + * function. + */ + uint32_t mrav_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t mrav_entry_size; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tim_entry_size; + /* Maximum number of Timer context entries supported for this function. */ + uint32_t tim_max_entries; + /* + * When this field is zero, the 32b `mrav_num_entries` field in the + * `backing_store_cfg` and `backing_store_qcfg` commands represents + * the total number of MR plus AV entries allowed in the MR/AV backing + * store PBL. + * + * When this field is non-zero, the 32b `mrav_num_entries` field in + * the `backing_store_cfg` and `backing_store_qcfg` commands is + * logically divided into two 16b fields. Bits `[31:16]` represents + * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`. + * Both of these values are represented in a unit granularity + * specified by this field. For example, if this field is 16 and + * `mrav_num_entries` is `0x02000100`, then the number of MR entries + * is 8192 and the number of AV entries is 4096. + */ + uint16_t mrav_num_entries_units; + /* + * The number of entries specified for any TQM ring must be a + * multiple of this value to prevent any resource allocation + * limitations. + */ + uint8_t tqm_entries_multiple; + /* + * Initializer to be used by drivers + * to initialize context memory to ensure + * context subsystem flags an error for an attack + * before the first time context load. + */ + uint8_t ctx_kind_initializer; + /* + * Specifies which context kinds need to be initialized with the + * ctx_kind_initializer. + */ + uint16_t ctx_init_mask; + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \ + UINT32_C(0x1) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \ + UINT32_C(0x2) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \ + UINT32_C(0x4) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \ + UINT32_C(0x8) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \ + UINT32_C(0x10) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \ + UINT32_C(0x20) + /* + * If this bit is '1' then the Tx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \ + UINT32_C(0x40) + /* + * If this bit is '1' then the Rx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \ + UINT32_C(0x80) + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t qp_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t srq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t cq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t vnic_init_offset; + /* + * Count of TQM fastpath rings to be used for allocating backing store. + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + * Only first 8 TQM FP rings will be advertised with this field. + */ + uint8_t tqm_fp_rings_count; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t stat_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t mrav_init_offset; + /* + * Count of TQM extended fastpath rings to be used for allocating + * backing store beyond 8 rings(rings 9,10,11) + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count_ext; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Tx + * KTLS context type. + */ + uint8_t tkc_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Rx + * KTLS context type. + */ + uint8_t rkc_init_offset; + /* Tx KTLS context entry size in bytes. */ + uint16_t tkc_entry_size; + /* Rx KTLS context entry size in bytes. */ + uint16_t rkc_entry_size; + /* + * Maximum number of Tx KTLS context entries supported for this + * function. + */ + uint32_t tkc_max_entries; + /* + * Maximum number of Rx KTLS context entries supported for this + * function. + */ + uint32_t rkc_max_entries; + /* Reserved for future. */ + uint8_t rsvd1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* tqm_fp_ring_cfg (size:128b/16B) */ +struct tqm_fp_ring_cfg { + /* TQM ring page size and level. */ + uint8_t tqm_ring_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 + /* 4KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G + uint8_t unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring_page_dir; +} __rte_packed; + +/******************************* + * hwrm_func_backing_store_cfg * + *******************************/ + + +/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ +struct hwrm_func_backing_store_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and does not + * expect any backing store to be provided by the host driver. This + * mode provides minimal L2 functionality (e.g. limited L2 resources, + * no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* + * When set, the 32b `mrav_num_entries` field is logically divided + * into two 16b fields, `mr_num_entries` and `av_num_entries`. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \ + UINT32_C(0x2) + uint32_t enables; + /* + * This bit must be '1' for the qp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the srq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vnic fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ + UINT32_C(0x8) + /* + * This bit must be '1' for the stat fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ + UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_sp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ + UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ + UINT32_C(0x80) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ + UINT32_C(0x100) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ + UINT32_C(0x400) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ + UINT32_C(0x800) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the mrav fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the tim fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \ + UINT32_C(0x100000) + /* QPC page size and level. */ + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 + /* QPC page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G + /* SRQ page size and level. */ + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G + /* CQ page size and level. */ + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 + /* CQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G + /* VNIC page size and level. */ + uint8_t vnic_pg_size_vnic_lvl; + /* VNIC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 + /* VNIC page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G + /* Stat page size and level. */ + uint8_t stat_pg_size_stat_lvl; + /* Stat PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 + /* Stat page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G + /* TQM slow path page size and level. */ + uint8_t tqm_sp_pg_size_tqm_sp_lvl; + /* TQM slow path PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 + /* TQM slow path page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* MR/AV page size and level. */ + uint8_t mrav_pg_size_mrav_lvl; + /* MR/AV PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 + /* MR/AV page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G + /* Timer page size and level. */ + uint8_t tim_pg_size_tim_lvl; + /* Timer PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 + /* Timer page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G + /* QP page directory. */ + uint64_t qpc_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* VNIC page directory. */ + uint64_t vnic_page_dir; + /* Stat page directory. */ + uint64_t stat_page_dir; + /* TQM slowpath page directory. */ + uint64_t tqm_sp_page_dir; + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* MR/AV page directory. */ + uint64_t mrav_page_dir; + /* Timer page directory. */ + uint64_t tim_page_dir; + /* Number of QPs. */ + uint32_t qp_num_entries; + /* Number of SRQs. */ + uint32_t srq_num_entries; + /* Number of CQs. */ + uint32_t cq_num_entries; + /* Number of Stats. */ + uint32_t stat_num_entries; + /* + * Number of TQM slowpath entries. + * + * TQM slowpath rings should be sized as follows: + * + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size + * + * Where: + * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_l2_tx_rings is the number of L2 rings in the QP backing store + * num_roce_qps is the number of RoCE QPs in the QP backing store + * tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_sp_num_entries; + /* + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring0_num_entries; + /* + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring1_num_entries; + /* + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring2_num_entries; + /* + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring3_num_entries; + /* + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring4_num_entries; + /* + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring5_num_entries; + /* + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring6_num_entries; + /* + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_ring7_num_entries; + /* + * If the MR/AV split reservation flag is not set, then this field + * represents the total number of MR plus AV entries. For versions + * of firmware that support the split reservation, when it is not + * specified half of the entries will be reserved for MRs and the + * other half for AVs. + * + * If the MR/AV split reservation flag is set, then this + * field is logically divided into two 16b fields. Bits `[31:16]` + * represents the `mr_num_entries` and bits `[15:0]` represents + * `av_num_entries`. The granularity of these values is defined by + * the `mrav_num_entries_unit` field returned by the + * `backing_store_qcaps` command. + */ + uint32_t mrav_num_entries; + /* Number of Timer entries. */ + uint32_t tim_num_entries; + /* Number of entries to reserve for QP1 */ + uint16_t qp_num_qp1_entries; + /* Number of entries to reserve for L2 */ + uint16_t qp_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t qp_entry_size; + /* Number of entries to reserve for L2 */ + uint16_t srq_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t srq_entry_size; + /* Number of entries to reserve for L2 */ + uint16_t cq_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t cq_entry_size; + /* Number of entries to reserve for VNIC entries */ + uint16_t vnic_num_vnic_entries; + /* Number of entries to reserve for Ring table entries */ + uint16_t vnic_num_ring_table_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t vnic_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t stat_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t mrav_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tim_entry_size; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries allocated. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries allocated. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Number of bytes allocated for each Tx KTLS context entry. */ + uint16_t tkc_entry_size; + /* Number of bytes allocated for each Rx KTLS context entry. */ + uint16_t rkc_entry_size; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G + /* Reserved for future. */ + uint8_t rsvd[2]; +} __rte_packed; + +/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_func_backing_store_qcfg * + ********************************/ + + +/* hwrm_func_backing_store_qcfg_input (size:128b/16B) */ +struct hwrm_func_backing_store_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */ +struct hwrm_func_backing_store_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and does not + * expect any backing store to be provided by the host driver. This + * mode provides minimal L2 functionality (e.g. limited L2 resources, + * no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* + * When set, the 32b `mrav_num_entries` field is logically divided + * into two 16b fields, `mr_num_entries` and `av_num_entries`. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \ + UINT32_C(0x2) + uint32_t enables; + /* + * This bit must be '1' for the qp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the srq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vnic fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \ + UINT32_C(0x8) + /* + * This bit must be '1' for the stat fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \ + UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_sp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \ + UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \ + UINT32_C(0x80) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \ + UINT32_C(0x100) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \ + UINT32_C(0x400) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \ + UINT32_C(0x800) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the mrav fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the tim fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \ + UINT32_C(0x100000) + /* QPC page size and level. */ + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 + /* QPC page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G + /* SRQ page size and level. */ + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G + /* CQ page size and level. */ + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 + /* CQ page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G + /* VNIC page size and level. */ + uint8_t vnic_pg_size_vnic_lvl; + /* VNIC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 + /* VNIC page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G + /* Stat page size and level. */ + uint8_t stat_pg_size_stat_lvl; + /* Stat PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 + /* Stat page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G + /* TQM slow path page size and level. */ + uint8_t tqm_sp_pg_size_tqm_sp_lvl; + /* TQM slow path PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 + /* TQM slow path page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G - /* VNIC page size and level. */ - uint8_t vnic_pg_size_vnic_lvl; - /* VNIC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 - /* VNIC page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G - /* Stat page size and level. */ - uint8_t stat_pg_size_stat_lvl; - /* Stat PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 - /* Stat page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G - /* TQM slow path page size and level. */ - uint8_t tqm_sp_pg_size_tqm_sp_lvl; - /* TQM slow path PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 - /* TQM slow path page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G - /* TQM ring 0 page size and level. */ - uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; - /* TQM ring 0 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 - /* TQM ring 0 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G - /* TQM ring 1 page size and level. */ - uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; - /* TQM ring 1 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 - /* TQM ring 1 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G - /* TQM ring 2 page size and level. */ - uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; - /* TQM ring 2 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G + /* MR/AV page size and level. */ + uint8_t mrav_pg_size_mrav_lvl; + /* MR/AV PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 + /* MR/AV page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G + /* Timer page size and level. */ + uint8_t tim_pg_size_tim_lvl; + /* Timer PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 + /* Timer page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G + /* QP page directory. */ + uint64_t qpc_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* VNIC page directory. */ + uint64_t vnic_page_dir; + /* Stat page directory. */ + uint64_t stat_page_dir; + /* TQM slowpath page directory. */ + uint64_t tqm_sp_page_dir; + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* MR/AV page directory. */ + uint64_t mrav_page_dir; + /* Timer page directory. */ + uint64_t tim_page_dir; + /* Number of entries to reserve for QP1 */ + uint16_t qp_num_qp1_entries; + /* Number of entries to reserve for L2 */ + uint16_t qp_num_l2_entries; + /* Number of QPs. */ + uint32_t qp_num_entries; + /* Number of SRQs. */ + uint32_t srq_num_entries; + /* Number of entries to reserve for L2 */ + uint16_t srq_num_l2_entries; + /* Number of entries to reserve for L2 */ + uint16_t cq_num_l2_entries; + /* Number of CQs. */ + uint32_t cq_num_entries; + /* Number of entries to reserve for VNIC entries */ + uint16_t vnic_num_vnic_entries; + /* Number of entries to reserve for Ring table entries */ + uint16_t vnic_num_ring_table_entries; + /* Number of Stats. */ + uint32_t stat_num_entries; + /* Number of TQM slowpath entries. */ + uint32_t tqm_sp_num_entries; + /* Number of TQM ring 0 entries. */ + uint32_t tqm_ring0_num_entries; + /* Number of TQM ring 1 entries. */ + uint32_t tqm_ring1_num_entries; + /* Number of TQM ring 2 entries. */ + uint32_t tqm_ring2_num_entries; + /* Number of TQM ring 3 entries. */ + uint32_t tqm_ring3_num_entries; + /* Number of TQM ring 4 entries. */ + uint32_t tqm_ring4_num_entries; + /* Number of TQM ring 5 entries. */ + uint32_t tqm_ring5_num_entries; + /* Number of TQM ring 6 entries. */ + uint32_t tqm_ring6_num_entries; + /* Number of TQM ring 7 entries. */ + uint32_t tqm_ring7_num_entries; + /* + * If the MR/AV split reservation flag is not set, then this field + * represents the total number of MR plus AV entries. For versions + * of firmware that support the split reservation, when it is not + * specified half of the entries will be reserved for MRs and the + * other half for AVs. + * + * If the MR/AV split reservation flag is set, then this + * field is logically divided into two 16b fields. Bits `[31:16]` + * represents the `mr_num_entries` and bits `[15:0]` represents + * `av_num_entries`. The granularity of these values is defined by + * the `mrav_num_entries_unit` field returned by the + * `backing_store_qcaps` command. + */ + uint32_t mrav_num_entries; + /* Number of Timer entries. */ + uint32_t tim_num_entries; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \ + 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 - /* TQM ring 2 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G - /* TQM ring 3 page size and level. */ - uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; - /* TQM ring 3 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \ + 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 - /* TQM ring 3 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G - /* TQM ring 4 page size and level. */ - uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; - /* TQM ring 4 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \ + 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 - /* TQM ring 4 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G - /* TQM ring 5 page size and level. */ - uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; - /* TQM ring 5 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 - /* TQM ring 5 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G - /* TQM ring 6 page size and level. */ - uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; - /* TQM ring 6 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 - /* TQM ring 6 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G - /* TQM ring 7 page size and level. */ - uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; - /* TQM ring 7 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G + uint8_t unused_1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as 1 + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_error_recovery_qcfg * + ****************************/ + + +/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ +struct hwrm_error_recovery_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ +struct hwrm_error_recovery_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this flag is set to 1, error recovery will be initiated + * through master function driver. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1) + /* + * When this flag is set to 1, error recovery will be performed + * through Co processor. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2) + /* + * Driver Polling frequency. This value is in units of 100msec. + * Typical value would be 10 to indicate 1sec. + * Drivers can poll FW health status, Heartbeat, reset_counter with + * this frequency. + */ + uint32_t driver_polling_freq; + /* + * This value is in units of 100msec. + * Typical value would be 30 to indicate 3sec. + * Master function wait period from detecting a fatal error to + * initiating reset. In this time period Master PF expects every + * active driver will detect fatal error. + */ + uint32_t master_func_wait_period; + /* + * This value is in units of 100msec. + * Typical value would be 50 to indicate 5sec. + * Normal function wait period from fatal error detection to + * polling FW health status. In this time period, drivers should not + * do any PCIe MMIO transaction and should not send any HWRM commands. + */ + uint32_t normal_func_wait_period; + /* + * This value is in units of 100msec. + * Typical value would be 20 to indicate 2sec. + * This field indicates that, master function wait period after chip + * reset. After this time, master function should reinitialize with + * FW. + */ + uint32_t master_func_wait_period_after_reset; + /* + * This value is in units of 100msec. + * Typical value would be 60 to indicate 6sec. + * This field is applicable to both master and normal functions. + * Even after chip reset, if FW status not changed to ready, + * then all the functions can poll for this much time and bailout. + */ + uint32_t max_bailout_time_after_reset; + /* + * FW health status register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates upper 30bits of the register address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_health_status_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \ + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \ + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 - /* TQM ring 7 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G - /* MR/AV page size and level. */ - uint8_t mrav_pg_size_mrav_lvl; - /* MR/AV PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \ + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \ + 2 + /* + * FW HeartBeat register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_heartbeat_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \ + 2 + /* + * FW reset counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_reset_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \ + 2 + /* + * Reset Inprogress Register address for PFs. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t reset_inprogress_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \ + 2 + /* This field indicates the mask value for reset_inprogress_reg. */ + uint32_t reset_inprogress_reg_mask; + uint8_t unused_0[3]; + /* + * Array of registers and value count to reset the Chip + * Each array count has reset_reg, reset_reg_val, delay_after_reset + * in TLV format. Depending upon Chip type, number of reset registers + * will vary. Drivers have to write reset_reg_val in the reset_reg + * location in the same sequence in order to recover from a fatal + * error. + */ + uint8_t reg_array_cnt; + /* + * Reset register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t reset_reg[16]; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \ + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \ + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 - /* MR/AV page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G - /* Timer page size and level. */ - uint8_t tim_pg_size_tim_lvl; - /* Timer PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \ + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2 + /* Value to be written in reset_reg to reset the controller. */ + uint32_t reset_reg_val[16]; + /* + * This value is in units of 1msec. + * Typical value would be 10 to indicate 10msec. + * Some of the operations like Core reset require delay before + * accessing PCIE MMIO register space. + * If this value is non-zero, drivers have to wait for + * this much time after writing reset_reg_val in reset_reg. + */ + uint8_t delay_after_reset[16]; + /* + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \ + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \ + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 - /* Timer page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G - /* QP page directory. */ - uint64_t qpc_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* VNIC page directory. */ - uint64_t vnic_page_dir; - /* Stat page directory. */ - uint64_t stat_page_dir; - /* TQM slowpath page directory. */ - uint64_t tqm_sp_page_dir; - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; - /* MR/AV page directory. */ - uint64_t mrav_page_dir; - /* Timer page directory. */ - uint64_t tim_page_dir; - /* Number of QPs. */ - uint32_t qp_num_entries; - /* Number of SRQs. */ - uint32_t srq_num_entries; - /* Number of CQs. */ - uint32_t cq_num_entries; - /* Number of Stats. */ - uint32_t stat_num_entries; /* - * Number of TQM slowpath entries. - * - * TQM slowpath rings should be sized as follows: - * - * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size - * - * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. */ - uint32_t tqm_sp_num_entries; + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; /* - * Number of TQM ring 0 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ - uint32_t tqm_ring0_num_entries; + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_echo_response * + ***************************/ + + +/* hwrm_func_echo_response_input (size:192b/24B) */ +struct hwrm_func_echo_response_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Number of TQM ring 1 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t tqm_ring1_num_entries; + uint16_t cmpl_ring; /* - * Number of TQM ring 2 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t tqm_ring2_num_entries; + uint16_t seq_id; /* - * Number of TQM ring 3 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t tqm_ring3_num_entries; + uint16_t target_id; /* - * Number of TQM ring 4 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t tqm_ring4_num_entries; + uint64_t resp_addr; + uint32_t event_data1; + uint32_t event_data2; +} __rte_packed; + +/* hwrm_func_echo_response_output (size:128b/16B) */ +struct hwrm_func_echo_response_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Number of TQM ring 5 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t tqm_ring5_num_entries; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ + + +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Number of TQM ring 6 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t tqm_ring6_num_entries; + uint16_t cmpl_ring; /* - * Number of TQM ring 7 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t tqm_ring7_num_entries; + uint16_t seq_id; /* - * If the MR/AV split reservation flag is not set, then this field - * represents the total number of MR plus AV entries. For versions - * of firmware that support the split reservation, when it is not - * specified half of the entries will be reserved for MRs and the - * other half for AVs. - * - * If the MR/AV split reservation flag is set, then this - * field is logically divided into two 16b fields. Bits `[31:16]` - * represents the `mr_num_entries` and bits `[15:0]` represents - * `av_num_entries`. The granularity of these values is defined by - * the `mrav_num_entries_unit` field returned by the - * `backing_store_qcaps` command. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t mrav_num_entries; - /* Number of Timer entries. */ - uint32_t tim_num_entries; - /* Number of entries to reserve for QP1 */ - uint16_t qp_num_qp1_entries; - /* Number of entries to reserve for L2 */ - uint16_t qp_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t qp_entry_size; - /* Number of entries to reserve for L2 */ - uint16_t srq_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t srq_entry_size; - /* Number of entries to reserve for L2 */ - uint16_t cq_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t cq_entry_size; - /* Number of entries to reserve for VNIC entries */ - uint16_t vnic_num_vnic_entries; - /* Number of entries to reserve for Ring table entries */ - uint16_t vnic_num_ring_table_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t vnic_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t stat_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t tqm_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t mrav_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t tim_entry_size; + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. + */ + uint8_t num_pins; + /* Pin state */ + uint8_t state; + /* + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ + + +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the pin0_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the pin0_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the pin1_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the pin1_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) + /* + * This bit must be '1' for the pin2_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the pin2_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the pin3_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) + /* + * This bit must be '1' for the pin3_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ -struct hwrm_func_backing_store_cfg_output { +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -12982,13 +20870,13 @@ struct hwrm_func_backing_store_cfg_output { uint8_t valid; } __rte_packed; -/******************************** - * hwrm_func_backing_store_qcfg * - ********************************/ +/********************* + * hwrm_func_ptp_cfg * + *********************/ -/* hwrm_func_backing_store_qcfg_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcfg_input { +/* hwrm_func_ptp_cfg_input (size:384b/48B) */ +struct hwrm_func_ptp_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13017,892 +20905,1065 @@ struct hwrm_func_backing_store_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; - -/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ -struct hwrm_func_backing_store_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; - /* - * When set, the firmware only uses on-chip resources and does not - * expect any backing store to be provided by the host driver. This - * mode provides minimal L2 functionality (e.g. limited L2 resources, - * no RoCE). - */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \ - UINT32_C(0x1) - /* - * When set, the 32b `mrav_num_entries` field is logically divided - * into two 16b fields, `mr_num_entries` and `av_num_entries`. - */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \ - UINT32_C(0x2) - uint8_t unused_0[4]; + uint16_t enables; /* - * This bit must be '1' for the qp fields to be + * This bit must be '1' for the ptp_pps_event field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ UINT32_C(0x1) /* - * This bit must be '1' for the srq fields to be + * This bit must be '1' for the ptp_freq_adj_dll_source field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ UINT32_C(0x2) /* - * This bit must be '1' for the cq fields to be + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ UINT32_C(0x4) /* - * This bit must be '1' for the vnic fields to be + * This bit must be '1' for the ptp_freq_adj_ext_period field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ UINT32_C(0x8) /* - * This bit must be '1' for the stat fields to be + * This bit must be '1' for the ptp_freq_adj_ext_up field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ UINT32_C(0x10) /* - * This bit must be '1' for the tqm_sp fields to be + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ UINT32_C(0x20) + /* This bit must be '1' for ptp_set_time field to be configured. */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME \ + UINT32_C(0x40) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; /* - * This bit must be '1' for the tqm_ring0 fields to be - * configured. + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \ - UINT32_C(0x40) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) /* - * This bit must be '1' for the tqm_ring1 fields to be - * configured. + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \ - UINT32_C(0x80) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) /* - * This bit must be '1' for the tqm_ring2 fields to be - * configured. + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \ - UINT32_C(0x100) + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID /* - * This bit must be '1' for the tqm_ring3 fields to be - * configured. + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \ - UINT32_C(0x200) + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; /* - * This bit must be '1' for the tqm_ring4 fields to be - * configured. + * Period in nanoseconds (ns) for external signal + * input. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \ - UINT32_C(0x400) + uint32_t ptp_freq_adj_ext_period; /* - * This bit must be '1' for the tqm_ring5 fields to be - * configured. + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \ - UINT32_C(0x800) + uint32_t ptp_freq_adj_ext_up; /* - * This bit must be '1' for the tqm_ring6 fields to be - * configured. + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \ - UINT32_C(0x1000) + uint32_t ptp_freq_adj_ext_phase_lower; /* - * This bit must be '1' for the tqm_ring7 fields to be - * configured. + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \ - UINT32_C(0x2000) + uint32_t ptp_freq_adj_ext_phase_upper; /* - * This bit must be '1' for the mrav fields to be - * configured. + * Allows driver to set the full 64bit time in FW. The upper 16 bits + * will be stored in FW and the lower 48bits will be programmed in + * PHC. Firmware will send a broadcast async event to all functions + * to indicate the programmed upper 16 bits. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \ - UINT32_C(0x4000) + uint64_t ptp_set_time; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the tim fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \ - UINT32_C(0x8000) - /* QPC page size and level. */ - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 - /* QPC page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G - /* SRQ page size and level. */ - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G - /* CQ page size and level. */ - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 - /* CQ page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G - /* VNIC page size and level. */ - uint8_t vnic_pg_size_vnic_lvl; - /* VNIC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 - /* VNIC page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G - /* Stat page size and level. */ - uint8_t stat_pg_size_stat_lvl; - /* Stat PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 - /* Stat page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G - /* TQM slow path page size and level. */ - uint8_t tqm_sp_pg_size_tqm_sp_lvl; - /* TQM slow path PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 - /* TQM slow path page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G - /* TQM ring 0 page size and level. */ - uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; - /* TQM ring 0 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 - /* TQM ring 0 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G - /* TQM ring 1 page size and level. */ - uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; - /* TQM ring 1 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 - /* TQM ring 1 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G - /* TQM ring 2 page size and level. */ - uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; - /* TQM ring 2 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 - /* TQM ring 2 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G - /* TQM ring 3 page size and level. */ - uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; - /* TQM ring 3 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \ + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 - /* TQM ring 3 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G - /* TQM ring 4 page size and level. */ - uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; - /* TQM ring 4 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \ + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* KTLS Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \ + /* KTLS Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \ + /* QUIC Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 - /* TQM ring 4 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G - /* TQM ring 5 page size and level. */ - uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; - /* TQM ring 5 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \ + /* QUIC Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX \ + UINT32_C(0x3) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_func_backing_store_cfg_v2 * + **********************************/ + + +/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ +struct hwrm_func_backing_store_cfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \ + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \ + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 - /* TQM ring 5 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G - /* TQM ring 6 page size and level. */ - uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; - /* TQM ring 6 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \ + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \ + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and + * does not expect any backing store to be provided by the + * host driver. This mode provides minimal L2 functionality + * (e.g. limited L2 resources, no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 - /* TQM ring 6 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G - /* TQM ring 7 page size and level. */ - uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; - /* TQM ring 7 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \ + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Number of bytes allocated for each entry */ + uint16_t entry_size; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 - /* TQM ring 7 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G - /* MR/AV page size and level. */ - uint8_t mrav_pg_size_mrav_lvl; - /* MR/AV PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G + /* + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | Count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | + */ + uint8_t subtype_valid_cnt; + /* + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; +} __rte_packed; + +/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_func_backing_store_qcfg_v2 * + ***********************************/ + + +/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \ + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + uint8_t rsvd[4]; +} __rte_packed; + +/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ +struct hwrm_func_backing_store_qcfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 - /* MR/AV page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G - /* Timer page size and level. */ - uint8_t tim_pg_size_tim_lvl; - /* Timer PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 - /* Timer page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G - /* QP page directory. */ - uint64_t qpc_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* VNIC page directory. */ - uint64_t vnic_page_dir; - /* Stat page directory. */ - uint64_t stat_page_dir; - /* TQM slowpath page directory. */ - uint64_t tqm_sp_page_dir; - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; - /* MR/AV page directory. */ - uint64_t mrav_page_dir; - /* Timer page directory. */ - uint64_t tim_page_dir; - /* Number of entries to reserve for QP1 */ - uint16_t qp_num_qp1_entries; - /* Number of entries to reserve for L2 */ - uint16_t qp_num_l2_entries; - /* Number of QPs. */ - uint32_t qp_num_entries; - /* Number of SRQs. */ - uint32_t srq_num_entries; - /* Number of entries to reserve for L2 */ - uint16_t srq_num_l2_entries; - /* Number of entries to reserve for L2 */ - uint16_t cq_num_l2_entries; - /* Number of CQs. */ - uint32_t cq_num_entries; - /* Number of entries to reserve for VNIC entries */ - uint16_t vnic_num_vnic_entries; - /* Number of entries to reserve for Ring table entries */ - uint16_t vnic_num_ring_table_entries; - /* Number of Stats. */ - uint32_t stat_num_entries; - /* Number of TQM slowpath entries. */ - uint32_t tqm_sp_num_entries; - /* Number of TQM ring 0 entries. */ - uint32_t tqm_ring0_num_entries; - /* Number of TQM ring 1 entries. */ - uint32_t tqm_ring1_num_entries; - /* Number of TQM ring 2 entries. */ - uint32_t tqm_ring2_num_entries; - /* Number of TQM ring 3 entries. */ - uint32_t tqm_ring3_num_entries; - /* Number of TQM ring 4 entries. */ - uint32_t tqm_ring4_num_entries; - /* Number of TQM ring 5 entries. */ - uint32_t tqm_ring5_num_entries; - /* Number of TQM ring 6 entries. */ - uint32_t tqm_ring6_num_entries; - /* Number of TQM ring 7 entries. */ - uint32_t tqm_ring7_num_entries; - /* - * If the MR/AV split reservation flag is not set, then this field - * represents the total number of MR plus AV entries. For versions - * of firmware that support the split reservation, when it is not - * specified half of the entries will be reserved for MRs and the - * other half for AVs. - * - * If the MR/AV split reservation flag is set, then this - * field is logically divided into two 16b fields. Bits `[31:16]` - * represents the `mr_num_entries` and bits `[15:0]` represents - * `av_num_entries`. The granularity of these values is defined by - * the `mrav_num_entries_unit` field returned by the - * `backing_store_qcaps` command. - */ - uint32_t mrav_num_entries; - /* Number of Timer entries. */ - uint32_t tim_num_entries; - uint8_t unused_1[7]; + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G + /* + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | + */ + uint8_t subtype_valid_cnt; + uint8_t rsvd[2]; + /* + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; + uint8_t rsvd2[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as 1 - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. */ uint8_t valid; } __rte_packed; -/**************************** - * hwrm_error_recovery_qcfg * - ****************************/ +/************************************ + * hwrm_func_backing_store_qcaps_v2 * + ************************************/ -/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ -struct hwrm_error_recovery_qcfg_input { +/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcaps_v2_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13931,11 +21992,72 @@ struct hwrm_error_recovery_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t unused_0[8]; + /* Type of backing store to be queried. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID + uint8_t rsvd[6]; } __rte_packed; -/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ -struct hwrm_error_recovery_qcfg_output { +/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ +struct hwrm_func_backing_store_qcaps_v2_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13944,368 +22066,521 @@ struct hwrm_error_recovery_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Type of backing store to be queried. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM \ + UINT32_C(0xf) + /* KTLS Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* KTLS Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID + /* Number of bytes per backing store entry. */ + uint16_t entry_size; + /* Control flags. */ uint32_t flags; /* - * When this flag is set to 1, error recovery will be initiated - * through master function driver. + * When set, it indicates the context type should be initialized + * with the “ctx_init_value” at the specified offset. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT \ + UINT32_C(0x1) + /* When set, it indicates the context type is valid. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID \ + UINT32_C(0x2) /* - * When this flag is set to 1, error recovery will be performed - * through Co processor. + * When set, it indicates the region for this type is not a regular + * context memory but a driver managed memory that is created, + * initialized and managed by the driver. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY \ + UINT32_C(0x4) /* - * Driver Polling frequency. This value is in units of 100msec. - * Typical value would be 10 to indicate 1sec. - * Drivers can poll FW health status, Heartbeat, reset_counter with - * this frequency. + * Bit map of the valid instances associated with the + * backing store type. */ - uint32_t driver_polling_freq; + uint32_t instance_bit_map; /* - * This value is in units of 100msec. - * Typical value would be 30 to indicate 3sec. - * Master function wait period from detecting a fatal error to - * initiating reset. In this time period Master PF expects every - * active driver will detect fatal error. + * Initializer to be used by drivers to initialize context memory + * to ensure context subsystem flags an error for an attack before + * the first time context load. */ - uint32_t master_func_wait_period; + uint8_t ctx_init_value; /* - * This value is in units of 100msec. - * Typical value would be 50 to indicate 5sec. - * Normal function wait period from fatal error detection to - * polling FW health status. In this time period, drivers should not - * do any PCIe MMIO transaction and should not send any HWRM commands. + * Specifies the doubleword offset of ctx_init_value for this + * context type. */ - uint32_t normal_func_wait_period; + uint8_t ctx_init_offset; /* - * This value is in units of 100msec. - * Typical value would be 20 to indicate 2sec. - * This field indicates that, master function wait period after chip - * reset. After this time, master function should reinitialize with - * FW. + * Some backing store types, e.g., TQM rings, require the number + * of entries to be a multiple of this value to prevent any + * resource allocation limitations. If not applicable, leave + * this field with "0". */ - uint32_t master_func_wait_period_after_reset; + uint8_t entry_multiple; + uint8_t rsvd; + /* Maximum number of backing store entries supported for this type. */ + uint32_t max_num_entries; /* - * This value is in units of 100msec. - * Typical value would be 60 to indicate 6sec. - * This field is applicable to both master and normal functions. - * Even after chip reset, if FW status not changed to ready, - * then all the functions can poll for this much time and bailout. + * Minimum number of backing store entries required for this type. + * This field is only valid for some backing store types, e.g., + * TQM rings. If not applicable, leave this field with "0". */ - uint32_t max_bailout_time_after_reset; + uint32_t min_num_entries; /* - * FW health status register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates upper 30bits of the register address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * Next valid backing store type. If current type queried is already + * the last valid type, firmware must set this field to invalid type. */ - uint32_t fw_health_status_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \ - 0 + uint16_t next_valid_type; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint8_t subtype_valid_cnt; + uint8_t rsvd2; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; + uint8_t rsvd3[3]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_func_dbr_pacing_cfg * + ****************************/ + + +/* hwrm_func_dbr_pacing_cfg_input (size:320b/40B) */ +struct hwrm_func_dbr_pacing_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * Drivers have to map appropriate window to access this - * register. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \ - 2 + uint16_t seq_id; /* - * FW HeartBeat register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t fw_heartbeat_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \ - 0 + uint16_t target_id; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint64_t resp_addr; + uint8_t flags; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * This bit must be '1' to enable DBR NQ events. The NQ ID to + * receive the events must be specified in the primary_nq_id + * field. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE \ UINT32_C(0x1) + /* This bit must be '1' to disable DBR NQ events. */ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE \ + UINT32_C(0x2) + uint8_t unused_0[7]; + uint32_t enables; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * This bit must be '1' for the primary_nq_id field to be + * configured. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the pacing_threshold field to be + * configured. + */ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID \ UINT32_C(0x2) /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * Specify primary function’s NQ ID to receive the doorbell pacing + * threshold crossing events. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \ - 2 + uint32_t primary_nq_id; /* - * FW reset counter. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * Specify pacing threshold value, as a percentage of the max + * doorbell FIFO depth. The range is 1 to 36. */ - uint32_t fw_reset_cnt_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \ - 0 + uint32_t pacing_threshold; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_dbr_pacing_cfg_output (size:128b/16B) */ +struct hwrm_func_dbr_pacing_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_func_dbr_pacing_qcfg * + *****************************/ + + +/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint16_t seq_id; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \ - 2 + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ +struct hwrm_func_dbr_pacing_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t flags; + /* When this bit is '1', it indicates DBR NQ events are enabled. */ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED \ + UINT32_C(0x1) + uint8_t unused_0[7]; /* - * Reset Inprogress Register address for PFs. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * The Doorbell global FIFO occupancy register. This field should be + * used by the driver and user library in the doorbell pacing + * algorithm. Lower 2 bits indicates address space location and upper + * 30 bits indicates upper 30bits of the register address. A value of + * 0xFFFF-FFFF indicates this register does not exist. */ - uint32_t reset_inprogress_reg; + uint32_t dbr_stat_db_fifo_reg; /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT \ 0 /* * If value is 0, this register is located in PCIe config space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) /* * If value is 1, this register is located in GRC address space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) /* * If value is 2, this register is located in first BAR address * space. Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) /* * If value is 3, this register is located in second BAR address * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST \ + HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK \ UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SFT \ 2 - /* This field indicates the mask value for reset_inprogress_reg. */ - uint32_t reset_inprogress_reg_mask; - uint8_t unused_0[3]; /* - * Array of registers and value count to reset the Chip - * Each array count has reset_reg, reset_reg_val, delay_after_reset - * in TLV format. Depending upon Chip type, number of reset registers - * will vary. Drivers have to write reset_reg_val in the reset_reg - * location in the same sequence in order to recover from a fatal - * error. + * This field indicates the mask value for dbr_stat_db_fifo_reg + * to get the high watermark for doorbell FIFO. */ - uint8_t reg_array_cnt; + uint32_t dbr_stat_db_fifo_reg_watermark_mask; /* - * Reset register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * This field indicates the shift value for dbr_stat_db_fifo_reg + * to get the high watermark for doorbell FIFO. */ - uint32_t reset_reg[16]; + uint8_t dbr_stat_db_fifo_reg_watermark_shift; + uint8_t unused_1[3]; + /* + * This field indicates the mask value for dbr_stat_db_fifo_reg + * to get the amount of room left for doorbell FIFO. + */ + uint32_t dbr_stat_db_fifo_reg_fifo_room_mask; + /* + * This field indicates the shift value for dbr_stat_db_fifo_reg + * to get the amount of room left for doorbell FIFO. + */ + uint8_t dbr_stat_db_fifo_reg_fifo_room_shift; + uint8_t unused_2[3]; + /* + * DBR_REG_AEQ_ARM register. This field should be used by the driver + * to rearm the interrupt for regeneration of a notification to the + * host from the hardware when the global doorbell occupancy threshold + * is above the threshold value. Lower 2 bits indicates address space + * location and upper 30 bits indicates upper 30bits of the register + * address. A value of 0xFFFF-FFFF indicates this register does not + * exist. + */ + uint32_t dbr_throttling_aeq_arm_reg; /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0 + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT \ + 0 /* * If value is 0, this register is located in PCIe config space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) /* * If value is 1, this register is located in GRC address space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) /* * If value is 2, this register is located in first BAR address * space. Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) /* * If value is 3, this register is located in second BAR address * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST \ + HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK \ UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2 - /* Value to be written in reset_reg to reset the controller. */ - uint32_t reset_reg_val[16]; + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT \ + 2 /* - * This value is in units of 1msec. - * Typical value would be 10 to indicate 10msec. - * Some of the operations like Core reset require delay before - * accessing PCIE MMIO register space. - * If this value is non-zero, drivers have to wait for - * this much time after writing reset_reg_val in reset_reg. + * This field indicates the value to be written for + * dbr_throttling_aeq_arm_reg register. */ - uint8_t delay_after_reset[16]; + uint8_t dbr_throttling_aeq_arm_reg_val; + uint8_t unused_3[7]; /* - * Error recovery counter. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * Specifies primary function’s NQ ID. + * A value of 0xFFFF indicates NQ ID is invalid. */ - uint32_t err_recovery_cnt_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ - 0 + uint32_t primary_nq_id; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * Specifies the pacing threshold value, as a percentage of the + * max doorbell FIFO depth. The range is 1 to 100. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint32_t pacing_threshold; + uint8_t unused_4[7]; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint8_t valid; +} __rte_packed; + +/**************************************** + * hwrm_func_dbr_pacing_broadcast_event * + ****************************************/ + + +/* hwrm_func_dbr_pacing_broadcast_event_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_broadcast_event_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ - 2 - uint8_t unused_1[3]; + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_dbr_pacing_broadcast_event_output (size:128b/16B) */ +struct hwrm_func_dbr_pacing_broadcast_event_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -14984,59 +23259,421 @@ struct hwrm_func_host_pf_ids_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t host; - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to SOC host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP0 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP1 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP2 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP3 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10) - /* - * This provides a filter of what PF(s) will be returned in the - * query.. - */ - uint8_t filter; - /* - * all available PF(s) belong to the host(s) (defined in the - * host field). This includes the hidden PFs. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0) - /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for L2 traffic. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1) - /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for ROCE traffic. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2) - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ - HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE - uint8_t unused_1[6]; + uint8_t host; + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to SOC host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP0 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP1 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP2 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP3 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10) + /* + * This provides a filter of what PF(s) will be returned in the + * query.. + */ + uint8_t filter; + /* + * all available PF(s) belong to the host(s) (defined in the + * host field). This includes the hidden PFs. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0) + /* + * all available PF(s) belong to the host(s) (defined in the + * host field) that is available for L2 traffic. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1) + /* + * all available PF(s) belong to the host(s) (defined in the + * host field) that is available for ROCE traffic. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2) + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ + HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ +struct hwrm_func_host_pf_ids_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This provides the first PF ID of the device. */ + uint16_t first_pf_id; + uint16_t pf_ordinal_mask; + /* + * When this bit is '1', it indicates first PF belongs to one of + * the hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates 2nd PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates 3rd PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates 4th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates 5th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates 6th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates 7th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates 8th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates 9th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates 10th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \ + UINT32_C(0x200) + /* + * When this bit is '1', it indicates 11th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates 12th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \ + UINT32_C(0x800) + /* + * When this bit is '1', it indicates 13th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \ + UINT32_C(0x1000) + /* + * When this bit is '1', it indicates 14th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \ + UINT32_C(0x2000) + /* + * When this bit is '1', it indicates 15th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates 16th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \ + UINT32_C(0x8000) + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_spd_cfg * + *********************/ + + +/* hwrm_func_spd_cfg_input (size:384b/48B) */ +struct hwrm_func_spd_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Set this bit is '1' to enable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1) + /* Set this bit is '1' to disable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2) + /* + * Set this bit is '1' to enable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4) + /* + * Set this bit is '1' to disable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8) + /* + * Set this bit is '1' to enable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10) + /* + * Set this bit is '1' to disable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20) + uint32_t enables; + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the hash_mode_flags field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hash_type field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ring_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the hash_key_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \ + UINT32_C(0x10) + /* + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. + */ + uint16_t ethertype; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1; + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; +} __rte_packed; + +/* hwrm_func_spd_cfg_output (size:128b/16B) */ +struct hwrm_func_spd_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_spd_qcfg * + **********************/ + + +/* hwrm_func_spd_qcfg_input (size:128b/16B) */ +struct hwrm_func_spd_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; } __rte_packed; -/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ -struct hwrm_func_host_pf_ids_query_output { +/* hwrm_func_spd_qcfg_output (size:512b/64B) */ +struct hwrm_func_spd_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -15045,106 +23682,112 @@ struct hwrm_func_host_pf_ids_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This provides the first PF ID of the device. */ - uint16_t first_pf_id; - uint16_t pf_ordinal_mask; + uint32_t flags; /* - * When this bit is '1', it indicates first PF belongs to one of - * the hosts defined in the input request. + * The SPD datapath forwarding is currently enabled when this + * flag is set to '1'. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \ - UINT32_C(0x1) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1) /* - * When this bit is '1', it indicates 2nd PF belongs to one of the - * hosts defined in the input request. + * The SPD datapath checksum feature is currently enabled when + * this flag is set to '1'. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \ - UINT32_C(0x2) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2) /* - * When this bit is '1', it indicates 3rd PF belongs to one of the - * hosts defined in the input request. + * The SPD datapath debug feature is currently enabled when + * this flag is set to '1'. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \ - UINT32_C(0x4) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4) + uint32_t hash_type; /* - * When this bit is '1', it indicates 4th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \ - UINT32_C(0x8) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * When this bit is '1', it indicates 5th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \ - UINT32_C(0x10) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * When this bit is '1', it indicates 6th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \ - UINT32_C(0x20) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * When this bit is '1', it indicates 7th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \ - UINT32_C(0x40) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * When this bit is '1', it indicates 8th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \ - UINT32_C(0x80) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * When this bit is '1', it indicates 9th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \ - UINT32_C(0x100) - /* - * When this bit is '1', it indicates 10th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \ - UINT32_C(0x200) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates 11th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \ - UINT32_C(0x400) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) /* - * When this bit is '1', it indicates 12th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \ - UINT32_C(0x800) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) /* - * When this bit is '1', it indicates 13th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \ - UINT32_C(0x1000) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) /* - * When this bit is '1', it indicates 14th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \ - UINT32_C(0x2000) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) /* - * When this bit is '1', it indicates 15th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \ - UINT32_C(0x4000) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1; /* - * When this bit is '1', it indicates 16th PF belongs to one of the - * hosts defined in the input request. + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \ - UINT32_C(0x8000) - uint8_t unused_1[3]; + uint16_t ethertype; + uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15275,7 +23918,15 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x80) /* * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. + * on this port if supported. When enabled, at least one of the + * FEC modes must be advertised by enabling the fec_clause_74_enable, + * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable, + * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none + * of the FEC mode is currently enabled, the HWRM shall choose + * a default advertisement setting. + * The default advertisement setting can be queried by calling + * hwrm_port_phy_qcfg. Note that the link speed must be + * in autonegotiation mode for FEC autonegotiation to take effect. * When set to 0, then this flag shall be ignored. * If FEC autonegotiation is not supported, then the HWRM shall ignore this * flag. @@ -15284,7 +23935,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x100) /* * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port if supported. + * on this port and use forced FEC mode. In forced FEC mode, one + * or more FEC forced settings under the same clause can be set. * When set to 0, then this flag shall be ignored. * If FEC autonegotiation is not supported, then the HWRM shall ignore this * flag. @@ -15293,7 +23945,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x200) /* * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -15302,7 +23955,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x400) /* * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by not advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -15310,20 +23964,26 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \ UINT32_C(0x800) /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. + * When set to 1, then the HWRM shall enable FEC CLAUSE 91 + * (Reed Solomon RS(528,514) for NRZ) on this port if supported, + * by advertising FEC RS(528,514) if FEC autonegotiation is enabled + * or force enabled otherwise. In forced FEC mode, this flag + * will only take effect if the speed is NRZ. Additional + * RS544 or RS272 flags (also under clause 91) may be set for PAM4 + * in forced FEC mode. * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. + * If FEC RS(528,514) is not supported, then the HWRM shall ignore + * this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \ UINT32_C(0x1000) /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. + * When set to 1, then the HWRM shall disable FEC CLAUSE 91 + * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by + * not advertising RS(528,514) if FEC autonegotiation is enabled or + * force disabled otherwise. When set to 0, then this flag shall be + * ignored. If FEC RS(528,514) is not supported, then the HWRM + * shall ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \ UINT32_C(0x2000) @@ -15347,6 +24007,100 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ UINT32_C(0x4000) + /* + * When set to 1, then the HWRM shall enable FEC RS544_1XN + * on this port if supported, by advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs544_ieee_enable are set, the + * HWRM shall choose one of the RS544 modes. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \ + UINT32_C(0x8000) + /* + * When set to 1, then the HWRM shall disable FEC RS544_1XN + * on this port if supported, by not advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \ + UINT32_C(0x10000) + /* + * When set to 1, then the HWRM shall enable FEC RS(544,514) + * on this port if supported, by advertising FEC RS(544,514) if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs544_1xn_enable are set, the + * HWRM shall choose one of the RS544 modes. + * When set to 0, then this flag shall be ignored. + * If FEC RS(544,514) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \ + UINT32_C(0x20000) + /* + * When set to 1, then the HWRM shall disable FEC RS(544,514) + * on this port if supported, by not advertising FEC RS(544,514) if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS(544,514) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \ + UINT32_C(0x40000) + /* + * When set to 1, then the HWRM shall enable FEC RS272_1XN + * on this port if supported, by advertising FEC RS272_1XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs272_ieee_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 + * and RS544 modes cannot be set at the same time in forced FEC mode. + * When set to 0, then this flag shall be ignored. + * If FEC RS272_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \ + UINT32_C(0x80000) + /* + * When set to 1, then the HWRM shall disable FEC RS272_1XN + * on this port if supported, by not advertising FEC RS272_1XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS272_1XN is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \ + UINT32_C(0x100000) + /* + * When set to 1, then the HWRM shall enable FEC RS(272,257) + * on this port if supported, by advertising FEC RS(272,257) if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs272_1xn_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 + * and RS544 modes cannot be set at the same time in forced FEC mode. + * When set to 0, then this flag shall be ignored. + * If FEC RS(272,257) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \ + UINT32_C(0x200000) + /* + * When set to 1, then the HWRM shall disable FEC RS(272,257) + * on this port if supported, by not advertising FEC RS(272,257) if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS(272,257) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \ + UINT32_C(0x400000) uint32_t enables; /* * This bit must be '1' for the auto_mode field to be @@ -15414,6 +24168,18 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \ UINT32_C(0x400) + /* + * This bit must be '1' for the force_pam4_link_speed field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \ + UINT32_C(0x800) + /* + * This bit must be '1' for the auto_pam4_link_speed_mask field to + * be configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \ + UINT32_C(0x1000) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -15442,8 +24208,6 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \ @@ -15468,8 +24232,9 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* - * Select the speeds based on the corresponding link speed mask value - * that is provided. + * Select the speeds based on the corresponding link speed mask values + * that are provided. The included speeds are specified in the + * auto_link_speed and auto_pam4_link_speed fields. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \ @@ -15483,7 +24248,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) /* Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) - /* Both Half and Full dupex will be requested. */ + /* Both Half and Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \ HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH @@ -15548,8 +24313,6 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \ @@ -15602,9 +24365,6 @@ struct hwrm_port_phy_cfg_input { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \ - UINT32_C(0x4000) /* This value controls the wirespeed feature. */ uint8_t wirespeed; /* Wirespeed feature is disabled. */ @@ -15715,7 +24475,15 @@ struct hwrm_port_phy_cfg_input { uint32_t tx_lpi_timer; #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 - uint32_t unused_3; + /* This field specifies which PAM4 speeds are enabled for auto mode. */ + uint16_t auto_link_pam4_speed_mask; + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \ + UINT32_C(0x4) + uint8_t unused_2[2]; } __rte_packed; /* hwrm_port_phy_cfg_output (size:128b/16B) */ @@ -15828,8 +24596,54 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2) #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK - uint8_t unused_0; - /* This value indicates the current link speed of the connection. */ + uint8_t active_fec_signal_mode; + /* + * This value indicates the current link signaling mode of the + * connection. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \ + UINT32_C(0xf) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0 + /* NRZ signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \ + UINT32_C(0x0) + /* PAM4 signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 + /* This value indicates the current active FEC mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \ + UINT32_C(0xf0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4 + /* No active FEC */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \ + (UINT32_C(0x0) << 4) + /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \ + (UINT32_C(0x1) << 4) + /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \ + (UINT32_C(0x2) << 4) + /* FEC RS544_1XN active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \ + (UINT32_C(0x3) << 4) + /* FEC RS(544,528) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \ + (UINT32_C(0x4) << 4) + /* FEC RS272_1XN active, autonegotiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \ + (UINT32_C(0x5) << 4) + /* FEC RS(272,257) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \ + (UINT32_C(0x6) << 4) + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE + /* + * This value indicates the current link speed of the connection. + * The signal_mode field indicates if the link is using + * NRZ or PAM4 signaling. + */ uint16_t link_speed; /* 100Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1) @@ -15886,7 +24700,7 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2) /* * The supported speeds for the port. This is a bit mask. - * For each speed that is supported, the corrresponding + * For each speed that is supported, the corresponding * bit will be set to '1'. */ uint16_t support_speeds; @@ -15932,9 +24746,6 @@ struct hwrm_port_phy_qcfg_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \ - UINT32_C(0x4000) /* * Current setting of forced link speed. * When the link speed is not being forced, this @@ -15964,9 +24775,6 @@ struct hwrm_port_phy_qcfg_output { /* 100Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \ UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \ - UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \ UINT32_C(0xffff) @@ -16053,8 +24861,6 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \ UINT32_C(0xffff) @@ -16110,9 +24916,6 @@ struct hwrm_port_phy_qcfg_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \ - UINT32_C(0x4000) /* Current setting for wirespeed. */ uint8_t wirespeed; /* Wirespeed feature is disabled. */ @@ -16282,20 +25085,44 @@ struct hwrm_port_phy_qcfg_output { /* 1G_baseCX */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ UINT32_C(0x1b) - /* 100G_BASECR4 */ + /* 200G_BASECR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \ UINT32_C(0x1c) - /* 100G_BASESR4 */ + /* 200G_BASESR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \ UINT32_C(0x1d) - /* 100G_BASELR4 */ + /* 200G_BASELR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \ UINT32_C(0x1e) - /* 100G_BASEER4 */ + /* 200G_BASEER4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \ UINT32_C(0x1f) + /* 50G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \ + UINT32_C(0x20) + /* 50G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \ + UINT32_C(0x21) + /* 50G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \ + UINT32_C(0x22) + /* 50G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \ + UINT32_C(0x23) + /* 100G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \ + UINT32_C(0x24) + /* 100G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \ + UINT32_C(0x25) + /* 100G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \ + UINT32_C(0x26) + /* 100G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \ + UINT32_C(0x27) #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -16372,7 +25199,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ uint8_t parallel_detect; @@ -16381,7 +25208,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) @@ -16573,9 +25400,6 @@ struct hwrm_port_phy_qcfg_output { * is set to 1, then all other FEC configuration flags shall be ignored. * When set to 0, then FEC is supported as indicated by other * configuration flags. - * If no cable is attached and the HWRM does not yet know the FEC - * capability, then the HWRM shall set this flag to 1 when reporting - * FEC capability. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \ UINT32_C(0x1) @@ -16599,25 +25423,91 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \ UINT32_C(0x8) /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port. + * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this + * port. This means that FEC CLAUSE 74 is either advertised if + * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled. * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \ UINT32_C(0x10) /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port. + * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for + * NRZ) is supported on this port. + * When set to 0, then FEC RS(528,418) is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \ UINT32_C(0x20) /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported. + * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for + * NRZ) is enabled on this port. This means that FEC RS(528,514) is + * either advertised if FEC autonegotiation is enabled or FEC + * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) + * is disabled if supported. * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \ UINT32_C(0x40) + /* + * When set to 1, then FEC RS544_1XN is supported on this port. + * When set to 0, then FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \ + UINT32_C(0x80) + /* + * When set to 1, then RS544_1XN is enabled on this + * port. This means that FEC RS544_1XN is either advertised if + * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled. + * When set to 0, then FEC RS544_1XN is disabled if supported. + * This flag should be ignored if FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \ + UINT32_C(0x100) + /* + * When set to 1, then FEC RS(544,514) is supported on this port. + * When set to 0, then FEC RS(544,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \ + UINT32_C(0x200) + /* + * When set to 1, then RS(544,514) is enabled on this + * port. This means that FEC RS(544,514) is either advertised if + * FEC autonegotiation is enabled or FEC RS(544,514) is force + * enabled. When set to 0, then FEC RS(544,514) is disabled if supported. + * This flag should be ignored if FEC RS(544,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \ + UINT32_C(0x400) + /* + * When set to 1, then FEC RS272_1XN is supported on this port. + * When set to 0, then FEC RS272_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \ + UINT32_C(0x800) + /* + * When set to 1, then RS272_1XN is enabled on this + * port. This means that FEC RS272_1XN is either advertised if + * FEC autonegotiation is enabled or FEC RS272_1XN is force + * enabled. When set to 0, then FEC RS272_1XN is disabled if supported. + * This flag should be ignored if FEC RS272_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \ + UINT32_C(0x1000) + /* + * When set to 1, then FEC RS(272,514) is supported on this port. + * When set to 0, then FEC RS(272,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \ + UINT32_C(0x2000) + /* + * When set to 1, then RS(272,257) is enabled on this + * port. This means that FEC RS(272,257) is either advertised if + * FEC autonegotiation is enabled or FEC RS(272,257) is force + * enabled. When set to 0, then FEC RS(272,257) is disabled if supported. + * This flag should be ignored if FEC RS(272,257) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \ + UINT32_C(0x4000) /* * This value is indicates the duplex of the current * connection state. @@ -16634,6 +25524,12 @@ struct hwrm_port_phy_qcfg_output { /* When this bit is '1', Media auto detect is enabled. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \ UINT32_C(0x1) + /* + * When this bit is '1', active_fec_signal_mode can be + * trusted. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \ + UINT32_C(0x2) /* * Up to 16 bytes of null padded ASCII string representing * PHY vendor. @@ -16648,7 +25544,63 @@ struct hwrm_port_phy_qcfg_output { * part number is not available. */ char phy_vendor_partnumber[16]; - uint8_t unused_2[7]; + /* + * The supported PAM4 speeds for the port. This is a bit mask. + * For each speed that is supported, the corresponding + * bit will be set to '1'. + */ + uint16_t support_pam4_speeds; + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \ + UINT32_C(0x4) + /* + * Current setting of forced PAM4 link speed. + * When the link speed is not being forced, this + * value shall be set to 0. + */ + uint16_t force_pam4_link_speed; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \ + UINT32_C(0x7d0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB + /* + * Current setting for auto_pam4_link_speed_mask that is used to + * advertise speeds during autonegotiation. + * This field is only valid when auto_mode is set to "mask". + * The speeds specified in this field shall be a subset of + * supported speeds on this port. + */ + uint16_t auto_pam4_link_speed_mask; + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \ + UINT32_C(0x4) + /* + * The advertised PAM4 speeds for the port by the link partner. + * Each advertised speed will be set to '1'. + */ + uint8_t link_partner_pam4_adv_speeds; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \ + UINT32_C(0x1) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \ + UINT32_C(0x2) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \ + UINT32_C(0x4) /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16664,7 +25616,7 @@ struct hwrm_port_phy_qcfg_output { *********************/ -/* hwrm_port_mac_cfg_input (size:384b/48B) */ +/* hwrm_port_mac_cfg_input (size:448b/56B) */ struct hwrm_port_mac_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -16810,6 +25762,20 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \ UINT32_C(0x2000) + /* + * When this bit is '1', the controller is requested to enable + * timestamp capture capability on all packets (not just PTP) + * of the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE \ + UINT32_C(0x4000) + /* + * When this bit is '1', the controller is requested to disable + * timestamp capture capability on all packets (not just PTP) + * of the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE \ + UINT32_C(0x8000) uint32_t enables; /* * This bit must be '1' for the ipg field to be @@ -16865,6 +25831,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -17058,6 +26030,12 @@ struct hwrm_port_mac_cfg_input { */ int32_t ptp_freq_adj_ppb; uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + int64_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -17208,7 +26186,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -17257,7 +26235,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -17271,7 +26249,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -17458,7 +26436,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -17491,10 +26469,29 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) + /* + * When this bit is set to '1', it indicates that driver has + * configured 64bit RTC. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED \ + UINT32_C(0x20) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -17512,9 +26509,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -17522,6 +26525,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -17549,7 +26556,7 @@ struct tx_port_stats { /* Total Number of 1024-1518 Bytes frames transmitted */ uint64_t tx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame transmitted which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -17690,7 +26697,7 @@ struct rx_port_stats { /* Total Number of 1024-1518 Bytes frames received */ uint64_t rx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame received which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -18045,7 +27052,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -18127,7 +27134,7 @@ struct rx_port_stats_ext { uint64_t rx_buffer_passed_threshold; /* * The number of symbol errors that wasn't corrected by FEC correction - * alogirithm + * algorithm */ uint64_t rx_pcs_symbol_err; /* The number of corrected bits on the port according to active FEC */ @@ -18164,6 +27171,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -18848,7 +27862,7 @@ struct hwrm_port_lpbk_qstats_output { ************************/ -/* hwrm_port_ecn_qstats_input (size:192b/24B) */ +/* hwrm_port_ecn_qstats_input (size:256b/32B) */ struct hwrm_port_ecn_qstats_input { /* The HWRM command request type. */ uint16_t req_type; @@ -18883,10 +27897,31 @@ struct hwrm_port_ecn_qstats_input { * multi-host mode. */ uint16_t port_id; - uint8_t unused_0[6]; + /* + * Size of the DMA buffer the caller has allocated for the firmware to + * write into. + */ + uint16_t ecn_stat_buf_size; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \ + HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[3]; + /* + * This is the host address where + * ECN port statistics will be stored + */ + uint64_t ecn_stat_host_addr; } __rte_packed; -/* hwrm_port_ecn_qstats_output (size:384b/48B) */ +/* hwrm_port_ecn_qstats_output (size:128b/16B) */ struct hwrm_port_ecn_qstats_output { /* The specific error status for the command. */ uint16_t error_code; @@ -18896,28 +27931,14 @@ struct hwrm_port_ecn_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of packets marked in CoS queue 0. */ - uint32_t mark_cnt_cos0; - /* Number of packets marked in CoS queue 1. */ - uint32_t mark_cnt_cos1; - /* Number of packets marked in CoS queue 2. */ - uint32_t mark_cnt_cos2; - /* Number of packets marked in CoS queue 3. */ - uint32_t mark_cnt_cos3; - /* Number of packets marked in CoS queue 4. */ - uint32_t mark_cnt_cos4; - /* Number of packets marked in CoS queue 5. */ - uint32_t mark_cnt_cos5; - /* Number of packets marked in CoS queue 6. */ - uint32_t mark_cnt_cos6; - /* Number of packets marked in CoS queue 7. */ - uint32_t mark_cnt_cos7; + /* Number of bytes of stats the firmware wrote to the DMA buffer. */ + uint16_t ecn_stat_buf_size; /* * Bitmask that indicates which CoS queues have ECN marking enabled. * Bit i corresponds to CoS queue i. */ uint8_t mark_en; - uint8_t unused_0[6]; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18928,6 +27949,59 @@ struct hwrm_port_ecn_qstats_output { uint8_t valid; } __rte_packed; +/* ECN mark statistics format */ +/* port_stats_ecn (size:512b/64B) */ +struct port_stats_ecn { + /* + * Number of packets marked in CoS queue 0. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos0; + /* + * Number of packets marked in CoS queue 1. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos1; + /* + * Number of packets marked in CoS queue 2. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos2; + /* + * Number of packets marked in CoS queue 3. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos3; + /* + * Number of packets marked in CoS queue 4. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos4; + /* + * Number of packets marked in CoS queue 5. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos5; + /* + * Number of packets marked in CoS queue 6. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos6; + /* + * Number of packets marked in CoS queue 7. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos7; +} __rte_packed; + /*********************** * hwrm_port_clr_stats * ***********************/ @@ -19040,7 +28114,7 @@ struct hwrm_port_phy_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_phy_qcaps_output (size:192b/24B) */ +/* hwrm_port_phy_qcaps_output (size:256b/32B) */ struct hwrm_port_phy_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -19080,12 +28154,39 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ UINT32_C(0x8) /* - * Reserved field. The HWRM shall set this field to 0. - * An HWRM client shall ignore this field. + * If set to 1, it indicates that the port counters and extended + * port counters will not reset when the firmware shuts down or + * resets the PHY. These counters will only be reset during power + * cycle or by calling HWRM_PORT_CLR_STATS. + * If set to 0, the state of the counters is unspecified when + * firmware shuts down or resets the PHY. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xf0) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \ + UINT32_C(0x10) + /* + * If set to 1, then this field indicates that the + * local loopback is not supported on this controller. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \ + UINT32_C(0x20) + /* + * If set to 1, then this field indicates that the + * PHY/Link down policy during PF shutdown is totally + * controlled by the firmware. It can shutdown the link + * even when there are active VFs associated with the PF. + * Host PF driver can send HWRM_PHY_CFG command to bring + * down the PHY even when the port is shared between VFs + * and PFs. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \ + UINT32_C(0x40) + /* + * If set to 1, this field indicates that the FCS may + * be disabled for a given packet via the transmit + * buffer descriptor. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \ + UINT32_C(0x80) /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -19098,8 +28199,10 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) /* 4-port device */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) + /* 12-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc) #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ - HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 /* * This is a bit mask to indicate what speeds are supported * as forced speeds on this link. @@ -19149,9 +28252,6 @@ struct hwrm_port_phy_qcaps_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \ - UINT32_C(0x4000) /* * This is a bit mask to indicate what speeds are supported * for autonegotiation on this link. @@ -19201,15 +28301,12 @@ struct hwrm_port_phy_qcaps_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \ - UINT32_C(0x4000) /* * This is a bit mask to indicate what speeds are supported * for EEE on this link. * For each speed that can be autonegotiated when EEE is enabled * on this link, the corresponding mask bit shall be set to '1'. - * This field is only valid when the eee_suppotred is set to '1'. + * This field is only valid when the eee_supported is set to '1'. */ uint16_t supported_speeds_eee_mode; /* Reserved */ @@ -19258,6 +28355,57 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \ UINT32_C(0xffffff) #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0 + /* + * Reserved field. The HWRM shall set this field to 0. + * An HWRM client shall ignore this field. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \ + UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24 + /* + * This field is used to advertise which PAM4 speeds are supported + * in auto mode. + */ + uint16_t supported_pam4_speeds_auto_mode; + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \ + UINT32_C(0x4) + /* + * This field is used to advertise which PAM4 speeds are supported + * in forced mode. + */ + uint16_t supported_pam4_speeds_force_mode; + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \ + UINT32_C(0x4) + /* More PHY capability flags */ + uint16_t flags2; + /* + * If set to 1, then this field indicates that + * 802.3x flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \ + UINT32_C(0x1) + /* + * If set to 1, then this field indicates that + * priority-based flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ + UINT32_C(0x2) + /* + * Number of internal ports for this device. This field allows the FW + * to advertise how many internal ports are present. Manufacturing + * tools uses this to determine how many internal ports should have + * the PRBS test run on them. This field always return 0 unless NVM + * option "HPTN_MODE" is set to 1. + */ + uint8_t internal_port_cnt; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -19265,9 +28413,7 @@ struct hwrm_port_phy_qcaps_output { * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ - UINT32_C(0xff000000) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 + uint8_t valid; } __rte_packed; /**************************** @@ -20548,7 +29694,13 @@ struct hwrm_port_prbs_test_input { * use this entire buffer or less than the entire buffer, but never more. */ uint16_t data_len; - uint16_t unused_0; + uint16_t flags; + /* + * If set, the port_id field should be interpreted as an internal + * port. The internal port id range is returned in port_phy_qcaps + * response internal_port_cnt field. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1) uint32_t unused_1; /* Port ID of port where PRBS test to be run. */ uint16_t port_id; @@ -20845,14 +29997,14 @@ struct hwrm_port_sfp_sideband_cfg_input { /* * This bit along with rs1 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ UINT32_C(0x1) /* * This bit along with rs0 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ UINT32_C(0x2) @@ -20976,16 +30128,16 @@ struct hwrm_port_sfp_sideband_qcfg_output { #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ UINT32_C(0x2) /* - * This bit along with rs1 indiactes the current speed of the dual + * This bit along with rs1 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ UINT32_C(0x4) /* - * This bit along with rs0 indiactes the current speed of the dual + * This bit along with rs0 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ UINT32_C(0x8) @@ -21175,11 +30327,475 @@ struct hwrm_port_phy_mdio_bus_release_output { uint16_t clients_id; uint8_t unused_1[3]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_port_tx_fir_cfg * + ************************/ + + +/* hwrm_port_tx_fir_cfg_input (size:320b/40B) */ +struct hwrm_port_tx_fir_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Modulation types of TX FIR: NRZ, PAM4. */ + uint8_t mod_type; + /* For NRZ */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \ + HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 + /* The lane mask of the lane TX FIR will be configured. */ + uint8_t lane_mask; + uint8_t unused_0[2]; + /* Value1 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_1; + /* Value2 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_2; + /* Value3 of TX FIR, required for PAM4. */ + uint32_t txfir_val_3; + /* Value4 of TX FIR, required for PAM4. */ + uint32_t txfir_val_4; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_tx_fir_cfg_output (size:128b/16B) */ +struct hwrm_port_tx_fir_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_port_tx_fir_qcfg * + *************************/ + + +/* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */ +struct hwrm_port_tx_fir_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Modulation types of TX FIR: NRZ, PAM4. */ + uint8_t mod_type; + /* For NRZ */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \ + HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 + /* The ID of the lane TX FIR will be queried. */ + uint8_t lane_id; + uint8_t unused[6]; +} __rte_packed; + +/* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */ +struct hwrm_port_tx_fir_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Value1 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_1; + /* Value2 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_2; + /* Value3 of TX FIR, required for PAM4. */ + uint32_t txfir_val_3; + /* Value4 of TX FIR, required for PAM4. */ + uint32_t txfir_val_4; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for an endpoint. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \ + UINT32_C(0x6) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -21251,7 +30867,7 @@ struct hwrm_queue_qportcfg_input { uint8_t unused_0; } __rte_packed; -/* hwrm_queue_qportcfg_output (size:256b/32B) */ +/* hwrm_queue_qportcfg_output (size:1344b/168B) */ struct hwrm_queue_qportcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -21300,6 +30916,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -21347,27 +30970,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id0; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id0_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21383,27 +31008,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id1; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id1_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21419,27 +31046,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id2; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id2_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21455,27 +31084,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id3; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id3_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21491,27 +31122,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id4; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id4_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21527,27 +31160,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id5; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id5_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21563,27 +31198,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id6; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id6_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -21592,41 +31229,621 @@ struct hwrm_queue_qportcfg_output { #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN /* - * ID of CoS Queue 7. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * ID of CoS Queue 7. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. + */ + uint8_t queue_id7; + /* This value specifies service profile kind for CoS queue */ + uint8_t queue_id7_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE (deprecated) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP (deprecated) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC (deprecated) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id0_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * Up to 16 bytes of null padded ASCII string describing this queue. + * The queue name includes a CoS queue index and, in some cases, text + * that distinguishes the queue from other queues in the group. + */ + char qid0_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid1_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid2_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid3_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid4_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid5_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid6_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid7_name[16]; + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id1_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id2_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id3_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id4_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id5_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id6_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id7_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_queue_qcfg * + *******************/ + + +/* hwrm_queue_qcfg_input (size:192b/24B) */ +struct hwrm_queue_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX + /* Queue ID of the queue. */ + uint32_t queue_id; +} __rte_packed; + +/* hwrm_queue_qcfg_output (size:128b/16B) */ +struct hwrm_queue_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This value is the estimate packet length used in the + * TX arbiter. + */ + uint32_t queue_len; + /* This value is applicable to CoS queues only. */ + uint8_t service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN + /* Information about queue configuration. */ + uint8_t queue_cfg_info; + /* + * If this flag is set to '1', then the queue is + * configured asymmetrically on TX and RX sides. + * If this flag is set to '0', then this queue is + * configured symmetrically on TX and RX sides. + */ + #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + UINT32_C(0x1) + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_queue_cfg * + ******************/ + + +/* hwrm_queue_cfg_input (size:320b/40B) */ +struct hwrm_queue_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX, or both directions applicable to the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 + /* tx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + /* Bi-directional (Symmetrically applicable to TX and RX paths) */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR + uint32_t enables; + /* + * This bit must be '1' for the dflt_len field to be + * configured. + */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1) + /* + * This bit must be '1' for the service_profile field to be + * configured. + */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2) + /* Queue ID of queue that is to be configured by this function. */ + uint32_t queue_id; + /* + * This value is a the estimate packet length used in the + * TX arbiter. + * Set to 0xFF... (All Fs) to not adjust this value. + */ + uint32_t dflt_len; + /* This value is applicable to CoS queues only. */ + uint8_t service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_cfg_output (size:128b/16B) */ +struct hwrm_queue_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_queue_pfcenable_qcfg * + *****************************/ + + +/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ +struct hwrm_queue_pfcenable_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ +struct hwrm_queue_pfcenable_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* If set to 1, then PFC is enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \ + UINT32_C(0x1) + /* If set to 1, then PFC is enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \ + UINT32_C(0x2) + /* If set to 1, then PFC is enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \ + UINT32_C(0x4) + /* If set to 1, then PFC is enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \ + UINT32_C(0x8) + /* If set to 1, then PFC is enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \ + UINT32_C(0x10) + /* If set to 1, then PFC is enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \ + UINT32_C(0x20) + /* If set to 1, then PFC is enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \ + UINT32_C(0x40) + /* If set to 1, then PFC is enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ + UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_queue_pfcenable_cfg * + ****************************/ + + +/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ +struct hwrm_queue_pfcenable_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set to 1, then PFC is requested to be enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \ + UINT32_C(0x1) + /* If set to 1, then PFC is requested to be enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ + UINT32_C(0x2) + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ + UINT32_C(0x4) + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ + UINT32_C(0x8) + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ + UINT32_C(0x10) + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ + UINT32_C(0x20) + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ + UINT32_C(0x40) + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ + UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - uint8_t queue_id7; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id7_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN + uint16_t port_id; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ +struct hwrm_queue_pfcenable_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21637,13 +31854,13 @@ struct hwrm_queue_qportcfg_output { uint8_t valid; } __rte_packed; -/******************* - * hwrm_queue_qcfg * - *******************/ +/*************************** + * hwrm_queue_pri2cos_qcfg * + ***************************/ -/* hwrm_queue_qcfg_input (size:192b/24B) */ -struct hwrm_queue_qcfg_input { +/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ +struct hwrm_queue_pri2cos_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21678,19 +31895,31 @@ struct hwrm_queue_qcfg_input { * This enumeration is used for resources that are similar for both * TX and RX paths of the chip. */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) /* tx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) /* rx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX - /* Queue ID of the queue. */ - uint32_t queue_id; + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX + /* + * When this bit is set to '0', the query is + * for PRI from tunnel headers. + * When this bit is set to '1', the query is + * for PRI from inner packet headers. + */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; } __rte_packed; -/* hwrm_queue_qcfg_output (size:128b/16B) */ -struct hwrm_queue_qcfg_output { +/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ +struct hwrm_queue_pri2cos_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21700,31 +31929,72 @@ struct hwrm_queue_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This value is the estimate packet length used in the - * TX arbiter. + * CoS Queue assigned to priority 0. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - uint32_t queue_len; - /* This value is applicable to CoS queues only. */ - uint8_t service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) - /* Lossless */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN + uint8_t pri0_cos_queue_id; + /* + * CoS Queue assigned to priority 1. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri1_cos_queue_id; + /* + * CoS Queue assigned to priority 2. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri2_cos_queue_id; + /* + * CoS Queue assigned to priority 3. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri3_cos_queue_id; + /* + * CoS Queue assigned to priority 4. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri4_cos_queue_id; + /* + * CoS Queue assigned to priority 5. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri5_cos_queue_id; + /* + * CoS Queue assigned to priority 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri6_cos_queue_id; + /* + * CoS Queue assigned to priority 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri7_cos_queue_id; /* Information about queue configuration. */ uint8_t queue_cfg_info; /* - * If this flag is set to '1', then the queue is - * configured asymmetrically on TX and RX sides. - * If this flag is set to '0', then this queue is - * configured symmetrically on TX and RX sides. + * If this flag is set to '1', then the PRI to CoS + * configuration is asymmetric on TX and RX sides. + * If this flag is set to '0', then PRI to CoS configuration + * is symmetric on TX and RX sides. */ - #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) - uint8_t unused_0; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21735,13 +32005,13 @@ struct hwrm_queue_qcfg_output { uint8_t valid; } __rte_packed; -/****************** - * hwrm_queue_cfg * - ******************/ +/************************** + * hwrm_queue_pri2cos_cfg * + **************************/ -/* hwrm_queue_cfg_input (size:320b/40B) */ -struct hwrm_queue_cfg_input { +/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ +struct hwrm_queue_pri2cos_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21776,50 +32046,123 @@ struct hwrm_queue_cfg_input { * This enumeration is used for resources that are similar for both * TX and RX paths of the chip. */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 /* tx path */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) /* rx path */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) /* Bi-directional (Symmetrically applicable to TX and RX paths) */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR + /* + * When this bit is set to '0', the mapping is requested + * for PRI from tunnel headers. + * When this bit is set to '1', the mapping is requested + * for PRI from inner packet headers. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) uint32_t enables; /* - * This bit must be '1' for the dflt_len field to be + * This bit must be '1' for the pri0_cos_queue_id field to be * configured. */ - #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \ + UINT32_C(0x1) /* - * This bit must be '1' for the service_profile field to be + * This bit must be '1' for the pri1_cos_queue_id field to be * configured. */ - #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2) - /* Queue ID of queue that is to be configured by this function. */ - uint32_t queue_id; + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \ + UINT32_C(0x2) /* - * This value is a the estimate packet length used in the - * TX arbiter. - * Set to 0xFF... (All Fs) to not adjust this value. + * This bit must be '1' for the pri2_cos_queue_id field to be + * configured. */ - uint32_t dflt_len; - /* This value is applicable to CoS queues only. */ - uint8_t service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) - /* Lossless */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the pri3_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the pri4_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the pri5_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the pri6_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the pri7_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + /* + * CoS Queue assigned to priority 0. This value can only + * be changed before traffic has started. + */ + uint8_t pri0_cos_queue_id; + /* + * CoS Queue assigned to priority 1. This value can only + * be changed before traffic has started. + */ + uint8_t pri1_cos_queue_id; + /* + * CoS Queue assigned to priority 2 This value can only + * be changed before traffic has started. + */ + uint8_t pri2_cos_queue_id; + /* + * CoS Queue assigned to priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t pri3_cos_queue_id; + /* + * CoS Queue assigned to priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t pri4_cos_queue_id; + /* + * CoS Queue assigned to priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t pri5_cos_queue_id; + /* + * CoS Queue assigned to priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t pri6_cos_queue_id; + /* + * CoS Queue assigned to priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t pri7_cos_queue_id; uint8_t unused_0[7]; } __rte_packed; -/* hwrm_queue_cfg_output (size:128b/16B) */ -struct hwrm_queue_cfg_output { +/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ +struct hwrm_queue_pri2cos_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21839,375 +32182,1039 @@ struct hwrm_queue_cfg_output { uint8_t valid; } __rte_packed; -/***************************** - * hwrm_queue_pfcenable_qcfg * - *****************************/ +/************************** + * hwrm_queue_cos2bw_qcfg * + **************************/ -/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_qcfg_input { +/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ +struct hwrm_queue_cos2bw_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure TC BW assignment on this port. + */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ +struct hwrm_queue_cos2bw_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; /* The HWRM command request type. */ uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* ID of CoS Queue 0. */ + uint8_t queue_id0; + uint8_t unused_0; + uint16_t unused_1; + /* + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id0_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id0_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id0_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) + /* + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. + */ + uint8_t queue_id0_pri_lvl; + /* + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. + */ + uint8_t queue_id0_bw_weight; + /* ID of CoS Queue 1. */ + uint8_t queue_id1; + /* + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id1_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t cmpl_ring; + uint32_t queue_id1_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id1_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint16_t seq_id; + uint8_t queue_id1_pri_lvl; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t target_id; + uint8_t queue_id1_bw_weight; + /* ID of CoS Queue 2. */ + uint8_t queue_id2; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint64_t resp_addr; + uint32_t queue_id2_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t port_id; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; - /* If set to 1, then PFC is enabled on PRI 0. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \ + uint32_t queue_id2_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id2_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ UINT32_C(0x1) - /* If set to 1, then PFC is enabled on PRI 1. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \ + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) - /* If set to 1, then PFC is enabled on PRI 2. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \ - UINT32_C(0x4) - /* If set to 1, then PFC is enabled on PRI 3. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \ - UINT32_C(0x8) - /* If set to 1, then PFC is enabled on PRI 4. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \ - UINT32_C(0x10) - /* If set to 1, then PFC is enabled on PRI 5. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \ - UINT32_C(0x20) - /* If set to 1, then PFC is enabled on PRI 6. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \ - UINT32_C(0x40) - /* If set to 1, then PFC is enabled on PRI 7. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ - UINT32_C(0x80) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x100) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x200) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x400) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x800) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x1000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x2000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x4000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x8000) - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/**************************** - * hwrm_queue_pfcenable_cfg * - ****************************/ - - -/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint16_t cmpl_ring; + uint8_t queue_id2_pri_lvl; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t seq_id; + uint8_t queue_id2_bw_weight; + /* ID of CoS Queue 3. */ + uint8_t queue_id3; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t target_id; + uint32_t queue_id3_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint64_t resp_addr; - uint32_t flags; - /* If set to 1, then PFC is requested to be enabled on PRI 0. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \ + uint32_t queue_id3_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id3_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ UINT32_C(0x1) - /* If set to 1, then PFC is requested to be enabled on PRI 1. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) - /* If set to 1, then PFC is requested to be enabled on PRI 2. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ - UINT32_C(0x4) - /* If set to 1, then PFC is requested to be enabled on PRI 3. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ - UINT32_C(0x8) - /* If set to 1, then PFC is requested to be enabled on PRI 4. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ - UINT32_C(0x10) - /* If set to 1, then PFC is requested to be enabled on PRI 5. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ - UINT32_C(0x20) - /* If set to 1, then PFC is requested to be enabled on PRI 6. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ - UINT32_C(0x40) - /* If set to 1, then PFC is requested to be enabled on PRI 7. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ - UINT32_C(0x80) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x100) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x200) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x400) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x800) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x1000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x2000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x4000) - /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ - UINT32_C(0x8000) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint16_t port_id; - uint8_t unused_0[2]; -} __rte_packed; - -/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/*************************** - * hwrm_queue_pri2cos_qcfg * - ***************************/ - - -/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. + */ + uint8_t queue_id3_pri_lvl; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t cmpl_ring; + uint8_t queue_id3_bw_weight; + /* ID of CoS Queue 4. */ + uint8_t queue_id4; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t seq_id; + uint32_t queue_id4_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t target_id; + uint32_t queue_id4_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id4_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint64_t resp_addr; - uint32_t flags; + uint8_t queue_id4_pri_lvl; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX + uint8_t queue_id4_bw_weight; + /* ID of CoS Queue 5. */ + uint8_t queue_id5; /* - * When this bit is set to '0', the query is - * for PRI from tunnel headers. - * When this bit is set to '1', the query is - * for PRI from inner packet headers. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) + uint32_t queue_id5_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t port_id; - uint8_t unused_0[3]; -} __rte_packed; - -/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint32_t queue_id5_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id5_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * CoS Queue assigned to priority 0. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t pri0_cos_queue_id; + uint8_t queue_id5_pri_lvl; /* - * CoS Queue assigned to priority 1. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint8_t pri1_cos_queue_id; + uint8_t queue_id5_bw_weight; + /* ID of CoS Queue 6. */ + uint8_t queue_id6; /* - * CoS Queue assigned to priority 2. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t pri2_cos_queue_id; + uint32_t queue_id6_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID /* - * CoS Queue assigned to priority 3. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t pri3_cos_queue_id; + uint32_t queue_id6_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id6_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * CoS Queue assigned to priority 4. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t pri4_cos_queue_id; + uint8_t queue_id6_pri_lvl; /* - * CoS Queue assigned to priority 5. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint8_t pri5_cos_queue_id; + uint8_t queue_id6_bw_weight; + /* ID of CoS Queue 7. */ + uint8_t queue_id7; /* - * CoS Queue assigned to priority 6. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t pri6_cos_queue_id; + uint32_t queue_id7_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id7_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id7_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * CoS Queue assigned to priority 7. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t pri7_cos_queue_id; - /* Information about queue configuration. */ - uint8_t queue_cfg_info; + uint8_t queue_id7_pri_lvl; /* - * If this flag is set to '1', then the PRI to CoS - * configuration is asymmetric on TX and RX sides. - * If this flag is set to '0', then PRI to CoS configuration - * is symmetric on TX and RX sides. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ - UINT32_C(0x1) - uint8_t unused_0[6]; + uint8_t queue_id7_bw_weight; + uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22218,13 +33225,13 @@ struct hwrm_queue_pri2cos_qcfg_output { uint8_t valid; } __rte_packed; -/************************** - * hwrm_queue_pri2cos_cfg * - **************************/ +/************************* + * hwrm_queue_cos2bw_cfg * + *************************/ -/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ -struct hwrm_queue_pri2cos_cfg_input { +/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ +struct hwrm_queue_cos2bw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22254,205 +33261,64 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint64_t resp_addr; uint32_t flags; - /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 - /* tx path */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - /* Bi-directional (Symmetrically applicable to TX and RX paths) */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR - /* - * When this bit is set to '0', the mapping is requested - * for PRI from tunnel headers. - * When this bit is set to '1', the mapping is requested - * for PRI from inner packet headers. - */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) uint32_t enables; /* - * This bit must be '1' for the pri0_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id0 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \ UINT32_C(0x1) /* - * This bit must be '1' for the pri1_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id1 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \ UINT32_C(0x2) /* - * This bit must be '1' for the pri2_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id2 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \ UINT32_C(0x4) /* - * This bit must be '1' for the pri3_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id3 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \ UINT32_C(0x8) /* - * This bit must be '1' for the pri4_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id4 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \ UINT32_C(0x10) /* - * This bit must be '1' for the pri5_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id5 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \ UINT32_C(0x20) /* - * This bit must be '1' for the pri6_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id6 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \ UINT32_C(0x40) /* - * This bit must be '1' for the pri7_cos_queue_id field to be - * configured. + * If this bit is set to 1, then all queue_id7 related + * parameters in this command are valid. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \ UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - /* - * CoS Queue assigned to priority 0. This value can only - * be changed before traffic has started. - */ - uint8_t pri0_cos_queue_id; - /* - * CoS Queue assigned to priority 1. This value can only - * be changed before traffic has started. - */ - uint8_t pri1_cos_queue_id; - /* - * CoS Queue assigned to priority 2 This value can only - * be changed before traffic has started. - */ - uint8_t pri2_cos_queue_id; - /* - * CoS Queue assigned to priority 3. This value can only - * be changed before traffic has started. - */ - uint8_t pri3_cos_queue_id; - /* - * CoS Queue assigned to priority 4. This value can only - * be changed before traffic has started. - */ - uint8_t pri4_cos_queue_id; - /* - * CoS Queue assigned to priority 5. This value can only - * be changed before traffic has started. - */ - uint8_t pri5_cos_queue_id; - /* - * CoS Queue assigned to priority 6. This value can only - * be changed before traffic has started. - */ - uint8_t pri6_cos_queue_id; - /* - * CoS Queue assigned to priority 7. This value can only - * be changed before traffic has started. - */ - uint8_t pri7_cos_queue_id; - uint8_t unused_0[7]; -} __rte_packed; - -/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ -struct hwrm_queue_pri2cos_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/************************** - * hwrm_queue_cos2bw_qcfg * - **************************/ - - -/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ -struct hwrm_queue_cos2bw_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed * to configure TC BW assignment on this port. */ uint16_t port_id; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ -struct hwrm_queue_cos2bw_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; /* ID of CoS Queue 0. */ uint8_t queue_id0; uint8_t unused_0; - uint16_t unused_1; /* * Minimum BW allocated to CoS Queue. * The HWRM will translate this value into byte counter and @@ -22460,46 +33326,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id0_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS Queue. * The HWRM will translate this value into byte counter and @@ -22507,59 +33373,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id0_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id0_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -22582,46 +33448,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id1_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -22629,59 +33495,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id1_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id1_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -22704,46 +33570,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id2_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -22751,59 +33617,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id2_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id2_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -22826,46 +33692,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id3_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -22873,59 +33739,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id3_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id3_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -22948,46 +33814,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id4_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -22995,59 +33861,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id4_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id4_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -23070,46 +33936,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id5_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -23117,59 +33983,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id5_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id5_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -23192,46 +34058,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id6_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -23239,59 +34105,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id6_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id6_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -23314,46 +34180,46 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id7_min_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated to CoS queue. * The HWRM will translate this value into byte counter and @@ -23361,59 +34227,59 @@ struct hwrm_queue_cos2bw_qcfg_output { */ uint32_t queue_id7_max_bw; /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID /* Transmission Selection Algorithm (TSA) for CoS Queue. */ uint8_t queue_id7_tsa_assign; /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ UINT32_C(0x0) /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ UINT32_C(0x1) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ UINT32_C(0xff) /* * Priority level for strict priority. Valid only when the @@ -23421,13 +34287,179 @@ struct hwrm_queue_cos2bw_qcfg_output { * 0..7 - Valid values. * 8..255 - Reserved. */ - uint8_t queue_id7_pri_lvl; + uint8_t queue_id7_pri_lvl; + /* + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. + */ + uint8_t queue_id7_bw_weight; + uint8_t unused_1[5]; +} __rte_packed; + +/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ +struct hwrm_queue_cos2bw_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ + + +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ + + +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This is the default PRI which un-initialized DSCP values are + * mapped to. */ - uint8_t queue_id7_bw_weight; - uint8_t unused_2[4]; + uint8_t default_pri; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23438,13 +34470,13 @@ struct hwrm_queue_cos2bw_qcfg_output { uint8_t valid; } __rte_packed; -/************************* - * hwrm_queue_cos2bw_cfg * - *************************/ +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ -/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ -struct hwrm_queue_cos2bw_cfg_input { +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23473,1044 +34505,405 @@ struct hwrm_queue_cos2bw_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. A non-zero mask "adds" a tuple, while + * a mask equal to 0 triggers the firmware to remove a tuple. + * Only tuples with unique DSCP values are stored. On chips + * prior to Thor a mask can be 0 - 0x3f, while on Thor it can + * be 0 or 0x3f. + */ + uint64_t src_data_addr; uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + UINT32_C(0x1) uint32_t enables; /* - * If this bit is set to 1, then all queue_id0 related - * parameters in this command are valid. + * This bit must be '1' for the default_pri field to be + * configured. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ UINT32_C(0x1) /* - * If this bit is set to 1, then all queue_id1 related - * parameters in this command are valid. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \ - UINT32_C(0x2) + uint8_t port_id; /* - * If this bit is set to 1, then all queue_id2 related - * parameters in this command are valid. + * This is the default PRI which un-initialized DSCP values will be + * mapped to. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \ - UINT32_C(0x4) + uint8_t default_pri; /* - * If this bit is set to 1, then all queue_id3 related - * parameters in this command are valid. + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \ - UINT32_C(0x8) + uint16_t entry_cnt; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * If this bit is set to 1, then all queue_id4 related - * parameters in this command are valid. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \ - UINT32_C(0x10) + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_mpls_qcaps * + *************************/ + + +/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ +struct hwrm_queue_mpls_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If this bit is set to 1, then all queue_id5 related - * parameters in this command are valid. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \ - UINT32_C(0x20) + uint16_t cmpl_ring; /* - * If this bit is set to 1, then all queue_id6 related - * parameters in this command are valid. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \ - UINT32_C(0x40) + uint16_t seq_id; /* - * If this bit is set to 1, then all queue_id7 related - * parameters in this command are valid. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \ - UINT32_C(0x80) + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed - * to configure TC BW assignment on this port. + * to configure MPLS TC(EXP) to pri mapping on this port. */ - uint16_t port_id; - /* ID of CoS Queue 0. */ - uint8_t queue_id0; - uint8_t unused_0; + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ +struct hwrm_queue_mpls_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_mplstc2pri_cfg command. + * + * Each bit represents a specific pri where bit 0 represents + * pri 0 and bit 7 represents pri 7. + * # A value of 0 indicates that the pri is not configurable + * by the hwrm_queue_mplstc2pri_cfg command. + * # A value of 1 indicates that the pri is configurable. + * # A hwrm_queue_mplstc2pri_cfg command shall return error when + * trying to configure a pri that is not configurable. */ - uint32_t queue_id0_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t queue_mplstc2pri_cfg_allowed; /* - * Maximum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This is the default PRI which un-initialized MPLS values will be + * mapped to. */ - uint32_t queue_id0_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id0_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t hw_default_pri; + uint8_t unused_0[5]; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t queue_id0_pri_lvl; + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_mplstc2pri_qcfg * + ******************************/ + + +/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t queue_id0_bw_weight; - /* ID of CoS Queue 1. */ - uint8_t queue_id1; + uint16_t cmpl_ring; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t queue_id1_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t seq_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t queue_id1_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id1_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t target_id; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t queue_id1_pri_lvl; + uint64_t resp_addr; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. */ - uint8_t queue_id1_bw_weight; - /* ID of CoS Queue 2. */ - uint8_t queue_id2; + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 0. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 0. */ - uint32_t queue_id2_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 1. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 2. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 3. + */ + uint8_t tc3_pri_queue_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 4. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 4. */ - uint32_t queue_id2_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id2_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t tc4_pri_queue_id; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * pri assigned to MPLS TC(EXP) 5. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 5. */ - uint8_t queue_id2_pri_lvl; + uint8_t tc5_pri_queue_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 6. */ - uint8_t queue_id2_bw_weight; - /* ID of CoS Queue 3. */ - uint8_t queue_id3; + uint8_t tc6_pri_queue_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 7. */ - uint32_t queue_id3_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t tc7_pri_queue_id; + uint8_t unused_0[7]; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t queue_id3_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id3_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_queue_mplstc2pri_cfg * + *****************************/ + + +/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_mplstc2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t queue_id3_pri_lvl; + uint16_t cmpl_ring; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id3_bw_weight; - /* ID of CoS Queue 4. */ - uint8_t queue_id4; + uint16_t seq_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t queue_id4_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t target_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id4_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id4_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the mplstc0_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + /* + * This bit must be '1' for the mplstc1_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This bit must be '1' for the mplstc2_pri_queue_id field to be + * configured. */ - uint8_t queue_id4_pri_lvl; + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ + UINT32_C(0x4) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This bit must be '1' for the mplstc3_pri_queue_id field to be + * configured. */ - uint8_t queue_id4_bw_weight; - /* ID of CoS Queue 5. */ - uint8_t queue_id5; + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ + UINT32_C(0x8) /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the mplstc4_pri_queue_id field to be + * configured. */ - uint32_t queue_id5_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ + UINT32_C(0x10) /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the mplstc5_pri_queue_id field to be + * configured. */ - uint32_t queue_id5_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id5_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ + UINT32_C(0x20) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This bit must be '1' for the mplstc6_pri_queue_id field to be + * configured. */ - uint8_t queue_id5_pri_lvl; + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ + UINT32_C(0x40) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This bit must be '1' for the mplstc7_pri_queue_id field to be + * configured. */ - uint8_t queue_id5_bw_weight; - /* ID of CoS Queue 6. */ - uint8_t queue_id6; + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ + UINT32_C(0x80) /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP)to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only + * be changed before traffic has started. */ - uint32_t queue_id6_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t tc0_pri_queue_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 1. This value can only + * be changed before traffic has started. */ - uint32_t queue_id6_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id6_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t tc1_pri_queue_id; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * pri assigned to MPLS TC(EXP) 2 This value can only + * be changed before traffic has started. */ - uint8_t queue_id6_pri_lvl; + uint8_t tc2_pri_queue_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * pri assigned to MPLS TC(EXP) 3. This value can only + * be changed before traffic has started. */ - uint8_t queue_id6_bw_weight; - /* ID of CoS Queue 7. */ - uint8_t queue_id7; + uint8_t tc3_pri_queue_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 4. This value can only + * be changed before traffic has started. */ - uint32_t queue_id7_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t tc4_pri_queue_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * pri assigned to MPLS TC(EXP) 5. This value can only + * be changed before traffic has started. */ - uint32_t queue_id7_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id7_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t tc5_pri_queue_id; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. */ - uint8_t queue_id7_pri_lvl; + uint8_t tc6_pri_queue_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. */ - uint8_t queue_id7_bw_weight; - uint8_t unused_1[5]; + uint8_t tc7_pri_queue_id; } __rte_packed; -/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ -struct hwrm_queue_cos2bw_cfg_output { +/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_mplstc2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24530,13 +34923,13 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t valid; } __rte_packed; -/************************* - * hwrm_queue_dscp_qcaps * - *************************/ +/**************************** + * hwrm_queue_vlanpri_qcaps * + ****************************/ -/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ -struct hwrm_queue_dscp_qcaps_input { +/* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */ +struct hwrm_queue_vlanpri_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24568,14 +34961,14 @@ struct hwrm_queue_dscp_qcaps_input { /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; uint8_t unused_0[7]; } __rte_packed; -/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ -struct hwrm_queue_dscp_qcaps_output { +/* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */ +struct hwrm_queue_vlanpri_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24584,12 +34977,12 @@ struct hwrm_queue_dscp_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of bits provided by the hardware for the DSCP value. */ - uint8_t num_dscp_bits; - uint8_t unused_0; - /* Max number of DSCP-MASK-PRI entries supported. */ - uint16_t max_entries; - uint8_t unused_1[3]; + /* + * This is the default user priority which all VLAN priority values + * are mapped to if there is no VLAN priority to user priority mapping. + */ + uint8_t hw_default_pri; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24600,13 +34993,13 @@ struct hwrm_queue_dscp_qcaps_output { uint8_t valid; } __rte_packed; -/**************************** - * hwrm_queue_dscp2pri_qcfg * - ****************************/ +/******************************* + * hwrm_queue_vlanpri2pri_qcfg * + *******************************/ -/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ -struct hwrm_queue_dscp2pri_qcfg_input { +/* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24635,25 +35028,17 @@ struct hwrm_queue_dscp2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI - * tuple(s) will be copied to. - */ - uint64_t dest_data_addr; /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; - uint8_t unused_0; - /* Size of the buffer pointed to by dest_data_addr. */ - uint16_t dest_data_buffer_size; - uint8_t unused_1[4]; + uint8_t unused_0[7]; } __rte_packed; -/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_qcfg_output { +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24663,16 +35048,54 @@ struct hwrm_queue_dscp2pri_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * A count of the number of DSCP-MASK-PRI tuple(s) pointed to - * by the dest_data_addr. + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. */ - uint16_t entry_cnt; + uint8_t vlanpri0_user_pri_id; /* - * This is the default PRI which un-initialized DSCP values are - * mapped to. + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. */ - uint8_t default_pri; - uint8_t unused_0[4]; + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24683,13 +35106,13 @@ struct hwrm_queue_dscp2pri_qcfg_output { uint8_t valid; } __rte_packed; -/*************************** - * hwrm_queue_dscp2pri_cfg * - ***************************/ +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ -/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ -struct hwrm_queue_dscp2pri_cfg_input { +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24718,43 +35141,106 @@ struct hwrm_queue_dscp2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * This is the host address where the 24-bits DSCP-MASK-PRI tuple - * will be copied from. + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. */ - uint64_t src_data_addr; - uint32_t flags; - /* use_hw_default_pri is 1 b */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ UINT32_C(0x1) - uint32_t enables; /* - * This bit must be '1' for the default_pri field to be + * This bit must be '1' for the vlanpri1_user_pri_id field to be * configured. */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ - UINT32_C(0x1) + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; + uint8_t unused_0[3]; /* - * This is the default PRI which un-initialized DSCP values will be - * mapped to. + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. */ - uint8_t default_pri; + uint8_t vlanpri0_user_pri_id; /* - * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed - * to by src_data_addr. + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. */ - uint16_t entry_cnt; - uint8_t unused_0[4]; + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri7_user_pri_id; } __rte_packed; -/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_cfg_output { +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24775,12 +35261,12 @@ struct hwrm_queue_dscp2pri_cfg_output { } __rte_packed; /************************* - * hwrm_queue_mpls_qcaps * + * hwrm_queue_global_cfg * *************************/ -/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ -struct hwrm_queue_mpls_qcaps_input { +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24810,16 +35296,83 @@ struct hwrm_queue_mpls_qcaps_input { */ uint64_t resp_addr; /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP) to pri mapping on this port. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - uint8_t port_id; - uint8_t unused_0[7]; + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) + /* + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) + /* + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) + /* + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) + /* + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) + /* + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g1_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g2_max_bw; + /* + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. + */ + uint8_t g3_max_bw; } __rte_packed; -/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ -struct hwrm_queue_mpls_qcaps_output { +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24828,25 +35381,7 @@ struct hwrm_queue_mpls_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_mplstc2pri_cfg command. - * - * Each bit represents a specific pri where bit 0 represents - * pri 0 and bit 7 represents pri 7. - * # A value of 0 indicates that the pri is not configurable - * by the hwrm_queue_mplstc2pri_cfg command. - * # A value of 1 indicates that the pri is configurable. - * # A hwrm_queue_mplstc2pri_cfg command shall return error when - * trying to configure a pri that is not configurable. - */ - uint8_t queue_mplstc2pri_cfg_allowed; - /* - * This is the default PRI which un-initialized MPLS values will be - * mapped to. - */ - uint8_t hw_default_pri; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24857,13 +35392,13 @@ struct hwrm_queue_mpls_qcaps_output { uint8_t valid; } __rte_packed; -/****************************** - * hwrm_queue_mplstc2pri_qcfg * - ******************************/ +/************************** + * hwrm_queue_global_qcfg * + **************************/ -/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_input { +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24892,17 +35427,10 @@ struct hwrm_queue_mplstc2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP) to pri mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; } __rte_packed; -/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24911,63 +35439,95 @@ struct hwrm_queue_mplstc2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; /* - * pri assigned to MPLS TC(EXP) 0. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 0. + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint */ - uint8_t tc0_pri_queue_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) /* - * pri assigned to MPLS TC(EXP) 1. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 1. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. */ - uint8_t tc1_pri_queue_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) /* - * pri assigned to MPLS TC(EXP) 2. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 2. + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. */ - uint8_t tc2_pri_queue_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT /* - * pri assigned to MPLS TC(EXP) 3. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 3. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - uint8_t tc3_pri_queue_id; + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) /* - * pri assigned to MPLS TC(EXP) 4. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 4. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - uint8_t tc4_pri_queue_id; + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; /* - * pri assigned to MPLS TC(EXP) 5. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 5. + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t tc5_pri_queue_id; + uint8_t g0_max_bw; /* - * pri assigned to MPLS TC(EXP) 6. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 6. + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t tc6_pri_queue_id; + uint8_t g1_max_bw; /* - * pri assigned to MPLS TC(EXP) 7. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 7. + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. */ - uint8_t tc7_pri_queue_id; - uint8_t unused_0[7]; + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24978,13 +35538,13 @@ struct hwrm_queue_mplstc2pri_qcfg_output { uint8_t valid; } __rte_packed; -/***************************** - * hwrm_queue_mplstc2pri_cfg * - *****************************/ +/******************* + * hwrm_vnic_alloc * + *******************/ -/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_mplstc2pri_cfg_input { +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25013,106 +35573,31 @@ struct hwrm_queue_mplstc2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; + uint32_t flags; /* - * This bit must be '1' for the mplstc0_pri_queue_id field to be - * configured. + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \ UINT32_C(0x1) /* - * This bit must be '1' for the mplstc1_pri_queue_id field to be - * configured. + * When this bit is '1', proxy VEE PF is requesting + * allocation of a default VNIC on behalf of virtio-net + * function given in virtio_net_fid field. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \ UINT32_C(0x2) /* - * This bit must be '1' for the mplstc2_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the mplstc3_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ - UINT32_C(0x8) - /* - * This bit must be '1' for the mplstc4_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ - UINT32_C(0x10) - /* - * This bit must be '1' for the mplstc5_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the mplstc6_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the mplstc7_pri_queue_id field to be - * configured. - */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP)to pri mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[3]; - /* - * pri assigned to MPLS TC(EXP) 0. This value can only - * be changed before traffic has started. - */ - uint8_t tc0_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 1. This value can only - * be changed before traffic has started. - */ - uint8_t tc1_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 2 This value can only - * be changed before traffic has started. - */ - uint8_t tc2_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 3. This value can only - * be changed before traffic has started. - */ - uint8_t tc3_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 4. This value can only - * be changed before traffic has started. - */ - uint8_t tc4_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 5. This value can only - * be changed before traffic has started. - */ - uint8_t tc5_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 6. This value can only - * be changed before traffic has started. - */ - uint8_t tc6_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 7. This value can only - * be changed before traffic has started. + * Virtio-net function's FID. + * This virtio-net function is requesting allocation of default + * VNIC through proxy VEE PF. */ - uint8_t tc7_pri_queue_id; + uint16_t virtio_net_fid; + uint8_t unused_0[2]; } __rte_packed; -/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_mplstc2pri_cfg_output { +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25121,10 +35606,12 @@ struct hwrm_queue_mplstc2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -25132,13 +35619,13 @@ struct hwrm_queue_mplstc2pri_cfg_output { uint8_t valid; } __rte_packed; -/******************* - * hwrm_vnic_alloc * - *******************/ +/******************** + * hwrm_vnic_update * + ********************/ -/* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { +/* hwrm_vnic_update_input (size:256b/32B) */ +struct hwrm_vnic_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25167,17 +35654,77 @@ struct hwrm_vnic_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + /* Logical vnic ID */ + uint32_t vnic_id; + uint32_t enables; /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. + * This bit must be '1' for the vnic_state field to be + * configured. */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - uint8_t unused_0[4]; + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the metadata_format_type field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \ + UINT32_C(0x4) + /* + * This will update the context variable with the same name if + * the corresponding enable is set. + */ + uint8_t vnic_state; + /* Normal operation state for the VNIC. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* All packets are dropped in this state. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \ + HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP + /* + * The metadata format type used in all the RX packet completions + * going through this VNIC. + */ + uint8_t metadata_format_type; + /* No metadata information. */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \ + UINT32_C(0x0) + /* + * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], + * vtag[19:0]). + */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \ + UINT32_C(0x1) + /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \ + UINT32_C(0x2) + /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \ + UINT32_C(0x3) + /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \ + UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \ + HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { +/* hwrm_vnic_update_output (size:128b/16B) */ +struct hwrm_vnic_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25186,15 +35733,14 @@ struct hwrm_vnic_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -25414,6 +35960,9 @@ struct hwrm_vnic_cfg_input { /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \ UINT32_C(0x100) + /* This bit must be '1' for the l2_cqe_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE \ + UINT32_C(0x200) /* Logical vnic ID */ uint16_t vnic_id; /* @@ -25464,7 +36013,7 @@ struct hwrm_vnic_cfg_input { * queue ID will be arriving on this VNIC. Packet priority to CoS mapping * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, * ntuple filters with VNIC destination specified are invalid since they - * conflict with the the CoS to VNIC steering rules in this mode. + * conflict with the CoS to VNIC steering rules in this mode. * * If this field is not specified, packet to VNIC steering will be * subject to the standard L2 filter rules and any additional ntuple @@ -25505,7 +36054,37 @@ struct hwrm_vnic_cfg_input { #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX - uint8_t unused0[5]; + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to configure the + * CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * When configured with this cqe mode, A normal (32B) CQE + * will be generated. This is the default mode. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this cqe mode, A compressed (16B) CQE + * will be generated. In this mode TPA and HDS are not supported. + * Host drivers should not configure the TPA and HDS along with + * compressed mode, per VNIC. FW returns error, if host drivers + * try to configure the VNIC with compressed mode and (TPA or HDS). + * The compressed completion does not include PTP data. Host + * drivers should not use this mode to receive the PTP data. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * When configured with this cqe mode, HW generates either a 32B + * completion or a 16B completion depending on use case within a + * VNIC. For ex. a simple L2 packet could use the compressed form + * while a PTP packet on the same VNIC would use the 32B form. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST \ + HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED + uint8_t unused0[4]; } __rte_packed; /* hwrm_vnic_cfg_output (size:128b/16B) */ @@ -25674,6 +36253,12 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) + /* + * When this bit is '0', VNIC is in normal operation state. + * When this bit is '1', VNIC drops all the received packets. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \ + UINT32_C(0x80) /* * When returned with a valid CoS Queue id, the CoS Queue/VNIC association * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS @@ -25706,7 +36291,31 @@ struct hwrm_vnic_qcfg_output { #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \ HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX - uint8_t unused_1[4]; + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to convey the + * configured CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * This value indicates that the VNIC is configured with normal + * (32B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured with compressed + * (16B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * This value indicates that the VNIC is configured with mixed + * CQE mode. HW generates either a 32B completion or a 16B + * completion depending on use case within a VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -25820,7 +36429,7 @@ struct hwrm_vnic_qcaps_output { UINT32_C(0x20) /* * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. + * mirror the RoCE traffic is supported. * If set to '0', then the capability to mirror the * RoCE traffic is not supported. */ @@ -25838,7 +36447,7 @@ struct hwrm_vnic_qcaps_output { * ability to steer incoming packets from one CoS queue to one * VNIC. This optional feature can then be enabled * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classfication” is set + * available when NVM option “enable_cos_classification” is set * to 1. If set to '0', firmware does not support this feature. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ @@ -25848,16 +36457,110 @@ struct hwrm_vnic_qcaps_output { * the use of RX V2 and RX TPA start V2 completion records for all * the RX rings of a VNIC. Once set, this feature is mandatory to * be used for the RX rings of the VNIC. Additionally, two new RX - * checksum features supported by these ompletion records can be + * checksum features supported by these completion records can be * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the * HW and the firmware does not support this feature. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \ UINT32_C(0x200) + /* + * When this bit is '1', it indicates that HW and firmware support + * vnic state change. Host drivers can change the vnic state using + * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not + * support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates that firmware supports + * virtio-net functions default VNIC allocation using + * HWRM_VNIC_ALLOC. + * This capability is available only on Proxy VEE PF. If set to '0', + * firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \ + UINT32_C(0x800) + /* + * When this bit is set '1', then the capability to configure the + * metadata format in the RX completion is supported for the VNIC. + * When this bit is set to '0', then the capability to configure + * the metadata format in the RX completion is not supported for + * the VNIC. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ + UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) + /* + * When this bit is set '1', it indicates that firmware supports + * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that HW is capable of using + * Toeplitz algorithm. This mode uses Toeplitz algorithm and + * provided Toeplitz hash key to hash the packets according to the + * configured hash type and hash mode. The Toeplitz hash results and + * the provided Toeplitz RSS indirection table are used to determine + * the RSS rings. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that HW is capable of using + * XOR algorithm. This mode uses XOR algorithm to hash the packets + * according to the configured hash type and hash mode. The XOR + * hash results and the provided XOR RSS indirection table are + * used to determine the RSS rings. Host drivers provided hash key + * is not honored in this mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP \ + UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that HW is capable of using + * checksum algorithm. In this mode, HW uses inner packets checksum + * algorithm to distribute the packets across the rings and Toeplitz + * algorithm to calculate the hash to convey it in the RX + * completions. Host drivers should provide Toeplitz hash key. + * As HW uses innermost packets checksum to distribute the packets + * across the rings, host drivers can't convey hash mode to choose + * outer headers to calculate Toeplitz hash. FW will fail such + * configuration. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP \ + UINT32_C(0x20000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPV6 flow labels. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \ + UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V3 and RX TPA start V3 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP \ + UINT32_C(0x80000) + /* + * When this bit is '1' HW supports different RX CQE record types. + * Host drivers can choose the mode based on their application + * requirements like performance, TPA, HDS and PTP. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \ + UINT32_C(0x100000) /* * This field advertises the maximum concurrent TPA aggregations - * supported by the VNIC on new devices that support TPA v2. - * '0' means that TPA v2 is not supported. + * supported by the VNIC on new devices that support TPA v2 or v3. + * '0' means that both the TPA v2 and v3 are not supported. */ uint16_t max_aggs_supported; uint8_t unused_1[5]; @@ -26118,37 +36821,54 @@ struct hwrm_vnic_rss_cfg_input { * over source and destination IPv4 addresses of IPv4 * packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 \ + UINT32_C(0x1) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 \ + UINT32_C(0x2) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 \ + UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 \ + UINT32_C(0x8) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 \ + UINT32_C(0x10) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 \ + UINT32_C(0x20) + /* + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. Host drivers should set this bit based on + * rss_ipv6_flow_label_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \ + UINT32_C(0x40) /* VNIC ID of VNIC associated with RSS table being configured. */ uint16_t vnic_id; /* @@ -26204,7 +36924,66 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t ring_select_mode; + /* + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ \ + UINT32_C(0x0) + /* + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR \ + UINT32_C(0x1) + /* + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST \ + HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[4]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -26320,7 +37099,7 @@ struct hwrm_vnic_rss_qcfg_output { #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -26381,7 +37160,39 @@ struct hwrm_vnic_rss_qcfg_output { */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) - uint8_t unused_1[6]; + uint8_t ring_select_mode; + /* + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ \ + UINT32_C(0x0) + /* + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR \ + UINT32_C(0x1) + /* + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_LAST \ + HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -26547,7 +37358,7 @@ struct hwrm_vnic_plcmodes_cfg_input { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -26711,7 +37522,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -26929,11 +37740,17 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ UINT32_C(0x100) /* - * This bit must be '1' for the sq_id field to be + * This bit must be '1' for the schq_id field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \ UINT32_C(0x200) + /* + * This bit must be '1' for the mpc_chnls_type field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \ + UINT32_C(0x400) /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ @@ -26950,7 +37767,47 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; + /* + * This field controls the number of packets transmitted before a TX + * completion is generated. Non-zero values for the field are only + * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion + * records capability is supported. + */ + uint8_t cmpl_coal_cnt; + /* Generates a legacy TX completion on every packet. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) + /* Generates a TX coalesced completion for up to 4 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) + /* Generates a TX coalesced completion for up to 8 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) + /* Generates a TX coalesced completion for up to 12 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) + /* Generates a TX coalesced completion for up to 16 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) + /* Generates a TX coalesced completion for up to 24 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) + /* Generates a TX coalesced completion for up to 32 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) + /* Generates a TX coalesced completion for up to 48 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) + /* Generates a TX coalesced completion for up to 64 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) + /* Generates a TX coalesced completion for up to 96 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) + /* Generates a TX coalesced completion for up to 128 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) + /* Generates a TX coalesced completion for up to 192 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) + /* Generates a TX coalesced completion for up to 256 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) + /* Generates a TX coalesced completion for up to 320 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) + /* Generates a TX coalesced completion for up to 384 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) + /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \ + HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX /* Ring allocation flags. */ uint16_t flags; /* @@ -26961,7 +37818,20 @@ struct hwrm_ring_alloc_input { * Rx rings and is ignored for all other rings included Rx * Aggregation rings. */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD \ + UINT32_C(0x1) + /* + * When the HW Doorbell Drop Recovery feature is enabled, + * HW can flag false CQ overflow when CQ consumer index + * doorbells are dropped when there really wasn't any overflow. + * The CQE values could have already been processed by the driver, + * but HW doesn't know about this because of the doorbell drop. + * To avoid false detection of CQ overflow events, + * it is recommended that CQ overflow detection is disabled + * by the driver when HW based doorbell recovery is enabled. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \ + UINT32_C(0x2) /* * This value is a pointer to the page table for the * Ring. @@ -26999,8 +37869,8 @@ struct hwrm_ring_alloc_input { * element of the ring. */ uint8_t page_tbl_depth; - /* Used by a PF driver to associate a SQ with one of its TX rings. */ - uint16_t sq_id; + /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ + uint16_t schq_id; /* * Number of 16B units in the ring. Minimum size for * a ring is 16 16B entries. @@ -27166,7 +38036,36 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ HWRM_RING_ALLOC_INPUT_INT_MODE_POLL - uint8_t unused_4[3]; + /* Midpath channel type */ + uint8_t mpc_chnls_type; + /* + * Indicate the TX ring alloc MPC channel type is a MPC channel + * with destination to the TX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the TX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the primate processor block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \ + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE + uint8_t unused_4[2]; /* * The cq_handle is specified when allocating a completion ring. For * devices that support NQs, this cq_handle will be included in the @@ -27193,7 +38092,20 @@ struct hwrm_ring_alloc_output { uint16_t ring_id; /* Logical number of ring allocated. */ uint16_t logical_ring_id; - uint8_t unused_0[3]; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -27209,7 +38121,7 @@ struct hwrm_ring_alloc_output { ******************/ -/* hwrm_ring_free_input (size:192b/24B) */ +/* hwrm_ring_free_input (size:256b/32B) */ struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; @@ -27255,10 +38167,37 @@ struct hwrm_ring_free_input { #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; + uint8_t flags; + /* + * If this bit is set to '1', ring_id in this command belongs to + * virtio function. prod_idx in this command corresponds to doorbell + * producer index. opaque field in this command needs to be inserted + * by firmware in VEE_FLUSH completion record. + * Firmware will poll the corresponding ring context to reach the + * given producer index before sending successful response. It will + * finish the completion using VEE_FLUSH completion record. + * + * If this bit is '0', firmware will not treat ring_id as virtio + * ring and ignore prod_idx, opaque fields. + * + * This feature is not applicable for L2 or RoCE. + */ + #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1) + #define HWRM_RING_FREE_INPUT_FLAGS_LAST \ + HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID /* Physical number of ring allocated. */ uint16_t ring_id; - uint8_t unused_1[4]; + /* + * Ring BD producer index posted by the virtio block. + * This field is valid if virtio_ring_valid flag is set. + */ + uint32_t prod_idx; + /* + * User defined opaque field to be inserted into VEE_FLUSH completion + * record. This field is valid if virtio_ring_valid flag is set. + */ + uint32_t opaque; + uint32_t unused_1; } __rte_packed; /* hwrm_ring_free_output (size:128b/16B) */ @@ -27354,7 +38293,20 @@ struct hwrm_ring_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[4]; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[3]; /* Position of consumer index after ring reset completes. */ uint8_t consumer_idx[3]; /* @@ -27372,7 +38324,7 @@ struct hwrm_ring_reset_output { *****************/ -/* hwrm_ring_cfg_input (size:256b/32B) */ +/* hwrm_ring_cfg_input (size:320b/40B) */ struct hwrm_ring_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -27453,12 +38405,22 @@ struct hwrm_ring_cfg_input { */ #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ UINT32_C(0x4) - /* The sq_id field is valid */ - #define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \ + /* The schq_id field is valid */ + #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \ UINT32_C(0x8) /* Update completion ring ID associated with Tx or Rx ring. */ #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \ UINT32_C(0x10) + /* + * When set to '1', metadata value provided by tx_metadata + * field in this command is inserted in the lb_header_metadata + * QP context field. When set to '0', no change done to metadata. + * Firmware rejects the tx ring metadata programming with + * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD + * metadata feature is not disabled. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \ + UINT32_C(0x20) /* * Proxy function FID value. * This value is only used when either proxy_mode_enable flag or @@ -27471,12 +38433,12 @@ struct hwrm_ring_cfg_input { */ uint16_t proxy_fid; /* - * Identifies the new scheduler queue (SQ) to associate with the ring. - * Only valid for Tx rings. + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. * A value of zero indicates that the Tx ring should be associated - * with the default scheduler queue (SQ). + * with the default scheduler queue (SCHQ). */ - uint16_t sq_id; + uint16_t schq_id; /* * This field is valid for TX or Rx rings. This value identifies the * new completion ring ID to associate with the TX or Rx ring. @@ -27488,6 +38450,12 @@ struct hwrm_ring_cfg_input { */ uint8_t rx_sop_pad_bytes; uint8_t unused_1[3]; + /* + * When tx_metadata enable bit is set, value specified in this field + * is copied to lb_header_metadata in the QP context. + */ + uint32_t tx_metadata; + uint8_t unused_2[4]; } __rte_packed; /* hwrm_ring_cfg_output (size:128b/16B) */ @@ -27560,7 +38528,7 @@ struct hwrm_ring_qcfg_input { uint16_t ring_id; } __rte_packed; -/* hwrm_ring_qcfg_output (size:192b/24B) */ +/* hwrm_ring_qcfg_output (size:256b/32B) */ struct hwrm_ring_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -27622,12 +38590,12 @@ struct hwrm_ring_qcfg_output { */ uint16_t proxy_fid; /* - * Identifies the new scheduler queue (SQ) to associate with the ring. - * Only valid for Tx rings. + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. * A value of zero indicates that the Tx ring should be associated with - * the default scheduler queue (SQ). + * the default scheduler queue (SCHQ). */ - uint16_t sq_id; + uint16_t schq_id; /* * This field is used when ring_type is a TX or Rx ring. * This value indicates what completion ring the TX or Rx ring @@ -27639,7 +38607,10 @@ struct hwrm_ring_qcfg_output { * This value is only used when rx_sop_pad_enable flag is set to '1'. */ uint8_t rx_sop_pad_bytes; - uint8_t unused_0[6]; + uint8_t unused_0[3]; + /* lb_header_metadata in the QP context is copied to this field. */ + uint32_t tx_metadata; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -28222,13 +39193,13 @@ struct hwrm_ring_grp_free_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_ring_sq_alloc * - **********************/ +/************************ + * hwrm_ring_schq_alloc * + ************************/ -/* hwrm_ring_sq_alloc_input (size:1088b/136B) */ -struct hwrm_ring_sq_alloc_input { +/* hwrm_ring_schq_alloc_input (size:1088b/136B) */ +struct hwrm_ring_schq_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28262,380 +39233,396 @@ struct hwrm_ring_sq_alloc_input { * This bit must be '1' for the tqm_ring0 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) /* * This bit must be '1' for the tqm_ring1 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) /* * This bit must be '1' for the tqm_ring2 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) /* * This bit must be '1' for the tqm_ring3 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) /* * This bit must be '1' for the tqm_ring4 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) /* * This bit must be '1' for the tqm_ring5 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) /* * This bit must be '1' for the tqm_ring6 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) /* * This bit must be '1' for the tqm_ring7 fields to be * configured. */ - #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) /* Reserved for future use. */ uint32_t reserved; /* TQM ring 0 page size and level. */ uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; /* TQM ring 0 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 /* TQM ring 0 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G /* TQM ring 1 page size and level. */ uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; /* TQM ring 1 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 /* TQM ring 1 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G /* TQM ring 2 page size and level. */ uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; /* TQM ring 2 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 /* TQM ring 2 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G /* TQM ring 3 page size and level. */ uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; /* TQM ring 3 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 /* TQM ring 3 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G /* TQM ring 4 page size and level. */ uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; /* TQM ring 4 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 /* TQM ring 4 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G /* TQM ring 5 page size and level. */ uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; /* TQM ring 5 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 /* TQM ring 5 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G /* TQM ring 6 page size and level. */ uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; /* TQM ring 6 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 /* TQM ring 6 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G /* TQM ring 7 page size and level. */ uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; /* TQM ring 7 PBL indirect levels. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to PTE * tables. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 /* TQM ring 7 page size. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \ - HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G /* TQM ring 0 page directory. */ uint64_t tqm_ring0_page_dir; /* TQM ring 1 page directory. */ @@ -28661,7 +39648,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring0_num_entries; /* @@ -28673,7 +39660,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring1_num_entries; /* @@ -28685,7 +39672,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring2_num_entries; /* @@ -28697,7 +39684,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring3_num_entries; /* @@ -28709,7 +39696,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring4_num_entries; /* @@ -28721,7 +39708,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring5_num_entries; /* @@ -28733,7 +39720,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring6_num_entries; /* @@ -28745,7 +39732,7 @@ struct hwrm_ring_sq_alloc_input { * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SQ and then reallocate it. + * to delete the SCHQ and then reallocate it. */ uint32_t tqm_ring7_num_entries; /* Number of bytes that have been allocated for each context entry. */ @@ -28753,8 +39740,8 @@ struct hwrm_ring_sq_alloc_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_ring_sq_alloc_output (size:128b/16B) */ -struct hwrm_ring_sq_alloc_output { +/* hwrm_ring_schq_alloc_output (size:128b/16B) */ +struct hwrm_ring_schq_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28764,11 +39751,11 @@ struct hwrm_ring_sq_alloc_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This is an identifier for the SQ to be used in other HWRM commands - * that need to reference this SQ. This value is greater than zero - * (i.e. a sq_id of zero references the default SQ). + * This is an identifier for the SCHQ to be used in other HWRM commands + * that need to reference this SCHQ. This value is greater than zero + * (i.e. a schq_id of zero references the default SCHQ). */ - uint16_t sq_id; + uint16_t schq_id; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -28780,13 +39767,13 @@ struct hwrm_ring_sq_alloc_output { uint8_t valid; } __rte_packed; -/******************** - * hwrm_ring_sq_cfg * - ********************/ +/********************** + * hwrm_ring_schq_cfg * + **********************/ -/* hwrm_ring_sq_cfg_input (size:768b/96B) */ -struct hwrm_ring_sq_cfg_input { +/* hwrm_ring_schq_cfg_input (size:768b/96B) */ +struct hwrm_ring_schq_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28816,23 +39803,23 @@ struct hwrm_ring_sq_cfg_input { */ uint64_t resp_addr; /* - * Identifies the SQ being configured. A sq_id of zero refers to the - * default SQ. + * Identifies the SCHQ being configured. A schq_id of zero refers to + * the default SCHQ. */ - uint16_t sq_id; + uint16_t schq_id; /* * This field is an 8 bit bitmap that indicates which TCs are enabled - * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents + * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents * traffic class 7. */ uint8_t tc_enabled; uint8_t unused_0; uint32_t flags; /* The tc_max_bw array and the max_bw parameters are valid */ - #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \ UINT32_C(0x1) /* The tc_min_bw array is valid */ - #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \ UINT32_C(0x2) /* Maximum bandwidth of the traffic class, specified in Mbps. */ uint32_t max_bw_tc0; @@ -28854,68 +39841,68 @@ struct hwrm_ring_sq_cfg_input { * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc0; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc1; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc2; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc3; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc4; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc5; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc6; /* * Bandwidth reservation for the traffic class, specified in Mbps. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of - * the default SQ. + * the default SCHQ. */ uint32_t min_bw_tc7; /* * Indicates the max bandwidth for all enabled traffic classes in - * this SQ, specified in Mbps. + * this SCHQ, specified in Mbps. */ uint32_t max_bw; uint8_t unused_1[4]; } __rte_packed; -/* hwrm_ring_sq_cfg_output (size:128b/16B) */ -struct hwrm_ring_sq_cfg_output { +/* hwrm_ring_schq_cfg_output (size:128b/16B) */ +struct hwrm_ring_schq_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28935,13 +39922,13 @@ struct hwrm_ring_sq_cfg_output { uint8_t valid; } __rte_packed; -/********************* - * hwrm_ring_sq_free * - *********************/ +/*********************** + * hwrm_ring_schq_free * + ***********************/ -/* hwrm_ring_sq_free_input (size:192b/24B) */ -struct hwrm_ring_sq_free_input { +/* hwrm_ring_schq_free_input (size:192b/24B) */ +struct hwrm_ring_schq_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28970,13 +39957,13 @@ struct hwrm_ring_sq_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Identifies the SQ being freed. */ - uint16_t sq_id; + /* Identifies the SCHQ being freed. */ + uint16_t schq_id; uint8_t unused_0[6]; } __rte_packed; -/* hwrm_ring_sq_free_output (size:128b/16B) */ -struct hwrm_ring_sq_free_output { +/* hwrm_ring_schq_free_output (size:128b/16B) */ +struct hwrm_ring_schq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29067,12 +40054,15 @@ struct hwrm_cfa_l2_filter_alloc_input { UINT32_C(0x1) #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ UINT32_C(0x4) @@ -29366,13 +40356,19 @@ struct hwrm_cfa_l2_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -29488,8 +40484,9 @@ struct hwrm_cfa_l2_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -29551,8 +40548,9 @@ struct hwrm_cfa_l2_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -29609,8 +40607,8 @@ struct hwrm_cfa_l2_filter_cfg_input { #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ UINT32_C(0x2) @@ -29679,8 +40677,9 @@ struct hwrm_cfa_l2_filter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -29861,8 +40860,9 @@ struct hwrm_cfa_l2_set_rx_mask_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -29954,8 +40954,9 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30034,8 +41035,9 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30076,7 +41078,10 @@ struct hwrm_cfa_tunnel_filter_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) uint32_t enables; @@ -30219,13 +41224,19 @@ struct hwrm_cfa_tunnel_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -30344,8 +41355,9 @@ struct hwrm_cfa_tunnel_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30404,8 +41416,9 @@ struct hwrm_cfa_tunnel_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30479,13 +41492,19 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -30495,7 +41514,10 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* Tunnel alloc flags. */ uint8_t flags; - /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ + /* + * Setting of this flag indicates modify existing redirect tunnel + * to new destination function ID. + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ UINT32_C(0x1) uint8_t unused_0[4]; @@ -30516,8 +41538,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30591,13 +41614,19 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -30623,8 +41652,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30698,13 +41728,19 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -30732,8 +41768,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -30836,7 +41873,10 @@ struct hwrm_cfa_encap_data_vxlan { uint16_t dst_port; /* VXLAN Network Identifier. */ uint32_t vni; - /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ + /* + * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN + * header. + */ uint8_t hdr_rsvd0[3]; /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ uint8_t hdr_rsvd1; @@ -30881,13 +41921,16 @@ struct hwrm_cfa_encap_record_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) /* - * Setting of this flag indicates this encap record is external encap record. - * Resetting of this flag indicates this flag is internal encap record and - * this is the default setting. + * Setting of this flag indicates this encap record is external + * encap record. Resetting of this flag indicates this flag is + * internal encap record and this is the default setting. */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ UINT32_C(0x2) @@ -30920,13 +41963,19 @@ struct hwrm_cfa_encap_record_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ @@ -30953,8 +42002,9 @@ struct hwrm_cfa_encap_record_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -31014,8 +42064,9 @@ struct hwrm_cfa_encap_record_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -31056,42 +42107,55 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ UINT32_C(0x2) /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ UINT32_C(0x4) /* - * Setting of this flag indicates that the dst_id field contains function ID. - * If this is not set it indicates dest_id is VNIC or VPORT. + * Setting of this flag indicates that the dst_id field contains + * function ID. If this is not set it indicates dest_id is VNIC + * or VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ UINT32_C(0x8) /* - * Setting of this flag indicates match on arp reply when ethertype is 0x0806. - * If this is not set it indicates no specific arp opcode matching. + * Setting of this flag indicates match on arp reply when ethertype + * is 0x0806. If this is not set it indicates no specific arp opcode + * matching. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ UINT32_C(0x10) /* - * Setting of this flag indicates that the dst_id field contains RFS ring - * table index. If this is not set it indicates dst_id is VNIC or VPORT - * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at - * the same time. + * Setting of this flag indicates that the dst_id field contains RFS + * ring table index. If this is not set it indicates dst_id is VNIC + * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x40) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -31309,13 +42373,19 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -31452,8 +42522,9 @@ struct hwrm_cfa_ntuple_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -31530,8 +42601,9 @@ struct hwrm_cfa_ntuple_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -31593,18 +42665,27 @@ struct hwrm_cfa_ntuple_filter_cfg_input { uint32_t flags; /* * Setting this bit to 1 indicates that dest_id field contains FID. - * Setting this to 0 indicates that dest_id field contains VNIC or VPORT. + * Setting this to 0 indicates that dest_id field contains VNIC or + * VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ UINT32_C(0x1) /* * Setting of this flag indicates that the new_dst_id field contains - * RFS ring table index. If this is not set it indicates new_dst_id is - * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx - * can’t be set at the same time. + * RFS ring table index. If this is not set it indicates new_dst_id + * is VNIC or VPORT or function ID. Note dest_fid and + * dest_rfs_ring_idx can’t be set at the same time. */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x2) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x4) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -31651,8 +42732,9 @@ struct hwrm_cfa_ntuple_filter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -31706,28 +42788,34 @@ struct hwrm_cfa_em_flow_alloc_input { #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX /* - * Setting of this flag indicates enabling of a byte counter for a given - * flow. + * Setting of this flag indicates enabling of a byte counter for a + * given flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) /* - * Setting of this flag indicates enabling of a packet counter for a given - * flow. + * Setting of this flag indicates enabling of a packet counter for a + * given flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) - /* Setting of this flag indicates de-capsulation action for the given flow. */ + /* + * Setting of this flag indicates de-capsulation action for the + * given flow. + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) - /* Setting of this flag indicates encapsulation action for the given flow. */ + /* + * Setting of this flag indicates encapsulation action for the + * given flow. + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) uint32_t enables; @@ -31876,13 +42964,19 @@ struct hwrm_cfa_em_flow_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -32057,8 +43151,9 @@ struct hwrm_cfa_em_flow_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32117,8 +43212,9 @@ struct hwrm_cfa_em_flow_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32172,9 +43268,9 @@ struct hwrm_cfa_meter_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * Enumeration denoting the clock at which the Meter is running with. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the clock at which the Meter is running + * with. This enumeration is used for resources that are similar + * for both TX and RX paths of the chip. */ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 @@ -32230,8 +43326,9 @@ struct hwrm_cfa_meter_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32508,8 +43605,9 @@ struct hwrm_cfa_meter_profile_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32593,8 +43691,9 @@ struct hwrm_cfa_meter_profile_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32864,8 +43963,9 @@ struct hwrm_cfa_meter_profile_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32960,8 +44060,9 @@ struct hwrm_cfa_meter_instance_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33031,8 +44132,8 @@ struct hwrm_cfa_meter_instance_cfg_input { #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * This value identifies the ID of a meter instance that needs to be updated with - * a new meter profile specified in this command. + * This value identifies the ID of a meter instance that needs to be + * updated with a new meter profile specified in this command. */ uint16_t meter_instance_id; uint8_t unused_1[2]; @@ -33053,8 +44154,9 @@ struct hwrm_cfa_meter_instance_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33138,8 +44240,9 @@ struct hwrm_cfa_meter_instance_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33326,13 +44429,19 @@ struct hwrm_cfa_decap_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -33440,8 +44549,8 @@ struct hwrm_cfa_decap_filter_alloc_input { */ uint16_t dst_id; /* - * If set, this value shall represent the L2 context that matches the L2 - * information of the decap filter. + * If set, this value shall represent the L2 context that matches the + * L2 information of the decap filter. */ uint16_t l2_ctxt_ref_id; } __rte_packed; @@ -33463,8 +44572,9 @@ struct hwrm_cfa_decap_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33524,8 +44634,9 @@ struct hwrm_cfa_decap_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33600,29 +44711,35 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * when set to 1, indicates TX flow offload for function specified in src_fid and - * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both - * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload - * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV - * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID - * belong to the children VFs of the same PF to indicate VM to VM flow. + * when set to 1, indicates TX flow offload for function specified + * in src_fid and the dst_fid should be set to invalid value. To + * indicate a VM to VM flow, both of the path_tx and path_rx flags + * need to be set. For virtio vSwitch offload case, the src_fid and + * dst_fid is set to the same fid value. For the SRIOV vSwitch + * offload case, the src_fid and dst_fid must be set to the same VF + * FID belong to the children VFs of the same PF to indicate VM to + * VM flow. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ UINT32_C(0x40) /* - * when set to 1, indicates RX flow offload for function specified in dst_fid and - * the src_fid should be set to invalid value. + * when set to 1, indicates RX flow offload for function specified + * in dst_fid and the src_fid should be set to invalid value. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ UINT32_C(0x80) /* - * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is - * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. - * This flag is only valid when the flow direction is RX. + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan + * header is required and the VXLAN VNI value is stored in the first + * 24 bits of the dmac field. This flag is only valid when the flow + * direction is RX. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ UINT32_C(0x100) - /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */ + /* + * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci + * field. + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ UINT32_C(0x200) /* @@ -33634,8 +44751,8 @@ struct hwrm_cfa_flow_alloc_input { uint32_t tunnel_handle; uint16_t action_flags; /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ UINT32_C(0x1) @@ -33643,8 +44760,8 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ UINT32_C(0x4) @@ -33670,10 +44787,10 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ UINT32_C(0x200) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. The type of tunnel - * is specified in the tunnel_type field. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. + * The type of tunnel is specified in the tunnel_type field. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ UINT32_C(0x400) @@ -33681,18 +44798,19 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ UINT32_C(0x800) /* - * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be - * placed to the default flow table resource. + * If set to 1 an attempt will be made to try to offload this flow + * to the most optimal flow table resource. If set to 0, the flow + * will be placed to the default flow table resource. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ UINT32_C(0x1000) /* - * If set to 1 there will be no attempt to allocate an on-chip try to - * offload this flow. If set to 0, which will keep compatibility with the - * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior - * with EM flows which always had an associated flow counter. + * If set to 1 there will be no attempt to allocate an on-chip try + * to offload this flow. If set to 0, which will keep compatibility + * with the older drivers, will cause the FW to attempt to allocate + * an on-chip flow counter for the newly created flow. This will + * keep the existing behavior with EM flows which always had an + * associated flow counter. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ UINT32_C(0x2000) @@ -33796,13 +44914,19 @@ struct hwrm_cfa_flow_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -33873,8 +44997,9 @@ struct hwrm_cfa_flow_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33896,7 +45021,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) /* No more wild-card TCAM */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collsion in exact match tables */ + /* Hash collision in exact match tables */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) /* Key is already installed */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) @@ -33970,8 +45095,9 @@ struct hwrm_cfa_flow_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33995,9 +45121,9 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ UINT32_C(0x10) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ UINT32_C(0x20) @@ -34044,11 +45170,17 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 @@ -34091,13 +45223,19 @@ struct hwrm_cfa_flow_tunnel_hdr_data { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -34304,8 +45442,9 @@ struct hwrm_cfa_flow_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34348,32 +45487,39 @@ struct hwrm_cfa_flow_flush_input { /* flags is 32 b */ uint32_t flags; /* - * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr - * fields are valid. The flow flush operation should only flush the flows from the - * flow table specified. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * Set to 1 to indicate the page size, page layers, and + * flow_handle_table_dma_addr fields are valid. The flow flush + * operation should only flush the flows from the flow table + * specified. This flag is set to 0 by older driver. For older + * firmware, setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ UINT32_C(0x1) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables etc. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * Set to 1 to indicate flow flush operation to cleanup all the + * flows, meters, CFA context memory tables etc. This flag is set to + * 0 by older driver. For older firmware, setting this flag has no + * effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ UINT32_C(0x2) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller. - * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect. + * Set to 1 to indicate flow flush operation to cleanup all the + * flows by the caller. This flag is set to 0 by older driver. For + * older firmware, setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ UINT32_C(0x4) - /* Set to 1 to indicate the flow counter IDs are included in the flow table. */ + /* + * Set to 1 to indicate the flow counter IDs are included in the + * flow table. + */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ UINT32_C(0x8000000) /* - * This specifies the size of flow handle entries provided by the driver - * in the flow table specified below. Only two flow handle size enums are defined. + * This specifies the size of flow handle entries provided by the + * driver in the flow table specified below. Only two flow handle + * size enums are defined. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ UINT32_C(0xc0000000) @@ -34413,7 +45559,10 @@ struct hwrm_cfa_flow_flush_input { #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 @@ -34438,8 +45587,9 @@ struct hwrm_cfa_flow_flush_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34579,8 +45729,9 @@ struct hwrm_cfa_flow_stats_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34647,8 +45798,9 @@ struct hwrm_cfa_flow_aging_timer_reset_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34690,28 +45842,52 @@ struct hwrm_cfa_flow_aging_cfg_input { uint64_t resp_addr; /* The bit field to enable per flow aging configuration. */ uint16_t enables; - /* This bit must be '1' for the tcp flow timer field to be configured */ + /* + * This bit must be '1' for the tcp flow timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ UINT32_C(0x1) - /* This bit must be '1' for the tcp finish timer field to be configured */ + /* + * This bit must be '1' for the tcp finish timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ UINT32_C(0x2) - /* This bit must be '1' for the udp flow timer field to be configured */ + /* + * This bit must be '1' for the udp flow timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ UINT32_C(0x4) - /* This bit must be '1' for the eem dma interval field to be configured */ + /* + * This bit must be '1' for the eem dma interval field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ UINT32_C(0x8) - /* This bit must be '1' for the eem notice interval field to be configured */ + /* + * This bit must be '1' for the eem notice interval field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ UINT32_C(0x10) - /* This bit must be '1' for the eem context memory maximum entries field to be configured */ + /* + * This bit must be '1' for the eem context memory maximum entries + * field to be configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ UINT32_C(0x20) - /* This bit must be '1' for the eem context memory ID field to be configured */ + /* + * This bit must be '1' for the eem context memory ID field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ UINT32_C(0x40) - /* This bit must be '1' for the eem context memory type field to be configured */ + /* + * This bit must be '1' for the eem context memory type field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ UINT32_C(0x80) uint8_t flags; @@ -34723,7 +45899,10 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the enable, disable eem flow aging configuration. */ + /* + * Enumeration denoting the enable, disable eem flow aging + * configuration. + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) /* tx path */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ @@ -34734,22 +45913,40 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE uint8_t unused_0; - /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */ + /* + * The flow aging timer for all TCP flows, the unit is 100 + * milliseconds. + */ uint32_t tcp_flow_timer; - /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */ + /* + * The TCP finished timer for all TCP flows, the unit is 100 + * milliseconds. + */ uint32_t tcp_fin_timer; - /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */ + /* + * The flow aging timer for all UDP flows, the unit is 100 + * milliseconds. + */ uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ uint16_t eem_notice_interval; /* The maximum entries number in the eem context memory. */ uint32_t eem_ctx_max_entries; /* The context memory ID for eem flow aging. */ uint16_t eem_ctx_id; uint16_t eem_ctx_mem_type; - /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */ + /* + * The content of context memory is eem ejection data, the size of + * each entry is 4 bytes. + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ UINT32_C(0x0) #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ @@ -34772,8 +45969,9 @@ struct hwrm_cfa_flow_aging_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34813,7 +46011,10 @@ struct hwrm_cfa_flow_aging_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ + /* + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. + */ uint8_t flags; /* Enumeration denoting the RX, TX type of the resource. */ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) @@ -34836,15 +46037,30 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The current flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t tcp_flow_timer; - /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The current TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t tcp_fin_timer; - /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */ + /* + * The current flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ uint16_t eem_notice_interval; /* The maximum entries number in the eem context memory. */ uint32_t eem_ctx_max_entries; @@ -34857,8 +46073,9 @@ struct hwrm_cfa_flow_aging_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34873,46 +46090,513 @@ struct hwrm_cfa_flow_aging_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. + */ + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ +struct hwrm_cfa_flow_aging_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The maximum flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t max_tcp_flow_timer; + /* + * The maximum TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t max_tcp_fin_timer; + /* + * The maximum flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ + uint32_t max_udp_flow_timer; + /* The maximum aging flows that HW can support. */ + uint32_t max_aging_flows; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_cfa_tcp_flag_process_qcfg * + **********************************/ + + +/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The port 0 RX mirror action record ID. */ + uint16_t rx_ar_id_port0; + /* The port 1 RX mirror action record ID. */ + uint16_t rx_ar_id_port1; + /* + * The port 0 RX action record ID for TX TCP flag packets from + * loopback path. + */ + uint16_t tx_ar_id_port0; + /* + * The port 1 RX action record ID for TX TCP flag packets from + * loopback path. + */ + uint16_t tx_ar_id_port1; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_vf_pair_alloc * + **************************/ + + +/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + uint8_t unused_0[4]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; +} __rte_packed; + +/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_vf_pair_free * + *************************/ + + +/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ +struct hwrm_cfa_vf_pair_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF Pair name (32 byte string). */ + char pair_name[32]; +} __rte_packed; + +/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_vf_pair_info * + *************************/ + + +/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* vf pair table index. */ + uint16_t vf_pair_index; + uint8_t unused_0[2]; + /* VF Pair name (32 byte string). */ + char vf_pair_name[32]; +} __rte_packed; + +/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ +struct hwrm_cfa_vf_pair_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* vf pair table index. */ + uint16_t next_vf_pair_index; + /* vf pair member a's vf_fid. */ + uint16_t vf_a_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* vf pair member b's vf_fid. */ + uint16_t vf_b_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* vf pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + uint8_t unused_0[5]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_cfa_pair_alloc * + ***********************/ + + +/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ +struct hwrm_cfa_pair_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). + */ + uint16_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \ + UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \ + UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \ + UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \ + UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \ + UINT32_C(0x4) + /* Modify existing rep2fn pair and move pair to new PF. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \ + UINT32_C(0x5) + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \ + UINT32_C(0x6) + /* + * Truflow pair between REP on local host with PF or VF on specified + * host. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \ + UINT32_C(0x7) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical Host (0xff-local host). */ + uint8_t host_b_id; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + /* Loopback port (0xff-internal loopback), valid for mode-3. */ + uint8_t port_id; + /* Priority used for encap of loopback packets valid for mode-3. */ + uint8_t pri; + /* New PF for rep2fn modify, valid for mode 5. */ + uint16_t new_pf_fid; + uint32_t enables; + /* + * This bit must be '1' for the q_ab field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) + /* + * This bit must be '1' for the q_ba field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) + /* + * This bit must be '1' for the fc_ab field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) + /* + * This bit must be '1' for the fc_ba field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) + /* VF Pair name (32 byte string). */ + char pair_name[32]; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The q_ab value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the A to B direction of + * the interface pair. The default value is 0. */ - uint16_t seq_id; + uint8_t q_ab; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The q_ba value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the B to A direction of + * the interface pair. The default value is 1. */ - uint16_t target_id; + uint8_t q_ba; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the A to B direction. The default value is 0, meaning that + * packets will be dropped when the B-side RX rings are full. */ - uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; + uint8_t fc_ab; + /* + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the B to A direction. The default value is 1, meaning that + * the RX CoS queue will be flow controlled when the A-side RX rings + * are full. + */ + uint8_t fc_ba; + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ -struct hwrm_cfa_flow_aging_qcaps_output { +/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ +struct hwrm_cfa_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34921,32 +46605,33 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_flow_timer; - /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_fin_timer; - /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */ - uint32_t max_udp_flow_timer; - /* The maximum aging flows that HW can support. */ - uint32_t max_aging_flows; + /* Only valid for modes 1 and 2. */ + uint16_t rx_cfa_code_a; + /* Only valid for modes 1 and 2. */ + uint16_t tx_cfa_action_a; + /* Only valid for mode 2. */ + uint16_t rx_cfa_code_b; + /* Only valid for mode 2. */ + uint16_t tx_cfa_action_b; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************************** - * hwrm_cfa_tcp_flag_process_qcfg * - **********************************/ +/********************** + * hwrm_cfa_pair_free * + **********************/ -/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_input { +/* hwrm_cfa_pair_free_input (size:448b/56B) */ +struct hwrm_cfa_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34975,10 +46660,46 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + uint8_t unused_0[3]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). + */ + uint16_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + /* Modify existing rep2fn pair and move pair to new PF. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) + /* + * Truflow pair between REP on local host with PF or VF on + * specified host. + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW } __rte_packed; -/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_output { +/* hwrm_cfa_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34987,21 +46708,14 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The port 0 RX mirror action record ID. */ - uint16_t rx_ar_id_port0; - /* The port 1 RX mirror action record ID. */ - uint16_t rx_ar_id_port1; - /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port0; - /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port1; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35121,8 +46835,151 @@ struct hwrm_cfa_pair_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ + + +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vfr_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; +} __rte_packed; + +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vfr_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_cfa_vfr_free * + *********************/ + + +/* hwrm_cfa_vfr_free_input (size:448b/56B) */ +struct hwrm_cfa_vfr_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +struct hwrm_cfa_vfr_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35209,7 +47066,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ UINT32_C(0x200) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ UINT32_C(0x400) /* Any tunneled traffic */ @@ -35218,7 +47078,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ UINT32_C(0x1000) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ UINT32_C(0x2000) uint8_t unused_0[3]; @@ -35226,8 +47089,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35274,7 +47138,10 @@ struct hwrm_cfa_ctx_mem_rgtr_input { #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 @@ -35314,8 +47181,8 @@ struct hwrm_cfa_ctx_mem_rgtr_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[5]; @@ -35323,8 +47190,9 @@ struct hwrm_cfa_ctx_mem_rgtr_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35365,8 +47233,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[6]; @@ -35387,8 +47255,9 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35429,15 +47298,366 @@ struct hwrm_cfa_ctx_mem_qctx_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. + */ + uint16_t ctx_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ +struct hwrm_cfa_ctx_mem_qctx_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G + uint8_t unused_0[4]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_ctx_mem_qcaps * + **************************/ + + +/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Indicates the maximum number of context memory which can be + * registered. + */ + uint16_t max_entries; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_counter_qcaps * + **************************/ + + +/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_counter_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ +struct hwrm_cfa_counter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* Enumeration denoting the supported CFA counter format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \ + UINT32_C(0x1) + /* CFA counter types are not supported. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \ + UINT32_C(0x0) + /* 64-bit packet counters followed by 64-bit byte counters format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \ + HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT + uint32_t unused_0; + /* + * Minimum guaranteed number of flow counters supported for this + * function, in RX direction. + */ + uint32_t min_rx_fc; + /* + * Maximum non-guaranteed number of flow counters supported for this + * function, in RX direction. + */ + uint32_t max_rx_fc; + /* + * Minimum guaranteed number of flow counters supported for this + * function, in TX direction. + */ + uint32_t min_tx_fc; + /* + * Maximum non-guaranteed number of flow counters supported for this + * function, in TX direction. + */ + uint32_t max_tx_fc; + /* + * Minimum guaranteed number of extension flow counters supported for + * this function, in RX direction. + */ + uint32_t min_rx_efc; + /* + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in RX direction. + */ + uint32_t max_rx_efc; + /* + * Minimum guaranteed number of extension flow counters supported for + * this function, in TX direction. + */ + uint32_t min_tx_efc; + /* + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in TX direction. + */ + uint32_t max_tx_efc; + /* + * Minimum guaranteed number of meter drop counters supported for + * this function, in RX direction. + */ + uint32_t min_rx_mdc; + /* + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in RX direction. + */ + uint32_t max_rx_mdc; + /* + * Minimum guaranteed number of meter drop counters supported for this + * function, in TX direction. + */ + uint32_t min_tx_mdc; + /* + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in TX direction. + */ + uint32_t max_tx_mdc; + /* + * Maximum guaranteed number of flow counters which can be used during + * flow alloc. + */ + uint32_t max_flow_alloc_fc; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_cfa_counter_cfg * + ************************/ + + +/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ +struct hwrm_cfa_counter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ + uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \ + UINT32_C(0x1) + /* Disable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \ + UINT32_C(0x0) + /* Enable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x2) + /* Tx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \ + (UINT32_C(0x0) << 1) + /* Rx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 + /* Push mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \ + (UINT32_C(0x0) << 2) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \ + (UINT32_C(0x1) << 2) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + /* Flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) + /* Extended flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) + /* Meter drop counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC + /* Ctx memory handle to be used for the counter. */ uint16_t ctx_id; - uint8_t unused_0[6]; + /* Counter update cadence hint (only in Push mode). */ + uint16_t update_tmr_ms; + /* Total number of entries. */ + uint32_t num_entries; + uint32_t unused_0; } __rte_packed; -/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_qctx_output { +/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_counter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35446,58 +47666,25 @@ struct hwrm_cfa_ctx_mem_qctx_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G - uint8_t unused_0[4]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************** - * hwrm_cfa_ctx_mem_qcaps * - **************************/ +/*************************** + * hwrm_cfa_counter_qstats * + ***************************/ -/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_input { +/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ +struct hwrm_cfa_counter_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35526,10 +47713,27 @@ struct hwrm_cfa_ctx_mem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX + uint16_t counter_type; + uint16_t input_flow_ctx_id; + uint16_t num_entries; + uint16_t delta_time_ms; + uint16_t meter_instance_id; + uint16_t mdc_ctx_id; + uint8_t unused_0[2]; + uint64_t expected_count; } __rte_packed; -/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_output { +/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ +struct hwrm_cfa_counter_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35538,15 +47742,14 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Indicates the maximum number of context memory which can be registered. */ - uint16_t max_entries; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35633,14 +47836,14 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ UINT32_C(0x2) /* - * When set to 1, indicates the the FW supports the Centralized + * When set to 1, indicates the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* - * When set to 1, indicates the the FW supports the Detached + * When set to 1, indicates the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -35676,17 +47879,21 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ UINT32_C(0x8) /* - * If set to 1, then FID table used for implicit flow flush is supported. - * If set to 0, then FID table used for implicit flow flush is not supported. + * If set to 1, then FID table used for implicit flow flush is + * supported. + * If set to 0, then FID table used for implicit flow flush is + * not supported. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ UINT32_C(0x10) /* - * The maximum number of entries supported by EEM. When configuring the host memory - * the number of numbers of entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. - * Any value that are not these values, the FW will round down to the closest support - * number of entries. + * The maximum number of entries supported by EEM. When configuring + * the host memory, the number of numbers of entries that can + * supported are: + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M + * entries. + * Any value that are not these values, the FW will round down to the + * closest support number of entries. */ uint32_t max_entries_supported; /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ @@ -35702,8 +47909,9 @@ struct hwrm_cfa_eem_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35771,9 +47979,10 @@ struct hwrm_cfa_eem_cfg_input { uint16_t group_id; uint16_t unused_0; /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, - * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * Configured EEM with the given number of entries. All the EEM tables + * KEY0, KEY1, RECORD, EFC all have the same number of entries and all + * tables will be configured using this value. Current minimum value + * is 32k. Current maximum value is 128M. */ uint32_t num_entries; uint32_t unused_1; @@ -35806,8 +48015,9 @@ struct hwrm_cfa_eem_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35892,8 +48102,9 @@ struct hwrm_cfa_eem_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35989,8 +48200,9 @@ struct hwrm_cfa_eem_op_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36030,144 +48242,655 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; -} __rte_packed; - -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + uint32_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + UINT32_C(0x1) + /* + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + UINT32_C(0x2) + /* + * Value of 1 to indicate firmware support flow batch delete + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow + * batch delete operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + UINT32_C(0x4) + /* + * Value of 1 to indicate that the firmware support flow reset all + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all + * operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + UINT32_C(0x8) + /* + * Value of 1 to indicate that firmware supports use of FID as + * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as + * dest_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + UINT32_C(0x10) + /* + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x20) + /* + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x40) + /* + * Value of 1 to indicate that firmware supports the dynamic + * allocation of an on-chip flow counter which can be used for EEM + * flows. Value of 0 indicates firmware does not support the dynamic + * allocation of an on-chip flow counter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + UINT32_C(0x80) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + UINT32_C(0x100) + /* + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + UINT32_C(0x200) + /* + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ + UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that core firmware is + * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX + * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \ + UINT32_C(0x8000) + /* + * If set to 1, firmware is capable of supporting L2/ROCE as + * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. + * By default, this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \ + UINT32_C(0x10000) + /* + * If set to 1, firmware is capable of HW LAG. This bit is only + * advertised if the calling function is a PAXC function. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \ + UINT32_C(0x20000) + /* + * If set to 1, firmware is capable installing ntuple rules without + * additional classification on the L2 Context. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ + UINT32_C(0x40000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_cfa_tflib * + ******************/ + + +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} __rte_packed; + +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_cfa_tls_filter_alloc * + *****************************/ + + +/* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */ +struct hwrm_cfa_tls_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t unused_0; + uint32_t enables; /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. + * This bit must be '1' for the l2_filter_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ UINT32_C(0x1) /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x2) /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. + * This bit must be '1' for the ipaddr_type field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ UINT32_C(0x4) /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ UINT32_C(0x8) /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ UINT32_C(0x10) /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. + * This bit must be '1' for the ip_protocol field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ UINT32_C(0x20) /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. + * This bit must be '1' for the src_port field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ UINT32_C(0x40) /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. + * This bit must be '1' for the dst_port field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ UINT32_C(0x80) /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + * This bit must be '1' for the kid field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID \ UINT32_C(0x100) /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. + * This bit must be '1' for the dst_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ UINT32_C(0x200) /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ UINT32_C(0x400) /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) + uint64_t l2_filter_id; + uint8_t unused_1[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * If set to 1, firmware is capable of supporting ARP ethertype as - * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the - * RX direction. By default, this flag should be 0 for older version - * of firmware. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ - UINT32_C(0x1000) + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC - * command. Value of 0 indicates firmware does not support - * rfs_ring_tbl_idx in dst_id field. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ - UINT32_C(0x2000) + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP /* - * If set to 1, firmware is capable of supporting IPv4/IPv6 as - * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX - * direction. By default, this flag should be 0 for older version - * of firmware. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ - UINT32_C(0x4000) + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + uint8_t unused_2[2]; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * The Key Context Identifier (KID) for use with KTLS. + * KID is limited to 20-bits. + */ + uint32_t kid; +} __rte_packed; + +/* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_tls_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/****************** - * hwrm_cfa_tflib * - ******************/ +/**************************** + * hwrm_cfa_tls_filter_free * + ****************************/ -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { +/* hwrm_cfa_tls_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_tls_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36196,18 +48919,12 @@ struct hwrm_cfa_tflib_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; } __rte_packed; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_cfa_tls_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_tls_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36216,22 +48933,14 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; - /* unused. */ - uint8_t unused1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36349,7 +49058,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -36366,7 +49075,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -36437,8 +49153,29 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; - /* unused. */ - uint32_t unused0; + /* This field is used to return the status of fw session to host. */ + uint32_t flags; + /* + * Indicates if the shared session has been created. Shared session + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ + UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates the shared session + * has been created by another session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \ + UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates the shared session + * is created by this session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \ + HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR /* unused. */ uint8_t unused1[3]; /* @@ -36903,7 +49640,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -36960,8 +49697,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* @@ -37018,7 +49760,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -37117,7 +49859,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -37201,7 +49943,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -37242,6 +49984,105 @@ struct hwrm_tf_session_resc_flush_output { uint8_t valid; } __rte_packed; +/***************************** + * hwrm_tf_session_resc_info * + *****************************/ + + +/* hwrm_tf_session_resc_info_input (size:320b/40B) */ +struct hwrm_tf_session_resc_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /* TruFlow RM capability of a resource. */ /* tf_rm_resc_req_entry (size:64b/8B) */ struct tf_rm_resc_req_entry { @@ -37304,13 +50145,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -37396,7 +50246,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -37440,6 +50290,222 @@ struct hwrm_tf_tbl_type_set_output { uint8_t valid; } __rte_packed; +/************************** + * hwrm_tf_ctxt_mem_alloc * + **************************/ + + +/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Size in KB of memory to be allocated. */ + uint32_t mem_size; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; +} __rte_packed; + +/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G + /* unused. */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_tf_ctxt_mem_free * + *************************/ + + +/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */ +struct hwrm_tf_ctxt_mem_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G + /* unused. */ + uint8_t unused0[2]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; + /* unused. */ + uint8_t unused1[4]; +} __rte_packed; + +/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /************************* * hwrm_tf_ctxt_mem_rgtr * *************************/ @@ -37498,20 +50564,26 @@ struct hwrm_tf_ctxt_mem_rgtr_input { #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) /* 64KB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5) /* 256KB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7) /* 1MB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) /* 2MB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) /* 4MB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb) /* 1GB page size. */ #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; } __rte_packed; @@ -37585,7 +50657,9 @@ struct hwrm_tf_ctxt_mem_unrgtr_input { */ uint16_t ctx_id; /* unused. */ - uint8_t unused0[6]; + uint8_t unused0[2]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ @@ -37654,7 +50728,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -37662,11 +50736,11 @@ struct hwrm_tf_ext_em_qcaps_input { /* When set to 1, all offloaded flows will be sent to EXT EM. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x2) - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */ +/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */ struct hwrm_tf_ext_em_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -37678,14 +50752,14 @@ struct hwrm_tf_ext_em_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * When set to 1, indicates the the FW supports the Centralized + * When set to 1, indicates the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x1) /* - * When set to 1, indicates the the FW supports the Detached + * When set to 1, indicates the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -37693,6 +50767,12 @@ struct hwrm_tf_ext_em_qcaps_output { */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x2) + /* When set to 1, indicates FW support for host based EEM memory. */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \ + UINT32_C(0x4) + /* When set to 1, indicates FW support for on-chip based EEM memory. */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \ + UINT32_C(0x8) /* unused. */ uint32_t unused0; /* Support flags. */ @@ -37735,6 +50815,12 @@ struct hwrm_tf_ext_em_qcaps_output { */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ UINT32_C(0x10) + /* + * If set to 1, then table scopes are supported. + * If set to 0, then table scopes are not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \ + UINT32_C(0x20) /* * The maximum number of entries supported by EXT EM. When * configuring the host memory the number of numbers of @@ -37759,6 +50845,13 @@ struct hwrm_tf_ext_em_qcaps_output { uint16_t efc_entry_size; /* The FID size in bytes of each entry in the EXT EM FID tables. */ uint16_t fid_entry_size; + /* Maximum number of ctxt mem allocations allowed. */ + uint32_t max_ctxt_mem_allocs; + /* + * Maximum number of static buckets that can be assigned to lookup + * table scopes. + */ + uint32_t max_static_buckets; /* unused. */ uint8_t unused1[7]; /* @@ -37777,7 +50870,7 @@ struct hwrm_tf_ext_em_qcaps_output { *********************/ -/* hwrm_tf_ext_em_op_input (size:192b/24B) */ +/* hwrm_tf_ext_em_op_input (size:256b/32B) */ struct hwrm_tf_ext_em_op_input { /* The HWRM command request type. */ uint16_t req_type; @@ -37813,7 +50906,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -37848,6 +50941,10 @@ struct hwrm_tf_ext_em_op_input { HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP /* unused. */ uint16_t unused1; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused2; } __rte_packed; /* hwrm_tf_ext_em_op_output (size:128b/16B) */ @@ -37878,7 +50975,7 @@ struct hwrm_tf_ext_em_op_output { **********************/ -/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */ +/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */ struct hwrm_tf_ext_em_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -37907,48 +51004,125 @@ struct hwrm_tf_ext_em_cfg_input { * physical address (HPA) or a guest physical address (GPA) and must * point to a physically contiguous block of memory. */ - uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ - UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ - UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ - UINT32_C(0x1) - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x2) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ - UINT32_C(0x4) + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x4) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* + * Dynamically reconfigure EEM pending cache every 1/10th of second. + * If set to 0 it will disable the EEM HW flush of the pending cache. + */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused0; + /* + * Configured EXT EM with the given number of entries. All + * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the + * same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current + * maximum value is 128M. + */ + uint32_t num_entries; + uint32_t enables; + /* + * This bit must be '1' for the group_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the flush_interval field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \ + UINT32_C(0x2) + /* + * This bit must be '1' for the num_entries field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \ + UINT32_C(0x4) + /* + * This bit must be '1' for the key0_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the key1_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the record_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the efc_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the fid_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \ + UINT32_C(0x80) + /* + * This bit must be '1' for the action_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \ + UINT32_C(0x100) + /* + * This bit must be '1' for the action_tbl_scope field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \ + UINT32_C(0x200) /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. + * This bit must be '1' for the lkup_ctx_id field to be + * configured. */ - uint16_t group_id; + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \ + UINT32_C(0x400) /* - * Dynamically reconfigure EEM pending cache every 1/10th of second. - * If set to 0 it will disable the EEM HW flush of the pending cache. + * This bit must be '1' for the lkup_tbl_scope field to be + * configured. */ - uint8_t flush_interval; - /* unused. */ - uint8_t unused0; + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \ + UINT32_C(0x800) /* - * Configured EXT EM with the given number of entries. All - * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the - * same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current - * maximum value is 128M. + * This bit must be '1' for the lkup_static_buckets field to be + * configured. */ - uint32_t num_entries; - /* unused. */ - uint32_t unused1; + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \ + UINT32_C(0x1000) /* Configured EXT EM with the given context if for KEY0 table. */ uint16_t key0_ctx_id; /* Configured EXT EM with the given context if for KEY1 table. */ @@ -37959,10 +51133,25 @@ struct hwrm_tf_ext_em_cfg_input { uint16_t efc_ctx_id; /* Configured EXT EM with the given context if for EFC table. */ uint16_t fid_ctx_id; + /* Context id of action table scope. */ + uint16_t action_ctx_id; + /* Table scope id used for action record entries. */ + uint16_t action_tbl_scope; + /* Context id of lookup table scope. */ + uint16_t lkup_ctx_id; + /* Table scope id used for EM lookup entries. */ + uint16_t lkup_tbl_scope; /* unused. */ - uint16_t unused2; + uint16_t unused1; + /* + * Number of 32B static buckets to be allocated at the beginning + * of table scope. + */ + uint32_t lkup_static_buckets; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* unused. */ - uint32_t unused3; + uint32_t unused2; } __rte_packed; /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ @@ -38029,15 +51218,15 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ +/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ struct hwrm_tf_ext_em_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -38055,7 +51244,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -38076,7 +51265,71 @@ struct hwrm_tf_ext_em_qcfg_output { /* Configured EXT EM with the given context if for EFC table. */ uint16_t fid_ctx_id; /* unused. */ - uint8_t unused0[5]; + uint16_t unused0; + uint32_t supported; + /* This bit must be '1' for the group_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \ + UINT32_C(0x1) + /* This bit must be '1' for the flush_interval field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \ + UINT32_C(0x2) + /* This bit must be '1' for the num_entries field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \ + UINT32_C(0x4) + /* This bit must be '1' for the key0_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \ + UINT32_C(0x8) + /* This bit must be '1' for the key1_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \ + UINT32_C(0x10) + /* This bit must be '1' for the record_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \ + UINT32_C(0x20) + /* This bit must be '1' for the efc_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the fid_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \ + UINT32_C(0x80) + /* This bit must be '1' for the action_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \ + UINT32_C(0x100) + /* This bit must be '1' for the action_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \ + UINT32_C(0x200) + /* This bit must be '1' for the lkup_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \ + UINT32_C(0x400) + /* This bit must be '1' for the lkup_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \ + UINT32_C(0x800) + /* This bit must be '1' for the lkup_static_buckets field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \ + UINT32_C(0x1000) + /* + * Group id is used by firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* EEM pending cache flush interval in 1/10th of second. */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused1; + /* Context id of action table scope. */ + uint16_t action_ctx_id; + /* Table scope id used for action record entries. */ + uint16_t action_tbl_scope; + /* Context id of lookup table scope. */ + uint16_t lkup_ctx_id; + /* Table scope id used for EM lookup entries. */ + uint16_t lkup_tbl_scope; + /* + * Number of 32B static buckets to be allocated at the beginning + * of table scope. + */ + uint32_t lkup_static_buckets; + /* unused. */ + uint8_t unused2[7]; /* * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be @@ -38131,7 +51384,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -38169,6 +51422,87 @@ struct hwrm_tf_em_insert_output { uint32_t unused0; } __rte_packed; +/************************** + * hwrm_tf_em_hash_insert * + **************************/ + + +/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ +struct hwrm_tf_em_hash_insert_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX + /* Number of bits in the EM record. */ + uint16_t em_record_size_bits; + /* CRC32 hash of key. */ + uint32_t key0_hash; + /* Lookup3 hash of key. */ + uint32_t key1_hash; + /* Index of EM record. */ + uint32_t em_record_idx; + /* Unused. */ + uint32_t unused0; + /* EM record. */ + uint64_t em_record[11]; +} __rte_packed; + +/* hwrm_tf_em_hash_insert_output (size:128b/16B) */ +struct hwrm_tf_em_hash_insert_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; +} __rte_packed; + /********************* * hwrm_tf_em_delete * *********************/ @@ -38212,13 +51546,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -38244,6 +51578,79 @@ struct hwrm_tf_em_delete_output { uint16_t unused0[3]; } __rte_packed; +/******************* + * hwrm_tf_em_move * + *******************/ + + +/* hwrm_tf_em_move_input (size:320b/40B) */ +struct hwrm_tf_em_move_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX + /* Number of EM entry blocks */ + uint16_t num_blocks; + /* New index for entry */ + uint32_t new_index; + /* Unused */ + uint32_t unused0; + /* EM internal flow handle. */ + uint64_t flow_handle; +} __rte_packed; + +/* hwrm_tf_em_move_output (size:128b/16B) */ +struct hwrm_tf_em_move_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Index of old entry. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + /******************** * hwrm_tf_tcam_set * ********************/ @@ -38287,7 +51694,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -38317,8 +51724,8 @@ struct hwrm_tf_tcam_set_input { /* unused. */ uint8_t unused0[6]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[88]; } __rte_packed; @@ -38389,7 +51796,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -38425,8 +51832,8 @@ struct hwrm_tf_tcam_get_output { /* unused. */ uint8_t unused0[4]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[272]; /* unused. */ @@ -38485,7 +51892,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -38563,30 +51970,365 @@ struct hwrm_tf_tcam_free_input { /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; +} __rte_packed; + +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tf_global_cfg_set * + **************************/ + + +/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ +struct hwrm_tf_global_cfg_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[8]; + /* Mask of data to set, 0 indicates no mask */ + uint8_t mask[8]; +} __rte_packed; + +/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ +struct hwrm_tf_global_cfg_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tf_global_cfg_get * + **************************/ + + +/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ +struct hwrm_tf_global_cfg_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +struct hwrm_tf_global_cfg_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Size of the data read in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[16]; +} __rte_packed; + +/********************** + * hwrm_tf_if_tbl_get * + **********************/ + + +/* hwrm_tf_if_tbl_get_input (size:256b/32B) */ +struct hwrm_tf_if_tbl_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Size of the data to set. */ + uint16_t size; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} __rte_packed; + +/* hwrm_tf_if_tbl_get_output (size:1216b/152B) */ +struct hwrm_tf_if_tbl_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_tf_if_tbl_type_set * + ***************************/ + + +/* hwrm_tf_if_tbl_set_input (size:1024b/128B) */ +struct hwrm_tf_if_tbl_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; /* - * TCAM type of the resource, defined globally in the + * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Number of TCAM index to be deleted for the device. */ - uint16_t count; - /* unused. */ - uint16_t unused0; - /* TCAM index list to be deleted for the device. */ - uint16_t idx_list[48]; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; } __rte_packed; -/* hwrm_tf_tcam_free_output (size:128b/16B) */ -struct hwrm_tf_tcam_free_output { +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +struct hwrm_tf_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38598,23 +52340,23 @@ struct hwrm_tf_tcam_free_output { /* unused. */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; -/************************** - * hwrm_tf_global_cfg_set * - **************************/ +/***************************** + * hwrm_tf_tbl_type_bulk_get * + *****************************/ -/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ -struct hwrm_tf_global_cfg_set_input { +/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ +struct hwrm_tf_tbl_type_bulk_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38646,109 +52388,43 @@ struct hwrm_tf_global_cfg_set_input { /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX - /* Global Cfg type */ - uint32_t type; - /* Offset of the type */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; - /* unused. */ - uint8_t unused0[6]; - /* Data to set */ - uint8_t data[16]; -} __rte_packed; - -/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ -struct hwrm_tf_global_cfg_set_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/************************** - * hwrm_tf_global_cfg_get * - **************************/ - - -/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ -struct hwrm_tf_global_cfg_get_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When set use the special access register access to clear + * the table entries on read. */ - uint16_t target_id; + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) + /* unused. */ + uint8_t unused0[2]; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX - /* Global Cfg type */ uint32_t type; - /* Offset of the type */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; - /* unused. */ - uint8_t unused0[6]; + /* Starting index of the type to retrieve. */ + uint32_t start_index; + /* Number of entries to retrieve. */ + uint32_t num_entries; + /* Number of entries to retrieve. */ + uint32_t unused1; + /* Host memory where data will be stored. */ + uint64_t host_addr; } __rte_packed; -/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ -struct hwrm_tf_global_cfg_get_output { +/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_bulk_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38757,12 +52433,21 @@ struct hwrm_tf_global_cfg_get_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Size of the data read in bytes */ + /* Response code. */ + uint32_t resp_code; + /* Response size. */ uint16_t size; - /* unused. */ - uint8_t unused0[6]; - /* Data to set */ - uint8_t data[16]; + /* unused */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; } __rte_packed; /****************************** @@ -39099,7 +52784,7 @@ struct ctx_hw_stats { * support TPA v2, additional TPA related stats exist and can be retrieved * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. */ -/* ctx_hw_stats_ext (size:1344b/168B) */ +/* ctx_hw_stats_ext (size:1408b/176B) */ struct ctx_hw_stats_ext { /* Number of received unicast packets */ uint64_t rx_ucast_pkts; @@ -39143,6 +52828,8 @@ struct ctx_hw_stats_ext { uint64_t rx_tpa_bytes; /* Number of TPA errors */ uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; } __rte_packed; /* Periodic Engine statistics context DMA to host. */ @@ -39418,10 +53105,10 @@ struct hwrm_stat_ctx_query_output { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; - /* Number of transmitted packets with error */ - uint64_t tx_err_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; + /* Number of packets discarded in transmit path */ + uint64_t tx_discard_pkts; + /* Number of packets in transmit path with error */ + uint64_t tx_error_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -39434,10 +53121,10 @@ struct hwrm_stat_ctx_query_output { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of received packets with error */ - uint64_t rx_err_pkts; - /* Number of dropped packets on receive path */ - uint64_t rx_drop_pkts; + /* Number of packets discarded in receive path */ + uint64_t rx_discard_pkts; + /* Number of packets in receive path with errors */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -39511,7 +53198,7 @@ struct hwrm_stat_ext_ctx_query_input { uint8_t unused_0[3]; } __rte_packed; -/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */ +/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ struct hwrm_stat_ext_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; @@ -39563,6 +53250,8 @@ struct hwrm_stat_ext_ctx_query_output { uint64_t rx_tpa_bytes; /* Number of TPA errors */ uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -40490,7 +54179,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -40525,20 +54214,31 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Type (valid values are defined in the + * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). + */ uint16_t dir_type; /* * Directory ordinal. * The 0-based instance of the combined Directory Entry Type and Extension. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_attr; /* - * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. + * The data length stored in the directory entry will be updated to + * reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -40551,13 +54251,46 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. + * This value may be greater than or equal to the specified data + * length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, + * which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes + * for an item's data is to pre-allocate extra storage (padding) to + * accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -40572,8 +54305,11 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be + * greater than or equal to the specified data length or the requested + * item length. + * The actual item length used when creating a new directory entry will + * be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -40782,7 +54518,8 @@ struct hwrm_nvm_find_dir_entry_output { uint32_t dir_data_length; /* * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + * Only valid if the directory entry is for embedded firmware stored + * in APE_BIN Format. */ uint32_t fw_ver; /* Directory ordinal. */ @@ -40898,7 +54635,7 @@ struct hwrm_nvm_get_dev_info_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ +/* hwrm_nvm_get_dev_info_output (size:640b/80B) */ struct hwrm_nvm_get_dev_info_output { /* The specific error status for the command. */ uint16_t error_code; @@ -40917,7 +54654,10 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ + /* + * Available size that can be used, in bytes. Available size is the + * NVRAM size take away the used size and reserved size. + */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -40925,6 +54665,82 @@ struct hwrm_nvm_get_dev_info_output { uint8_t nvm_cfg_ver_min; /* This field represents the update version of NVM cfg */ uint8_t nvm_cfg_ver_upd; + uint8_t flags; + /* + * If set to 1, firmware will provide various firmware version + * information stored in the flash. + */ + #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \ + UINT32_C(0x1) + /* + * This field represents the board package name stored in the flash. + * (ASCII chars with NULL at the end). + */ + char pkg_name[16]; + /* + * This field represents the major version of HWRM firmware, stored in + * the flash. + */ + uint16_t hwrm_fw_major; + /* + * This field represents the minor version of HWRM firmware, stored in + * the flash. + */ + uint16_t hwrm_fw_minor; + /* + * This field represents the build version of HWRM firmware, stored in + * the flash. + */ + uint16_t hwrm_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the HWRM firmware. + */ + uint16_t hwrm_fw_patch; + /* + * This field represents the major version of mgmt firmware, stored in + * the flash. + */ + uint16_t mgmt_fw_major; + /* + * This field represents the minor version of mgmt firmware, stored in + * the flash. + */ + uint16_t mgmt_fw_minor; + /* + * This field represents the build version of mgmt firmware, stored in + * the flash. + */ + uint16_t mgmt_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the mgmt firmware. + */ + uint16_t mgmt_fw_patch; + /* + * This field represents the major version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_major; + /* + * This field represents the minor version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_minor; + /* + * This field represents the build version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the roce firmware. + */ + uint16_t roce_fw_patch; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -40983,9 +54799,15 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for + * extension flag definitions). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). + */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -41060,8 +54882,10 @@ struct hwrm_nvm_verify_update_input { /* * The Directory Entry Extension flags. * The "UPDATE" extension flag must be set in this value. - * A corresponding directory entry with the same type and ordinal values but *without* - * the "UPDATE" extension flag must also exist. The other flags of the extension must + * A corresponding directory entry with the same type and ordinal + * values but *without* + * the "UPDATE" extension flag must also exist. The other flags of + * the extension must * be identical between the active and update entries. */ uint16_t dir_ext; @@ -41148,18 +54972,25 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \ HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL uint16_t flags; - /* If set to 1, then securely erase all unused locations in persistent storage. */ + /* + * If set to 1, then securely erase all unused locations in + * persistent storage. + */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, will be safely deleted. - * When combined with erase_unused_space then unspecified images will be securely erased. + * If set to 1, then unspecified images, images not in the package + * file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will + * be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) /* - * If set to 1, FW will defragment the NVM if defragmentation is required for the update. - * Allow additional time for this command to complete if this bit is set to 1. + * If set to 1, FW will defragment the NVM if defragmentation is + * required for the update. + * Allow additional time for this command to complete if this bit is + * set to 1. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) @@ -41189,12 +55020,94 @@ struct hwrm_nvm_install_update_output { * A value of 0 indicates that no items were successfully installed. */ uint64_t installed_items; - /* result is 8 b */ + /* result is 8 b corresponding to BCMRETVAL error codes */ uint8_t result; /* There was no problem with the package installation. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \ + UINT32_C(0x0) + /* Generic failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \ + UINT32_C(0xff) + /* Allocation error malloc failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \ + UINT32_C(0xfd) + /* NVM install error due to invalid index */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \ + UINT32_C(0xfb) + /* NVM install error due to invalid type */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \ + UINT32_C(0xf3) + /* Invalid package due to invalid prerequisite */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \ + UINT32_C(0xf2) + /* Invalid package due to invalid file header */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \ + UINT32_C(0xec) + /* Invalid package due to invalid format */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \ + UINT32_C(0xeb) + /* Invalid package due to invalid property stream */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \ + UINT32_C(0xea) + /* Invalid package due to invalid property length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \ + UINT32_C(0xe9) + /* Invalid package due to invalid manifest */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \ + UINT32_C(0xe8) + /* Invalid package due to invalid trailer */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \ + UINT32_C(0xe7) + /* Invalid package due to invalid checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \ + UINT32_C(0xe6) + /* Invalid package due to invalid item checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \ + UINT32_C(0xe5) + /* Invalid package due to invalid length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \ + UINT32_C(0xe4) + /* Invalid package due to invalid directive */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \ + UINT32_C(0xe1) + /* Invalid device due to unsupported chip revision */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \ + UINT32_C(0xce) + /* Invalid device due to unsupported device ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \ + UINT32_C(0xcd) + /* Invalid device due to unsupported subsystem vendor */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \ + UINT32_C(0xcc) + /* Invalid device due to unsupported subsystem ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \ + UINT32_C(0xcb) + /* Invalid device due to unsupported product ID or customer ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \ + UINT32_C(0xc5) + /* Invalid package due to duplicate item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \ + UINT32_C(0xc4) + /* Invalid package due to zero length item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \ + UINT32_C(0xc3) + /* NVM integrity error checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \ + UINT32_C(0xb9) + /* NVM integrity error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \ + UINT32_C(0xb8) + /* Authentication error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \ + UINT32_C(0xb7) + /* NVM install error item not found */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \ + UINT32_C(0xb0) + /* NVM install error item locked */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \ + UINT32_C(0xa7) #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \ - HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED /* problem_item is 8 b */ uint8_t problem_item; /* There was no problem with any packaged items. */ @@ -41250,13 +55163,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -41424,12 +55343,13 @@ struct hwrm_nvm_get_variable_output { /* size of data of the actual variable retrieved in bits */ uint16_t data_len; /* - * option_num is the option number for the data retrieved. It is possible in the - * future that the option number returned would be different than requested. This - * condition could occur if an option is deprecated and a new option id is defined - * with similar characteristics, but has a slightly different definition. This - * also makes it convenient for the caller to identify the variable result with - * the option id from the response. + * option_num is the option number for the data retrieved. It is + * possible in the future that the option number returned would be + * different than requested. This condition could occur if an option is + * deprecated and a new option id is defined with similar + * characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable + * result with the option id from the response. */ uint16_t option_num; /* reserved. */ @@ -41538,7 +55458,10 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ + /* + * When this bit is 1, flush internal cache after this write + * operation (see hwrm_nvm_flush command.) + */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -41689,9 +55612,15 @@ struct hwrm_nvm_validate_option_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; uint8_t result; - /* indicates that the value provided for the option is not matching with the saved data. */ + /* + * indicates that the value provided for the option is not matching + * with the saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) - /* indicates that the value provided for the option is matching the saved data. */ + /* + * indicates that the value provided for the option is matching the + * saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \ HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH @@ -41720,6 +55649,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ @@ -41840,7 +55847,10 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \ UINT32_C(0x4) - /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */ + /* + * AP processor complex (in multi-host environment). + * Use host_idx to control which core is reset + */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \ UINT32_C(0x5) /* Reset all blocks of the chip (including all processors) */ @@ -42059,12 +56069,12 @@ struct hcomm_status { #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL /************************** - * hwrm_cfa_counter_qcaps * + * hwrm_port_phy_i2c_read * **************************/ -/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_counter_qcaps_input { +/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ +struct hwrm_port_phy_i2c_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42093,236 +56103,33 @@ struct hwrm_cfa_counter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; - -/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ -struct hwrm_cfa_counter_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; uint32_t flags; - /* Enumeration denoting the supported CFA counter format. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \ - UINT32_C(0x1) - /* CFA counter types are not supported. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \ - UINT32_C(0x0) - /* 64-bit packet counters followed by 64-bit byte counters format. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \ - UINT32_C(0x1) - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \ - HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT - uint32_t unused_0; - /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */ - uint32_t min_rx_fc; - /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */ - uint32_t max_rx_fc; - /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */ - uint32_t min_tx_fc; - /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */ - uint32_t max_tx_fc; - /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */ - uint32_t min_rx_efc; - /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */ - uint32_t max_rx_efc; - /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */ - uint32_t min_tx_efc; - /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */ - uint32_t max_tx_efc; - /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */ - uint32_t min_rx_mdc; - /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */ - uint32_t max_rx_mdc; - /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */ - uint32_t min_tx_mdc; - /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */ - uint32_t max_tx_mdc; - /* Maximum guaranteed number of flow counters which can be used during flow alloc. */ - uint32_t max_flow_alloc_fc; - uint8_t unused_1[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/************************ - * hwrm_cfa_counter_cfg * - ************************/ - - -/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ -struct hwrm_cfa_counter_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint16_t flags; - /* Enumeration denoting the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \ - UINT32_C(0x1) - /* Disable the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \ - UINT32_C(0x0) - /* Enable the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \ - UINT32_C(0x1) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \ - HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \ - UINT32_C(0x2) - /* Tx path. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \ - (UINT32_C(0x0) << 1) - /* Rx path. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \ - (UINT32_C(0x1) << 1) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the data transfer mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \ - UINT32_C(0xc) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 - /* Push mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \ - (UINT32_C(0x0) << 2) - /* Pull mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \ - (UINT32_C(0x1) << 2) - /* Pull on async update. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \ - (UINT32_C(0x2) << 2) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \ - HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC - uint16_t counter_type; - /* Flow counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) - /* Extended flow counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) - /* Meter drop counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \ - HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC - /* Ctx memory handle to be used for the counter. */ - uint16_t ctx_id; - /* Counter update cadence hint (only in Push mode). */ - uint16_t update_tmr_ms; - /* Total number of entries. */ - uint32_t num_entries; - uint32_t unused_0; -} __rte_packed; - -/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_counter_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/*************************** - * hwrm_cfa_counter_qstats * - ***************************/ - - -/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ -struct hwrm_cfa_counter_qstats_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; + uint32_t enables; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit must be '1' for the page_offset field to be + * configured. */ - uint16_t target_id; + #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL + /* Port ID of port. */ + uint16_t port_id; + /* 8-bit I2C slave address. */ + uint8_t i2c_slave_addr; + uint8_t unused_0; + /* The page number that is being accessed over I2C. */ + uint16_t page_number; + /* Offset within the page that is being accessed over I2C. */ + uint16_t page_offset; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Length of data to read, in bytes starting at the offset + * specified above. If the offset is not specified, then + * the data shall be read from the beginning of the page. */ - uint64_t resp_addr; - uint16_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* Tx path. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* Rx path. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX - uint16_t counter_type; - uint16_t input_flow_ctx_id; - uint16_t num_entries; - uint16_t delta_time_ms; - uint16_t meter_instance_id; - uint16_t mdc_ctx_id; - uint8_t unused_0[2]; - uint64_t expected_count; + uint8_t data_length; + uint8_t unused_1[7]; } __rte_packed; -/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ -struct hwrm_cfa_counter_qstats_output { +/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ +struct hwrm_port_phy_i2c_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42331,6 +56138,8 @@ struct hwrm_cfa_counter_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Up to 64B of data. */ + uint32_t data[16]; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -42341,5 +56150,4 @@ struct hwrm_cfa_counter_qstats_output { */ uint8_t valid; } __rte_packed; - #endif /* _HSI_STRUCT_DEF_DPDK_H_ */