X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=380dec4d3ed1b6f12606968e16e3fca278788f83;hb=447a0721ff9acfc14f5c64c031be7da956e9344a;hp=aea930548671da0b53d36ab3cabdd2ebcc108097;hpb=8ea894a7437f85d184f26a9caa8311bd9ac38023;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index aea9305486..380dec4d3e 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2021 Broadcom Inc. + * Copyright (c) 2014-2022 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -364,6 +364,8 @@ struct cmd_nums { #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83) #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84) #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) + #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) + #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -438,6 +440,8 @@ struct cmd_nums { #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) /* Tells the fw to collect dsc dump on a given port and lane. */ #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) + #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda) + #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -535,6 +539,14 @@ struct cmd_nums { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127) + /* Experimental */ + #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128) + /* Experimental */ + #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ @@ -637,6 +649,35 @@ struct cmd_nums { #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a) /* Query SoC packet DMA settings */ #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b) + /* PTP - Queries configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c) + /* PTP - Configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d) + /* PTP - Configuration for disciplining PHC. */ + #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e) + /* PTP - Queries for PHC timestamps. */ + #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f) + /* PTP - Extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) + /* PTP - Query extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS or QUIC key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) + /* The is the new API to configure backing stores. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3) + /* The is the new API to query backing store configurations. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4) + /* To support doorbell pacing configuration. */ + #define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5) + /* To query doorbell pacing configuration. */ + #define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6) + /* + * To broadcast the doorbell event to the drivers to + * initiate pacing of doorbells. + */ + #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7) + /* The is the new API to query backing store capabilities. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -674,6 +715,38 @@ struct cmd_nums { #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) /* Tells the fw to get the health of seeprom data */ #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* + * The command is used for certificate provisioning to export a + * Certificate Signing Request (CSR) from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211) + /* + * The command is used for certificate provisioning to import a + * CA-signed certificate chain to the device. + */ + #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212) + /* + * The command is used for certificate provisioning to query the + * provisioned state. + */ + #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213) + /* + * The command is used to get the hash of the NVM configuration that is + * calculated during firmware boot. + */ + #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214) + /* Retrieves the PSOC status and provisioning information. */ + #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215) + /* + * This command allows manufacturing tool to determine which selftests + * are available to be run. + */ + #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216) + /* + * This command allows manufacturing tool to request which selftests + * to run. + */ + #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -699,6 +772,8 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) /* Experimental */ + #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) @@ -727,6 +802,8 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec) /* Experimental */ + #define HWRM_TF_EM_MOVE UINT32_C(0x2ed) + /* Experimental */ #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) /* Experimental */ #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) @@ -781,6 +858,25 @@ struct cmd_nums { #define HWRM_DBG_QCFG UINT32_C(0xff21) /* Set destination parameters for crashdump medium */ #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + /* Experimental */ + #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23) + /* Experimental */ + #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24) + /* Experimental */ + #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25) + /* Experimental */ + #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26) + /* Experimental */ + #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27) + /* Experimental */ + #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28) + /* Experimental */ + #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29) + /* Experimental */ + #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) + /* Experimental */ + #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) @@ -899,6 +995,13 @@ struct ret_codes { * by the host is not allowed due to a secure lock violation. */ #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11) + /* + * This error code is reported by Firmware when an operation requested + * by a VF cannot be forwarded to the parent PF as required, either + * because the PF is down or otherwise doesn't have an appropriate + * async completion ring or associated forwarding buffers configured. + */ + #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -986,8 +1089,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 15 -#define HWRM_VERSION_STR "1.10.2.15" +#define HWRM_VERSION_RSVD 83 +#define HWRM_VERSION_STR "1.10.2.83" /**************** * hwrm_ver_get * @@ -1287,6 +1390,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1379,7 +1488,7 @@ struct hwrm_ver_get_output { * backing store not been available. * For Example, PCIe hot-plug: * Hot plug timing is system dependent. It generally takes up to - * 600 miliseconds for firmware to clear DEV_NOT_RDY flag. + * 600 milliseconds for firmware to clear DEV_NOT_RDY flag. * If set to 0, device is ready to accept all HWRM commands. */ #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \ @@ -1543,7 +1652,18 @@ struct hwrm_ver_get_output { * used with the short cmd request format. */ uint16_t max_ext_req_len; - uint8_t unused_1[5]; + /* + * This field returns the maximum request timeout value in seconds. + * For backward compatibility, a value of zero should be interpreted + * as the default value of 40 seconds. Drivers should always honor the + * maximum timeout, but are permitted to warn if a longer duration than + * this default is advertised. Values larger than 40 seconds should + * only be used as a stopgap measure to address a device limitation or + * for the purposes of test and debugging. The long term goal is for + * firmware to significantly reduce this value in the passage of time. + */ + uint16_t max_req_timeout; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -1916,9 +2036,8 @@ struct ce_bds_add_data_msg { /* * Version number of TLS connection. HW will provide registers that * converts the 4b encoded version number to 16b of actual version - * number in the TLS Header. * Initialized --> By mid-path command * - * Updated --> Never though another mid-path command will result in an - * update. + * number in the TLS Header. This field is initialized/updated by + * this "KTLS crypto add" mid-path command. */ #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \ UINT32_C(0xf0000000) @@ -1931,19 +2050,28 @@ struct ce_bds_add_data_msg { (UINT32_C(0x1) << 28) #define CE_BDS_ADD_DATA_MSG__LAST \ CE_BDS_ADD_DATA_MSG__TLS1_3 + uint8_t cmd_type_ctx_kind; /* * Command Type in the TLS header. HW will provide registers that - * converts the 3b encoded command type to 8b of actual command type in - * the TLS Header. * Initialized --> By mid-path command * Updated --> - * Never though another mid-path command will result in an update + * converts the 3b encoded command type to 8b of actual command + * type in the TLS Header. This field is initialized/updated by + * this "KTLS crypto add" mid-path command. */ - uint8_t cmd_type; #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7) - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 /* Application */ - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \ CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP + /* This field selects the context kind for the request. */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3 + /* Crypto key transmit context */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3) + /* Crypto key receive context */ + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX uint8_t unused0[3]; /* * Salt is part of the nonce that is used as the Initial Vector (IV) in @@ -1994,13 +2122,13 @@ struct ce_bds_add_data_msg { /* ce_bds_delete_data_msg (size:64b/8B) */ struct ce_bds_delete_data_msg { - uint32_t kid_opcode; + uint32_t kid_opcode_ctx_kind; /* * This value selects the operation for the mid-path command for the * crypto blocks. */ - #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf) - #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0 + #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0 /* * This is the delete command. Using this opcode, the host Driver * can remove a key context from the CFCK. If context is deleted @@ -2010,15 +2138,28 @@ struct ce_bds_delete_data_msg { * receive packets, no crypto operation will be performed, * payload will be unmodified. */ - #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2) #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \ CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE /* * This field is the Crypto Context ID. The KID is used to store * information used by the associated kTLS offloaded connection. */ - #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0) - #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4 + #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0) + #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4 + /* This field selects the context kind for the request. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000) + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_SFT 24 + /* Crypto Key Transmit Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24) + /* Crypto Key Receive Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24) + /* QUIC Key Transmit Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24) + /* QUIC Key Receive Context. */ + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24) + #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX uint32_t unused0; } __rte_packed; @@ -2182,7 +2323,7 @@ struct crypto_presync_bd_cmd { uint32_t end_tcp_seq_num; /* * For TLS1.2, an explicit nonce is used as part of the IV (concatenated - * with the SALT). For retans packets, this field is extracted from the + * with the SALT). For retrans packets, this field is extracted from the * TLS record, field right after the TLS Header and stored in the * context. This field needs to be stored in context as TCP segmentation * could have split the field into multiple TCP packets. This value is @@ -2246,6 +2387,12 @@ struct bd_base { * sync command through the fast path and destined for TCE. */ #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9) + /* + * Indicates a timed transmit BD. This is a 16b BD that is inserted + * into a packet BD chain immediately after the first BD. It is used + * to control the flow in a timed transmit operation. + */ + #define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa) /* * Indicates that this BD is 32B long and is used for * normal L2 packet transmission. @@ -2527,10 +2674,22 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) /* - * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC for 2-step time sync. + * This bit, in conjunction with the stamp_1step bit, controls whether + * a TX packet timestamp is collected and the type of timestamp that + * is collected. * * This bit must be valid on the first BD of a packet. + * + * Enumerations of the concatenation { stamp, stamp_1step } are + * as follows: + * + * - 2'b00: ts_none - no timestamp + * - 2'b01: ts_ptp_1step - 1-step PTP + * - 2'b10: ts_2cmpl - 2-step PTP timestamp or PA timestamp + * - 2'b11: ts_rsvd - reserved, same behavior as ts_none + * For the ts_2cmpl enumeration, an additional completion is returned. + * This additional completion may carry a 2-step PTP timestamp or a PA + * timestamp, depending on parsing of the transmitted packet. */ #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8) /* @@ -2539,15 +2698,15 @@ struct tx_bd_long_hi { * of the packet associated with this descriptor. * * For outer UDP checksum, global outer UDP checksum TE_NIC register - * needs to be enabled. If the global outer UDP checksum TE_NIC register - * bit is set, outer UDP checksum will be calculated for the following - * cases: - * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner - * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for - * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP - * checksum will not be calculated. - * 2. Packets with lso flag set which implies inner TCP checksum calculation - * as part of LSO operation. + * needs to be enabled. If the global outer UDP checksum TE_NIC + * register bit is set, outer UDP checksum will be calculated for + * the following cases: + * 1. Packets with tcp_udp_chksum flag set to offload checksum for + * inner packet AND the inner packet is TCP/UDP. If the inner packet + * is ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is + * set, the outer UDP checksum will not be calculated. + * 2. Packets with lso flag set which implies inner TCP checksum + * calculation as part of LSO operation. */ #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* @@ -2605,26 +2764,32 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800) /* - * If set to '1', the device will record the time at which the packet - * was actually transmitted at the TX MAC for 1-step time sync. This - * bit must be valid on the first BD of a packet. + * This bit, in conjunction with the stamp bit, controls whether a + * TX packet timestamp is collected and the type of timestamp that + * is collected. + * + * See the stamp field for a description of the valid combinations of + * stamp and stamp_1step. + * + * This bit must be valid on the first BD of a packet. */ #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000) /* * If set to '1', the controller replaces the Outer-tunnel IP checksum * field with hardware calculated IP checksum for the IP header of the * packet associated with this descriptor. For outer UDP checksum, it - * will be the following behavior for all cases independent of settings - * of inner LSO and checksum offload BD flags. If outer UDP checksum - * is 0, then do not update it. If outer UDP checksum is non zero, then - * the hardware should compute and update it. + * will be the following behavior for all cases independent of + * settings of inner LSO and checksum offload BD flags. + * If outer UDP checksum is 0, then do not update it. + * If outer UDP checksum is non zero, then the hardware should + * compute and update it. */ #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) /* - * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP - * header will not be modified during LSO operations. If set to one - * when LSO is '1', then the IPID of the Outer-tunnel IP header will be - * incremented for each subsequent segment of an LSO operation. The + * If set to zero when LSO is '1', then the IPID of the Outer-tunnel + * IP header will not be modified during LSO operations. If set to one + * when LSO is '1', then the IPID of the Outer-tunnel IP header will + * be incremented for each subsequent segment of an LSO operation. The * flag is ignored if the LSO packet is a normal (non-tunneled) TCP * packet. */ @@ -2648,8 +2813,8 @@ struct tx_bd_long_hi { #define TX_BD_LONG_HDR_SIZE_SFT 0 /* * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit - * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the - * 20-bit KID. + * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of + * the 20-bit KID. */ #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00) #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9 @@ -2756,11 +2921,11 @@ struct tx_bd_long_hi { } __rte_packed; /* - * This structure is used to inform the NIC of packet data that needs to be - * transmitted with additional processing that requires extra data such as - * VLAN insertion plus attached inline data. This BD type may be used to - * improve latency for small packets needing the additional extended features - * supported by long BDs. + * This structure is used to inform the NIC of packet data that needs to + * be transmitted with additional processing that requires extra data + * such as VLAN insertion plus attached inline data. + * This BD type may be used to improve latency for small packets needing + * the additional extended features supported by long BDs. */ /* tx_bd_long_inline (size:256b/32B) */ struct tx_bd_long_inline { @@ -2828,13 +2993,13 @@ struct tx_bd_long_inline { uint16_t len; /* * The opaque data field is passed through to the completion and can be - * used for any data that the driver wants to associate with the transmit - * BD. This field must be valid on the first BD of a packet. If - * completion coalescing is enabled on the TX ring, it is suggested that - * the driver populate the opaque field to indicate the specific TX ring - * with which the completion is associated, then utilize the opaque and - * sq_cons_idx fields in the coalesced completion record to determine - * the specific packets that are to be completed on that ring. + * used for any data that the driver wants to associate with the + * transmit BD. This field must be valid on the first BD of a packet. + * If completion coalescing is enabled on the TX ring, it is suggested + * that the driver populate the opaque field to indicate the specific + * TX ring with which the completion is associated, then utilize the + * opaque and sq_cons_idx fields in the coalesced completion record to + * determine the specific packets that are to be completed on that ring. * * This field must be valid on the first BD of a packet. */ @@ -3416,10 +3581,10 @@ struct cfa_cmpls_cmp_data_msg { #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \ UINT32_C(0xf0000000) #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28 - /* TX configrable flow processing block. */ + /* TX configurable flow processing block. */ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \ (UINT32_C(0x2) << 28) - /* RX configrable flow processing block. */ + /* RX configurable flow processing block. */ #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \ (UINT32_C(0x3) << 28) #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ @@ -3539,8 +3704,20 @@ struct ce_cmpls_cmp_data_msg { /* FID check error. */ #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \ (UINT32_C(0x2) << 10) + /* Context kind / MP version mismatch error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \ + (UINT32_C(0x3) << 10) + /* Unsupported Destination Connection ID Length. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \ + (UINT32_C(0x4) << 10) + /* + * Invalid MP Command [anything other than ADD or DELETE + * triggers this for QUIC]. + */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \ + (UINT32_C(0x5) << 10) #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \ - CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR + CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR uint8_t unused0; uint8_t mp_clients; #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf) @@ -3611,6 +3788,11 @@ struct cmpl_base { * Completion of PTP TX packet. Length = 32B */ #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) + /* + * TX L2 Packet Timestamp completion: + * Completion of an L2 Packet Timestamp Packet. Length = 16B + */ + #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4) /* * RX L2 TPA Start V2 Completion: * Completion of and L2 RX packet. Length = 32B @@ -3625,13 +3807,19 @@ struct cmpl_base { * and later chips. */ #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf) + /* + * RX L2 completion: + * This is the compressed version of Rx Completion for performance + * applications. Length = 16B + */ + #define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10) /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B */ #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11) /* - * RX Aggregation Buffer completion : + * RX Aggregation Buffer completion: * Completion of an L2 aggregation buffer in support of * TPA, HDS, or Jumbo packet completion. Length = 16B */ @@ -3648,6 +3836,24 @@ struct cmpl_base { * Length = 32B */ #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15) + /* + * RX TPA Aggregation Buffer Completion: + * Completion of an L2 aggregation buffer in support of TPA packet + * completion. + * Length = 16B + */ + #define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16) + /* + * RX L2 completion: Completion of and L2 RX packet. + * Length = 32B + */ + #define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17) + /* + * RX L2 TPA Start completion: Completion at the beginning of a TPA + * operation. + * Length = 32B + */ + #define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19) /* * Statistics Ejection Completion: * Completion of statistics data ejection buffer. @@ -3815,7 +4021,7 @@ struct tx_cmpl { */ #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200) /* - * When this bit is '1', it was not possible to collect a a timestamp + * When this bit is '1', it was not possible to collect a timestamp * for a PTP completion, in which case the timestamp_hi and * timestamp_lo fields are invalid. When this bit is '0' for a PTP * completion, the timestamp_hi and timestamp_lo fields are valid. @@ -4100,8 +4306,9 @@ struct tx_cmpl_ptp_hi { uint64_t v2; /* * This value is written by the NIC such that it will be different for - * each pass through the completion queue.The even passes will write 1. - * The odd passes will write 0 + * each pass through the completion queue. + * The even passes will write 1. + * The odd passes will write 0. */ #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) } __rte_packed; @@ -4116,53 +4323,60 @@ struct rx_pkt_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_PKT_CMPL_TYPE_SFT 0 + #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_CMPL_TYPE_SFT 0 /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B */ - #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11) - #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2 - #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_PKT_CMPL_FLAGS_SFT 6 + #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11) + #define RX_PKT_CMPL_TYPE_LAST \ + RX_PKT_CMPL_TYPE_RX_L2 + #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an * error of some type. Type of error is indicated in * error_flags. */ - #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Normal: * Packet was placed using normal algorithm. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: * Packet was placed using jumbo algorithm. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \ RX_PKT_CMPL_FLAGS_PLACEMENT_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. + */ + #define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12 /* * Not Known: * Indicates that the packet type was not known. @@ -4212,15 +4426,15 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \ (UINT32_C(0x7) << 12) /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP * packet. */ #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ (UINT32_C(0x8) << 12) /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP * packet and that a timestamp was taken for the packet. */ #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ @@ -4260,37 +4474,49 @@ struct rx_pkt_cmpl { /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of inner * IP and TCP or UDP headers. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0) + /* + * The RSS hash was computed over source IP address and destination * IP address of inner IP header. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3) + #define RX_PKT_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. * * A value of zero indicates that header is 256B into the packet. */ @@ -4777,15 +5003,15 @@ struct rx_pkt_v2_cmpl { #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \ (UINT32_C(0x7) << 12) /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP * packet. */ #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ (UINT32_C(0x8) << 12) /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP * packet and that a timestamp was taken for the packet. */ #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ @@ -4825,33 +5051,45 @@ struct rx_pkt_v2_cmpl { /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of inner * IP and TCP or UDP headers. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0) + /* + * The RSS hash was computed over source IP address and destination * IP address of inner IP header. Note: For non-tunneled packets, * the packet headers are considered inner packet headers for the RSS * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3) + #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 uint16_t metadata1_payload_offset; /* * This is data from the CFA as indicated by the meta_format field. @@ -4943,7 +5181,7 @@ struct rx_pkt_v2_cmpl_hi { * information: * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i + * value, justified to LSB. * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier * - NVGRE = TNI[23:0] -> Tenant Network ID @@ -5303,12 +5541,8 @@ struct rx_pkt_v2_cmpl_hi { uint32_t timestamp; } __rte_packed; -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +/* rx_pkt_v3_cmpl (size:128b/16B) */ +struct rx_pkt_v3_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -5317,84 +5551,145 @@ struct rx_tpa_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_START_CMPL_TYPE_SFT 0 + #define RX_PKT_V3_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_V3_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B + * RX L2 V3 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in Thor2 + * and later chips. */ - #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) - #define RX_TPA_START_CMPL_TYPE_LAST \ - RX_TPA_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_START_CMPL_FLAGS_SFT 6 - /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 UINT32_C(0x17) + #define RX_PKT_V3_CMPL_TYPE_LAST \ + RX_PKT_V3_CMPL_TYPE_RX_L2_V3 + #define RX_PKT_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_V3_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_V3_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Normal: + * Packet was placed using normal algorithm. + */ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Packet was placed using jumbo algorithm. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Truncation: + * Packet was placed using truncation algorithm. The + * placed (truncated) length is indicated in the payload_offset + * field. The original length is indicated in the len field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION \ + (UINT32_C(0x3) << 7) + #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_LAST \ + RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* * TCP Packet: * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP + * packet. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP + * packet and that a timestamp was taken for the packet. + * The 4b sub-nanosecond portion of the timestamp is in + * the payload_offset field. + */ + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_V3_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -5402,197 +5697,955 @@ struct rx_tpa_start_cmpl { * corresponds to. */ uint32_t opaque; + uint16_t rss_hash_type_agg_bufs_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t v1; + #define RX_PKT_V3_CMPL_V1 UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + #define RX_PKT_V3_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_V3_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 1 b */ + #define RX_PKT_V3_CMPL_UNUSED1 UINT32_C(0x40) /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. - * * The value of tuple_extrac_op provides the information about * what fields the hash was computed on. - * * 0: The RSS hash was computed over source IP address, - * destination IP address, source port, and destination port of inner - * IP and TCP or UDP headers. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 1: The RSS hash was computed over source IP address and destination - * IP address of inner IP header. Note: For non-tunneled packets, - * the packet headers are considered inner packet headers for the RSS - * hash computation purpose. - * * 2: The RSS hash was computed over source IP address, + * Note that 4-tuples values listed below are applicable + * for layer 4 protocols supported and enabled for RSS in the + * hardware, HWRM firmware, and drivers. For example, if RSS hash + * is supported and enabled for TCP traffic only, then the values of + * tuple_extract_op corresponding to 4-tuples are only valid for + * TCP traffic. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_SFT 7 + /* + * The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * inner IP and TCP or UDP headers. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (UINT32_C(0x0) << 7) + /* + * The RSS hash was computed over source IP address and + * destination IP address of inner IP header. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (UINT32_C(0x1) << 7) + /* + * The RSS hash was computed over source IP address, * destination IP address, source port, and destination port of * IP and TCP or UDP headers of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * * 3: The RSS hash was computed over source IP address and + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2 (UINT32_C(0x2) << 7) + /* + * The RSS hash was computed over source IP address and * destination IP address of IP header of outer tunnel headers. * Note: For non-tunneled packets, this value is not applicable. - * - * Note that 4-tuples values listed above are applicable - * for layer 4 protocols supported and enabled for RSS in the hardware, - * HWRM firmware, and drivers. For example, if RSS hash is supported and - * enabled for TCP traffic only, then the values of tuple_extract_op - * corresponding to 4-tuples are only valid for TCP traffic. */ - uint8_t rss_hash_type; + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (UINT32_C(0x3) << 7) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * The RSS hash was computed over source IP address of the inner + * IP header. */ - uint16_t agg_id; - /* unused2 is 9 b */ - #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (UINT32_C(0x4) << 7) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * The RSS hash was computed over destination IP address of the + * inner IP header. */ - #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) - #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (UINT32_C(0x5) << 7) + /* + * The RSS hash was computed over source IP address of the outer + * IP header. + * Note: For non-tunneled packets, this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (UINT32_C(0x6) << 7) + /* + * The RSS hash was computed over destination IP address of the + * outer IP header. + * Note: For non-tunneled packets, this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (UINT32_C(0x7) << 7) + /* + * The RSS hash was computed over source IP address, destination + * IP address, and flow label of the inner IP header. + * Note: For packets without an inner IPv6 header, this value is not + * this value is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (UINT32_C(0x8) << 7) + /* + * The RSS hash was computed over the flow label of the inner + * IP header. + * Note: For packets without an inner IPv6 header, this value + * is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (UINT32_C(0x9) << 7) + /* + * The RSS hash was computed over source IP address, destination + * IP address, and flow label of the outer IP header. + * Note: For packets without an outer IPv6 header, this value is not + * applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (UINT32_C(0xa) << 7) + /* + * The RSS hash was computed over the flow label of the outer + * IP header. + * Note: For packets without an outer IPv6 header, this value + * is not applicable. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST \ + RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 + uint16_t metadata1_payload_offset; + /* + * If truncation placement is not used, this value indicates the offset + * in bytes from the beginning of the packet where the inner payload + * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. + * For PTP packets with timestamp (as indicated by the flags_itype + * field), this field contains the 4b sub-nanosecond portion of the + * timestamp. + * + * If truncation placement is used, this value represents the placed + * (truncated) length of the packet. + */ + #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_V3_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V3_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_V3_CMPL_METADATA1_VALID UINT32_C(0x8000) /* * This value is the RSS hash value calculated for the packet - * based on the mode bits and key value in the VNIC. + * based on the mode bits and key value in the VNIC. When hairpin_en + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. */ uint32_t rss_hash; } __rte_packed; -/* - * Last 16 bytes of rx_tpa_start_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_cmpl_hi { +/* Last 16 bytes of RX Packet V3 Completion Record */ +/* rx_pkt_v3_cmpl_hi (size:128b/16B) */ +struct rx_pkt_v3_cmpl_hi { uint32_t flags2; /* - * This indicates that the ip checksum was calculated for the - * inner packet and that the sum passed for all segments - * included in the aggregation. + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * This indicates that the TCP, UDP or ICMP checksum was - * calculated for the inner packet and that the sum passed - * for all segments included in the aggregation. + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. */ - #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * This indicates that the ip checksum was calculated for the - * tunnel header and that the sum passed for all segments - * included in the aggregation. + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the sum passed for - * all segments included in the aggregation. + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. */ - #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) /* This value indicates what format the metadata field is. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* - * The metadata field contains the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. - * - metadata[31:16] contains the vlan TPID value. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \ (UINT32_C(0x1) << 4) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_LAST \ + RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE \ + UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 10) + #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_LAST \ + RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] */ - uint32_t metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 - uint16_t v2; + uint32_t metadata2; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_V2 \ + UINT32_C(0x1) + #define RX_PKT_V3_CMPL_HI_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_PKT_V3_CMPL_HI_ERRORS_SFT 1 /* - * This field identifies the CFA action rule that was used for this - * packet. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - uint16_t cfa_code; + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 8 physical buffers. */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. For regular placement, this error is + * not valid. For HDS and jumbo placement, this means that not + * enough agg BDs were posted to place the packet. */ - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. + * Bad Format: + * BDs were not formatted correctly. */ - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. + * Flush: + * There was a bad_format error on the previous operation */ - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH + /* This indicates that there was an error in the IP header checksum. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR \ + UINT32_C(0x10) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * This indicates that there was an error in the TCP, UDP or ICMP + * checksum. */ - #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 + #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR \ + UINT32_C(0x20) + /* + * This indicates that there was an error in the tunnel IP header + * checksum. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR \ + UINT32_C(0x40) + /* This indicates that there was an error in the tunnel UDP checksum. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR \ + UINT32_C(0x80) + /* + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR \ + UINT32_C(0x100) + /* + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe00) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9 + /* + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 9) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 9) + /* + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 9) + /* + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 9) + /* + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 9) + /* + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 9) + /* + * Indicates that the IP checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 9) + /* + * Indicates that the L4 checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 9) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0xf000) + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_SFT 12 + /* + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 12) + /* + * Indicates that the IP checksum failed its check in the + * inner header. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \ + (UINT32_C(0x9) << 12) + /* + * Indicates that the L4 checksum failed its check in the + * inner header. + */ + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \ + (UINT32_C(0xa) << 12) + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST \ + RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_SFT 13 + /* + * The timestamp field contains the 32b timestamp for the packet from + * the MAC. + * + * When hairpin_en is set in VNIC context, this is the upper 32b of the + * host address from the first BD used to place the packet. + */ + uint32_t timestamp; +} __rte_packed; + +/* rx_pkt_compress_cmpl (size:128b/16B) */ +struct rx_pkt_compress_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_PKT_COMPRESS_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_COMPRESS_CMPL_TYPE_SFT 0 + /* + * RX L2 completion: + * This is the compressed version of Rx Completion for performance + * applications. Length = 16B + * This version of the completion record is used in Thor2 and later + * chips. + */ + #define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS \ + UINT32_C(0x10) + #define RX_PKT_COMPRESS_CMPL_TYPE_LAST \ + RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS + #define RX_PKT_COMPRESS_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_PKT_COMPRESS_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE \ + UINT32_C(0x100) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 8) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 8) + #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_LAST \ + RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE \ + UINT32_C(0x200) + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + /* + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PTP packet wo/timestamp: + * Indicates that the packet was recognized as a PTP + * packet. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PTP packet w/timestamp: + * Indicates that the packet was recognized as a PTP + * packet and that a timestamp was taken for the packet. + * The 4b sub-nanosecond portion of the timestamp is in + * the payload_offset field. + */ + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. + */ + uint16_t len; + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. When hairpin_en + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. + */ + uint32_t rss_hash; + uint16_t metadata1_cs_error_calc_v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_PKT_COMPRESS_CMPL_V1 \ + UINT32_C(0x1) + /* unused is 3 b */ + #define RX_PKT_COMPRESS_CMPL_UNUSED_MASK \ + UINT32_C(0xe) + #define RX_PKT_COMPRESS_CMPL_UNUSED_SFT 1 + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK \ + UINT32_C(0xff0) + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_SFT 4 + /* This indicates that there was an error in the IP header checksum. */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR \ + UINT32_C(0x10) + /* + * This indicates that there was an error in the TCP, UDP or ICMP + * checksum. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR \ + UINT32_C(0x20) + /* + * This indicates that there was an error in the tunnel IP header + * checksum. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR \ + UINT32_C(0x40) + /* This indicates that there was an error in the tunnel UDP checksum. */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR \ + UINT32_C(0x80) + /* + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC \ + UINT32_C(0x100) + /* + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC \ + UINT32_C(0x200) + /* + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC \ + UINT32_C(0x400) + /* + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC \ + UINT32_C(0x800) + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_PKT_COMPRESS_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_COMPRESS_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t vlanc_tcid; + /* When meta_format!=0, this value is the VLAN VID. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff) + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_SFT 0 + /* When meta_format!=0, this value is the VLAN DE. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE UINT32_C(0x1000) + /* When meta_format!=0, this value is the VLAN PRI. */ + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_SFT 13 + uint32_t errors_agg_bufs_opaque; + /* Lower 16bits of the Opaque field provided in the Rx BD. */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK \ + UINT32_C(0xffff) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_SFT \ + 0 + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK \ + UINT32_C(0x1f0000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_SFT \ + 16 + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK \ + UINT32_C(0x1fe00000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_SFT \ + 21 + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0x1e00000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_SFT \ + 21 + /* + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 21) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 21) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 21) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 21) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 21) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 21) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 21) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 21) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 21) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_LAST \ + RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + /* + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe000000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_SFT \ + 25 + /* + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 25) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 25) + /* + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 25) + /* + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 25) + /* + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 25) + /* + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 25) + /* + * Indicates that the IP checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 25) + /* + * Indicates that the L4 checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 25) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + /* + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. + */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR \ + UINT32_C(0x10000000) + /* unused1 is 3 b */ + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK \ + UINT32_C(0xe0000000) + #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_SFT \ + 29 } __rte_packed; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte - * struct) */ -/* rx_tpa_start_v2_cmpl (size:128b/16B) */ -struct rx_tpa_start_v2_cmpl { +/* rx_tpa_start_cmpl (size:128b/16B) */ +struct rx_tpa_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -5601,33 +6654,23 @@ struct rx_tpa_start_v2_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_V2_CMPL_TYPE_MASK \ - UINT32_C(0x3f) - #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start V2 Completion: + * RX L2 TPA Start Completion: * Completion at the beginning of a TPA operation. * Length = 32B - * This is the new version of the RX_TPA_START completion used - * in SR2 and later chips. - */ - #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ - UINT32_C(0xd) - #define RX_TPA_START_V2_CMPL_TYPE_LAST \ - RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 - #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ - UINT32_C(0xffc0) - #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 - /* - * When this bit is '1', it indicates a packet that has an error - * of some type. Type of error is indicated in error_flags. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ - UINT32_C(0x40) + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + #define RX_TPA_START_CMPL_TYPE_LAST \ + RX_TPA_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ - UINT32_C(0x380) - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -5636,24 +6679,15 @@ struct rx_tpa_start_v2_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) - /* - * IOC/Jumbo: - * Packet will be placed using In-Order Completion/Jumbo where - * the first packet of the aggregation is placed using Jumbo - * Placement. Subsequent packets will be placed such that each - * packet starts at the beginning of an aggregation buffer. - */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ - (UINT32_C(0x4) << 7) /* * GRO/Jumbo: * Packet will be placed using GRO/Jumbo where the first @@ -5662,7 +6696,7 @@ struct rx_tpa_start_v2_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -5673,47 +6707,28 @@ struct rx_tpa_start_v2_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - /* - * IOC/Header-Data Separation: - * Packet will be placed using In-Order Completion/HDS where - * the header is in the first packet buffer. Payload of each - * packet will be placed such that each packet starts at the - * beginning of an aggregation buffer. - */ - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ - (UINT32_C(0x7) << 7) - #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ - UINT32_C(0x400) - /* - * This bit is '1' if metadata has been added to the end of the - * packet in host memory. Metadata starts at the first 32B boundary - * after the end of the packet for regular and jumbo placement. It - * starts at the first 32B boundary after the end of the header for - * HDS placement. The length of the metadata is indicated in the - * metadata itself. - */ - #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ - UINT32_C(0x800) + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ - UINT32_C(0xf000) - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 /* * TCP Packet: * Indicates that the packet was IP and TCP. */ - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* * This value indicates the amount of packet data written to the * buffer the opaque field in this completion corresponds to. @@ -5721,9 +6736,7 @@ struct rx_tpa_start_v2_cmpl { uint16_t len; /* * This is a copy of the opaque field from the RX BD this completion - * corresponds to. If the VNIC is configured to not use an Rx BD for - * the TPA Start completion, then this is a copy of the opaque field - * from the first BD used to place the TPA Start packet. + * corresponds to. */ uint32_t opaque; /* @@ -5737,7 +6750,331 @@ struct rx_tpa_start_v2_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + uint16_t agg_id; + /* unused2 is 9 b */ + #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) + #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + */ + uint32_t rss_hash; +} __rte_packed; + +/* + * Last 16 bytes of rx_tpa_start_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_cmpl_hi { + uint32_t flags2; + /* + * This indicates that the ip checksum was calculated for the + * inner packet and that the sum passed for all segments + * included in the aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + /* + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the sum passed + * for all segments included in the aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + /* + * This indicates that the ip checksum was calculated for the + * tunnel header and that the sum passed for all segments + * included in the aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + /* + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the sum passed for + * all segments included in the aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Value is zero. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The metadata field contains the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. + * - metadata[31:16] contains the vlan TPID value. + */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + (UINT32_C(0x1) << 4) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + */ + #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint32_t metadata; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 + uint16_t v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + /* + * This field identifies the CFA action rule that was used for this + * packet. + */ + uint16_t cfa_code; + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + /* + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. + */ + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. + */ + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. + */ + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte + * struct) + */ +/* rx_tpa_start_v2_cmpl (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_START_V2_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA Start V2 Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ + UINT32_C(0xd) + #define RX_TPA_START_V2_CMPL_TYPE_LAST \ + RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 + #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 /* * This is the RSS hash type for the packet. The value is packed @@ -5872,7 +7209,7 @@ struct rx_tpa_start_v2_cmpl_hi { * information: * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i + * value, justified to LSB. * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier * - NVGRE = TNI[23:0] -> Tenant Network ID @@ -6035,9 +7372,11 @@ struct rx_tpa_start_v2_cmpl_hi { /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V3 Completion Record (32 bytes split to 2 16-byte + * struct) */ -/* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { +/* rx_tpa_start_v3_cmpl (size:128b/16B) */ +struct rx_tpa_start_v3_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -6046,27 +7385,33 @@ struct rx_tpa_end_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_END_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V3_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V3_CMPL_TYPE_SFT 0 /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. + * RX L2 TPA Start V3 completion: + * Completion at the beginning of a TPA operation. * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in Thor2 and later chips. */ - #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_END_CMPL_TYPE_LAST \ - RX_TPA_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_END_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 \ + UINT32_C(0x19) + #define RX_TPA_START_V3_CMPL_TYPE_LAST \ + RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 + #define RX_TPA_START_V3_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V3_CMPL_FLAGS_SFT 6 /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_START_V3_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -6075,14 +7420,14 @@ struct rx_tpa_end_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* * IOC/Jumbo: @@ -6091,7 +7436,7 @@ struct rx_tpa_end_cmpl { * Placement. Subsequent packets will be placed such that each * packet starts at the beginning of an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ (UINT32_C(0x4) << 7) /* * GRO/Jumbo: @@ -6101,7 +7446,7 @@ struct rx_tpa_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -6112,7 +7457,7 @@ struct rx_tpa_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) /* * IOC/Header-Data Separation: @@ -6121,149 +7466,625 @@ struct rx_tpa_end_cmpl { * packet will be placed such that each packet starts at the * beginning of an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS \ (UINT32_C(0x7) << 7) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS - /* unused is 1 b */ - #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400) + #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) /* * This bit is '1' if metadata has been added to the end of the * packet in host memory. Metadata starts at the first 32B boundary - * after the end of the packet for regular and jumbo placement. - * It starts at the first 32B boundary after the end of the header - * for HDS placement. The length of the metadata is indicated in the + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the * metadata itself. */ - #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) + #define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK \ UINT32_C(0xf000) - #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_SFT 12 /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. */ uint32_t opaque; + uint16_t rss_hash_type_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t agg_bufs_v1; - /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. - */ - #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V3_CMPL_V1 UINT32_C(0x1) + /* unused1 is 6 b. */ + #define RX_TPA_START_V3_CMPL_UNUSED1_MASK UINT32_C(0x7e) + #define RX_TPA_START_V3_CMPL_UNUSED1_SFT 1 /* - * This value is the number of aggregation buffers that follow this - * entry in the completion ring that are a part of this aggregation - * packet. - * If the value is zero, then the packet is completely contained - * in the buffer space provided in the aggregation start completion. + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. + * * 1: The RSS hash was computed over source IP address and + * destination IP address of inner IP header. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 4: The RSS hash was computed over source IP address of the inner + * IP header. + * * 5: The RSS hash was computed over destination IP address of the + * inner IP header. + * * 6: The RSS hash was computed over source IP address of the outer + * IP header. Note: For non-tunneled packets, this value is not + * applicable + * * 7: The RSS hash was computed over destination IP address of the + * outer IP header. + * Note: For non-tunneled packets, this value is not applicable. + * * 8: The RSS hash was computed over source IP address, destination + * IP address, and flow label of the inner IP header. + * Note: For packets without an inner IPv6 header, this value is not + * applicable. + * * 9: The RSS hash was computed over the flow label of the inner + * IP header. + * Note: For packets without an inner IPv6 header, this value + * is not applicable. + * * 10: The RSS hash was computed over source IP address, destination + * IP address, and flow label of the outer IP header. + * Note: For packets without an outer IPv6 header, this value is not + * applicable. + * * 11: The RSS hash was computed over the flow label of the outer + * IP header. Note: For packets without an outer IPv6 header, this + * value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported + * and enabled for TCP traffic only, then the values of + * tuple_extract_op corresponding to 4-tuples are only valid for TCP + * traffic */ - #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) - #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80) + #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_SFT 7 /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * - * A value of zero indicates an offset of 256 bytes. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - uint8_t payload_offset; - uint8_t agg_id; - /* unused2 is 1 b */ - #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + uint16_t agg_id; /* * This is the aggregation ID that the completion is associated * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ - #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) - #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + #define RX_TPA_START_V3_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V3_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V3_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V3_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_LAST \ + RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V3_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. */ - uint32_t tsdelta; + uint32_t rss_hash; } __rte_packed; /* - * Last 16 bytes of rx_tpa_end_cmpl. + * Last 16 bytes of RX L2 TPA Start V3 Completion Record * * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { - uint32_t tpa_dup_acks; +/* rx_tpa_start_v3_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v3_cmpl_hi { + uint32_t flags2; /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + #define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * This value is the valid when TPA completion is active. It - * indicates the length of the longest segment of the TPA operation - * for LRO mode and the length of the first segment in GRO mode. - * - * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used - * to indicate MSS size to the stack. + * This indicates that the TCP, UDP or ICMP checksum was calculated + * for the inner packet and that the l4_cs_error field indicates if + * there was an error. */ - uint16_t tpa_seg_len; - /* unused4 is 16 b */ - uint16_t unused3; - uint16_t errors_v2; + #define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define RX_TPA_END_CMPL_ERRORS_SFT 1 + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as - * invalid. + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 - /* - * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + #define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE \ + UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4 */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4 \ + (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6 */ + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 \ + (UINT32_C(0x1) << 10) + #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_LAST \ + RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x800) + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_V3_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_START_V3_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_START_V3_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for the packetThe packet should be treated as + * invalid. + */ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. + */ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V3_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V3_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V3_CMPL_METADATA0_PRI_SFT 13 + /* + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. + * + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. + */ + uint32_t hdr_offsets; +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl (size:128b/16B) */ +struct rx_tpa_end_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B + */ + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_END_CMPL_TYPE_LAST \ + RX_TPA_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* When set, this bit indicates that the timestamp field is valid. */ + #define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. + */ + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + /* + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t agg_bufs_v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. + */ + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; + /* + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t payload_offset; + uint8_t agg_id; + /* unused2 is 1 b */ + #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + /* + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. + */ + uint32_t tsdelta; +} __rte_packed; + +/* + * Last 16 bytes of rx_tpa_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + /* + * This value is the valid when TPA completion is active. It + * indicates the length of the longest segment of the TPA operation + * for LRO mode and the length of the first segment in GRO mode. + * + * This value may be used by GRO software to re-construct the original + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used + * to indicate MSS size to the stack. + */ + uint16_t tpa_seg_len; + /* + * The lower 16b of the timestamp of the last packet added to the + * aggregation. Only valid when flags.timestamp_valid is set. + */ + uint16_t timestamp_lower; + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_TPA_END_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. + */ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* + * This error occurs when there is a fatal HW problem in + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ @@ -6283,8 +8104,11 @@ struct rx_tpa_end_cmpl_hi { (UINT32_C(0x4) << 1) #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR - /* unused5 is 16 b */ - uint16_t unused_4; + /* + * The upper 16b of the timestamp of the last packet added to the + * aggregation. Only valid when flags.timestamp_valid is set. + */ + uint16_t timestamp_upper; /* * This is the opaque value that was completed for the TPA start * completion that corresponds to this TPA end completion. @@ -6961,7 +8785,7 @@ struct rx_tpa_v2_abuf_cmpl { #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 /* - * RX TPA Aggregation Buffer completion : + * RX TPA Aggregation Buffer completion: * Completion of an L2 aggregation buffer in support of * TPA packet completion. Length = 16B */ @@ -7011,7 +8835,7 @@ struct rx_abuf_cmpl { #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) #define RX_ABUF_CMPL_TYPE_SFT 0 /* - * RX Aggregation Buffer completion : + * RX Aggregation Buffer completion: * Completion of an L2 aggregation buffer in support of * TPA, HDS, or Jumbo packet completion. Length = 16B */ @@ -7462,9 +9286,37 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \ UINT32_C(0x42) + /* + * An event from firmware indicating who has been selected as the + * PHC Master or secondary. Also indicates the last time a failover + * happens. Event will also be sent when PHC rolls over. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE \ + UINT32_C(0x43) + /* + * An event from firmware showing the last PPS timestamp that has been + * latched. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + /* + * An event from firmware indicating that an error has occurred. + * The driver should log the event so that an administrator can be + * aware that a problem has occurred that may need attention. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + /* + * An event from firmware indicating that the programmed pacing + * threshold for the doorbell global FIFO has been crossed. The driver + * needs to take appropriate action to pace the doorbells when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \ + UINT32_C(0x46) /* Maximum Registrable event id. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ - UINT32_C(0x43) + UINT32_C(0x47) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -7757,6 +9609,9 @@ struct hwrm_async_event_cmpl_dcb_config_change { /* APP configuration change */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ UINT32_C(0x4) + /* DSCP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \ + UINT32_C(0x8) uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -8127,15 +9982,15 @@ struct hwrm_async_event_cmpl_reset_notify { #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 /* * 8-lsb timestamp (100-msec resolution) - * The Minimum time required for the Firmware readiness after sending this - * notification to the driver instances. + * The Minimum time required for the Firmware readiness after sending + * this notification to the driver instances. */ uint8_t timestamp_lo; /* * 16-lsb timestamp (100-msec resolution) * The Maximum Firmware Reset bail out value in the order of 100 - * milli seconds. The driver instances will use this value to re-initiate the - * registration process again if the core firmware didn’t set the ready + * milliseconds. The driver instances will use this value to reinitiate + * the registration process again if the core firmware didn’t set the * state bit. */ uint16_t timestamp_hi; @@ -8179,10 +10034,17 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* - * Minimum time before driver should attempt access - units 100ms ticks. + * Minimum time before driver should attempt access - units 100ms + * ticks. * Range 0-65535 */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ @@ -8319,7 +10181,7 @@ struct hwrm_async_event_cmpl_ring_monitor_msg { /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* - * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl + * Event specific data. If ring_type_disabled indicates a tx, rx or cmpl * then this field will indicate the ring id. */ uint32_t event_data1; @@ -8771,6 +10633,17 @@ struct hwrm_async_event_cmpl_vf_cfg_change { HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE /* Event specific data */ uint32_t event_data2; + /* + * This value indicates the VF ID of the VF whose configuration + * is changing if this async. event is sent to the parent PF. + * The firmware supports sending this to the parent PF if the + * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1. + * This value is undefined when the async. event is sent to the + * VF. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -9663,6 +11536,298 @@ struct hwrm_async_event_cmpl_echo_request { uint32_t event_data1; } __rte_packed; +/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ +struct hwrm_async_event_cmpl_phc_update { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async event is used to notify driver of changes + * in PHC master. Only one master function can configure + * PHC. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE \ + UINT32_C(0x43) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE + /* Event specific data */ + uint32_t event_data2; + /* This field provides the current master function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT \ + 0 + /* This field provides the current secondary function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT \ + 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates to the driver the type of PHC event. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK \ + UINT32_C(0xf) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT \ + 0 + /* + * Indicates PHC Master selection event. The master fid is + * specified in event_data2.phc_master_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER \ + UINT32_C(0x1) + /* + * Indicates PHC Secondary selection event. The secondary fid is + * specified in event_data2.phc_sec_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY \ + UINT32_C(0x2) + /* + * Indicates PHC failover event. Failover happens from + * event_data2.phc_master_fid to event_data2.phc_sec_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER \ + UINT32_C(0x3) + /* + * Indicates that the 64bit Real time clock upper 16bits + * have been updated due to PHC rollover. The updated + * upper 16bits is in event_data1.phc_time_msb + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE + /* + * This field provides the upper 16bits of the 64bit real + * time clock. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT \ + 4 +} __rte_packed; + +/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ +struct hwrm_async_event_cmpl_pps_timestamp { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message can be used to inform + * driver of the latest PPS timestamp that has been latched. + * When driver enables PPS event, Firmware will generate + * PPS timestamps every second, Firmware informs driver + * of this timestamp through the async event. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP + /* Event specific data */ + uint32_t event_data2; + /* Indicates the PPS event type */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \ + UINT32_C(0x1) + /* This is an internal event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \ + UINT32_C(0x0) + /* This is an external event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL + /* + * Indicates the pin number on which the event is + * received. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \ + UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \ + 1 + /* + * Contains bits[47:32] of the upper PPS timestamp. + * Lower 32 bits are in event_data1. Together they + * provide the 48 bit PPS timestamp. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \ + 4 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Contains the lower 32 bits of the PPS timestamp. */ + uint32_t event_data1; + /* Contains the lower 32 bit PPS timestamp */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * Indicates the type of error being reported. See section on Error + * Report event error_types for details on each error. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_doorbell_pacing_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_doorbell_pacing_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the driver + * that the programmable pacing threshold for the doorbell FIFO is + * reached. The driver will take appropriate action to pace the + * doorbells when this async event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD \ + UINT32_C(0x46) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -9833,6 +11998,514 @@ struct hwrm_async_event_cmpl_hwrm_error { UINT32_C(0x1) } __rte_packed; +/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_base { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* Reserved */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \ + UINT32_C(0x0) + /* + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) + /* + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + /* + * Indicates the NIC's temperature has crossed one of the thermal + * thresholds. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_pause_storm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_invalid_signal { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the TSIO pin on which invalid signal is detected. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_thermal { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Current temperature. In Celsius */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT \ + 0 + /* + * The temperature setting of the threshold that was just crossed. + * In Celsius + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT \ + 8 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was thermal event. The type will be specified in the + * field threshold_type. event_data2 will contain the current + * temperature and the configured value for the threshold that + * was just crossed. The threshold values are lower thresholds, + * so the event will trigger with an active flag when the + * temperature is on an increasing trajectory. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT + /* The specific type of thermal threshold error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK \ + UINT32_C(0x700) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT \ + 8 + /* Warning thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN \ + (UINT32_C(0x0) << 8) + /* Critical thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL \ + (UINT32_C(0x1) << 8) + /* Fatal thermal threshold was crossed */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL \ + (UINT32_C(0x2) << 8) + /* + * Thermal shutdown threshold was crossed and a shutdown is + * imminent. This event will not occur if self shutdown + * is disabled. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN \ + (UINT32_C(0x3) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN + /* + * Indicates if the thermal crossing occurs while the temperature is + * increasing or decreasing. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR \ + UINT32_C(0x800) + /* Threshold is crossed while the temperature is falling. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING \ + (UINT32_C(0x0) << 11) + /* Threshold is crossed while the temperature is rising. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING \ + (UINT32_C(0x1) << 11) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -10651,6 +13324,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -10800,7 +13485,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -10870,7 +13558,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11234,7 +13922,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11337,6 +14031,103 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \ UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that core firmware supports + * NPAR 1.2 on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \ + UINT32_C(0x10000) + /* When this bit is '1', it indicates that PTM feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \ + UINT32_C(0x20000) + /* When this bit is '1', it indicates that PPS feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \ + UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that VF config. change + * async event is supported on the parent PF if the async. + * event is registered by the PF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \ + UINT32_C(0x80000) + /* + * When this bit is '1', the NIC supports configuration of + * partition_min_bw and partition_max_bw. Configuration of a + * minimum guaranteed bandwidth is only supported if the + * min_bw_supported flag is also set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \ + UINT32_C(0x100000) + /* + * When this bit is '1', the FW supports configuration of + * PCP and TPID values of the default VLAN. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \ + UINT32_C(0x200000) + /* When this bit is '1', it indicates that HW and FW support KTLS. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \ + UINT32_C(0x400000) + /* + * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG + * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions + * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive + * rate control. Configuration of a minimum guaranteed bandwidth + * is only supported if the min_bw_supported flag is also set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \ + UINT32_C(0x800000) + /* + * When this bit is '1', the firmware supports enforcement of + * minimum guaranteed bandwidth. A minimum guaranteed bandwidth + * could be configured for a partition or for an endpoint. Firmware + * only sets this flag if one or both of the ep_rate_control and + * partition_bw_supported flags are set. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED \ + UINT32_C(0x1000000) + /* + * When this bit is '1', HW supports TX coalesced completion + * records. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1', it indicates the FW has full support + * for all backing store types with the BACKING_STORE_CFG/QCFG + * V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates the FW forces to use the + * BACKING_STORE_CFG/QCFG V2 APIs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that FW will support a single + * 64bit real time clock for PTP. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting Doorbell Pacing. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED \ + UINT32_C(0x20000000) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting HW based doorbell drop recovery. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED \ + UINT32_C(0x40000000) + /* + * When this bit is '1', it indicates the driver can disable the CQ + * overflow detection and can also skip the index updates for CQ. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED \ + UINT32_C(0x80000000) /* The maximum number of SCHQs supported by this device. */ uint8_t max_schqs; uint8_t mpc_chnls_cap; @@ -11370,13 +14161,78 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint32_t flags_ext2; + /* + * When this bit is '1', it indicates that FW will support + * timestamping on all RX packets, not just PTP type packets. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED \ + UINT32_C(0x1) + /* When this bit is '1', it indicates that HW and FW support QUIC. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \ + UINT32_C(0x2) + uint16_t tunnel_disable_flag; + /* + * When this bit is '1', it indicates that the VXLAN parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the NGE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates that the NVGRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates that the L2GRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that the GRE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the IPINIP parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates that the MPLS parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the PPPOE parsing + * is disabled in hardware + */ + #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \ + UINT32_C(0x80) uint8_t unused_1; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -11427,7 +14283,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:768b/96B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11573,6 +14429,14 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \ UINT32_C(0x2000) + /* + * This flag indicates RDMA support for child VFS of + * a physical function. + * If set to 1, RoCE is supported on all child VFs. + * If set to 0, RoCE is disabled on all child VFs. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \ + UINT32_C(0x4000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -11616,12 +14480,15 @@ struct hwrm_func_qcfg_output { /* The allocated number of vnics to the function. */ uint16_t alloc_vnics; /* - * The maximum transmission unit of the function. - * If the reported mtu value is non-zero then it will used for the - * rings allocated on this function. otherwise the default + * The maximum transmission unit of the function + * configured by the admin pf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default * value is used if ring MTU is not specified. + * The driver cannot use any MTU bigger than this value + * if it is non-zero. */ - uint16_t mtu; + uint16_t admin_mtu; /* * The maximum receive unit of the function. * For vnics allocated on this function, this default @@ -11645,6 +14512,8 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) /* Network Partitioning 2.0 */ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Network Partitioning 1.2 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5) /* Unknown */ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ UINT32_C(0xff) @@ -11668,11 +14537,9 @@ struct hwrm_func_qcfg_output { uint16_t dflt_vnic_id; uint16_t max_mtu_configured; /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates the minimum bandwidth is not - * configured. + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. */ uint32_t min_bw; /* The bandwidth value. */ @@ -11706,7 +14573,7 @@ struct hwrm_func_qcfg_output { /* Value is in Gb or GB (base 10). */ #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ + /* Value is in 1/100th of a percentage of link bandwidth. */ #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ @@ -11715,11 +14582,9 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates that the maximum bandwidth is not - * configured. + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. */ uint32_t max_bw; /* The bandwidth value. */ @@ -11753,7 +14618,7 @@ struct hwrm_func_qcfg_output { /* Value is in Gb or GB (base 10). */ #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ + /* Value is in 1/100th of a percentage of link bandwidth. */ #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ @@ -11922,7 +14787,98 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ UINT32_C(0x10) - uint8_t unused_2[6]; + uint8_t unused_2[3]; + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. + * The format of this field is defined to match min_bw, even though + * the partition minimum rate is always specified as a percentage. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Always percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Bandwidth value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though + * the partition bandwidth must be specified as a percentage. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Always a percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum transmission unit of the function + * configured by the host pf/vf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default + * value is used if ring MTU is not specified. + */ + uint16_t host_mtu; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11938,7 +14894,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:768b/96B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -12204,10 +15160,10 @@ struct hwrm_func_cfg_input { UINT32_C(0x40000000) uint32_t enables; /* - * This bit must be '1' for the mtu field to be + * This bit must be '1' for the admin_mtu field to be * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \ UINT32_C(0x1) /* * This bit must be '1' for the mru field to be @@ -12360,6 +15316,45 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \ UINT32_C(0x2000000) /* + * This bit must be '1' for the partition_min_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \ + UINT32_C(0x4000000) + /* + * This bit must be '1' for the partition_max_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \ + UINT32_C(0x8000000) + /* + * This bit must be '1' for the tpid field to be + * configured. This bit is only valid when dflt_vlan enable + * bit is set. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \ + UINT32_C(0x10000000) + /* + * This bit must be '1' for the host_mtu field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ + UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) + /* + * This field can be used by the admin PF to configure + * mtu of foster PFs. * The maximum transmission unit of the function. * The HWRM should make sure that the mtu of * the function does not exceed the mtu of the physical @@ -12372,7 +15367,7 @@ struct hwrm_func_cfg_input { * The HWRM should make sure that the mtu of each transmit * ring that is assigned to a function has a valid mtu. */ - uint16_t mtu; + uint16_t admin_mtu; /* * The maximum receive unit of the function. * The HWRM should make sure that the mru of @@ -12436,9 +15431,9 @@ struct hwrm_func_cfg_input { */ uint32_t dflt_ip_addr[4]; /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. */ uint32_t min_bw; /* The bandwidth value. */ @@ -12481,9 +15476,9 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. */ uint32_t max_bw; /* The bandwidth value. */ @@ -12703,6 +15698,115 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \ UINT32_C(0x200) + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. The sum of the + * minimum bandwidths for all partitions on a link must not exceed + * 100%. + * The format of this field is defined to match min_bw, even though + * it does not allow all the options for min_bw at this time. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though it + * does not allow all the options for max_bw at this time. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The TPID for the function for which default VLAN + * is configured. If the dflt_vlan is not specified + * with the TPID, FW returns error. If the TPID is + * not specified with dflt_vlan, the default TPID of + * 0x8100 will be used. This field is specified in + * network byte order. + */ + uint16_t tpid; + /* + * This field can be used by the host PF to configure + * mtu value. + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; uint8_t unused_0[4]; } __rte_packed; @@ -12727,6 +15831,33 @@ struct hwrm_func_cfg_output { uint8_t valid; } __rte_packed; +/* hwrm_func_cfg_cmd_err (size:64b/8B) */ +struct hwrm_func_cfg_cmd_err { + /* command specific error codes for the cmd_err field in hwrm_err_output */ + uint8_t code; + /* Unknown error. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The partition minimum bandwidth is out of range. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE \ + UINT32_C(0x1) + /* The minimum bandwidth is more than the maximum bandwidth. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX \ + UINT32_C(0x2) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for a partition. + */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED \ + UINT32_C(0x3) + /* Partition bandwidths must be specified as a percentage. */ + #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT \ + UINT32_C(0x4) + #define HWRM_FUNC_CFG_CMD_ERR_CODE_LAST \ + HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT + uint8_t unused_0[7]; +} __rte_packed; + /******************** * hwrm_func_qstats * ********************/ @@ -13271,6 +16402,22 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \ UINT32_C(0x80) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the vnic_rss_cfg's INVALID_PARAM error + * returned by firmware. Firmware returns error, if host driver + * configures the invalid hash_types bit combination for a given + * IP version. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ + UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -13832,7 +16979,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -13855,7 +17002,7 @@ struct hwrm_func_resource_qcaps_output { #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ UINT32_C(0x1) /* - * The PF driver should not reserve any resources for each VF until the + * The PF driver should not reserve any resources for each VF until * the VF interface is brought up. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ @@ -13907,6 +17054,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -13923,7 +17078,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13997,6 +17152,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14026,7 +17189,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14074,7 +17241,7 @@ struct hwrm_func_backing_store_qcaps_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ +/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14092,7 +17259,10 @@ struct hwrm_func_backing_store_qcaps_output { * this many QP context entries, even if RoCE will not be used. */ uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ + /* + * Maximum number of QP context entries that can be used for L2 and + * mid-path. + */ uint16_t qp_max_l2_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t qp_entry_size; @@ -14229,6 +17399,18 @@ struct hwrm_func_backing_store_qcaps_output { */ #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \ UINT32_C(0x20) + /* + * If this bit is '1' then the Tx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \ + UINT32_C(0x40) + /* + * If this bit is '1' then the Rx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \ + UINT32_C(0x80) /* * Specifies the doubleword offset of ctx_kind_initializer for this * context type. @@ -14273,8 +17455,32 @@ struct hwrm_func_backing_store_qcaps_output { * this count in `backing_store_cfg`. */ uint8_t tqm_fp_rings_count_ext; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Tx + * KTLS context type. + */ + uint8_t tkc_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Rx + * KTLS context type. + */ + uint8_t rkc_init_offset; + /* Tx KTLS context entry size in bytes. */ + uint16_t tkc_entry_size; + /* Rx KTLS context entry size in bytes. */ + uint16_t rkc_entry_size; + /* + * Maximum number of Tx KTLS context entries supported for this + * function. + */ + uint32_t tkc_max_entries; + /* + * Maximum number of Rx KTLS context entries supported for this + * function. + */ + uint32_t rkc_max_entries; /* Reserved for future. */ - uint8_t rsvd[5]; + uint8_t rsvd1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14343,7 +17549,7 @@ struct tqm_fp_ring_cfg { *******************************/ -/* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ +/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ struct hwrm_func_backing_store_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14503,6 +17709,18 @@ struct hwrm_func_backing_store_cfg_input { */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \ UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \ + UINT32_C(0x100000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -15521,6 +18739,105 @@ struct hwrm_func_backing_store_cfg_input { uint32_t tqm_ring10_num_entries; /* TQM ring page directory. */ uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries allocated. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries allocated. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Number of bytes allocated for each Tx KTLS context entry. */ + uint16_t tkc_entry_size; + /* Number of bytes allocated for each Rx KTLS context entry. */ + uint16_t rkc_entry_size; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G + /* Reserved for future. */ + uint8_t rsvd[2]; } __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -15581,7 +18898,7 @@ struct hwrm_func_backing_store_qcfg_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_func_backing_store_qcfg_output (size:2304b/288B) */ +/* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */ struct hwrm_func_backing_store_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15721,6 +19038,18 @@ struct hwrm_func_backing_store_qcfg_output { */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \ UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \ + UINT32_C(0x100000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -16304,338 +19633,2337 @@ struct hwrm_func_backing_store_qcfg_output { /* PBL pointer is physical start address. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 + /* MR/AV page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G + /* Timer page size and level. */ + uint8_t tim_pg_size_tim_lvl; + /* Timer PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 + /* Timer page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G + /* QP page directory. */ + uint64_t qpc_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* VNIC page directory. */ + uint64_t vnic_page_dir; + /* Stat page directory. */ + uint64_t stat_page_dir; + /* TQM slowpath page directory. */ + uint64_t tqm_sp_page_dir; + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* MR/AV page directory. */ + uint64_t mrav_page_dir; + /* Timer page directory. */ + uint64_t tim_page_dir; + /* Number of entries to reserve for QP1 */ + uint16_t qp_num_qp1_entries; + /* Number of entries to reserve for L2 */ + uint16_t qp_num_l2_entries; + /* Number of QPs. */ + uint32_t qp_num_entries; + /* Number of SRQs. */ + uint32_t srq_num_entries; + /* Number of entries to reserve for L2 */ + uint16_t srq_num_l2_entries; + /* Number of entries to reserve for L2 */ + uint16_t cq_num_l2_entries; + /* Number of CQs. */ + uint32_t cq_num_entries; + /* Number of entries to reserve for VNIC entries */ + uint16_t vnic_num_vnic_entries; + /* Number of entries to reserve for Ring table entries */ + uint16_t vnic_num_ring_table_entries; + /* Number of Stats. */ + uint32_t stat_num_entries; + /* Number of TQM slowpath entries. */ + uint32_t tqm_sp_num_entries; + /* Number of TQM ring 0 entries. */ + uint32_t tqm_ring0_num_entries; + /* Number of TQM ring 1 entries. */ + uint32_t tqm_ring1_num_entries; + /* Number of TQM ring 2 entries. */ + uint32_t tqm_ring2_num_entries; + /* Number of TQM ring 3 entries. */ + uint32_t tqm_ring3_num_entries; + /* Number of TQM ring 4 entries. */ + uint32_t tqm_ring4_num_entries; + /* Number of TQM ring 5 entries. */ + uint32_t tqm_ring5_num_entries; + /* Number of TQM ring 6 entries. */ + uint32_t tqm_ring6_num_entries; + /* Number of TQM ring 7 entries. */ + uint32_t tqm_ring7_num_entries; + /* + * If the MR/AV split reservation flag is not set, then this field + * represents the total number of MR plus AV entries. For versions + * of firmware that support the split reservation, when it is not + * specified half of the entries will be reserved for MRs and the + * other half for AVs. + * + * If the MR/AV split reservation flag is set, then this + * field is logically divided into two 16b fields. Bits `[31:16]` + * represents the `mr_num_entries` and bits `[15:0]` represents + * `av_num_entries`. The granularity of these values is defined by + * the `mrav_num_entries_unit` field returned by the + * `backing_store_qcaps` command. + */ + uint32_t mrav_num_entries; + /* Number of Timer entries. */ + uint32_t tim_num_entries; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G + uint8_t unused_1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as 1 + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_error_recovery_qcfg * + ****************************/ + + +/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ +struct hwrm_error_recovery_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ +struct hwrm_error_recovery_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this flag is set to 1, error recovery will be initiated + * through master function driver. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1) + /* + * When this flag is set to 1, error recovery will be performed + * through Co processor. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2) + /* + * Driver Polling frequency. This value is in units of 100msec. + * Typical value would be 10 to indicate 1sec. + * Drivers can poll FW health status, Heartbeat, reset_counter with + * this frequency. + */ + uint32_t driver_polling_freq; + /* + * This value is in units of 100msec. + * Typical value would be 30 to indicate 3sec. + * Master function wait period from detecting a fatal error to + * initiating reset. In this time period Master PF expects every + * active driver will detect fatal error. + */ + uint32_t master_func_wait_period; + /* + * This value is in units of 100msec. + * Typical value would be 50 to indicate 5sec. + * Normal function wait period from fatal error detection to + * polling FW health status. In this time period, drivers should not + * do any PCIe MMIO transaction and should not send any HWRM commands. + */ + uint32_t normal_func_wait_period; + /* + * This value is in units of 100msec. + * Typical value would be 20 to indicate 2sec. + * This field indicates that, master function wait period after chip + * reset. After this time, master function should reinitialize with + * FW. + */ + uint32_t master_func_wait_period_after_reset; + /* + * This value is in units of 100msec. + * Typical value would be 60 to indicate 6sec. + * This field is applicable to both master and normal functions. + * Even after chip reset, if FW status not changed to ready, + * then all the functions can poll for this much time and bailout. + */ + uint32_t max_bailout_time_after_reset; + /* + * FW health status register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates upper 30bits of the register address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_health_status_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \ + 2 + /* + * FW HeartBeat register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_heartbeat_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \ + 2 + /* + * FW reset counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t fw_reset_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \ + 2 + /* + * Reset Inprogress Register address for PFs. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t reset_inprogress_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \ + 2 + /* This field indicates the mask value for reset_inprogress_reg. */ + uint32_t reset_inprogress_reg_mask; + uint8_t unused_0[3]; + /* + * Array of registers and value count to reset the Chip + * Each array count has reset_reg, reset_reg_val, delay_after_reset + * in TLV format. Depending upon Chip type, number of reset registers + * will vary. Drivers have to write reset_reg_val in the reset_reg + * location in the same sequence in order to recover from a fatal + * error. + */ + uint8_t reg_array_cnt; + /* + * Reset register. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t reset_reg[16]; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2 + /* Value to be written in reset_reg to reset the controller. */ + uint32_t reset_reg_val[16]; + /* + * This value is in units of 1msec. + * Typical value would be 10 to indicate 10msec. + * Some of the operations like Core reset require delay before + * accessing PCIE MMIO register space. + * If this value is non-zero, drivers have to wait for + * this much time after writing reset_reg_val in reset_reg. + */ + uint8_t delay_after_reset[16]; + /* + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_echo_response * + ***************************/ + + +/* hwrm_func_echo_response_input (size:192b/24B) */ +struct hwrm_func_echo_response_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t event_data1; + uint32_t event_data2; +} __rte_packed; + +/* hwrm_func_echo_response_output (size:128b/16B) */ +struct hwrm_func_echo_response_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ + + +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. + */ + uint8_t num_pins; + /* Pin state */ + uint8_t state; + /* + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ + + +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the pin0_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the pin0_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the pin1_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the pin1_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) + /* + * This bit must be '1' for the pin2_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the pin2_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the pin3_state field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) + /* + * This bit must be '1' for the pin3_usage field to be + * configured. + */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_ptp_cfg * + *********************/ + + +/* hwrm_func_ptp_cfg_input (size:384b/48B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This bit must be '1' for ptp_set_time field to be configured. */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME \ + UINT32_C(0x40) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; + /* + * Allows driver to set the full 64bit time in FW. The upper 16 bits + * will be stored in FW and the lower 48bits will be programmed in + * PHC. Firmware will send a broadcast async event to all functions + * to indicate the programmed upper 16 bits. + */ + uint64_t ptp_set_time; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* KTLS Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX \ + UINT32_C(0x0) + /* KTLS Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX \ + UINT32_C(0x1) + /* QUIC Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX \ + UINT32_C(0x2) + /* QUIC Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX \ + UINT32_C(0x3) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_func_backing_store_cfg_v2 * + **********************************/ + + +/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ +struct hwrm_func_backing_store_cfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 - /* MR/AV page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G - /* Timer page size and level. */ - uint8_t tim_pg_size_tim_lvl; - /* Timer PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 - /* Timer page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G - /* QP page directory. */ - uint64_t qpc_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* VNIC page directory. */ - uint64_t vnic_page_dir; - /* Stat page directory. */ - uint64_t stat_page_dir; - /* TQM slowpath page directory. */ - uint64_t tqm_sp_page_dir; - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; - /* MR/AV page directory. */ - uint64_t mrav_page_dir; - /* Timer page directory. */ - uint64_t tim_page_dir; - /* Number of entries to reserve for QP1 */ - uint16_t qp_num_qp1_entries; - /* Number of entries to reserve for L2 */ - uint16_t qp_num_l2_entries; - /* Number of QPs. */ - uint32_t qp_num_entries; - /* Number of SRQs. */ - uint32_t srq_num_entries; - /* Number of entries to reserve for L2 */ - uint16_t srq_num_l2_entries; - /* Number of entries to reserve for L2 */ - uint16_t cq_num_l2_entries; - /* Number of CQs. */ - uint32_t cq_num_entries; - /* Number of entries to reserve for VNIC entries */ - uint16_t vnic_num_vnic_entries; - /* Number of entries to reserve for Ring table entries */ - uint16_t vnic_num_ring_table_entries; - /* Number of Stats. */ - uint32_t stat_num_entries; - /* Number of TQM slowpath entries. */ - uint32_t tqm_sp_num_entries; - /* Number of TQM ring 0 entries. */ - uint32_t tqm_ring0_num_entries; - /* Number of TQM ring 1 entries. */ - uint32_t tqm_ring1_num_entries; - /* Number of TQM ring 2 entries. */ - uint32_t tqm_ring2_num_entries; - /* Number of TQM ring 3 entries. */ - uint32_t tqm_ring3_num_entries; - /* Number of TQM ring 4 entries. */ - uint32_t tqm_ring4_num_entries; - /* Number of TQM ring 5 entries. */ - uint32_t tqm_ring5_num_entries; - /* Number of TQM ring 6 entries. */ - uint32_t tqm_ring6_num_entries; - /* Number of TQM ring 7 entries. */ - uint32_t tqm_ring7_num_entries; + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID /* - * If the MR/AV split reservation flag is not set, then this field - * represents the total number of MR plus AV entries. For versions - * of firmware that support the split reservation, when it is not - * specified half of the entries will be reserved for MRs and the - * other half for AVs. - * - * If the MR/AV split reservation flag is set, then this - * field is logically divided into two 16b fields. Bits `[31:16]` - * represents the `mr_num_entries` and bits `[15:0]` represents - * `av_num_entries`. The granularity of these values is defined by - * the `mrav_num_entries_unit` field returned by the - * `backing_store_qcaps` command. + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. */ - uint32_t mrav_num_entries; - /* Number of Timer entries. */ - uint32_t tim_num_entries; - /* TQM ring page size and level. */ - uint8_t tqm_ring8_pg_size_tqm_ring_lvl; - /* TQM ring PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and + * does not expect any backing store to be provided by the + * host driver. This mode provides minimal L2 functionality + * (e.g. limited L2 resources, no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Number of bytes allocated for each entry */ + uint16_t entry_size; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \ - 0 + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to * PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 - /* TQM ring page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \ - 4 + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G - uint8_t ring8_unused[3]; - /* Number of TQM ring entries. */ - uint32_t tqm_ring8_num_entries; - /* TQM ring page directory. */ - uint64_t tqm_ring8_page_dir; - /* TQM ring page size and level. */ - uint8_t tqm_ring9_pg_size_tqm_ring_lvl; - /* TQM ring PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \ - 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G + /* + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | Count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | + */ + uint8_t subtype_valid_cnt; + /* + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; +} __rte_packed; + +/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_func_backing_store_qcfg_v2 * + ***********************************/ + + +/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcfg_v2_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \ + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ \ UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID /* - * PBL pointer points to PDE table with each entry pointing to - * PTE tables. + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \ + uint16_t instance; + uint8_t rsvd[4]; +} __rte_packed; + +/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ +struct hwrm_func_backing_store_qcfg_v2_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Type of backing store to be configured. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 - /* TQM ring page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \ - 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G - uint8_t ring9_unused[3]; - /* Number of TQM ring entries. */ - uint32_t tqm_ring9_num_entries; - /* TQM ring page directory. */ - uint64_t tqm_ring9_page_dir; - /* TQM ring page size and level. */ - uint8_t tqm_ring10_pg_size_tqm_ring_lvl; - /* TQM ring PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \ + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \ - 0 + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID + /* + * Instance of the backing store type. It is zero-based, + * which means "0" indicates the first instance. For backing + * stores with single instance only, leave this field to 0. + */ + uint16_t instance; + /* Control flags. */ + uint32_t flags; + /* Page directory. */ + uint64_t page_dir; + /* Number of entries */ + uint32_t num_entries; + /* Page size and pbl level. */ + uint8_t page_size_pbl_level; + /* PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 \ UINT32_C(0x1) /* * PBL pointer points to PDE table with each entry pointing to * PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 - /* TQM ring page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 + /* Page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \ - 4 + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G - uint8_t ring10_unused[3]; - /* Number of TQM ring entries. */ - uint32_t tqm_ring10_num_entries; - /* TQM ring page directory. */ - uint64_t tqm_ring10_page_dir; - uint8_t unused_1[7]; + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G + /* + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | + */ + uint8_t subtype_valid_cnt; + uint8_t rsvd[2]; + /* + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; + uint8_t rsvd2[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as 1 - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. */ uint8_t valid; } __rte_packed; -/**************************** - * hwrm_error_recovery_qcfg * - ****************************/ +/************************************ + * hwrm_func_backing_store_qcaps_v2 * + ************************************/ -/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ -struct hwrm_error_recovery_qcfg_input { +/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ +struct hwrm_func_backing_store_qcaps_v2_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16664,11 +21992,72 @@ struct hwrm_error_recovery_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t unused_0[8]; + /* Type of backing store to be queried. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM \ + UINT32_C(0xf) + /* Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC \ + UINT32_C(0x13) + /* Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID + uint8_t rsvd[6]; } __rte_packed; -/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ -struct hwrm_error_recovery_qcfg_output { +/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ +struct hwrm_func_backing_store_qcaps_v2_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16677,379 +22066,473 @@ struct hwrm_error_recovery_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Type of backing store to be queried. */ + uint16_t type; + /* Queue pair. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP \ + UINT32_C(0x0) + /* Shared receive queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ \ + UINT32_C(0x1) + /* Completion queue. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ \ + UINT32_C(0x2) + /* Virtual NIC. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC \ + UINT32_C(0x3) + /* Statistic context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT \ + UINT32_C(0x4) + /* Slow-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING \ + UINT32_C(0x5) + /* Fast-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING \ + UINT32_C(0x6) + /* Memory Region and Memory Address Vector Context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV \ + UINT32_C(0xe) + /* TIM. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM \ + UINT32_C(0xf) + /* KTLS Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC \ + UINT32_C(0x13) + /* KTLS Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC \ + UINT32_C(0x14) + /* Mid-path TQM ring. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING \ + UINT32_C(0x15) + /* SQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW \ + UINT32_C(0x16) + /* RQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW \ + UINT32_C(0x17) + /* SRQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW \ + UINT32_C(0x18) + /* CQ Doorbell shadow region. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW \ + UINT32_C(0x19) + /* QUIC Tx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC \ + UINT32_C(0x1a) + /* QUIC Rx key context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC \ + UINT32_C(0x1b) + /* Invalid type. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID \ + UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_LAST \ + HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID + /* Number of bytes per backing store entry. */ + uint16_t entry_size; + /* Control flags. */ uint32_t flags; /* - * When this flag is set to 1, error recovery will be initiated - * through master function driver. + * When set, it indicates the context type should be initialized + * with the “ctx_init_value” at the specified offset. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT \ + UINT32_C(0x1) + /* When set, it indicates the context type is valid. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID \ + UINT32_C(0x2) /* - * When this flag is set to 1, error recovery will be performed - * through Co processor. + * When set, it indicates the region for this type is not a regular + * context memory but a driver managed memory that is created, + * initialized and managed by the driver. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY \ + UINT32_C(0x4) /* - * Driver Polling frequency. This value is in units of 100msec. - * Typical value would be 10 to indicate 1sec. - * Drivers can poll FW health status, Heartbeat, reset_counter with - * this frequency. + * Bit map of the valid instances associated with the + * backing store type. */ - uint32_t driver_polling_freq; + uint32_t instance_bit_map; /* - * This value is in units of 100msec. - * Typical value would be 30 to indicate 3sec. - * Master function wait period from detecting a fatal error to - * initiating reset. In this time period Master PF expects every - * active driver will detect fatal error. + * Initializer to be used by drivers to initialize context memory + * to ensure context subsystem flags an error for an attack before + * the first time context load. */ - uint32_t master_func_wait_period; + uint8_t ctx_init_value; /* - * This value is in units of 100msec. - * Typical value would be 50 to indicate 5sec. - * Normal function wait period from fatal error detection to - * polling FW health status. In this time period, drivers should not - * do any PCIe MMIO transaction and should not send any HWRM commands. + * Specifies the doubleword offset of ctx_init_value for this + * context type. */ - uint32_t normal_func_wait_period; + uint8_t ctx_init_offset; /* - * This value is in units of 100msec. - * Typical value would be 20 to indicate 2sec. - * This field indicates that, master function wait period after chip - * reset. After this time, master function should reinitialize with - * FW. + * Some backing store types, e.g., TQM rings, require the number + * of entries to be a multiple of this value to prevent any + * resource allocation limitations. If not applicable, leave + * this field with "0". */ - uint32_t master_func_wait_period_after_reset; + uint8_t entry_multiple; + uint8_t rsvd; + /* Maximum number of backing store entries supported for this type. */ + uint32_t max_num_entries; /* - * This value is in units of 100msec. - * Typical value would be 60 to indicate 6sec. - * This field is applicable to both master and normal functions. - * Even after chip reset, if FW status not changed to ready, - * then all the functions can poll for this much time and bailout. + * Minimum number of backing store entries required for this type. + * This field is only valid for some backing store types, e.g., + * TQM rings. If not applicable, leave this field with "0". */ - uint32_t max_bailout_time_after_reset; + uint32_t min_num_entries; /* - * FW health status register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates upper 30bits of the register address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * Next valid backing store type. If current type queried is already + * the last valid type, firmware must set this field to invalid type. */ - uint32_t fw_health_status_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \ - 0 + uint16_t next_valid_type; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * This field counts how many split entries contain valid data. + * Below is the table that maps the count value: + * | count | Indication | + * | ----- | -------------------------------------------------- | + * | 0 | None of the split entries has valid data. | + * | 1 | Only "split_entry_0" contains valid data. | + * | 2 | Only "split_entry_0" and "1" have valid data. | + * | 3 | Only "split_entry_0", "1" and "2" have valid data. | + * | 4 | All four split entries have valid data. | */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint8_t subtype_valid_cnt; + uint8_t rsvd2; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * Split entry #0. Note that the four split entries (as a group) + * must be cast to a type-specific data structure first before + * accessing it! Below is the table that maps a backing store + * type to the associated split entry casting data structure. + * | Type | Split Entry Casting Data Structure | + * | ---- | -------------------------------------------------- | + * | QPC | qpc_split_entries | + * | SRQ | srq_split_entries | + * | CQ | cq_split_entries | + * | VINC | vnic_split_entries | + * | MRAV | marv_split_entries | + */ + uint32_t split_entry_0; + /* Split entry #1. */ + uint32_t split_entry_1; + /* Split entry #2. */ + uint32_t split_entry_2; + /* Split entry #3. */ + uint32_t split_entry_3; + uint8_t rsvd3[3]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_func_dbr_pacing_cfg * + ****************************/ + + +/* hwrm_func_dbr_pacing_cfg_input (size:320b/40B) */ +struct hwrm_func_dbr_pacing_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint16_t seq_id; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * Drivers have to map appropriate window to access this - * register. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \ - 2 + uint16_t target_id; /* - * FW HeartBeat register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t fw_heartbeat_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \ - 0 + uint64_t resp_addr; + uint8_t flags; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * This bit must be '1' to enable DBR NQ events. The NQ ID to + * receive the events must be specified in the primary_nq_id + * field. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE \ + UINT32_C(0x1) + /* This bit must be '1' to disable DBR NQ events. */ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE \ + UINT32_C(0x2) + uint8_t unused_0[7]; + uint32_t enables; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * This bit must be '1' for the primary_nq_id field to be + * configured. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID \ UINT32_C(0x1) /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * This bit must be '1' for the pacing_threshold field to be + * configured. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID \ UINT32_C(0x2) /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * Specify primary function’s NQ ID to receive the doorbell pacing + * threshold crossing events. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \ - 2 + uint32_t primary_nq_id; /* - * FW reset counter. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * Specify pacing threshold value, as a percentage of the max + * doorbell FIFO depth. The range is 1 to 36. */ - uint32_t fw_reset_cnt_reg; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \ - 0 + uint32_t pacing_threshold; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_dbr_pacing_cfg_output (size:128b/16B) */ +struct hwrm_func_dbr_pacing_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_func_dbr_pacing_qcfg * + *****************************/ + + +/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint16_t seq_id; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \ - 2 + uint16_t target_id; /* - * Reset Inprogress Register address for PFs. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t reset_inprogress_reg; + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ +struct hwrm_func_dbr_pacing_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t flags; + /* When this bit is '1', it indicates DBR NQ events are enabled. */ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED \ + UINT32_C(0x1) + uint8_t unused_0[7]; + /* + * The Doorbell global FIFO occupancy register. This field should be + * used by the driver and user library in the doorbell pacing + * algorithm. Lower 2 bits indicates address space location and upper + * 30 bits indicates upper 30bits of the register address. A value of + * 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t dbr_stat_db_fifo_reg; /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT \ 0 /* * If value is 0, this register is located in PCIe config space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) /* * If value is 1, this register is located in GRC address space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) /* * If value is 2, this register is located in first BAR address * space. Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) /* * If value is 3, this register is located in second BAR address * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST \ + HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK \ UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SFT \ 2 - /* This field indicates the mask value for reset_inprogress_reg. */ - uint32_t reset_inprogress_reg_mask; - uint8_t unused_0[3]; - /* - * Array of registers and value count to reset the Chip - * Each array count has reset_reg, reset_reg_val, delay_after_reset - * in TLV format. Depending upon Chip type, number of reset registers - * will vary. Drivers have to write reset_reg_val in the reset_reg - * location in the same sequence in order to recover from a fatal - * error. - */ - uint8_t reg_array_cnt; - /* - * Reset register. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. - */ - uint32_t reset_reg[16]; - /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0 /* - * If value is 0, this register is located in PCIe config space. - * Drivers have to map appropriate window to access this - * register. - */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \ - UINT32_C(0x0) - /* - * If value is 1, this register is located in GRC address space. - * Drivers have to map appropriate window to access this - * register. + * This field indicates the mask value for dbr_stat_db_fifo_reg + * to get the high watermark for doorbell FIFO. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \ - UINT32_C(0x1) + uint32_t dbr_stat_db_fifo_reg_watermark_mask; /* - * If value is 2, this register is located in first BAR address - * space. Drivers have to map appropriate window to access this - * register. + * This field indicates the shift value for dbr_stat_db_fifo_reg + * to get the high watermark for doorbell FIFO. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \ - UINT32_C(0x2) + uint8_t dbr_stat_db_fifo_reg_watermark_shift; + uint8_t unused_1[3]; /* - * If value is 3, this register is located in second BAR address - * space. Drivers have to map appropriate window to access this - * register. + * This field indicates the mask value for dbr_stat_db_fifo_reg + * to get the amount of room left for doorbell FIFO. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \ - UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 - /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \ - UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2 - /* Value to be written in reset_reg to reset the controller. */ - uint32_t reset_reg_val[16]; + uint32_t dbr_stat_db_fifo_reg_fifo_room_mask; /* - * This value is in units of 1msec. - * Typical value would be 10 to indicate 10msec. - * Some of the operations like Core reset require delay before - * accessing PCIE MMIO register space. - * If this value is non-zero, drivers have to wait for - * this much time after writing reset_reg_val in reset_reg. + * This field indicates the shift value for dbr_stat_db_fifo_reg + * to get the amount of room left for doorbell FIFO. */ - uint8_t delay_after_reset[16]; + uint8_t dbr_stat_db_fifo_reg_fifo_room_shift; + uint8_t unused_2[3]; /* - * Error recovery counter. - * Lower 2 bits indicates address space location and upper 30 bits - * indicates actual address. - * A value of 0xFFFF-FFFF indicates this register does not exist. + * DBR_REG_AEQ_ARM register. This field should be used by the driver + * to rearm the interrupt for regeneration of a notification to the + * host from the hardware when the global doorbell occupancy threshold + * is above the threshold value. Lower 2 bits indicates address space + * location and upper 30 bits indicates upper 30bits of the register + * address. A value of 0xFFFF-FFFF indicates this register does not + * exist. */ - uint32_t err_recovery_cnt_reg; + uint32_t dbr_throttling_aeq_arm_reg; /* Lower 2 bits indicates address space location. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT \ 0 /* * If value is 0, this register is located in PCIe config space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG \ UINT32_C(0x0) /* * If value is 1, this register is located in GRC address space. * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC \ UINT32_C(0x1) /* * If value is 2, this register is located in first BAR address * space. Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 \ UINT32_C(0x2) /* * If value is 3, this register is located in second BAR address * space. Drivers have to map appropriate window to access this + * Drivers have to map appropriate window to access this * register. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 \ UINT32_C(0x3) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ - HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST \ + HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 /* Upper 30bits of the register address. */ - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK \ UINT32_C(0xfffffffc) - #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT \ 2 - uint8_t unused_1[3]; + /* + * This field indicates the value to be written for + * dbr_throttling_aeq_arm_reg register. + */ + uint8_t dbr_throttling_aeq_arm_reg_val; + uint8_t unused_3[7]; + /* + * Specifies primary function’s NQ ID. + * A value of 0xFFFF indicates NQ ID is invalid. + */ + uint32_t primary_nq_id; + /* + * Specifies the pacing threshold value, as a percentage of the + * max doorbell FIFO depth. The range is 1 to 100. + */ + uint32_t pacing_threshold; + uint8_t unused_4[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_func_echo_response * - ****************************/ +/**************************************** + * hwrm_func_dbr_pacing_broadcast_event * + ****************************************/ -/* hwrm_func_echo_response_input (size:192b/24B) */ -struct hwrm_func_echo_response_input { +/* hwrm_func_dbr_pacing_broadcast_event_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_broadcast_event_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17065,10 +22548,10 @@ struct hwrm_func_echo_response_input { uint16_t seq_id; /* * The target ID of the command: - * 0x0-0xFFF8 - The function ID - * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * 0xFFFD - Reserved for user-space HWRM interface - * 0xFFFF - HWRM + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ uint16_t target_id; /* @@ -17078,12 +22561,10 @@ struct hwrm_func_echo_response_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t event_data1; - uint32_t event_data2; } __rte_packed; -/* hwrm_func_echo_response_output (size:128b/16B) */ -struct hwrm_func_echo_response_output { +/* hwrm_func_dbr_pacing_broadcast_event_output (size:128b/16B) */ +struct hwrm_func_dbr_pacing_broadcast_event_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17097,8 +22578,9 @@ struct hwrm_func_echo_response_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -18766,7 +24248,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) /* Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) - /* Both Half and Full dupex will be requested. */ + /* Both Half and Full duplex will be requested. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \ HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH @@ -19603,20 +25085,44 @@ struct hwrm_port_phy_qcfg_output { /* 1G_baseCX */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ UINT32_C(0x1b) - /* 100G_BASECR4 */ + /* 200G_BASECR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \ UINT32_C(0x1c) - /* 100G_BASESR4 */ + /* 200G_BASESR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \ UINT32_C(0x1d) - /* 100G_BASELR4 */ + /* 200G_BASELR4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \ UINT32_C(0x1e) - /* 100G_BASEER4 */ + /* 200G_BASEER4 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \ UINT32_C(0x1f) + /* 50G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR \ + UINT32_C(0x20) + /* 50G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR \ + UINT32_C(0x21) + /* 50G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR \ + UINT32_C(0x22) + /* 50G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER \ + UINT32_C(0x23) + /* 100G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 \ + UINT32_C(0x24) + /* 100G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 \ + UINT32_C(0x25) + /* 100G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 \ + UINT32_C(0x26) + /* 100G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 \ + UINT32_C(0x27) #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -19693,7 +25199,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ uint8_t parallel_detect; @@ -19702,7 +25208,7 @@ struct hwrm_port_phy_qcfg_output { * the speed of the link partner. * * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable + * device is connected to a link partner that is not capable * of autonegotiation. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) @@ -20110,7 +25616,7 @@ struct hwrm_port_phy_qcfg_output { *********************/ -/* hwrm_port_mac_cfg_input (size:384b/48B) */ +/* hwrm_port_mac_cfg_input (size:448b/56B) */ struct hwrm_port_mac_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -20256,6 +25762,20 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \ UINT32_C(0x2000) + /* + * When this bit is '1', the controller is requested to enable + * timestamp capture capability on all packets (not just PTP) + * of the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE \ + UINT32_C(0x4000) + /* + * When this bit is '1', the controller is requested to disable + * timestamp capture capability on all packets (not just PTP) + * of the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE \ + UINT32_C(0x8000) uint32_t enables; /* * This bit must be '1' for the ipg field to be @@ -20311,6 +25831,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -20504,6 +26030,12 @@ struct hwrm_port_mac_cfg_input { */ int32_t ptp_freq_adj_ppb; uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + int64_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -20654,7 +26186,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -20703,7 +26235,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -20717,7 +26249,7 @@ struct hwrm_port_mac_qcfg_output { * indicates higher priority. * For example, a value of 0-3 is returned where 0 is being * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this + * # If the corresponding CoS mapping is not enabled, then this * field should be ignored. * # This value indicates the normalized priority value retained * in the HWRM. @@ -20904,7 +26436,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -20937,10 +26469,29 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) + /* + * When this bit is set to '1', it indicates that driver has + * configured 64bit RTC. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED \ + UINT32_C(0x20) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -20958,9 +26509,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -20968,6 +26525,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -20995,7 +26556,7 @@ struct tx_port_stats { /* Total Number of 1024-1518 Bytes frames transmitted */ uint64_t tx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame transmitted which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -21136,7 +26697,7 @@ struct rx_port_stats { /* Total Number of 1024-1518 Bytes frames received */ uint64_t rx_1024b_1518b_frames; /* - * Total Number of each good VLAN (exludes FCS errors) + * Total Number of each good VLAN (excludes FCS errors) * frame received which is 1519 to 1522 bytes in length * inclusive (excluding framing bits but including FCS bytes). */ @@ -21491,7 +27052,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -21573,7 +27134,7 @@ struct rx_port_stats_ext { uint64_t rx_buffer_passed_threshold; /* * The number of symbol errors that wasn't corrected by FEC correction - * alogirithm + * algorithm */ uint64_t rx_pcs_symbol_err; /* The number of corrected bits on the port according to active FEC */ @@ -21610,6 +27171,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -22631,8 +28199,10 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) /* 4-port device */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) + /* 12-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc) #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ - HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 /* * This is a bit mask to indicate what speeds are supported * as forced speeds on this link. @@ -22736,7 +28306,7 @@ struct hwrm_port_phy_qcaps_output { * for EEE on this link. * For each speed that can be autonegotiated when EEE is enabled * on this link, the corresponding mask bit shall be set to '1'. - * This field is only valid when the eee_suppotred is set to '1'. + * This field is only valid when the eee_supported is set to '1'. */ uint16_t supported_speeds_eee_mode; /* Reserved */ @@ -22814,7 +28384,28 @@ struct hwrm_port_phy_qcaps_output { UINT32_C(0x2) #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \ UINT32_C(0x4) - uint8_t unused_0[3]; + /* More PHY capability flags */ + uint16_t flags2; + /* + * If set to 1, then this field indicates that + * 802.3x flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED \ + UINT32_C(0x1) + /* + * If set to 1, then this field indicates that + * priority-based flow control is not supported. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ + UINT32_C(0x2) + /* + * Number of internal ports for this device. This field allows the FW + * to advertise how many internal ports are present. Manufacturing + * tools uses this to determine how many internal ports should have + * the PRBS test run on them. This field always return 0 unless NVM + * option "HPTN_MODE" is set to 1. + */ + uint8_t internal_port_cnt; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24103,7 +29694,13 @@ struct hwrm_port_prbs_test_input { * use this entire buffer or less than the entire buffer, but never more. */ uint16_t data_len; - uint16_t unused_0; + uint16_t flags; + /* + * If set, the port_id field should be interpreted as an internal + * port. The internal port id range is returned in port_phy_qcaps + * response internal_port_cnt field. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1) uint32_t unused_1; /* Port ID of port where PRBS test to be run. */ uint16_t port_id; @@ -24400,14 +29997,14 @@ struct hwrm_port_sfp_sideband_cfg_input { /* * This bit along with rs1 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ UINT32_C(0x1) /* * This bit along with rs0 configures the current speed of the dual * rate module. If these pins are GNDed then the speed can be changed - * by driectly writing to EEPROM. + * by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ UINT32_C(0x2) @@ -24531,16 +30128,16 @@ struct hwrm_port_sfp_sideband_qcfg_output { #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ UINT32_C(0x2) /* - * This bit along with rs1 indiactes the current speed of the dual + * This bit along with rs1 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ UINT32_C(0x4) /* - * This bit along with rs0 indiactes the current speed of the dual + * This bit along with rs0 indicates the current speed of the dual * rate module.If these pins are grounded then the speed can be - * changed by driectky writing to EEPROM. + * changed by directly writing to EEPROM. */ #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ UINT32_C(0x8) @@ -24894,6 +30491,315 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + /* + * The NIC does not support enforcement of a minimum guaranteed + * bandwidth for an endpoint. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED \ + UINT32_C(0x6) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -25010,6 +30916,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -28594,7 +34507,11 @@ struct hwrm_queue_dscp2pri_cfg_input { uint64_t resp_addr; /* * This is the host address where the 24-bits DSCP-MASK-PRI tuple - * will be copied from. + * will be copied from. A non-zero mask "adds" a tuple, while + * a mask equal to 0 triggers the firmware to remove a tuple. + * Only tuples with unique DSCP values are stored. On chips + * prior to Thor a mask can be 0 - 0x3f, while on Thor it can + * be 0 or 0x3f. */ uint64_t src_data_addr; uint32_t flags; @@ -29343,6 +35260,284 @@ struct hwrm_queue_vlanpri2pri_cfg_output { uint8_t valid; } __rte_packed; +/************************* + * hwrm_queue_global_cfg * + *************************/ + + +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) + /* + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) + /* + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) + /* + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) + /* + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. + */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) + /* + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g1_max_bw; + /* + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. + */ + uint8_t g2_max_bw; + /* + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. + */ + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; + /* + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g1_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /******************* * hwrm_vnic_alloc * *******************/ @@ -29765,6 +35960,9 @@ struct hwrm_vnic_cfg_input { /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \ UINT32_C(0x100) + /* This bit must be '1' for the l2_cqe_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE \ + UINT32_C(0x200) /* Logical vnic ID */ uint16_t vnic_id; /* @@ -29856,7 +36054,37 @@ struct hwrm_vnic_cfg_input { #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \ HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX - uint8_t unused0[5]; + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to configure the + * CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * When configured with this cqe mode, A normal (32B) CQE + * will be generated. This is the default mode. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this cqe mode, A compressed (16B) CQE + * will be generated. In this mode TPA and HDS are not supported. + * Host drivers should not configure the TPA and HDS along with + * compressed mode, per VNIC. FW returns error, if host drivers + * try to configure the VNIC with compressed mode and (TPA or HDS). + * The compressed completion does not include PTP data. Host + * drivers should not use this mode to receive the PTP data. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * When configured with this cqe mode, HW generates either a 32B + * completion or a 16B completion depending on use case within a + * VNIC. For ex. a simple L2 packet could use the compressed form + * while a PTP packet on the same VNIC would use the 32B form. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST \ + HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED + uint8_t unused0[4]; } __rte_packed; /* hwrm_vnic_cfg_output (size:128b/16B) */ @@ -30063,7 +36291,31 @@ struct hwrm_vnic_qcfg_output { #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \ HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX - uint8_t unused_1[4]; + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to convey the + * configured CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * This value indicates that the VNIC is configured with normal + * (32B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured with compressed + * (16B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * This value indicates that the VNIC is configured with mixed + * CQE mode. HW generates either a 32B completion or a 16B + * completion depending on use case within a VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30177,7 +36429,7 @@ struct hwrm_vnic_qcaps_output { UINT32_C(0x20) /* * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. + * mirror the RoCE traffic is supported. * If set to '0', then the capability to mirror the * RoCE traffic is not supported. */ @@ -30195,7 +36447,7 @@ struct hwrm_vnic_qcaps_output { * ability to steer incoming packets from one CoS queue to one * VNIC. This optional feature can then be enabled * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classfication” is set + * available when NVM option “enable_cos_classification” is set * to 1. If set to '0', firmware does not support this feature. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ @@ -30205,7 +36457,7 @@ struct hwrm_vnic_qcaps_output { * the use of RX V2 and RX TPA start V2 completion records for all * the RX rings of a VNIC. Once set, this feature is mandatory to * be used for the RX rings of the VNIC. Additionally, two new RX - * checksum features supported by these ompletion records can be + * checksum features supported by these completion records can be * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the * HW and the firmware does not support this feature. */ @@ -30237,10 +36489,78 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) + /* + * When this bit is set '1', it indicates that firmware supports + * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that HW is capable of using + * Toeplitz algorithm. This mode uses Toeplitz algorithm and + * provided Toeplitz hash key to hash the packets according to the + * configured hash type and hash mode. The Toeplitz hash results and + * the provided Toeplitz RSS indirection table are used to determine + * the RSS rings. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that HW is capable of using + * XOR algorithm. This mode uses XOR algorithm to hash the packets + * according to the configured hash type and hash mode. The XOR + * hash results and the provided XOR RSS indirection table are + * used to determine the RSS rings. Host drivers provided hash key + * is not honored in this mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP \ + UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that HW is capable of using + * checksum algorithm. In this mode, HW uses inner packets checksum + * algorithm to distribute the packets across the rings and Toeplitz + * algorithm to calculate the hash to convey it in the RX + * completions. Host drivers should provide Toeplitz hash key. + * As HW uses innermost packets checksum to distribute the packets + * across the rings, host drivers can't convey hash mode to choose + * outer headers to calculate Toeplitz hash. FW will fail such + * configuration. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP \ + UINT32_C(0x20000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPV6 flow labels. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP \ + UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V3 and RX TPA start V3 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP \ + UINT32_C(0x80000) + /* + * When this bit is '1' HW supports different RX CQE record types. + * Host drivers can choose the mode based on their application + * requirements like performance, TPA, HDS and PTP. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \ + UINT32_C(0x100000) /* * This field advertises the maximum concurrent TPA aggregations - * supported by the VNIC on new devices that support TPA v2. - * '0' means that TPA v2 is not supported. + * supported by the VNIC on new devices that support TPA v2 or v3. + * '0' means that both the TPA v2 and v3 are not supported. */ uint16_t max_aggs_supported; uint8_t unused_1[5]; @@ -30501,37 +36821,54 @@ struct hwrm_vnic_rss_cfg_input { * over source and destination IPv4 addresses of IPv4 * packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 \ + UINT32_C(0x1) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 \ + UINT32_C(0x2) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 \ + UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 \ + UINT32_C(0x8) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 \ + UINT32_C(0x10) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 \ + UINT32_C(0x20) + /* + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. Host drivers should set this bit based on + * rss_ipv6_flow_label_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \ + UINT32_C(0x40) /* VNIC ID of VNIC associated with RSS table being configured. */ uint16_t vnic_id; /* @@ -30587,7 +36924,66 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t ring_select_mode; + /* + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ \ + UINT32_C(0x0) + /* + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR \ + UINT32_C(0x1) + /* + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST \ + HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[4]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -30703,7 +37099,7 @@ struct hwrm_vnic_rss_qcfg_output { #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 + * over source and destination IPv6 addresses of IPv6 * packets. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) @@ -30764,7 +37160,39 @@ struct hwrm_vnic_rss_qcfg_output { */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) - uint8_t unused_1[6]; + uint8_t ring_select_mode; + /* + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ \ + UINT32_C(0x0) + /* + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR \ + UINT32_C(0x1) + /* + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM \ + UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_LAST \ + HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30930,7 +37358,7 @@ struct hwrm_vnic_plcmodes_cfg_input { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -31094,7 +37522,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -31339,7 +37767,47 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; + /* + * This field controls the number of packets transmitted before a TX + * completion is generated. Non-zero values for the field are only + * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion + * records capability is supported. + */ + uint8_t cmpl_coal_cnt; + /* Generates a legacy TX completion on every packet. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) + /* Generates a TX coalesced completion for up to 4 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) + /* Generates a TX coalesced completion for up to 8 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) + /* Generates a TX coalesced completion for up to 12 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) + /* Generates a TX coalesced completion for up to 16 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) + /* Generates a TX coalesced completion for up to 24 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) + /* Generates a TX coalesced completion for up to 32 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) + /* Generates a TX coalesced completion for up to 48 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) + /* Generates a TX coalesced completion for up to 64 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) + /* Generates a TX coalesced completion for up to 96 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) + /* Generates a TX coalesced completion for up to 128 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) + /* Generates a TX coalesced completion for up to 192 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) + /* Generates a TX coalesced completion for up to 256 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) + /* Generates a TX coalesced completion for up to 320 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) + /* Generates a TX coalesced completion for up to 384 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) + /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST \ + HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX /* Ring allocation flags. */ uint16_t flags; /* @@ -31350,7 +37818,20 @@ struct hwrm_ring_alloc_input { * Rx rings and is ignored for all other rings included Rx * Aggregation rings. */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD \ + UINT32_C(0x1) + /* + * When the HW Doorbell Drop Recovery feature is enabled, + * HW can flag false CQ overflow when CQ consumer index + * doorbells are dropped when there really wasn't any overflow. + * The CQE values could have already been processed by the driver, + * but HW doesn't know about this because of the doorbell drop. + * To avoid false detection of CQ overflow events, + * it is recommended that CQ overflow detection is disabled + * by the driver when HW based doorbell recovery is enabled. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \ + UINT32_C(0x2) /* * This value is a pointer to the page table for the * Ring. @@ -31640,7 +38121,7 @@ struct hwrm_ring_alloc_output { ******************/ -/* hwrm_ring_free_input (size:192b/24B) */ +/* hwrm_ring_free_input (size:256b/32B) */ struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; @@ -31686,10 +38167,37 @@ struct hwrm_ring_free_input { #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; + uint8_t flags; + /* + * If this bit is set to '1', ring_id in this command belongs to + * virtio function. prod_idx in this command corresponds to doorbell + * producer index. opaque field in this command needs to be inserted + * by firmware in VEE_FLUSH completion record. + * Firmware will poll the corresponding ring context to reach the + * given producer index before sending successful response. It will + * finish the completion using VEE_FLUSH completion record. + * + * If this bit is '0', firmware will not treat ring_id as virtio + * ring and ignore prod_idx, opaque fields. + * + * This feature is not applicable for L2 or RoCE. + */ + #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1) + #define HWRM_RING_FREE_INPUT_FLAGS_LAST \ + HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID /* Physical number of ring allocated. */ uint16_t ring_id; - uint8_t unused_1[4]; + /* + * Ring BD producer index posted by the virtio block. + * This field is valid if virtio_ring_valid flag is set. + */ + uint32_t prod_idx; + /* + * User defined opaque field to be inserted into VEE_FLUSH completion + * record. This field is valid if virtio_ring_valid flag is set. + */ + uint32_t opaque; + uint32_t unused_1; } __rte_packed; /* hwrm_ring_free_output (size:128b/16B) */ @@ -35640,6 +42148,14 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x40) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -36162,6 +42678,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input { */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x2) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT \ + UINT32_C(0x4) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -38497,7 +45021,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) /* No more wild-card TCAM */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collsion in exact match tables */ + /* Hash collision in exact match tables */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) /* Key is already installed */ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) @@ -41718,142 +48242,636 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; -} __rte_packed; - -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + uint32_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + UINT32_C(0x1) + /* + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + UINT32_C(0x2) + /* + * Value of 1 to indicate firmware support flow batch delete + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow + * batch delete operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + UINT32_C(0x4) + /* + * Value of 1 to indicate that the firmware support flow reset all + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all + * operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + UINT32_C(0x8) + /* + * Value of 1 to indicate that firmware supports use of FID as + * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as + * dest_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + UINT32_C(0x10) + /* + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x20) + /* + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x40) + /* + * Value of 1 to indicate that firmware supports the dynamic + * allocation of an on-chip flow counter which can be used for EEM + * flows. Value of 0 indicates firmware does not support the dynamic + * allocation of an on-chip flow counter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + UINT32_C(0x80) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + UINT32_C(0x100) + /* + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + UINT32_C(0x200) + /* + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ + UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that core firmware is + * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX + * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \ + UINT32_C(0x8000) + /* + * If set to 1, firmware is capable of supporting L2/ROCE as + * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. + * By default, this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \ + UINT32_C(0x10000) + /* + * If set to 1, firmware is capable of HW LAG. This bit is only + * advertised if the calling function is a PAXC function. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \ + UINT32_C(0x20000) + /* + * If set to 1, firmware is capable installing ntuple rules without + * additional classification on the L2 Context. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ + UINT32_C(0x40000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_cfa_tflib * + ******************/ + + +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} __rte_packed; + +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_cfa_tls_filter_alloc * + *****************************/ + + +/* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */ +struct hwrm_cfa_tls_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t unused_0; + uint32_t enables; /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. + * This bit must be '1' for the l2_filter_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ UINT32_C(0x1) /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x2) /* - * Value of 1 to indicate firmware support flow batch delete - * operation through HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow - * batch delete operation. + * This bit must be '1' for the ipaddr_type field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ UINT32_C(0x4) /* - * Value of 1 to indicate that the firmware support flow reset all - * operation through HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all - * operation. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ UINT32_C(0x8) /* - * Value of 1 to indicate that firmware supports use of FID as - * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as - * dest_id. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ UINT32_C(0x10) /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. + * This bit must be '1' for the ip_protocol field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ UINT32_C(0x20) /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. + * This bit must be '1' for the src_port field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ UINT32_C(0x40) /* - * Value of 1 to indicate that firmware supports the dynamic - * allocation of an on-chip flow counter which can be used for EEM - * flows. Value of 0 indicates firmware does not support the dynamic - * allocation of an on-chip flow counter. + * This bit must be '1' for the dst_port field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ UINT32_C(0x80) /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + * This bit must be '1' for the kid field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID \ UINT32_C(0x100) /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. + * This bit must be '1' for the dst_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ UINT32_C(0x200) /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ UINT32_C(0x400) /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) + uint64_t l2_filter_id; + uint8_t unused_1[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * If set to 1, firmware is capable of supporting ARP ethertype as - * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the - * RX direction. By default, this flag should be 0 for older version - * of firmware. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ - UINT32_C(0x1000) + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC - * command. Value of 0 indicates firmware does not support - * rfs_ring_tbl_idx in dst_id field. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ - UINT32_C(0x2000) + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP /* - * If set to 1, firmware is capable of supporting IPv4/IPv6 as - * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX - * direction. By default, this flag should be 0 for older version - * of firmware. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ - UINT32_C(0x4000) + uint16_t dst_id; /* - * When this bit is '1', it indicates that core firmware is - * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX - * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + * Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \ - UINT32_C(0x8000) + uint16_t mirror_vnic_id; + uint8_t unused_2[2]; /* - * If set to 1, firmware is capable of supporting L2/ROCE as - * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. - * By default, this flag should be 0 for older version of firmware. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \ - UINT32_C(0x10000) + uint32_t src_ipaddr[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * The Key Context Identifier (KID) for use with KTLS. + * KID is limited to 20-bits. + */ + uint32_t kid; +} __rte_packed; + +/* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_tls_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -41866,13 +48884,13 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { uint8_t valid; } __rte_packed; -/****************** - * hwrm_cfa_tflib * - ******************/ +/**************************** + * hwrm_cfa_tls_filter_free * + ****************************/ -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { +/* hwrm_cfa_tls_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_tls_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41901,18 +48919,12 @@ struct hwrm_cfa_tflib_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; } __rte_packed; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_cfa_tls_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_tls_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41921,16 +48933,7 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; - /* unused. */ - uint8_t unused1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -42055,7 +49058,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -42072,7 +49075,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -42143,8 +49153,29 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; - /* unused. */ - uint32_t unused0; + /* This field is used to return the status of fw session to host. */ + uint32_t flags; + /* + * Indicates if the shared session has been created. Shared session + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ + UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates the shared session + * has been created by another session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \ + UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates the shared session + * is created by this session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \ + HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR /* unused. */ uint8_t unused1[3]; /* @@ -42609,7 +49640,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -42666,8 +49697,13 @@ struct hwrm_tf_session_resc_qcaps_output { * qcaps_size. */ uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint16_t unused0; + uint8_t unused0; /* unused. */ uint8_t unused1[7]; /* @@ -42724,7 +49760,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -42823,7 +49859,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -42904,29 +49940,121 @@ struct hwrm_tf_session_resc_flush_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided flush_addr + * buffer. + */ + uint16_t flush_size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'flush_size' field in this + * message. + */ + uint64_t flush_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +struct hwrm_tf_session_resc_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tf_session_resc_info * + *****************************/ + + +/* hwrm_tf_session_resc_info_input (size:320b/40B) */ +struct hwrm_tf_session_resc_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX /* - * Defines the size, in bytes, of the provided flush_addr - * buffer. + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. */ - uint16_t flush_size; + uint16_t req_size; /* - * This is the DMA address for the flush input data array - * buffer. Array of tf_rm_resc_entry type. Size of the - * buffer is provided by the 'flush_size' field in this + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this * message. */ - uint64_t flush_addr; + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; } __rte_packed; -/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ -struct hwrm_tf_session_resc_flush_output { +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42935,8 +50063,15 @@ struct hwrm_tf_session_resc_flush_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -43010,13 +50145,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -43102,7 +50246,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -43584,7 +50728,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -43762,7 +50906,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -43869,7 +51013,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -44074,7 +51218,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -44100,7 +51244,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -44240,7 +51384,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -44321,7 +51465,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -44402,13 +51546,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -44434,6 +51578,79 @@ struct hwrm_tf_em_delete_output { uint16_t unused0[3]; } __rte_packed; +/******************* + * hwrm_tf_em_move * + *******************/ + + +/* hwrm_tf_em_move_input (size:320b/40B) */ +struct hwrm_tf_em_move_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX + /* Number of EM entry blocks */ + uint16_t num_blocks; + /* New index for entry */ + uint32_t new_index; + /* Unused */ + uint32_t unused0; + /* EM internal flow handle. */ + uint64_t flow_handle; +} __rte_packed; + +/* hwrm_tf_em_move_output (size:128b/16B) */ +struct hwrm_tf_em_move_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Index of old entry. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + /******************** * hwrm_tf_tcam_set * ********************/ @@ -44477,7 +51694,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -44507,8 +51724,8 @@ struct hwrm_tf_tcam_set_input { /* unused. */ uint8_t unused0[6]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[88]; } __rte_packed; @@ -44579,7 +51796,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -44615,8 +51832,8 @@ struct hwrm_tf_tcam_get_output { /* unused. */ uint8_t unused0[4]; /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. */ uint8_t dev_data[272]; /* unused. */ @@ -44675,7 +51892,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -44758,7 +51975,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -44841,7 +52058,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -44925,7 +52142,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -45000,7 +52217,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -45015,7 +52232,7 @@ struct hwrm_tf_if_tbl_get_input { uint32_t index; } __rte_packed; -/* hwrm_tf_if_tbl_get_output (size:256b/32B) */ +/* hwrm_tf_if_tbl_get_output (size:1216b/152B) */ struct hwrm_tf_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -45032,7 +52249,7 @@ struct hwrm_tf_if_tbl_get_output { /* unused */ uint16_t unused0; /* Response data. */ - uint8_t data[8]; + uint8_t data[128]; /* unused */ uint8_t unused1[7]; /* @@ -45051,7 +52268,7 @@ struct hwrm_tf_if_tbl_get_output { ***************************/ -/* hwrm_tf_if_tbl_set_input (size:384b/48B) */ +/* hwrm_tf_if_tbl_set_input (size:1024b/128B) */ struct hwrm_tf_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; @@ -45089,7 +52306,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -45107,7 +52324,7 @@ struct hwrm_tf_if_tbl_set_input { /* unused */ uint8_t unused1[6]; /* Data to be set. */ - uint8_t data[8]; + uint8_t data[88]; } __rte_packed; /* hwrm_tf_if_tbl_set_output (size:128b/16B) */ @@ -45173,13 +52390,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -46953,7 +54179,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -46989,8 +54215,8 @@ struct hwrm_nvm_write_input { */ uint64_t host_src_addr; /* - * The Directory Entry Type (valid values are defined in the bnxnvm - * directory_type enum defined in the file bnxnvm_defs.h). + * The Directory Entry Type (valid values are defined in the + * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* @@ -46998,15 +54224,21 @@ struct hwrm_nvm_write_input { * The 0-based instance of the combined Directory Entry Type and Extension. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ uint16_t dir_attr; /* - * Length of data to write, in bytes. May be less than or equal to the allocated - * size for the directory entry. - * The data length stored in the directory entry will be updated to reflect - * this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. + * The data length stored in the directory entry will be updated to + * reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -47019,17 +54251,46 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. This - * value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. + * This value may be greater than or equal to the specified data + * length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be - * greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with a - * size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, + * which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes + * for an item's data is to pre-allocate extra storage (padding) to + * accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -47047,8 +54308,8 @@ struct hwrm_nvm_write_output { * Length of the allocated NVM for the item, in bytes. The value may be * greater than or equal to the specified data length or the requested * item length. - * The actual item length used when creating a new directory entry will be - * a multiple of an NVM block size. + * The actual item length used when creating a new directory entry will + * be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -47257,7 +54518,8 @@ struct hwrm_nvm_find_dir_entry_output { uint32_t dir_data_length; /* * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + * Only valid if the directory entry is for embedded firmware stored + * in APE_BIN Format. */ uint32_t fw_ver; /* Directory ordinal. */ @@ -47538,13 +54800,13 @@ struct hwrm_nvm_mod_dir_entry_input { */ uint16_t dir_ordinal; /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension - * flag definitions). + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for + * extension flag definitions). */ uint16_t dir_ext; /* - * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag - * definitions). + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). */ uint16_t dir_attr; /* @@ -47620,8 +54882,10 @@ struct hwrm_nvm_verify_update_input { /* * The Directory Entry Extension flags. * The "UPDATE" extension flag must be set in this value. - * A corresponding directory entry with the same type and ordinal values but *without* - * the "UPDATE" extension flag must also exist. The other flags of the extension must + * A corresponding directory entry with the same type and ordinal + * values but *without* + * the "UPDATE" extension flag must also exist. The other flags of + * the extension must * be identical between the active and update entries. */ uint16_t dir_ext; @@ -47708,20 +54972,25 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \ HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL uint16_t flags; - /* If set to 1, then securely erase all unused locations in persistent storage. */ + /* + * If set to 1, then securely erase all unused locations in + * persistent storage. + */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package + * file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will + * be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) /* - * If set to 1, FW will defragment the NVM if defragmentation is required for the update. - * Allow additional time for this command to complete if this bit is set to 1. + * If set to 1, FW will defragment the NVM if defragmentation is + * required for the update. + * Allow additional time for this command to complete if this bit is + * set to 1. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) @@ -47751,12 +55020,94 @@ struct hwrm_nvm_install_update_output { * A value of 0 indicates that no items were successfully installed. */ uint64_t installed_items; - /* result is 8 b */ + /* result is 8 b corresponding to BCMRETVAL error codes */ uint8_t result; /* There was no problem with the package installation. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS \ + UINT32_C(0x0) + /* Generic failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE \ + UINT32_C(0xff) + /* Allocation error malloc failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE \ + UINT32_C(0xfd) + /* NVM install error due to invalid index */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER \ + UINT32_C(0xfb) + /* NVM install error due to invalid type */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER \ + UINT32_C(0xf3) + /* Invalid package due to invalid prerequisite */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE \ + UINT32_C(0xf2) + /* Invalid package due to invalid file header */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER \ + UINT32_C(0xec) + /* Invalid package due to invalid format */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE \ + UINT32_C(0xeb) + /* Invalid package due to invalid property stream */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM \ + UINT32_C(0xea) + /* Invalid package due to invalid property length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH \ + UINT32_C(0xe9) + /* Invalid package due to invalid manifest */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST \ + UINT32_C(0xe8) + /* Invalid package due to invalid trailer */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER \ + UINT32_C(0xe7) + /* Invalid package due to invalid checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM \ + UINT32_C(0xe6) + /* Invalid package due to invalid item checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM \ + UINT32_C(0xe5) + /* Invalid package due to invalid length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH \ + UINT32_C(0xe4) + /* Invalid package due to invalid directive */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE \ + UINT32_C(0xe1) + /* Invalid device due to unsupported chip revision */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV \ + UINT32_C(0xce) + /* Invalid device due to unsupported device ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID \ + UINT32_C(0xcd) + /* Invalid device due to unsupported subsystem vendor */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR \ + UINT32_C(0xcc) + /* Invalid device due to unsupported subsystem ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID \ + UINT32_C(0xcb) + /* Invalid device due to unsupported product ID or customer ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM \ + UINT32_C(0xc5) + /* Invalid package due to duplicate item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM \ + UINT32_C(0xc4) + /* Invalid package due to zero length item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM \ + UINT32_C(0xc3) + /* NVM integrity error checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR \ + UINT32_C(0xb9) + /* NVM integrity error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR \ + UINT32_C(0xb8) + /* Authentication error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR \ + UINT32_C(0xb7) + /* NVM install error item not found */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND \ + UINT32_C(0xb0) + /* NVM install error item locked */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED \ + UINT32_C(0xa7) #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \ - HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED /* problem_item is 8 b */ uint8_t problem_item; /* There was no problem with any packaged items. */ @@ -47812,13 +55163,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -47986,12 +55343,13 @@ struct hwrm_nvm_get_variable_output { /* size of data of the actual variable retrieved in bits */ uint16_t data_len; /* - * option_num is the option number for the data retrieved. It is possible in the - * future that the option number returned would be different than requested. This - * condition could occur if an option is deprecated and a new option id is defined - * with similar characteristics, but has a slightly different definition. This - * also makes it convenient for the caller to identify the variable result with - * the option id from the response. + * option_num is the option number for the data retrieved. It is + * possible in the future that the option number returned would be + * different than requested. This condition could occur if an option is + * deprecated and a new option id is defined with similar + * characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable + * result with the option id from the response. */ uint16_t option_num; /* reserved. */ @@ -48101,8 +55459,8 @@ struct hwrm_nvm_set_variable_input { uint16_t index_3; uint8_t flags; /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) + * When this bit is 1, flush internal cache after this write + * operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) @@ -48254,9 +55612,15 @@ struct hwrm_nvm_validate_option_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; uint8_t result; - /* indicates that the value provided for the option is not matching with the saved data. */ + /* + * indicates that the value provided for the option is not matching + * with the saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) - /* indicates that the value provided for the option is matching the saved data. */ + /* + * indicates that the value provided for the option is matching the + * saved data. + */ #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \ HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH @@ -48285,6 +55649,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ @@ -48406,8 +55848,8 @@ struct hwrm_fw_reset_input { #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \ UINT32_C(0x4) /* - * AP processor complex (in multi-host environment). Use host_idx to - * control which core is reset + * AP processor complex (in multi-host environment). + * Use host_idx to control which core is reset */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \ UINT32_C(0x5) @@ -48625,4 +56067,87 @@ struct hcomm_status { } __rte_packed; /* This is the GRC offset where the hcomm_status struct resides. */ #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + +/************************** + * hwrm_port_phy_i2c_read * + **************************/ + + +/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ +struct hwrm_port_phy_i2c_read_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the page_offset field to be + * configured. + */ + #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL + /* Port ID of port. */ + uint16_t port_id; + /* 8-bit I2C slave address. */ + uint8_t i2c_slave_addr; + uint8_t unused_0; + /* The page number that is being accessed over I2C. */ + uint16_t page_number; + /* Offset within the page that is being accessed over I2C. */ + uint16_t page_offset; + /* + * Length of data to read, in bytes starting at the offset + * specified above. If the offset is not specified, then + * the data shall be read from the beginning of the page. + */ + uint8_t data_length; + uint8_t unused_1[7]; +} __rte_packed; + +/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ +struct hwrm_port_phy_i2c_read_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Up to 64B of data. */ + uint32_t data[16]; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; #endif /* _HSI_STRUCT_DEF_DPDK_H_ */