X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=4d7efb19f42d6f30a58bcbf049ca72952dc87d6d;hb=586e6028371764452b7dbae3b1f50adde87be80e;hp=4b8b13e3bbb75931ca51e4c9760fbc9289154853;hpb=8b96a65ce5e98ae40f6aa9822a6059692543221c;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4b8b13e3bb..4d7efb19f4 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2020 Broadcom Inc. + * Copyright (c) 2014-2021 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -269,6 +269,7 @@ struct cmd_nums { */ uint16_t req_type; #define HWRM_VER_GET UINT32_C(0x0) + #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb) #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc) #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd) #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe) @@ -336,6 +337,8 @@ struct cmd_nums { #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48) #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49) #define HWRM_VNIC_QCAPS UINT32_C(0x4a) + /* Updates specific fields in RX VNIC structure */ + #define HWRM_VNIC_UPDATE UINT32_C(0x4b) #define HWRM_RING_ALLOC UINT32_C(0x50) #define HWRM_RING_FREE UINT32_C(0x51) #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) @@ -358,6 +361,11 @@ struct cmd_nums { #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) + #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83) + #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84) + #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) + #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) + #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -397,6 +405,8 @@ struct cmd_nums { #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb) #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc) #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd) + #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe) + #define HWRM_FW_LIVEPATCH UINT32_C(0xbf) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) @@ -430,6 +440,8 @@ struct cmd_nums { #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) /* Tells the fw to collect dsc dump on a given port and lane. */ #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) + #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda) + #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -527,6 +539,10 @@ struct cmd_nums { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126) + /* Experimental */ + #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ @@ -625,6 +641,22 @@ struct cmd_nums { #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198) /* Queries extended statistics context */ #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199) + /* Configure SoC packet DMA settings */ + #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a) + /* Query SoC packet DMA settings */ + #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b) + /* PTP - Queries configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c) + /* PTP - Configuration of timesync IO pins. */ + #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d) + /* PTP - Configuration for disciplining PHC. */ + #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e) + /* PTP - Queries for PHC timestamps. */ + #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f) + /* PTP - Extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) + /* PTP - Query extended PTP configuration. */ + #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -652,6 +684,36 @@ struct cmd_nums { #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) /* Tells the fw to read the fru memory */ #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Used to provision SoC software images */ + #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) + /* Retrieves the SoC status and image provisioning information */ + #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) + /* Tells the fw to program the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) + /* Tells the fw to read the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) + /* Tells the fw to get the health of seeprom data */ + #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* + * The command is used for certificate provisioning to export a + * Certificate Signing Request (CSR) from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211) + /* + * The command is used for certificate provisioning to import a + * CA-signed certificate chain to the device. + */ + #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212) + /* + * The command is used for certificate provisioning to query the + * provisioned state. + */ + #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213) + /* + * The command is used to get the hash of the NVM configuration that is + * calculated during firmware boot. + */ + #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -677,6 +739,8 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) /* Experimental */ + #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) @@ -703,6 +767,10 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) /* Experimental */ + #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec) + /* Experimental */ + #define HWRM_TF_EM_MOVE UINT32_C(0x2ed) + /* Experimental */ #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) /* Experimental */ #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) @@ -757,6 +825,25 @@ struct cmd_nums { #define HWRM_DBG_QCFG UINT32_C(0xff21) /* Set destination parameters for crashdump medium */ #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + /* Experimental */ + #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23) + /* Experimental */ + #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24) + /* Experimental */ + #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25) + /* Experimental */ + #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26) + /* Experimental */ + #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27) + /* Experimental */ + #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28) + /* Experimental */ + #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29) + /* Experimental */ + #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) + /* Experimental */ + #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) @@ -875,6 +962,13 @@ struct ret_codes { * by the host is not allowed due to a secure lock violation. */ #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11) + /* + * This error code is reported by Firmware when an operation requested + * by a VF cannot be forwarded to the parent PF as required, either + * because the PF is down or otherwise doesn't have an appropriate + * async completion ring or associated forwarding buffers configured. + */ + #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -960,10 +1054,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 1 +#define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 70 -#define HWRM_VERSION_STR "1.10.1.70" +#define HWRM_VERSION_RSVD 44 +#define HWRM_VERSION_STR "1.10.2.44" /**************** * hwrm_ver_get * @@ -1350,18 +1444,34 @@ struct hwrm_ver_get_output { * If set to 1, it will indicate to host drivers that firmware is * not ready to start full blown HWRM commands. Host drivers should * re-try HWRM_VER_GET with some timeout period. The timeout period - * can be selected up to 5 seconds. + * can be selected up to 5 seconds. Host drivers should also check + * for dev_not_rdy_backing_store to identify if flag is set due to + * backing store not been available. * For Example, PCIe hot-plug: * Hot plug timing is system dependent. It generally takes up to * 600 miliseconds for firmware to clear DEV_NOT_RDY flag. * If set to 0, device is ready to accept all HWRM commands. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1) + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \ + UINT32_C(0x1) /* * If set to 1, external version present. * If set to 0, external version not present. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2) + #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \ + UINT32_C(0x2) + /* + * Firmware sets this flag along with dev_not_rdy flag to indicate + * host drivers that it has not completed resource initialization + * required for data path operations. Host drivers should not send + * any HWRM command that requires data path resources. Firmware will + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry + * those commands once both the flags are cleared. + * If this flag and dev_not_rdy flag are set to 0, device is ready + * to accept all HWRM commands. + */ + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \ + UINT32_C(0x4) uint8_t unused_0[2]; /* * For backward compatibility this field must be set to 1. @@ -1503,7 +1613,18 @@ struct hwrm_ver_get_output { * used with the short cmd request format. */ uint16_t max_ext_req_len; - uint8_t unused_1[5]; + /* + * This field returns the maximum request timeout value in seconds. + * For backward compatibility, a value of zero should be interpreted + * as the default value of 40 seconds. Drivers should always honor the + * maximum timeout, but are permitted to warn if a longer duration than + * this default is advertised. Values larger than 40 seconds should + * only be used as a stopgap measure to address a device limitation or + * for the purposes of test and debugging. The long term goal is for + * firmware to significantly reduce this value in the passage of time. + */ + uint16_t max_req_timeout; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -1613,7 +1734,7 @@ struct cfa_bds_write_cmd_data_msg { uint32_t dta[32]; } __rte_packed; -/* cfa_bds_read_clr_cmd_data_msg (size:192b/24B) */ +/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */ struct cfa_bds_read_clr_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; @@ -1640,7 +1761,13 @@ struct cfa_bds_read_clr_cmd_data_msg { uint8_t table_scope; #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 - uint8_t unused0; + /* + * This value identifies the number of 32B units will be accessed. + * Always set the value to 1. + */ + uint8_t data_size; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0 /* This is the 32B index into the selected table to access. */ uint32_t table_index; #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \ @@ -1659,7 +1786,8 @@ struct cfa_bds_read_clr_cmd_data_msg { * of data read when set to '1'. */ uint16_t clear_mask; - uint16_t unused1[3]; + uint16_t unused0[3]; + uint16_t unused1[4]; } __rte_packed; /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */ @@ -1714,7 +1842,7 @@ struct cfa_bds_em_insert_cmd_data_msg { uint32_t dta[32]; } __rte_packed; -/* cfa_bds_em_delete_cmd_data_msg (size:192b/24B) */ +/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */ struct cfa_bds_em_delete_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; @@ -1756,9 +1884,10 @@ struct cfa_bds_em_delete_cmd_data_msg { * the data_size field. The bd_cnt in the encapsulating BD must also be */ uint64_t dta; + uint32_t unused1[2]; } __rte_packed; -/* cfa_bds_invalidate_cmd_data_msg (size:64b/8B) */ +/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */ struct cfa_bds_invalidate_cmd_data_msg { /* This value selects the format for the mid-path command for the CFA. */ uint8_t opcode; @@ -1786,12 +1915,16 @@ struct cfa_bds_invalidate_cmd_data_msg { uint8_t table_scope; #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 - uint8_t unused0; + /* This value specifies the number of cache lines to invalidate. */ + uint8_t data_size; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0 /* This is the 32B index into the selected table to access. */ uint32_t table_index; #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \ UINT32_C(0x3ffffff) #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + uint32_t unused[2]; } __rte_packed; /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */ @@ -2638,51 +2771,69 @@ struct tx_bd_long_hi { */ uint32_t cfa_meta; /* When key=1, This is the VLAN tag VID value. */ - #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 /* When key=1, This is the VLAN tag DE value. */ - #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) /* When key=1, This is the VLAN tag PRI value. */ - #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \ + (UINT32_C(0x0) << 16) /* 0x8100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \ + (UINT32_C(0x1) << 16) /* 0x9100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \ + (UINT32_C(0x2) << 16) /* 0x9200 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \ + (UINT32_C(0x3) << 16) /* 0x9300 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \ + (UINT32_C(0x4) << 16) /* Value programmed in CFA VLANTPID register. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \ + (UINT32_C(0x5) << 16) #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \ TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) - #define TX_BD_LONG_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define TX_BD_LONG_CFA_META_KEY_SFT 28 /* No editing */ - #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + #define TX_BD_LONG_CFA_META_KEY_NONE \ + (UINT32_C(0x0) << 28) /* * - meta[17:16] - TPID select value (0 = 0x8100). * - meta[15:12] - PRI/DE value. * - meta[11:0] - VID value. */ - #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \ + (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ - TX_BD_LONG_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* @@ -2912,16 +3063,19 @@ struct tx_bd_long_inline { */ uint32_t cfa_meta; /* When key = 1, this is the VLAN tag VID value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 /* When key = 1, this is the VLAN tag DE value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \ + UINT32_C(0x1000) /* When key = 1, this is the VLAN tag PRI value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \ + UINT32_C(0xe000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 /* When key = 1, this is the VLAN tag TPID select value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \ + UINT32_C(0x70000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \ (UINT32_C(0x0) << 16) @@ -2944,7 +3098,7 @@ struct tx_bd_long_inline { TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \ UINT32_C(0xff80000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. @@ -2953,7 +3107,7 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \ UINT32_C(0xf0000000) - #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 /* No editing */ #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \ (UINT32_C(0x0) << 28) @@ -2964,8 +3118,18 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \ (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ - TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* tx_bd_empty (size:128b/16B) */ @@ -7373,9 +7537,35 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ UINT32_C(0x41) + /* + * An echo request from the firmware. An echo response is expected by + * the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + /* + * An event from firmware indicating who has been selected as the + * PHC Master or secondary. Also indicates the last time a failover + * happens. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER \ + UINT32_C(0x43) + /* + * An event from firmware showing the last PPS timestamp that has been + * latched. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + /* + * An event from firmware indicating that an error has occurred. + * The driver should log the event so that an administrator can be + * aware that a problem has occurred that may need attention. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) /* Maximum Registrable event id. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ - UINT32_C(0x42) + UINT32_C(0x46) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -7668,6 +7858,9 @@ struct hwrm_async_event_cmpl_dcb_config_change { /* APP configuration change */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ UINT32_C(0x4) + /* DSCP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP \ + UINT32_C(0x8) uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -8014,6 +8207,18 @@ struct hwrm_async_event_cmpl_reset_notify { HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY /* Event specific data. The data is for internal debug use only. */ uint32_t event_data2; + /* + * These bits indicate the status as being reported by the firmware. + * This value is exactly the same as status code in fw_status register. + * If the status code is equal to 0x8000, then the reset is initiated + * by the Host using the FW_RESET command when the FW is in a healthy + * state. If the status code is not equal to 0x8000, then the reset is + * initiated by the FW to recover from the error or FATAL state. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \ + 0 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -8075,8 +8280,11 @@ struct hwrm_async_event_cmpl_reset_notify { /* A non-fatal firmware exception has occurred. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ (UINT32_C(0x3) << 8) + /* Fast reset */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ + (UINT32_C(0x4) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -8667,6 +8875,17 @@ struct hwrm_async_event_cmpl_vf_cfg_change { HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE /* Event specific data */ uint32_t event_data2; + /* + * This value indicates the VF ID of the VF whose configuration + * is changing if this async. event is sent to the parent PF. + * The firmware supports sending this to the parent PF if the + * `hwrm_func_qcaps.vf_cfg_async_for_pf_supported` value is 1. + * This value is undefined when the async. event is sent to the + * VF. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -9511,6 +9730,278 @@ struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { 8 } __rte_packed; +/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ +struct hwrm_async_event_cmpl_echo_request { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An echo request from the firmware. An echo response is expected by + * the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST + /* Event specific data that should be provided in the echo response */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data that should be provided in the echo response */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_phc_master (size:128b/16B) */ +struct hwrm_async_event_cmpl_phc_master { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async event is used to notify driver of changes + * in PHC master. Only one master function can configure + * PHC. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER \ + UINT32_C(0x43) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER + /* Event specific data */ + uint32_t event_data2; + /* This field provides the current master function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT \ + 0 + /* This field provides the current secondary function. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT \ + 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates to the driver the type of PHC event. */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK \ + UINT32_C(0xf) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT \ + 0 + /* + * Indicates PHC Master selection event. The master fid is + * specified in event_data2.phc_master_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER \ + UINT32_C(0x1) + /* + * Indicates PHC Secondary selection event. The secondary fid is + * specified in event_data2.phc_sec_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY \ + UINT32_C(0x2) + /* + * Indicates PHC failover event. Failover happens from + * event_data2.phc_master_fid to event_data2.phc_sec_fid. + */ + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST \ + HWRM_ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER +} __rte_packed; + +/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ +struct hwrm_async_event_cmpl_pps_timestamp { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message can be used to inform + * driver of the latest PPS timestamp that has been latched. + * When driver enables PPS event, Firmware will generate + * PPS timestamps every second, Firmware informs driver + * of this timestamp through the async event. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP \ + UINT32_C(0x44) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP + /* Event specific data */ + uint32_t event_data2; + /* Indicates the PPS event type */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE \ + UINT32_C(0x1) + /* This is an internal event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL \ + UINT32_C(0x0) + /* This is an external event. */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL + /* + * Indicates the pin number on which the event is + * received. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK \ + UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT \ + 1 + /* + * Contains bits[47:32] of the upper PPS timestamp. + * Lower 32 bits are in event_data1. Together they + * provide the 48 bit PPS timestamp. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT \ + 4 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Contains the lower 32 bits of the PPS timestamp. */ + uint32_t event_data1; + /* Contains the lower 32 bit PPS timestamp */ + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT \ + 0 +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * Indicates the type of error being reported. See section on Error + * Report event error_types for details on each error. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 +} __rte_packed; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -9681,6 +10172,220 @@ struct hwrm_async_event_cmpl_hwrm_error { UINT32_C(0x1) } __rte_packed; +/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_base { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* Reserved */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED \ + UINT32_C(0x0) + /* + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) + /* + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_pause_storm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * The NIC was subjected to an extended pause storm which caused it + * to disable flow control in order to avoid stalling the Tx path. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_invalid_signal { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the TSIO pin on which invalid signal is detected. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * The NIC received an interrupt storm on a TSIO pin being used as + * PPS_IN which caused it to disable the interrupt. The signal + * should be fixed to be a proper 1 PPS signal before re-enabling + * it. The pin number on which this signal was received is stored + * in event_data2 as pin_id. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11131,6 +11836,102 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ UINT32_C(0x80) + /* + * If set to 1, then this function doesn't have the privilege to + * configure the EVB mode of the port it uses. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \ + UINT32_C(0x100) + /* + * If set to 1, then the HW and FW support the SoC packet DMA + * datapath between SoC and NIC. This function can act as the + * HWRM communication transport agent on behalf of the SoC SPD + * software module. This capability is only advertised to the + * SoC PFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \ + UINT32_C(0x200) + /* + * If set to 1, then this function supports FW_LIVEPATCH for + * firmware livepatch commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates that core firmware is + * capable of fast Reset. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \ + UINT32_C(0x800) + /* + * When this bit is '1', it indicates that firmware and hardware + * are capable of updating tx_metadata via hwrm_ring_cfg command. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \ + UINT32_C(0x1000) + /* + * If set to 1, then the device can report the action + * needed to activate set nvm options. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \ + UINT32_C(0x2000) + /* + * When this bit is '1', it indicates that the BD metadata feature + * is supported for this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that the echo request feature + * is supported for this function. If the driver registers for the + * echo request asynchronous event, then the firmware can send an + * unsolicited echo request to the driver and expect an echo + * response. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \ + UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that core firmware supports + * NPAR 1.2 on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED \ + UINT32_C(0x10000) + /* When this bit is '1', it indicates that PTM feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED \ + UINT32_C(0x20000) + /* When this bit is '1', it indicates that PPS feature is supported. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED \ + UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that VF config. change + * async event is supported on the parent PF if the async. + * event is registered by the PF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED \ + UINT32_C(0x80000) + /* + * When this bit is '1', the NIC supports configuration of + * partition_min_bw and partition_max_bw. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED \ + UINT32_C(0x100000) + /* + * When this bit is '1', the FW supports configuration of + * PCP and TPID values of the default VLAN. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED \ + UINT32_C(0x200000) + /* When this bit is '1', it indicates that HW and FW support KTLS. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED \ + UINT32_C(0x400000) + /* + * When this bit is '1', the firmware supports HWRM_PORT_EP_TX_CFG + * and HWRM_PORT_EP_TX_QCFG for endpoint rate control, and additions + * to HWRM_QUEUE_GLOBAL_CFG and HWRM_QUEUE_GLOBAL_QCFG for receive + * rate control. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL \ + UINT32_C(0x800000) /* The maximum number of SCHQs supported by this device. */ uint8_t max_schqs; uint8_t mpc_chnls_cap; @@ -11169,8 +11970,9 @@ struct hwrm_func_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -11221,7 +12023,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:768b/96B) */ +/* hwrm_func_qcfg_output (size:832b/104B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11294,6 +12096,8 @@ struct hwrm_func_qcfg_output { UINT32_C(0x10) /* * If set to 1, then multi-host mode is active for this function. + * The NIC is attached to two or more independent host systems + * through two or more PCIe endpoints. * If set to 0, then multi-host mode is inactive for this function * or not applicable for this device. */ @@ -11347,6 +12151,32 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \ UINT32_C(0x800) + /* + * If set to 1, then the firmware and all currently registered driver + * instances support fast reset. The fast reset support will be + * updated dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * fast reset. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \ + UINT32_C(0x1000) + /* + * If set to 1, then multi-root mode is active for this function. + * The NIC is attached to a single host with a single operating + * system, but through two or more PCIe endpoints. + * If set to 0, then multi-root mode is inactive for this function + * or not applicable for this device. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \ + UINT32_C(0x2000) + /* + * This flag indicates RDMA support for child VFS of + * a physical function. + * If set to 1, RoCE is supported on all child VFs. + * If set to 0, RoCE is disabled on all child VFs. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV \ + UINT32_C(0x4000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -11390,12 +12220,15 @@ struct hwrm_func_qcfg_output { /* The allocated number of vnics to the function. */ uint16_t alloc_vnics; /* - * The maximum transmission unit of the function. - * If the reported mtu value is non-zero then it will used for the - * rings allocated on this function. otherwise the default + * The maximum transmission unit of the function + * configured by the admin pf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default * value is used if ring MTU is not specified. + * The driver cannot use any MTU bigger than this value + * if it is non-zero. */ - uint16_t mtu; + uint16_t admin_mtu; /* * The maximum receive unit of the function. * For vnics allocated on this function, this default @@ -11419,6 +12252,8 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) /* Network Partitioning 2.0 */ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Network Partitioning 1.2 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5) /* Unknown */ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ UINT32_C(0xff) @@ -11442,11 +12277,9 @@ struct hwrm_func_qcfg_output { uint16_t dflt_vnic_id; uint16_t max_mtu_configured; /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates the minimum bandwidth is not - * configured. + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. */ uint32_t min_bw; /* The bandwidth value. */ @@ -11480,7 +12313,7 @@ struct hwrm_func_qcfg_output { /* Value is in Gb or GB (base 10). */ #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ + /* Value is in 1/100th of a percentage of link bandwidth. */ #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ @@ -11489,11 +12322,9 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates that the maximum bandwidth is not - * configured. + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. */ uint32_t max_bw; /* The bandwidth value. */ @@ -11527,7 +12358,7 @@ struct hwrm_func_qcfg_output { /* Value is in Gb or GB (base 10). */ #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ + /* Value is in 1/100th of a percentage of link bandwidth. */ #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ @@ -11696,7 +12527,94 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ UINT32_C(0x10) - uint8_t unused_2[6]; + uint8_t unused_2[3]; + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. + * The format of this field is defined to match min_bw, even though + * the partition minimum rate is always specified as a percentage. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Always percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Bandwidth value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though + * the partition bandwidth must be specified as a percentage. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware never sets + * this field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Always a percentage of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum transmission unit of the function + * configured by the host pf/vf. + * If the reported mtu value is non-zero then it will be used for the + * rings allocated on this function, otherwise the default + * value is used if ring MTU is not specified. + */ + uint16_t host_mtu; + uint8_t unused_3; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11712,7 +12630,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:768b/96B) */ +/* hwrm_func_cfg_input (size:832b/104B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -11962,12 +12880,26 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ UINT32_C(0x10000000) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \ + UINT32_C(0x20000000) + /* + * If this bit is set to 1, the driver is requesting FW to disable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \ + UINT32_C(0x40000000) uint32_t enables; /* - * This bit must be '1' for the mtu field to be + * This bit must be '1' for the admin_mtu field to be * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU \ UINT32_C(0x1) /* * This bit must be '1' for the mru field to be @@ -12120,6 +13052,33 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \ UINT32_C(0x2000000) /* + * This bit must be '1' for the partition_min_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW \ + UINT32_C(0x4000000) + /* + * This bit must be '1' for the partition_max_bw field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW \ + UINT32_C(0x8000000) + /* + * This bit must be '1' for the tpid field to be + * configured. This bit is only valid when dflt_vlan enable + * bit is set. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID \ + UINT32_C(0x10000000) + /* + * This bit must be '1' for the host_mtu field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ + UINT32_C(0x20000000) + /* + * This field can be used by the admin PF to configure + * mtu of foster PFs. * The maximum transmission unit of the function. * The HWRM should make sure that the mtu of * the function does not exceed the mtu of the physical @@ -12132,7 +13091,7 @@ struct hwrm_func_cfg_input { * The HWRM should make sure that the mtu of each transmit * ring that is assigned to a function has a valid mtu. */ - uint16_t mtu; + uint16_t admin_mtu; /* * The maximum receive unit of the function. * The HWRM should make sure that the mru of @@ -12196,9 +13155,9 @@ struct hwrm_func_cfg_input { */ uint32_t dflt_ip_addr[4]; /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * Minimum guaranteed transmit bandwidth for this function. When + * specified for a PF, does not affect traffic from the PF's child VFs. + * A value of 0 indicates the minimum bandwidth is not configured. */ uint32_t min_bw; /* The bandwidth value. */ @@ -12241,9 +13200,9 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * Maximum transmit rate for this function. When specified for a PF, + * does not affect traffic from the PF's child VFs. + * A value of 0 indicates that the maximum bandwidth is not configured. */ uint32_t max_bw; /* The bandwidth value. */ @@ -12322,16 +13281,27 @@ struct hwrm_func_cfg_input { */ uint8_t allowed_vlan_pris; /* - * The HWRM shall allow a PF driver to change EVB mode for the - * partition it belongs to. - * The HWRM shall not allow a VF driver to change the EVB mode. - * The HWRM shall take into account the switching of EVB mode - * from one to another and reconfigure hardware resources as - * appropriately. - * The switching from VEB to VEPA mode requires - * the disabling of the loopback traffic. Additionally, - * source knock outs are handled differently in VEB and VEPA - * modes. + * The evb_mode is configured on a per port basis. The default evb_mode + * is configured based on the NVM EVB mode setting upon firmware + * initialization. The HWRM allows a PF driver to change EVB mode for a + * port used by the PF only when one of the following conditions is + * satisfied. + * 1. The current operating mode is single function mode. + * (ie. one PF per port) + * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the + * EVB mode of the port used by the PAXC PF. None of the X86 PFs + * should have privileges. + * The HWRM doesn't permit any PFs to change the underlying EVB mode + * when running as MHB or NPAR mode in performance NIC configuration. + * The HWRM doesn't permit a VF driver to change the EVB mode. + * Once the HWRM determines a function doesn't meet the conditions + * to configure the EVB mode, it sets the evb_mode_cfg_not_supported + * flag in HWRM_FUNC_QCAPS command response for the function. + * The HWRM takes into account the switching of EVB mode from one to + * another and reconfigure hardware resources as reqiured. The + * switching from VEB to VEPA mode requires the disabling of the + * loopback traffic. Additionally, source knockouts are handled + * differently in VEB and VEPA modes. */ uint8_t evb_mode; /* No Edge Virtual Bridging (EVB) */ @@ -12452,7 +13422,111 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \ UINT32_C(0x200) - uint8_t unused_0[4]; + /* + * Minimum guaranteed bandwidth for the network partition made up + * of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no minimum bandwidth is configured. The sum of the + * minimum bandwidths for all partitions on a link must not exceed + * 100%. + * The format of this field is defined to match min_bw, even though + * it does not allow all the options for min_bw at this time. + */ + uint32_t partition_min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The maximum bandwidth that may be used by the network partition + * made up of the caller physical function and all its child virtual + * functions. The rate is specified as a percentage of the bandwidth + * of the link the partition is associated with. A value of 0 + * indicates that no maximum bandwidth is configured. + * The format of this field is defined to match max_bw, even though it + * does not allow all the options for max_bw at this time. + */ + uint32_t partition_max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT \ + 0 + /* + * The granularity of the value (bits or bytes). Firmware ignores + * this field. + */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES + /* Bandwidth units. Must be set to percent1_100. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in hundredths of a percent of link bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 + /* + * The TPID for the function for which default VLAN + * is configured. If the dflt_vlan is not specified + * with the TPID, FW returns error. If the TPID is + * not specified with dflt_vlan, the default TPID of + * 0x8100 will be used. This field is specified in + * network byte order. + */ + uint16_t tpid; + /* + * This field can be used by the host PF to configure + * mtu value. + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t host_mtu; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -13007,6 +14081,28 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ UINT32_C(0x40) + /* + * When this bit is 1, the function is indicating the support of the + * fast reset capability. Fast reset support will be used by + * firmware only if all the driver instances support fast reset + * process. By setting this bit, driver is indicating support for + * corresponding async event completion message. These will be + * delivered to the driver even if they did not register for it. + * If supported, after receiving reset notify async event with fast + * reset flag set in event data1, then all the drivers have to tear + * down their resources without sending any HWRM commands to FW. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \ + UINT32_C(0x80) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the vnic_rss_cfg's INVALID_PARAM error + * returned by firmware. Firmware returns error, if host driver + * configures the invalid hash_types bit combination for a given + * IP version. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ + UINT32_C(0x100) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -13810,7 +14906,7 @@ struct hwrm_func_backing_store_qcaps_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ +/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -13924,16 +15020,129 @@ struct hwrm_func_backing_store_qcaps_output { * before the first time context load. */ uint8_t ctx_kind_initializer; - /* Reserved for future. */ - uint32_t rsvd; - /* Reserved for future. */ - uint16_t rsvd1; + /* + * Specifies which context kinds need to be initialized with the + * ctx_kind_initializer. + */ + uint16_t ctx_init_mask; + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \ + UINT32_C(0x1) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \ + UINT32_C(0x2) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \ + UINT32_C(0x4) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \ + UINT32_C(0x8) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \ + UINT32_C(0x10) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \ + UINT32_C(0x20) + /* + * If this bit is '1' then the Tx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC \ + UINT32_C(0x40) + /* + * If this bit is '1' then the Rx KTLS context type should be + * initialized with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC \ + UINT32_C(0x80) + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t qp_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t srq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t cq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t vnic_init_offset; /* * Count of TQM fastpath rings to be used for allocating backing store. * Backing store configuration must be specified for each TQM ring from * this count in `backing_store_cfg`. + * Only first 8 TQM FP rings will be advertised with this field. */ uint8_t tqm_fp_rings_count; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t stat_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t mrav_init_offset; + /* + * Count of TQM extended fastpath rings to be used for allocating + * backing store beyond 8 rings(rings 9,10,11) + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count_ext; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Tx + * KTLS context type. + */ + uint8_t tkc_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for Rx + * KTLS context type. + */ + uint8_t rkc_init_offset; + /* Tx KTLS context entry size in bytes. */ + uint16_t tkc_entry_size; + /* Rx KTLS context entry size in bytes. */ + uint16_t rkc_entry_size; + /* + * Maximum number of Tx KTLS context entries supported for this + * function. + */ + uint32_t tkc_max_entries; + /* + * Maximum number of Rx KTLS context entries supported for this + * function. + */ + uint32_t rkc_max_entries; + /* Reserved for future. */ + uint8_t rsvd[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -13944,12 +15153,65 @@ struct hwrm_func_backing_store_qcaps_output { uint8_t valid; } __rte_packed; +/* tqm_fp_ring_cfg (size:128b/16B) */ +struct tqm_fp_ring_cfg { + /* TQM ring page size and level. */ + uint8_t tqm_ring_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 + /* 4KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G + uint8_t unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring_page_dir; +} __rte_packed; + /******************************* * hwrm_func_backing_store_cfg * *******************************/ -/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ +/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ struct hwrm_func_backing_store_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14091,6 +15353,36 @@ struct hwrm_func_backing_store_cfg_input { */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC \ + UINT32_C(0x100000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -14956,6 +16248,258 @@ struct hwrm_func_backing_store_cfg_input { uint16_t mrav_entry_size; /* Number of bytes that have been allocated for each context entry. */ uint16_t tim_entry_size; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries allocated. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries allocated. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Number of bytes allocated for each Tx KTLS context entry. */ + uint16_t tkc_entry_size; + /* Number of bytes allocated for each Rx KTLS context entry. */ + uint16_t rkc_entry_size; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G + /* Reserved for future. */ + uint8_t rsvd[2]; } __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -15016,7 +16560,7 @@ struct hwrm_func_backing_store_qcfg_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ +/* hwrm_func_backing_store_qcfg_output (size:2496b/312B) */ struct hwrm_func_backing_store_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15041,103 +16585,133 @@ struct hwrm_func_backing_store_qcfg_output { */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \ UINT32_C(0x2) - uint8_t unused_0[4]; + uint32_t enables; /* * This bit must be '1' for the qp fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \ UINT32_C(0x1) /* * This bit must be '1' for the srq fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \ UINT32_C(0x2) /* * This bit must be '1' for the cq fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \ UINT32_C(0x4) /* * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \ UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \ UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \ UINT32_C(0x20) /* * This bit must be '1' for the tqm_ring0 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \ UINT32_C(0x40) /* * This bit must be '1' for the tqm_ring1 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \ UINT32_C(0x80) /* * This bit must be '1' for the tqm_ring2 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \ UINT32_C(0x100) /* * This bit must be '1' for the tqm_ring3 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \ UINT32_C(0x200) /* * This bit must be '1' for the tqm_ring4 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \ UINT32_C(0x400) /* * This bit must be '1' for the tqm_ring5 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \ UINT32_C(0x800) /* * This bit must be '1' for the tqm_ring6 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \ UINT32_C(0x1000) /* * This bit must be '1' for the tqm_ring7 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \ UINT32_C(0x2000) /* * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \ UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \ UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the Tx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the Rx KTLS context + * fields to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC \ + UINT32_C(0x100000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -15881,7 +17455,256 @@ struct hwrm_func_backing_store_qcfg_output { uint32_t mrav_num_entries; /* Number of Timer entries. */ uint32_t tim_num_entries; - uint8_t unused_1[7]; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; + /* Number of Tx KTLS context entries. */ + uint32_t tkc_num_entries; + /* Number of Rx KTLS context entries. */ + uint32_t rkc_num_entries; + /* Tx KTLS context page directory. */ + uint64_t tkc_page_dir; + /* Rx KTLS context page directory. */ + uint64_t rkc_page_dir; + /* Tx KTLS context page size and level. */ + uint8_t tkc_pg_size_tkc_lvl; + /* Tx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 + /* Tx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G + /* Rx KTLS context page size and level. */ + uint8_t rkc_pg_size_rkc_lvl; + /* Rx KTLS context PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 + /* Rx KTLS context page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as 1 @@ -16307,6 +18130,66 @@ struct hwrm_error_recovery_qcfg_output { uint8_t valid; } __rte_packed; +/*************************** + * hwrm_func_echo_response * + ****************************/ + + +/* hwrm_func_echo_response_input (size:192b/24B) */ +struct hwrm_func_echo_response_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * 0x0-0xFFF8 - The function ID + * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * 0xFFFD - Reserved for user-space HWRM interface + * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t event_data1; + uint32_t event_data2; +} __rte_packed; + +/* hwrm_func_echo_response_output (size:128b/16B) */ +struct hwrm_func_echo_response_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_func_vlan_qcfg * ***********************/ @@ -16892,26 +18775,510 @@ struct hwrm_func_drv_if_change_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * When this bit is '1', the function driver is indicating - * that the IF state is changing to UP state. The call should - * be made at the beginning of the driver's open call before - * resources are allocated. After making the call, the driver - * should check the response to see if any resources may have - * changed (see the response below). If the driver fails - * the open call, the driver should make this call again with - * this bit cleared to indicate that the IF state is not UP. - * During the driver's close call when the IF state is changing - * to DOWN, the driver should make this call with the bit cleared - * after all resources have been freed. - */ - #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) - uint32_t unused; + uint32_t flags; + /* + * When this bit is '1', the function driver is indicating + * that the IF state is changing to UP state. The call should + * be made at the beginning of the driver's open call before + * resources are allocated. After making the call, the driver + * should check the response to see if any resources may have + * changed (see the response below). If the driver fails + * the open call, the driver should make this call again with + * this bit cleared to indicate that the IF state is not UP. + * During the driver's close call when the IF state is changing + * to DOWN, the driver should make this call with the bit cleared + * after all resources have been freed. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) + uint32_t unused; +} __rte_packed; + +/* hwrm_func_drv_if_change_output (size:128b/16B) */ +struct hwrm_func_drv_if_change_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', it indicates that the resources reserved + * for this function may have changed. The driver should check + * resource capabilities and reserve resources again before + * allocating resources. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the firmware got changed / reset. + * The driver should do complete re-initialization when that bit is set. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \ + UINT32_C(0x2) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_host_pf_ids_query * + *******************************/ + + +/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */ +struct hwrm_func_host_pf_ids_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t host; + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to SOC host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP0 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP1 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP2 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8) + /* + * # If this bit is set to '1', the query will contain PF(s) + * belongs to EP3 host. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10) + /* + * This provides a filter of what PF(s) will be returned in the + * query.. + */ + uint8_t filter; + /* + * all available PF(s) belong to the host(s) (defined in the + * host field). This includes the hidden PFs. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0) + /* + * all available PF(s) belong to the host(s) (defined in the + * host field) that is available for L2 traffic. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1) + /* + * all available PF(s) belong to the host(s) (defined in the + * host field) that is available for ROCE traffic. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2) + #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ + HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ +struct hwrm_func_host_pf_ids_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This provides the first PF ID of the device. */ + uint16_t first_pf_id; + uint16_t pf_ordinal_mask; + /* + * When this bit is '1', it indicates first PF belongs to one of + * the hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates 2nd PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates 3rd PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates 4th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates 5th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates 6th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates 7th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates 8th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates 9th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates 10th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \ + UINT32_C(0x200) + /* + * When this bit is '1', it indicates 11th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates 12th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \ + UINT32_C(0x800) + /* + * When this bit is '1', it indicates 13th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \ + UINT32_C(0x1000) + /* + * When this bit is '1', it indicates 14th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \ + UINT32_C(0x2000) + /* + * When this bit is '1', it indicates 15th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates 16th PF belongs to one of the + * hosts defined in the input request. + */ + #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \ + UINT32_C(0x8000) + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_spd_cfg * + *********************/ + + +/* hwrm_func_spd_cfg_input (size:384b/48B) */ +struct hwrm_func_spd_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Set this bit is '1' to enable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1) + /* Set this bit is '1' to disable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2) + /* + * Set this bit is '1' to enable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4) + /* + * Set this bit is '1' to disable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8) + /* + * Set this bit is '1' to enable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10) + /* + * Set this bit is '1' to disable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20) + uint32_t enables; + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the hash_mode_flags field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hash_type field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ring_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the hash_key_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \ + UINT32_C(0x10) + /* + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. + */ + uint16_t ethertype; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1; + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; +} __rte_packed; + +/* hwrm_func_spd_cfg_output (size:128b/16B) */ +struct hwrm_func_spd_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_spd_qcfg * + **********************/ + + +/* hwrm_func_spd_qcfg_input (size:128b/16B) */ +struct hwrm_func_spd_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; } __rte_packed; -/* hwrm_func_drv_if_change_output (size:128b/16B) */ -struct hwrm_func_drv_if_change_output { +/* hwrm_func_spd_qcfg_output (size:512b/64B) */ +struct hwrm_func_spd_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16922,226 +19289,110 @@ struct hwrm_func_drv_if_change_output { uint16_t resp_len; uint32_t flags; /* - * When this bit is '1', it indicates that the resources reserved - * for this function may have changed. The driver should check - * resource capabilities and reserve resources again before - * allocating resources. - */ - #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates that the firmware got changed / reset. - * The driver should do complete re-initialization when that bit is set. - */ - #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \ - UINT32_C(0x2) - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/******************************* - * hwrm_func_host_pf_ids_query * - *******************************/ - - -/* hwrm_func_host_pf_ids_query_input (size:192b/24B) */ -struct hwrm_func_host_pf_ids_query_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The SPD datapath forwarding is currently enabled when this + * flag is set to '1'. */ - uint16_t target_id; + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The SPD datapath checksum feature is currently enabled when + * this flag is set to '1'. */ - uint64_t resp_addr; - uint8_t host; + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2) /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to SOC host. + * The SPD datapath debug feature is currently enabled when + * this flag is set to '1'. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP0 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2) - /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP1 host. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4) + uint32_t hash_type; /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP2 host. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * # If this bit is set to '1', the query will contain PF(s) - * belongs to EP3 host. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * This provides a filter of what PF(s) will be returned in the - * query.. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - uint8_t filter; + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * all available PF(s) belong to the host(s) (defined in the - * host field). This includes the hidden PFs. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for L2 traffic. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1) + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * all available PF(s) belong to the host(s) (defined in the - * host field) that is available for ROCE traffic. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2) - #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ - HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE - uint8_t unused_1[6]; -} __rte_packed; - -/* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ -struct hwrm_func_host_pf_ids_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This provides the first PF ID of the device. */ - uint16_t first_pf_id; - uint16_t pf_ordinal_mask; + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates first PF belongs to one of - * the hosts defined in the input request. + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) /* - * When this bit is '1', it indicates 2nd PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ UINT32_C(0x2) /* - * When this bit is '1', it indicates 3rd PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ UINT32_C(0x4) /* - * When this bit is '1', it indicates 4th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ UINT32_C(0x8) /* - * When this bit is '1', it indicates 5th PF belongs to one of the - * hosts defined in the input request. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) + uint8_t unused_1; /* - * When this bit is '1', it indicates 6th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \ - UINT32_C(0x20) - /* - * When this bit is '1', it indicates 7th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \ - UINT32_C(0x40) - /* - * When this bit is '1', it indicates 8th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \ - UINT32_C(0x80) - /* - * When this bit is '1', it indicates 9th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \ - UINT32_C(0x100) - /* - * When this bit is '1', it indicates 10th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \ - UINT32_C(0x200) - /* - * When this bit is '1', it indicates 11th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \ - UINT32_C(0x400) - /* - * When this bit is '1', it indicates 12th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \ - UINT32_C(0x800) - /* - * When this bit is '1', it indicates 13th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \ - UINT32_C(0x1000) - /* - * When this bit is '1', it indicates 14th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \ - UINT32_C(0x2000) - /* - * When this bit is '1', it indicates 15th PF belongs to one of the - * hosts defined in the input request. - */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \ - UINT32_C(0x4000) - /* - * When this bit is '1', it indicates 16th PF belongs to one of the - * hosts defined in the input request. + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. */ - #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \ - UINT32_C(0x8000) - uint8_t unused_1[3]; + uint16_t ethertype; + uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18854,6 +21105,12 @@ struct hwrm_port_phy_qcfg_output { /* When this bit is '1', Media auto detect is enabled. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \ UINT32_C(0x1) + /* + * When this bit is '1', active_fec_signal_mode can be + * trusted. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \ + UINT32_C(0x2) /* * Up to 16 bytes of null padded ASCII string representing * PHY vendor. @@ -21432,13 +23689,23 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \ UINT32_C(0x20) /* - * Reserved field. The HWRM shall set this field to 0. - * An HWRM client shall ignore this field. + * If set to 1, then this field indicates that the + * PHY/Link down policy during PF shutdown is totally + * controlled by the firmware. It can shutdown the link + * even when there are active VFs associated with the PF. + * Host PF driver can send HWRM_PHY_CFG command to bring + * down the PHY even when the port is shared between VFs + * and PFs. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \ + UINT32_C(0x40) + /* + * If set to 1, this field indicates that the FCS may + * be disabled for a given packet via the transmit + * buffer descriptor. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xc0) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \ - 6 + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \ + UINT32_C(0x80) /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -23885,21 +26152,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id0; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id0_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -23923,21 +26190,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id1; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id1_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -23961,21 +26228,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id2; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id2_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -23999,21 +26266,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id3; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id3_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -24037,21 +26304,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id4; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id4_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -24075,21 +26342,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id5; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id5_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -24113,21 +26380,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id6; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id6_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -24151,21 +26418,21 @@ struct hwrm_queue_qportcfg_output { * # Available queues may not be in sequential order. */ uint8_t queue_id7; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id7_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -24173,7 +26440,22 @@ struct hwrm_queue_qportcfg_output { UINT32_C(0xff) #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN - uint8_t unused_0; + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id0_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* * Up to 16 bytes of null padded ASCII string describing this queue. * The queue name includes a CoS queue index and, in some cases, text @@ -24194,7 +26476,118 @@ struct hwrm_queue_qportcfg_output { char qid6_name[16]; /* Up to 16 bytes of null padded ASCII string describing this queue. */ char qid7_name[16]; - uint8_t unused_1[7]; + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id1_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id2_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id3_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id4_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id5_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id6_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id7_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -27700,6 +30093,343 @@ struct hwrm_queue_mplstc2pri_cfg_output { uint8_t valid; } __rte_packed; +/**************************** + * hwrm_queue_vlanpri_qcaps * + ****************************/ + + +/* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */ +struct hwrm_queue_vlanpri_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */ +struct hwrm_queue_vlanpri_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the default user priority which all VLAN priority values + * are mapped to if there is no VLAN priority to user priority mapping. + */ + uint8_t hw_default_pri; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_queue_vlanpri2pri_qcfg * + *******************************/ + + +/* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /******************* * hwrm_vnic_alloc * *******************/ @@ -27740,8 +30470,22 @@ struct hwrm_vnic_alloc_input { * When this bit is '1', this VNIC is requested to * be the default VNIC for this function. */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - uint8_t unused_0[4]; + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', proxy VEE PF is requesting + * allocation of a default VNIC on behalf of virtio-net + * function given in virtio_net_fid field. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \ + UINT32_C(0x2) + /* + * Virtio-net function's FID. + * This virtio-net function is requesting allocation of default + * VNIC through proxy VEE PF. + */ + uint16_t virtio_net_fid; + uint8_t unused_0[2]; } __rte_packed; /* hwrm_vnic_alloc_output (size:128b/16B) */ @@ -27767,6 +30511,132 @@ struct hwrm_vnic_alloc_output { uint8_t valid; } __rte_packed; +/******************** + * hwrm_vnic_update * + ********************/ + + +/* hwrm_vnic_update_input (size:256b/32B) */ +struct hwrm_vnic_update_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint32_t enables; + /* + * This bit must be '1' for the vnic_state field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the metadata_format_type field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \ + UINT32_C(0x4) + /* + * This will update the context variable with the same name if + * the corresponding enable is set. + */ + uint8_t vnic_state; + /* Normal operation state for the VNIC. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* All packets are dropped in this state. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \ + HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP + /* + * The metadata format type used in all the RX packet completions + * going through this VNIC. + */ + uint8_t metadata_format_type; + /* No metadata information. */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \ + UINT32_C(0x0) + /* + * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], + * vtag[19:0]). + */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \ + UINT32_C(0x1) + /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \ + UINT32_C(0x2) + /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \ + UINT32_C(0x3) + /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \ + UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \ + HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_vnic_update_output (size:128b/16B) */ +struct hwrm_vnic_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /****************** * hwrm_vnic_free * ******************/ @@ -28242,6 +31112,12 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) + /* + * When this bit is '0', VNIC is in normal operation state. + * When this bit is '1', VNIC drops all the received packets. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \ + UINT32_C(0x80) /* * When returned with a valid CoS Queue id, the CoS Queue/VNIC association * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS @@ -28388,7 +31264,7 @@ struct hwrm_vnic_qcaps_output { UINT32_C(0x20) /* * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. + * mirror the RoCE traffic is supported. * If set to '0', then the capability to mirror the * RoCE traffic is not supported. */ @@ -28422,6 +31298,32 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \ UINT32_C(0x200) + /* + * When this bit is '1', it indicates that HW and firmware support + * vnic state change. Host drivers can change the vnic state using + * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not + * support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates that firmware supports + * virtio-net functions default VNIC allocation using + * HWRM_VNIC_ALLOC. + * This capability is available only on Proxy VEE PF. If set to '0', + * firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \ + UINT32_C(0x800) + /* + * When this bit is set '1', then the capability to configure the + * metadata format in the RX completion is supported for the VNIC. + * When this bit is set to '0', then the capability to configure + * the metadata format in the RX completion is not supported for + * the VNIC. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ + UINT32_C(0x1000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -29115,7 +32017,7 @@ struct hwrm_vnic_plcmodes_cfg_input { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -29279,7 +32181,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint16_t hds_threshold; /* * When virtio placement algorithm is enabled, this - * value is used to determine the the maximum number of BDs + * value is used to determine the maximum number of BDs * that can be used to place an Rx Packet. * If an incoming packet does not fit in the buffers described * by the max BDs, the packet will be dropped and an error @@ -29796,7 +32698,20 @@ struct hwrm_ring_alloc_output { uint16_t ring_id; /* Logical number of ring allocated. */ uint16_t logical_ring_id; - uint8_t unused_0[3]; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -29812,7 +32727,7 @@ struct hwrm_ring_alloc_output { ******************/ -/* hwrm_ring_free_input (size:192b/24B) */ +/* hwrm_ring_free_input (size:256b/32B) */ struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; @@ -29858,10 +32773,37 @@ struct hwrm_ring_free_input { #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; + uint8_t flags; + /* + * If this bit is set to '1', ring_id in this command belongs to + * virtio function. prod_idx in this command corresponds to doorbell + * producer index. opaque field in this command needs to be inserted + * by firmware in VEE_FLUSH completion record. + * Firmware will poll the corresponding ring context to reach the + * given producer index before sending successful response. It will + * finish the completion using VEE_FLUSH completion record. + * + * If this bit is '0', firmware will not treat ring_id as virtio + * ring and ignore prod_idx, opaque fields. + * + * This feature is not applicable for L2 or RoCE. + */ + #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1) + #define HWRM_RING_FREE_INPUT_FLAGS_LAST \ + HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID /* Physical number of ring allocated. */ uint16_t ring_id; - uint8_t unused_1[4]; + /* + * Ring BD producer index posted by the virtio block. + * This field is valid if virtio_ring_valid flag is set. + */ + uint32_t prod_idx; + /* + * User defined opaque field to be inserted into VEE_FLUSH completion + * record. This field is valid if virtio_ring_valid flag is set. + */ + uint32_t opaque; + uint32_t unused_1; } __rte_packed; /* hwrm_ring_free_output (size:128b/16B) */ @@ -29957,7 +32899,20 @@ struct hwrm_ring_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[4]; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[3]; /* Position of consumer index after ring reset completes. */ uint8_t consumer_idx[3]; /* @@ -29975,7 +32930,7 @@ struct hwrm_ring_reset_output { *****************/ -/* hwrm_ring_cfg_input (size:256b/32B) */ +/* hwrm_ring_cfg_input (size:320b/40B) */ struct hwrm_ring_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -30062,6 +33017,16 @@ struct hwrm_ring_cfg_input { /* Update completion ring ID associated with Tx or Rx ring. */ #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \ UINT32_C(0x10) + /* + * When set to '1', metadata value provided by tx_metadata + * field in this command is inserted in the lb_header_metadata + * QP context field. When set to '0', no change done to metadata. + * Firmware rejects the tx ring metadata programming with + * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD + * metadata feature is not disabled. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \ + UINT32_C(0x20) /* * Proxy function FID value. * This value is only used when either proxy_mode_enable flag or @@ -30091,6 +33056,12 @@ struct hwrm_ring_cfg_input { */ uint8_t rx_sop_pad_bytes; uint8_t unused_1[3]; + /* + * When tx_metadata enable bit is set, value specified in this field + * is copied to lb_header_metadata in the QP context. + */ + uint32_t tx_metadata; + uint8_t unused_2[4]; } __rte_packed; /* hwrm_ring_cfg_output (size:128b/16B) */ @@ -30163,7 +33134,7 @@ struct hwrm_ring_qcfg_input { uint16_t ring_id; } __rte_packed; -/* hwrm_ring_qcfg_output (size:192b/24B) */ +/* hwrm_ring_qcfg_output (size:256b/32B) */ struct hwrm_ring_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -30242,7 +33213,10 @@ struct hwrm_ring_qcfg_output { * This value is only used when rx_sop_pad_enable flag is set to '1'. */ uint8_t rx_sop_pad_bytes; - uint8_t unused_0[6]; + uint8_t unused_0[3]; + /* lb_header_metadata in the QP context is copied to this field. */ + uint32_t tx_metadata; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -31686,12 +34660,15 @@ struct hwrm_cfa_l2_filter_alloc_input { UINT32_C(0x1) #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ UINT32_C(0x4) @@ -31985,13 +34962,19 @@ struct hwrm_cfa_l2_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -32107,8 +35090,9 @@ struct hwrm_cfa_l2_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32170,8 +35154,9 @@ struct hwrm_cfa_l2_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32228,8 +35213,8 @@ struct hwrm_cfa_l2_filter_cfg_input { #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ UINT32_C(0x2) @@ -32298,8 +35283,9 @@ struct hwrm_cfa_l2_filter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32480,8 +35466,9 @@ struct hwrm_cfa_l2_set_rx_mask_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32573,8 +35560,9 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32653,8 +35641,9 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -32695,7 +35684,10 @@ struct hwrm_cfa_tunnel_filter_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) uint32_t enables; @@ -32838,13 +35830,19 @@ struct hwrm_cfa_tunnel_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -32963,8 +35961,9 @@ struct hwrm_cfa_tunnel_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33023,8 +36022,9 @@ struct hwrm_cfa_tunnel_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33098,13 +36098,19 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -33114,7 +36120,10 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* Tunnel alloc flags. */ uint8_t flags; - /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ + /* + * Setting of this flag indicates modify existing redirect tunnel + * to new destination function ID. + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ UINT32_C(0x1) uint8_t unused_0[4]; @@ -33135,8 +36144,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33210,13 +36220,19 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -33242,8 +36258,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33317,13 +36334,19 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -33351,8 +36374,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33455,7 +36479,10 @@ struct hwrm_cfa_encap_data_vxlan { uint16_t dst_port; /* VXLAN Network Identifier. */ uint32_t vni; - /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ + /* + * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN + * header. + */ uint8_t hdr_rsvd0[3]; /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ uint8_t hdr_rsvd1; @@ -33500,13 +36527,16 @@ struct hwrm_cfa_encap_record_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) /* - * Setting of this flag indicates this encap record is external encap record. - * Resetting of this flag indicates this flag is internal encap record and - * this is the default setting. + * Setting of this flag indicates this encap record is external + * encap record. Resetting of this flag indicates this flag is + * internal encap record and this is the default setting. */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ UINT32_C(0x2) @@ -33539,13 +36569,19 @@ struct hwrm_cfa_encap_record_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ @@ -33572,8 +36608,9 @@ struct hwrm_cfa_encap_record_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33633,8 +36670,9 @@ struct hwrm_cfa_encap_record_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -33675,39 +36713,44 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ UINT32_C(0x2) /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ UINT32_C(0x4) /* - * Setting of this flag indicates that the dst_id field contains function ID. - * If this is not set it indicates dest_id is VNIC or VPORT. + * Setting of this flag indicates that the dst_id field contains + * function ID. If this is not set it indicates dest_id is VNIC + * or VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ UINT32_C(0x8) /* - * Setting of this flag indicates match on arp reply when ethertype is 0x0806. - * If this is not set it indicates no specific arp opcode matching. + * Setting of this flag indicates match on arp reply when ethertype + * is 0x0806. If this is not set it indicates no specific arp opcode + * matching. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ UINT32_C(0x10) /* - * Setting of this flag indicates that the dst_id field contains RFS ring - * table index. If this is not set it indicates dst_id is VNIC or VPORT - * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at - * the same time. + * Setting of this flag indicates that the dst_id field contains RFS + * ring table index. If this is not set it indicates dst_id is VNIC + * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) @@ -33928,13 +36971,19 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -34071,8 +37120,9 @@ struct hwrm_cfa_ntuple_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34149,8 +37199,9 @@ struct hwrm_cfa_ntuple_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34212,15 +37263,16 @@ struct hwrm_cfa_ntuple_filter_cfg_input { uint32_t flags; /* * Setting this bit to 1 indicates that dest_id field contains FID. - * Setting this to 0 indicates that dest_id field contains VNIC or VPORT. + * Setting this to 0 indicates that dest_id field contains VNIC or + * VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ UINT32_C(0x1) /* * Setting of this flag indicates that the new_dst_id field contains - * RFS ring table index. If this is not set it indicates new_dst_id is - * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx - * can’t be set at the same time. + * RFS ring table index. If this is not set it indicates new_dst_id + * is VNIC or VPORT or function ID. Note dest_fid and + * dest_rfs_ring_idx can’t be set at the same time. */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x2) @@ -34270,8 +37322,9 @@ struct hwrm_cfa_ntuple_filter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34325,28 +37378,34 @@ struct hwrm_cfa_em_flow_alloc_input { #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX /* - * Setting of this flag indicates enabling of a byte counter for a given - * flow. + * Setting of this flag indicates enabling of a byte counter for a + * given flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) /* - * Setting of this flag indicates enabling of a packet counter for a given - * flow. + * Setting of this flag indicates enabling of a packet counter for a + * given flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) - /* Setting of this flag indicates de-capsulation action for the given flow. */ + /* + * Setting of this flag indicates de-capsulation action for the + * given flow. + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) - /* Setting of this flag indicates encapsulation action for the given flow. */ + /* + * Setting of this flag indicates encapsulation action for the + * given flow. + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) uint32_t enables; @@ -34495,13 +37554,19 @@ struct hwrm_cfa_em_flow_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -34676,8 +37741,9 @@ struct hwrm_cfa_em_flow_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34736,8 +37802,9 @@ struct hwrm_cfa_em_flow_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -34791,9 +37858,9 @@ struct hwrm_cfa_meter_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * Enumeration denoting the clock at which the Meter is running with. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the clock at which the Meter is running + * with. This enumeration is used for resources that are similar + * for both TX and RX paths of the chip. */ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 @@ -34849,8 +37916,9 @@ struct hwrm_cfa_meter_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35127,8 +38195,9 @@ struct hwrm_cfa_meter_profile_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35212,8 +38281,9 @@ struct hwrm_cfa_meter_profile_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35483,8 +38553,9 @@ struct hwrm_cfa_meter_profile_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35579,8 +38650,9 @@ struct hwrm_cfa_meter_instance_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35650,8 +38722,8 @@ struct hwrm_cfa_meter_instance_cfg_input { #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * This value identifies the ID of a meter instance that needs to be updated with - * a new meter profile specified in this command. + * This value identifies the ID of a meter instance that needs to be + * updated with a new meter profile specified in this command. */ uint16_t meter_instance_id; uint8_t unused_1[2]; @@ -35672,8 +38744,9 @@ struct hwrm_cfa_meter_instance_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35757,8 +38830,9 @@ struct hwrm_cfa_meter_instance_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -35945,13 +39019,19 @@ struct hwrm_cfa_decap_filter_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -36059,8 +39139,8 @@ struct hwrm_cfa_decap_filter_alloc_input { */ uint16_t dst_id; /* - * If set, this value shall represent the L2 context that matches the L2 - * information of the decap filter. + * If set, this value shall represent the L2 context that matches the + * L2 information of the decap filter. */ uint16_t l2_ctxt_ref_id; } __rte_packed; @@ -36082,8 +39162,9 @@ struct hwrm_cfa_decap_filter_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36143,8 +39224,9 @@ struct hwrm_cfa_decap_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36219,29 +39301,35 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * when set to 1, indicates TX flow offload for function specified in src_fid and - * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both - * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload - * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV - * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID - * belong to the children VFs of the same PF to indicate VM to VM flow. + * when set to 1, indicates TX flow offload for function specified + * in src_fid and the dst_fid should be set to invalid value. To + * indicate a VM to VM flow, both of the path_tx and path_rx flags + * need to be set. For virtio vSwitch offload case, the src_fid and + * dst_fid is set to the same fid value. For the SRIOV vSwitch + * offload case, the src_fid and dst_fid must be set to the same VF + * FID belong to the children VFs of the same PF to indicate VM to + * VM flow. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ UINT32_C(0x40) /* - * when set to 1, indicates RX flow offload for function specified in dst_fid and - * the src_fid should be set to invalid value. + * when set to 1, indicates RX flow offload for function specified + * in dst_fid and the src_fid should be set to invalid value. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ UINT32_C(0x80) /* - * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is - * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. - * This flag is only valid when the flow direction is RX. + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan + * header is required and the VXLAN VNI value is stored in the first + * 24 bits of the dmac field. This flag is only valid when the flow + * direction is RX. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ UINT32_C(0x100) - /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */ + /* + * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci + * field. + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ UINT32_C(0x200) /* @@ -36253,8 +39341,8 @@ struct hwrm_cfa_flow_alloc_input { uint32_t tunnel_handle; uint16_t action_flags; /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ UINT32_C(0x1) @@ -36262,8 +39350,8 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ UINT32_C(0x4) @@ -36289,10 +39377,10 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ UINT32_C(0x200) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. The type of tunnel - * is specified in the tunnel_type field. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. + * The type of tunnel is specified in the tunnel_type field. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ UINT32_C(0x400) @@ -36300,18 +39388,19 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ UINT32_C(0x800) /* - * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be - * placed to the default flow table resource. + * If set to 1 an attempt will be made to try to offload this flow + * to the most optimal flow table resource. If set to 0, the flow + * will be placed to the default flow table resource. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ UINT32_C(0x1000) /* - * If set to 1 there will be no attempt to allocate an on-chip try to - * offload this flow. If set to 0, which will keep compatibility with the - * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior - * with EM flows which always had an associated flow counter. + * If set to 1 there will be no attempt to allocate an on-chip try + * to offload this flow. If set to 0, which will keep compatibility + * with the older drivers, will cause the FW to attempt to allocate + * an on-chip flow counter for the newly created flow. This will + * keep the existing behavior with EM flows which always had an + * associated flow counter. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ UINT32_C(0x2000) @@ -36415,13 +39504,19 @@ struct hwrm_cfa_flow_alloc_input { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -36492,8 +39587,9 @@ struct hwrm_cfa_flow_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36589,8 +39685,9 @@ struct hwrm_cfa_flow_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36614,9 +39711,9 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ UINT32_C(0x10) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ UINT32_C(0x20) @@ -36663,11 +39760,17 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 @@ -36710,13 +39813,19 @@ struct hwrm_cfa_flow_tunnel_hdr_data { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ @@ -36923,8 +40032,9 @@ struct hwrm_cfa_flow_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -36967,32 +40077,39 @@ struct hwrm_cfa_flow_flush_input { /* flags is 32 b */ uint32_t flags; /* - * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr - * fields are valid. The flow flush operation should only flush the flows from the - * flow table specified. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * Set to 1 to indicate the page size, page layers, and + * flow_handle_table_dma_addr fields are valid. The flow flush + * operation should only flush the flows from the flow table + * specified. This flag is set to 0 by older driver. For older + * firmware, setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ UINT32_C(0x1) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables etc. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * Set to 1 to indicate flow flush operation to cleanup all the + * flows, meters, CFA context memory tables etc. This flag is set to + * 0 by older driver. For older firmware, setting this flag has no + * effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ UINT32_C(0x2) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller. - * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect. + * Set to 1 to indicate flow flush operation to cleanup all the + * flows by the caller. This flag is set to 0 by older driver. For + * older firmware, setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ UINT32_C(0x4) - /* Set to 1 to indicate the flow counter IDs are included in the flow table. */ + /* + * Set to 1 to indicate the flow counter IDs are included in the + * flow table. + */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ UINT32_C(0x8000000) /* - * This specifies the size of flow handle entries provided by the driver - * in the flow table specified below. Only two flow handle size enums are defined. + * This specifies the size of flow handle entries provided by the + * driver in the flow table specified below. Only two flow handle + * size enums are defined. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ UINT32_C(0xc0000000) @@ -37032,7 +40149,10 @@ struct hwrm_cfa_flow_flush_input { #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 @@ -37057,8 +40177,9 @@ struct hwrm_cfa_flow_flush_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37198,8 +40319,9 @@ struct hwrm_cfa_flow_stats_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37266,8 +40388,9 @@ struct hwrm_cfa_flow_aging_timer_reset_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37309,28 +40432,52 @@ struct hwrm_cfa_flow_aging_cfg_input { uint64_t resp_addr; /* The bit field to enable per flow aging configuration. */ uint16_t enables; - /* This bit must be '1' for the tcp flow timer field to be configured */ + /* + * This bit must be '1' for the tcp flow timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ UINT32_C(0x1) - /* This bit must be '1' for the tcp finish timer field to be configured */ + /* + * This bit must be '1' for the tcp finish timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ UINT32_C(0x2) - /* This bit must be '1' for the udp flow timer field to be configured */ + /* + * This bit must be '1' for the udp flow timer field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ UINT32_C(0x4) - /* This bit must be '1' for the eem dma interval field to be configured */ + /* + * This bit must be '1' for the eem dma interval field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ UINT32_C(0x8) - /* This bit must be '1' for the eem notice interval field to be configured */ + /* + * This bit must be '1' for the eem notice interval field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ UINT32_C(0x10) - /* This bit must be '1' for the eem context memory maximum entries field to be configured */ + /* + * This bit must be '1' for the eem context memory maximum entries + * field to be configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ UINT32_C(0x20) - /* This bit must be '1' for the eem context memory ID field to be configured */ + /* + * This bit must be '1' for the eem context memory ID field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ UINT32_C(0x40) - /* This bit must be '1' for the eem context memory type field to be configured */ + /* + * This bit must be '1' for the eem context memory type field to be + * configured + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ UINT32_C(0x80) uint8_t flags; @@ -37342,7 +40489,10 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the enable, disable eem flow aging configuration. */ + /* + * Enumeration denoting the enable, disable eem flow aging + * configuration. + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) /* tx path */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ @@ -37353,22 +40503,40 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE uint8_t unused_0; - /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */ + /* + * The flow aging timer for all TCP flows, the unit is 100 + * milliseconds. + */ uint32_t tcp_flow_timer; - /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */ + /* + * The TCP finished timer for all TCP flows, the unit is 100 + * milliseconds. + */ uint32_t tcp_fin_timer; - /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */ + /* + * The flow aging timer for all UDP flows, the unit is 100 + * milliseconds. + */ uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ uint16_t eem_notice_interval; /* The maximum entries number in the eem context memory. */ uint32_t eem_ctx_max_entries; /* The context memory ID for eem flow aging. */ uint16_t eem_ctx_id; uint16_t eem_ctx_mem_type; - /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */ + /* + * The content of context memory is eem ejection data, the size of + * each entry is 4 bytes. + */ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ UINT32_C(0x0) #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ @@ -37391,8 +40559,9 @@ struct hwrm_cfa_flow_aging_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37432,7 +40601,10 @@ struct hwrm_cfa_flow_aging_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ + /* + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. + */ uint8_t flags; /* Enumeration denoting the RX, TX type of the resource. */ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) @@ -37455,15 +40627,30 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The current flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t tcp_flow_timer; - /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The current TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t tcp_fin_timer; - /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */ + /* + * The current flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ uint16_t eem_notice_interval; /* The maximum entries number in the eem context memory. */ uint32_t eem_ctx_max_entries; @@ -37476,8 +40663,9 @@ struct hwrm_cfa_flow_aging_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37517,7 +40705,10 @@ struct hwrm_cfa_flow_aging_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ + /* + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. + */ uint8_t flags; /* Enumeration denoting the RX, TX type of the resource. */ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) @@ -37540,11 +40731,20 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The maximum flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t max_tcp_flow_timer; - /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */ + /* + * The maximum TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ uint32_t max_tcp_fin_timer; - /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */ + /* + * The maximum flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ uint32_t max_udp_flow_timer; /* The maximum aging flows that HW can support. */ uint32_t max_aging_flows; @@ -37553,8 +40753,9 @@ struct hwrm_cfa_flow_aging_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37610,17 +40811,24 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint16_t rx_ar_id_port0; /* The port 1 RX mirror action record ID. */ uint16_t rx_ar_id_port1; - /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */ + /* + * The port 0 RX action record ID for TX TCP flag packets from + * loopback path. + */ uint16_t tx_ar_id_port0; - /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */ + /* + * The port 1 RX action record ID for TX TCP flag packets from + * loopback path. + */ uint16_t tx_ar_id_port1; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37684,8 +40892,9 @@ struct hwrm_cfa_vf_pair_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37744,8 +40953,9 @@ struct hwrm_cfa_vf_pair_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37831,8 +41041,9 @@ struct hwrm_cfa_vf_pair_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -37895,10 +41106,16 @@ struct hwrm_cfa_pair_alloc_input { /* Modify existing rep2fn pair and move pair to new PF. */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \ UINT32_C(0x5) - /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */ + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \ UINT32_C(0x6) - /* Truflow pair between REP on local host with PF or VF on specified host. */ + /* + * Truflow pair between REP on local host with PF or VF on specified + * host. + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \ UINT32_C(0x7) #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \ @@ -37991,8 +41208,9 @@ struct hwrm_cfa_pair_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38056,9 +41274,15 @@ struct hwrm_cfa_pair_free_input { #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) /* Modify existing rep2fn pair and move pair to new PF. */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) - /* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */ + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) - /* Truflow pair between REP on local host with PF or VF on specified host. */ + /* + * Truflow pair between REP on local host with PF or VF on + * specified host. + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \ HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW @@ -38079,8 +41303,9 @@ struct hwrm_cfa_pair_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38200,8 +41425,9 @@ struct hwrm_cfa_pair_info_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38272,8 +41498,9 @@ struct hwrm_cfa_vfr_alloc_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38340,8 +41567,9 @@ struct hwrm_cfa_vfr_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38428,7 +41656,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ UINT32_C(0x200) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ UINT32_C(0x400) /* Any tunneled traffic */ @@ -38437,7 +41668,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ UINT32_C(0x1000) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ UINT32_C(0x2000) uint8_t unused_0[3]; @@ -38445,8 +41679,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38493,7 +41728,10 @@ struct hwrm_cfa_ctx_mem_rgtr_input { #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 @@ -38533,8 +41771,8 @@ struct hwrm_cfa_ctx_mem_rgtr_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[5]; @@ -38542,8 +41780,9 @@ struct hwrm_cfa_ctx_mem_rgtr_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38584,8 +41823,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[6]; @@ -38606,8 +41845,9 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38648,8 +41888,8 @@ struct hwrm_cfa_ctx_mem_qctx_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[6]; @@ -38672,7 +41912,10 @@ struct hwrm_cfa_ctx_mem_qctx_output { #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 @@ -38704,8 +41947,9 @@ struct hwrm_cfa_ctx_mem_qctx_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38757,15 +42001,19 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Indicates the maximum number of context memory which can be registered. */ + /* + * Indicates the maximum number of context memory which can be + * registered. + */ uint16_t max_entries; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -38831,53 +42079,53 @@ struct hwrm_cfa_counter_qcaps_output { HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT uint32_t unused_0; /* - * Minimum guaranteed number of flow counters supported for this function, - * in RX direction. + * Minimum guaranteed number of flow counters supported for this + * function, in RX direction. */ uint32_t min_rx_fc; /* - * Maximum non-guaranteed number of flow counters supported for this function, - * in RX direction. + * Maximum non-guaranteed number of flow counters supported for this + * function, in RX direction. */ uint32_t max_rx_fc; /* - * Minimum guaranteed number of flow counters supported for this function, - * in TX direction. + * Minimum guaranteed number of flow counters supported for this + * function, in TX direction. */ uint32_t min_tx_fc; /* - * Maximum non-guaranteed number of flow counters supported for this function, - * in TX direction. + * Maximum non-guaranteed number of flow counters supported for this + * function, in TX direction. */ uint32_t max_tx_fc; /* - * Minimum guaranteed number of extension flow counters supported for this - * function, in RX direction. + * Minimum guaranteed number of extension flow counters supported for + * this function, in RX direction. */ uint32_t min_rx_efc; /* - * Maximum non-guaranteed number of extension flow counters supported for - * this function, in RX direction. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in RX direction. */ uint32_t max_rx_efc; /* - * Minimum guaranteed number of extension flow counters supported for this - * function, in TX direction. + * Minimum guaranteed number of extension flow counters supported for + * this function, in TX direction. */ uint32_t min_tx_efc; /* - * Maximum non-guaranteed number of extension flow counters supported for - * this function, in TX direction. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in TX direction. */ uint32_t max_tx_efc; /* - * Minimum guaranteed number of meter drop counters supported for this - * function, in RX direction. + * Minimum guaranteed number of meter drop counters supported for + * this function, in RX direction. */ uint32_t min_rx_mdc; /* - * Maximum non-guaranteed number of meter drop counters supported for this - * function, in RX direction. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in RX direction. */ uint32_t max_rx_mdc; /* @@ -38886,19 +42134,23 @@ struct hwrm_cfa_counter_qcaps_output { */ uint32_t min_tx_mdc; /* - * Maximum non-guaranteed number of meter drop counters supported for this - * function, in TX direction. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in TX direction. */ uint32_t max_tx_mdc; - /* Maximum guaranteed number of flow counters which can be used during flow alloc. */ + /* + * Maximum guaranteed number of flow counters which can be used during + * flow alloc. + */ uint32_t max_flow_alloc_fc; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39009,8 +42261,9 @@ struct hwrm_cfa_counter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39084,8 +42337,9 @@ struct hwrm_cfa_counter_qstats_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39215,17 +42469,21 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ UINT32_C(0x8) /* - * If set to 1, then FID table used for implicit flow flush is supported. - * If set to 0, then FID table used for implicit flow flush is not supported. + * If set to 1, then FID table used for implicit flow flush is + * supported. + * If set to 0, then FID table used for implicit flow flush is + * not supported. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ UINT32_C(0x10) /* - * The maximum number of entries supported by EEM. When configuring the host memory - * the number of numbers of entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. - * Any value that are not these values, the FW will round down to the closest support - * number of entries. + * The maximum number of entries supported by EEM. When configuring + * the host memory, the number of numbers of entries that can + * supported are: + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M + * entries. + * Any value that are not these values, the FW will round down to the + * closest support number of entries. */ uint32_t max_entries_supported; /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ @@ -39241,8 +42499,9 @@ struct hwrm_cfa_eem_qcaps_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39310,9 +42569,10 @@ struct hwrm_cfa_eem_cfg_input { uint16_t group_id; uint16_t unused_0; /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, - * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * Configured EEM with the given number of entries. All the EEM tables + * KEY0, KEY1, RECORD, EFC all have the same number of entries and all + * tables will be configured using this value. Current minimum value + * is 32k. Current maximum value is 128M. */ uint32_t num_entries; uint32_t unused_1; @@ -39345,8 +42605,9 @@ struct hwrm_cfa_eem_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39431,8 +42692,9 @@ struct hwrm_cfa_eem_qcfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39528,8 +42790,9 @@ struct hwrm_cfa_eem_op_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39596,24 +42859,26 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ UINT32_C(0x2) /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. + * Value of 1 to indicate firmware support flow batch delete + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow + * batch delete operation. */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ UINT32_C(0x4) /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. + * Value of 1 to indicate that the firmware support flow reset all + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all + * operation. */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ UINT32_C(0x8) /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. + * Value of 1 to indicate that firmware supports use of FID as + * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as + * dest_id. */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ UINT32_C(0x10) @@ -39630,10 +42895,10 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ UINT32_C(0x40) /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. + * Value of 1 to indicate that firmware supports the dynamic + * allocation of an on-chip flow counter which can be used for EEM + * flows. Value of 0 indicates firmware does not support the dynamic + * allocation of an on-chip flow counter. */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ UINT32_C(0x80) @@ -39689,13 +42954,34 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that core firmware is + * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX + * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \ + UINT32_C(0x8000) + /* + * If set to 1, firmware is capable of supporting L2/ROCE as + * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. + * By default, this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \ + UINT32_C(0x10000) + /* + * If set to 1, firmware is capable of HW LAG. This bit is only + * advertised if the calling function is a PAXC function. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED \ + UINT32_C(0x20000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39769,8 +43055,9 @@ struct hwrm_cfa_tflib_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -39976,8 +43263,24 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; - /* unused. */ - uint32_t unused0; + uint32_t flags; + /* Indicates if the shared session has been created. */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ + UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates the shared session + * has been created by another session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \ + UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates the shared session + * is created by this session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \ + HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR /* unused. */ uint8_t unused1[3]; /* @@ -40781,6 +44084,105 @@ struct hwrm_tf_session_resc_flush_output { uint8_t valid; } __rte_packed; +/***************************** + * hwrm_tf_session_resc_info * + *****************************/ + + +/* hwrm_tf_session_resc_info_input (size:320b/40B) */ +struct hwrm_tf_session_resc_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +struct hwrm_tf_session_resc_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /* TruFlow RM capability of a resource. */ /* tf_rm_resc_req_entry (size:64b/8B) */ struct tf_rm_resc_req_entry { @@ -41016,8 +44418,8 @@ struct hwrm_tf_ctxt_mem_alloc_input { uint64_t resp_addr; /* Size in KB of memory to be allocated. */ uint32_t mem_size; - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */ @@ -41032,6 +44434,8 @@ struct hwrm_tf_ctxt_mem_alloc_output { uint16_t resp_len; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; /* Counter PBL indirect levels. */ uint8_t page_level; /* PBL pointer is physical start address. */ @@ -41072,7 +44476,7 @@ struct hwrm_tf_ctxt_mem_alloc_output { #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \ HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G /* unused. */ - uint8_t unused0[5]; + uint8_t unused0; /* * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be @@ -41089,7 +44493,7 @@ struct hwrm_tf_ctxt_mem_alloc_output { *************************/ -/* hwrm_tf_ctxt_mem_free_input (size:256b/32B) */ +/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */ struct hwrm_tf_ctxt_mem_free_input { /* The HWRM command request type. */ uint16_t req_type; @@ -41119,8 +44523,8 @@ struct hwrm_tf_ctxt_mem_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* Counter PBL indirect levels. */ uint8_t page_level; /* PBL pointer is physical start address. */ @@ -41161,7 +44565,13 @@ struct hwrm_tf_ctxt_mem_free_input { #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \ HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G /* unused. */ - uint8_t unused0[6]; + uint8_t unused0[2]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; + /* unused. */ + uint8_t unused1[4]; } __rte_packed; /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */ @@ -41263,8 +44673,8 @@ struct hwrm_tf_ctxt_mem_rgtr_input { #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; } __rte_packed; @@ -41338,7 +44748,9 @@ struct hwrm_tf_ctxt_mem_unrgtr_input { */ uint16_t ctx_id; /* unused. */ - uint8_t unused0[6]; + uint8_t unused0[2]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ @@ -41415,8 +44827,8 @@ struct hwrm_tf_ext_em_qcaps_input { /* When set to 1, all offloaded flows will be sent to EXT EM. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x2) - /* unused. */ - uint32_t unused0; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */ @@ -41531,13 +44943,8 @@ struct hwrm_tf_ext_em_qcaps_output { * table scopes. */ uint32_t max_static_buckets; - /* - * Maximum number of all (static and dynamic) buckets that can - * be assigned to lookup table scopes. - */ - uint32_t max_total_buckets; /* unused. */ - uint8_t unused1[3]; + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be @@ -41554,7 +44961,7 @@ struct hwrm_tf_ext_em_qcaps_output { *********************/ -/* hwrm_tf_ext_em_op_input (size:192b/24B) */ +/* hwrm_tf_ext_em_op_input (size:256b/32B) */ struct hwrm_tf_ext_em_op_input { /* The HWRM command request type. */ uint16_t req_type; @@ -41625,6 +45032,10 @@ struct hwrm_tf_ext_em_op_input { HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP /* unused. */ uint16_t unused1; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused2; } __rte_packed; /* hwrm_tf_ext_em_op_output (size:128b/16B) */ @@ -41803,12 +45214,6 @@ struct hwrm_tf_ext_em_cfg_input { */ #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \ UINT32_C(0x1000) - /* - * This bit must be '1' for the lkup_dynamic_buckets field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_DYNAMIC_BUCKETS \ - UINT32_C(0x2000) /* Configured EXT EM with the given context if for KEY0 table. */ uint16_t key0_ctx_id; /* Configured EXT EM with the given context if for KEY1 table. */ @@ -41834,8 +45239,8 @@ struct hwrm_tf_ext_em_cfg_input { * of table scope. */ uint32_t lkup_static_buckets; - /* Number of 32B dynamic buckets to be allocated. */ - uint32_t lkup_dynamic_buckets; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* unused. */ uint32_t unused2; } __rte_packed; @@ -41898,22 +45303,279 @@ struct hwrm_tf_ext_em_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; +} __rte_packed; + +/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ +struct hwrm_tf_ext_em_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint16_t unused0; + uint32_t supported; + /* This bit must be '1' for the group_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \ + UINT32_C(0x1) + /* This bit must be '1' for the flush_interval field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \ + UINT32_C(0x2) + /* This bit must be '1' for the num_entries field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \ + UINT32_C(0x4) + /* This bit must be '1' for the key0_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \ + UINT32_C(0x8) + /* This bit must be '1' for the key1_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \ + UINT32_C(0x10) + /* This bit must be '1' for the record_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \ + UINT32_C(0x20) + /* This bit must be '1' for the efc_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the fid_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \ + UINT32_C(0x80) + /* This bit must be '1' for the action_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \ + UINT32_C(0x100) + /* This bit must be '1' for the action_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \ + UINT32_C(0x200) + /* This bit must be '1' for the lkup_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \ + UINT32_C(0x400) + /* This bit must be '1' for the lkup_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \ + UINT32_C(0x800) + /* This bit must be '1' for the lkup_static_buckets field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \ + UINT32_C(0x1000) + /* + * Group id is used by firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* EEM pending cache flush interval in 1/10th of second. */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused1; + /* Context id of action table scope. */ + uint16_t action_ctx_id; + /* Table scope id used for action record entries. */ + uint16_t action_tbl_scope; + /* Context id of lookup table scope. */ + uint16_t lkup_ctx_id; + /* Table scope id used for EM lookup entries. */ + uint16_t lkup_tbl_scope; + /* + * Number of 32B static buckets to be allocated at the beginning + * of table scope. + */ + uint32_t lkup_static_buckets; + /* unused. */ + uint8_t unused2[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_em_insert * + *********************/ + + +/* hwrm_tf_em_insert_input (size:832b/104B) */ +struct hwrm_tf_em_insert_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX + /* Reported match strength. */ + uint16_t strength; + /* Index to action. */ + uint32_t action_ptr; + /* Index of EM record. */ + uint32_t em_record_idx; + /* EM Key value. */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + +/* hwrm_tf_em_insert_output (size:128b/16B) */ +struct hwrm_tf_em_insert_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; +} __rte_packed; + +/************************** + * hwrm_tf_em_hash_insert * + **************************/ + + +/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ +struct hwrm_tf_em_hash_insert_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX - /* unused. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX + /* Number of bits in the EM record. */ + uint16_t em_record_size_bits; + /* CRC32 hash of key. */ + uint32_t key0_hash; + /* Lookup3 hash of key. */ + uint32_t key1_hash; + /* Index of EM record. */ + uint32_t em_record_idx; + /* Unused. */ uint32_t unused0; + /* EM record. */ + uint64_t em_record[11]; } __rte_packed; -/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ -struct hwrm_tf_ext_em_qcfg_output { +/* hwrm_tf_em_hash_insert_output (size:128b/16B) */ +struct hwrm_tf_em_hash_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41922,123 +45584,23 @@ struct hwrm_tf_ext_em_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ - UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ - UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ - UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ - HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x2) - /* The number of entries the FW has configured for EXT EM. */ - uint32_t num_entries; - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - /* unused. */ - uint16_t unused0; - uint32_t supported; - /* This bit must be '1' for the group_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \ - UINT32_C(0x1) - /* This bit must be '1' for the flush_interval field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \ - UINT32_C(0x2) - /* This bit must be '1' for the num_entries field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \ - UINT32_C(0x4) - /* This bit must be '1' for the key0_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \ - UINT32_C(0x8) - /* This bit must be '1' for the key1_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \ - UINT32_C(0x10) - /* This bit must be '1' for the record_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \ - UINT32_C(0x20) - /* This bit must be '1' for the efc_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \ - UINT32_C(0x40) - /* This bit must be '1' for the fid_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \ - UINT32_C(0x80) - /* This bit must be '1' for the action_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \ - UINT32_C(0x100) - /* This bit must be '1' for the action_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \ - UINT32_C(0x200) - /* This bit must be '1' for the lkup_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \ - UINT32_C(0x400) - /* This bit must be '1' for the lkup_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \ - UINT32_C(0x800) - /* This bit must be '1' for the lkup_static_buckets field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \ - UINT32_C(0x1000) - /* This bit must be '1' for the lkup_dynamic_buckets field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_DYNAMIC_BUCKETS \ - UINT32_C(0x2000) - /* - * Group id is used by firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - /* EEM pending cache flush interval in 1/10th of second. */ - uint8_t flush_interval; - /* unused. */ - uint8_t unused1; - /* Context id of action table scope. */ - uint16_t action_ctx_id; - /* Table scope id used for action record entries. */ - uint16_t action_tbl_scope; - /* Context id of lookup table scope. */ - uint16_t lkup_ctx_id; - /* Table scope id used for EM lookup entries. */ - uint16_t lkup_tbl_scope; - /* - * Number of 32B static buckets to be allocated at the beginning - * of table scope. - */ - uint32_t lkup_static_buckets; - /* Number of 32B dynamic buckets to be allocated. */ - uint32_t lkup_dynamic_buckets; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; /* unused. */ - uint8_t unused2[3]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; + uint32_t unused0; } __rte_packed; /********************* - * hwrm_tf_em_insert * + * hwrm_tf_em_delete * *********************/ -/* hwrm_tf_em_insert_input (size:832b/104B) */ -struct hwrm_tf_em_insert_input { +/* hwrm_tf_em_delete_input (size:832b/104B) */ +struct hwrm_tf_em_delete_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42067,34 +45629,32 @@ struct hwrm_tf_em_insert_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware Session Id. */ + /* Session Id. */ uint32_t fw_session_id; - /* Control Flags. */ + /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX - /* Reported match strength. */ - uint16_t strength; - /* Index to action. */ - uint32_t action_ptr; - /* Index of EM record. */ - uint32_t em_record_idx; - /* EM Key value. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX + /* Unused0 */ + uint16_t unused0; + /* EM internal flow hanndle. */ + uint64_t flow_handle; + /* EM Key value */ uint64_t em_key[8]; /* Number of bits in em_key. */ uint16_t em_key_bitlen; /* unused. */ - uint16_t unused0[3]; + uint16_t unused1[3]; } __rte_packed; -/* hwrm_tf_em_insert_output (size:128b/16B) */ -struct hwrm_tf_em_insert_output { +/* hwrm_tf_em_delete_output (size:128b/16B) */ +struct hwrm_tf_em_delete_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42103,23 +45663,19 @@ struct hwrm_tf_em_insert_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* EM record pointer index. */ - uint16_t rptr_index; - /* EM record offset 0~3. */ - uint8_t rptr_entry; - /* Number of word entries consumed by the key. */ - uint8_t num_of_entries; + /* Original stack allocation index. */ + uint16_t em_index; /* unused. */ - uint32_t unused0; + uint16_t unused0[3]; } __rte_packed; -/********************* - * hwrm_tf_em_delete * - *********************/ +/******************* + * hwrm_tf_em_move * + *******************/ -/* hwrm_tf_em_delete_input (size:832b/104B) */ -struct hwrm_tf_em_delete_input { +/* hwrm_tf_em_move_input (size:320b/40B) */ +struct hwrm_tf_em_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42153,27 +45709,25 @@ struct hwrm_tf_em_delete_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX - /* Unused0 */ - uint16_t unused0; - /* EM internal flow hanndle. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX + /* Number of EM entry blocks */ + uint16_t num_blocks; + /* New index for entry */ + uint32_t new_index; + /* Unused */ + uint32_t unused0; + /* EM internal flow handle. */ uint64_t flow_handle; - /* EM Key value */ - uint64_t em_key[8]; - /* Number of bits in em_key. */ - uint16_t em_key_bitlen; - /* unused. */ - uint16_t unused1[3]; } __rte_packed; -/* hwrm_tf_em_delete_output (size:128b/16B) */ -struct hwrm_tf_em_delete_output { +/* hwrm_tf_em_move_output (size:128b/16B) */ +struct hwrm_tf_em_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42182,7 +45736,7 @@ struct hwrm_tf_em_delete_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Original stack allocation index. */ + /* Index of old entry. */ uint16_t em_index; /* unused. */ uint16_t unused0[3]; @@ -44743,8 +48297,8 @@ struct hwrm_nvm_write_input { */ uint64_t host_src_addr; /* - * The Directory Entry Type (valid values are defined in the bnxnvm - * directory_type enum defined in the file bnxnvm_defs.h). + * The Directory Entry Type (valid values are defined in the + * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* @@ -44757,10 +48311,10 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes. May be less than or equal to the allocated - * size for the directory entry. - * The data length stored in the directory entry will be updated to reflect - * this value once the write is complete. + * Length of data to write, in bytes.May be + * less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to + * reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -44773,15 +48327,15 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. This - * value may be greater than or equal to the specified data length (dir_data_length). + * The requested length of the allocated NVM for the item, in bytes. + * This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be - * greater than the requested item length. + * The response will contain the actual allocated item length, which may + * be greater than the requested item length. * The purpose for allocating more than the required number of bytes for * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with a - * size increase, log growth, expanded configuration data). + * the potential future growth of an item (e.g. upgraded firmware with + * a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; uint32_t unused_0; @@ -44799,10 +48353,9 @@ struct hwrm_nvm_write_output { uint16_t resp_len; /* * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested - * item length. - * The actual item length used when creating a new directory entry will be - * a multiple of an NVM block size. + * greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will + * be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -45292,14 +48845,11 @@ struct hwrm_nvm_mod_dir_entry_input { */ uint16_t dir_ordinal; /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension - * flag definitions). + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for + * extension flag definitions). */ uint16_t dir_ext; - /* - * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag - * definitions). - */ + /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -45474,8 +49024,7 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) /* - * If set to 1, FW will defragment the NVM if defragmentation is required - * for the update. + * If set to 1, FW will defragment the NVM if defragmentation is required for the update. * Allow additional time for this command to complete if this bit is set to 1. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ @@ -46161,8 +49710,8 @@ struct hwrm_fw_reset_input { #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \ UINT32_C(0x4) /* - * AP processor complex (in multi-host environment). Use host_idx to - * control which core is reset + * AP processor complex (in multi-host environment). + * Use host_idx to control which core is reset */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \ UINT32_C(0x5) @@ -46380,4 +49929,87 @@ struct hcomm_status { } __rte_packed; /* This is the GRC offset where the hcomm_status struct resides. */ #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + +/************************** + * hwrm_port_phy_i2c_read * + **************************/ + + +/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ +struct hwrm_port_phy_i2c_read_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the page_offset field to be + * configured. + */ + #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL + /* Port ID of port. */ + uint16_t port_id; + /* 8-bit I2C slave address. */ + uint8_t i2c_slave_addr; + uint8_t unused_0; + /* The page number that is being accessed over I2C. */ + uint16_t page_number; + /* Offset within the page that is being accessed over I2C. */ + uint16_t page_offset; + /* + * Length of data to read, in bytes starting at the offset + * specified above. If the offset is not specified, then + * the data shall be read from the beginning of the page. + */ + uint8_t data_length; + uint8_t unused_1[7]; +} __rte_packed; + +/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ +struct hwrm_port_phy_i2c_read_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Up to 64B of data. */ + uint32_t data[16]; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; #endif /* _HSI_STRUCT_DEF_DPDK_H_ */