X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=7cb93b7dd786d100ebf2e695b095025d5ff29c6f;hb=671eb37c81e8ec18b2463daf0fdd116b74b31e0d;hp=7e30c9ffcad3deeb278cb70d7ebb75bcf97395a2;hpb=f02ea89fcbcdd64b976d5db872e96144ed0a2cf5;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 7e30c9ffca..7cb93b7dd7 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -341,9 +341,14 @@ struct cmd_nums { #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53) #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54) + #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55) + #define HWRM_RING_SCHQ_CFG UINT32_C(0x56) + #define HWRM_RING_SCHQ_FREE UINT32_C(0x57) #define HWRM_RING_RESET UINT32_C(0x5e) #define HWRM_RING_GRP_ALLOC UINT32_C(0x60) #define HWRM_RING_GRP_FREE UINT32_C(0x61) + #define HWRM_RING_CFG UINT32_C(0x62) + #define HWRM_RING_QCFG UINT32_C(0x63) /* Reserved for future use. */ #define HWRM_RESERVED5 UINT32_C(0x64) /* Reserved for future use. */ @@ -408,6 +413,7 @@ struct cmd_nums { #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) #define HWRM_FW_ECN_CFG UINT32_C(0xcd) #define HWRM_FW_ECN_QCFG UINT32_C(0xce) + #define HWRM_FW_SECURE_CFG UINT32_C(0xcf) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -611,6 +617,10 @@ struct cmd_nums { #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196) /* Queries pf ids belong to specified host(s) */ #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197) + /* Queries extended stats per function */ + #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198) + /* Queries extended statistics context */ + #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -647,41 +657,57 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) /* Experimental */ - #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2c8) + #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) /* Experimental */ - #define HWRM_TF_SESSION_QCFG UINT32_C(0x2c9) + #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) /* Experimental */ - #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2ca) + #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca) /* Experimental */ - #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cb) + #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb) /* Experimental */ - #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2cc) + #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc) /* Experimental */ - #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cd) + #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd) /* Experimental */ - #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2d0) + #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce) /* Experimental */ - #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2d1) + #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) /* Experimental */ - #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2da) + #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ - #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2db) + #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) /* Experimental */ - #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2dc) + #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) /* Experimental */ - #define HWRM_TF_EXT_EM_OP UINT32_C(0x2dd) + #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) /* Experimental */ - #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2de) + #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) /* Experimental */ - #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2df) + #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) /* Experimental */ - #define HWRM_TF_TCAM_SET UINT32_C(0x2ee) + #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) /* Experimental */ - #define HWRM_TF_TCAM_GET UINT32_C(0x2ef) + #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) /* Experimental */ - #define HWRM_TF_TCAM_MOVE UINT32_C(0x2f0) + #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) /* Experimental */ - #define HWRM_TF_TCAM_FREE UINT32_C(0x2f1) + #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) + /* Experimental */ + #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) + /* Experimental */ + #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) + /* Experimental */ + #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa) + /* Experimental */ + #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd) + /* Experimental */ + #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) + /* Experimental */ + #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) /* Experimental */ #define HWRM_SV UINT32_C(0x400) /* Experimental */ @@ -715,6 +741,13 @@ struct cmd_nums { #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e) /* Send driver debug information to firmware */ #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f) + /* Query debug capabilities of firmware */ + #define HWRM_DBG_QCAPS UINT32_C(0xff20) + /* Retrieve debug settings of firmware */ + #define HWRM_DBG_QCFG UINT32_C(0xff21) + /* Set destination parameters for crashdump medium */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -914,8 +947,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 1 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 30 -#define HWRM_VERSION_STR "1.10.1.30" +#define HWRM_VERSION_RSVD 56 +#define HWRM_VERSION_STR "1.10.1.56" /**************** * hwrm_ver_get * @@ -2176,16 +2209,18 @@ struct rx_prod_pkt_bd { */ #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* + * This field has been deprecated. There can be no additional + * BDs for this packet from this ring. + * + * Old definition: * This value is the number of additional buffers in the ring that * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same - * network packet. - * - * Even if the packet to be placed does not need all the - * additional buffers, they will be consumed anyway. + * network packet. Even if the packet to be placed does not need + * all the additional buffers, they will be consumed anyway. */ #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300) #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8 @@ -2292,6 +2327,35 @@ struct cmpl_base { * Completion of TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) + /* + * NO-OP completion: + * Completion of NO-OP. Length = 16B + */ + #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1) + /* + * TX L2 coalesced completion: + * Completion of coalesced TX packet. Length = 16B + */ + #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2) + /* + * TX L2 PTP completion: + * Completion of PTP TX packet. Length = 32B + */ + #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) + /* + * RX L2 TPA Start V2 Completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd) + /* + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. + */ + #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf) /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B @@ -2321,6 +2385,24 @@ struct cmpl_base { * Length = 16B */ #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a) + /* + * VEE Flush Completion: + * This completion is inserted manually by + * the Primate and processed by the VEE hardware to ensure that + * all completions on a VEE function have been processed by the + * VEE hardware before FLR process is completed. + */ + #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c) + /* + * Mid Path Short Completion : + * Completion of a Mid Path Command. Length = 16B + */ + #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e) + /* + * Mid Path Long Completion : + * Completion of a Mid Path Command. Length = 32B + */ + #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f) /* * HWRM Command Completion: * Completion of an HWRM command. @@ -2398,7 +2480,9 @@ struct tx_cmpl { uint16_t unused_0; /* * This is a copy of the opaque field from the first TX BD of this - * transmitted packet. + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. */ uint32_t opaque; uint16_t errors_v; @@ -2407,58 +2491,352 @@ struct tx_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define TX_CMPL_V UINT32_C(0x1) - #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define TX_CMPL_ERRORS_SFT 1 + #define TX_CMPL_V UINT32_C(0x1) + #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem * with the BDs for the packet. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No error */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \ TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT /* * When this bit is '1', it indicates that the length of * the packet was zero. No packet was transmitted. */ - #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) /* * When this bit is '1', it indicates that the packet * was longer than the programmed limit in TDI. No * packet was transmitted. */ - #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) /* * When this bit is '1', it indicates that one or more of the * BDs associated with this packet generated a PCI error. * This probably means the address was not valid. */ - #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) + #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet was longer * than indicated by the hint. No packet was transmitted. */ - #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) /* * When this bit is '1', it indicates that the packet was * dropped due to Poison TLP error on one or more of the * TLPs in the PXP completion. */ - #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such completions + * are PTP completions or other TX completions. + */ + #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) /* unused2 is 16 b */ uint16_t unused_1; /* unused3 is 32 b */ uint32_t unused_2; } __rte_packed; +/* tx_cmpl_coal (size:128b/16B) */ +struct tx_cmpl_coal { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_COAL_TYPE_SFT 0 + /* + * TX L2 coalesced completion: + * Completion of TX packet. Length = 16B + */ + #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2) + #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL + #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_COAL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of the packet + * which corresponds with the reported sq_cons_idx. Note that, with + * coalesced completions, completions are generated for only some of the + * packets. The driver will see the opaque field for only those packets. + * Note that, if the packet was described by a short CSO or short CSO + * inline BD, then the 16-bit opaque field from the short CSO BD will + * appear in the bottom 16 bits of this field. For TX rings with + * completion coalescing enabled (which would use the coalesced + * completion record), it is suggested that the driver populate the + * opaque field to indicate the specific TX ring with which the + * completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_COAL_V UINT32_C(0x1) + #define TX_CMPL_COAL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define TX_CMPL_COAL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \ + UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \ + UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + uint32_t sq_cons_idx; + /* + * This value is SQ index for the start of the packet following the + * last completed packet. + */ + #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff) + #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 +} __rte_packed; + +/* tx_cmpl_ptp (size:128b/16B) */ +struct tx_cmpl_ptp { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_PTP_TYPE_SFT 0 + /* + * TX L2 PTP completion: + * Completion of TX packet. Length = 32B + */ + #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2) + #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP + #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_PTP_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of this + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_PTP_V UINT32_C(0x1) + #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_PTP_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped due + * to a transient internal error in TDC. The packet or LSO can be + * retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint32_t timestamp_lo; +} __rte_packed; + +/* tx_cmpl_ptp_hi (size:128b/16B) */ +struct tx_cmpl_ptp_hi { + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint16_t timestamp_hi[3]; + uint16_t reserved16; + uint64_t v2; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue.The even passes will write 1. + * The odd passes will write 0 + */ + #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) +} __rte_packed; + /* rx_pkt_cmpl (size:128b/16B) */ struct rx_pkt_cmpl { uint16_t flags_type; @@ -3003,12 +3381,8 @@ struct rx_pkt_cmpl_hi { #define RX_PKT_CMPL_REORDER_SFT 0 } __rte_packed; -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +/* rx_pkt_v2_cmpl (size:128b/16B) */ +struct rx_pkt_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -3017,84 +3391,143 @@ struct rx_tpa_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_START_CMPL_TYPE_SFT 0 + #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_V2_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. */ - #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) - #define RX_TPA_START_CMPL_TYPE_LAST \ - RX_TPA_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_START_CMPL_FLAGS_SFT 6 - /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf) + #define RX_PKT_V2_CMPL_TYPE_LAST \ + RX_PKT_V2_CMPL_TYPE_RX_L2_V2 + #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Normal: + * Packet was placed using normal algorithm. + */ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Packet was placed using jumbo algorithm. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Truncation: + * Packet was placed using truncation algorithm. The + * placed (truncated) length is indicated in the payload_offset + * field. The original length is indicated in the len field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \ + (UINT32_C(0x3) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* * TCP Packet: * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -3102,19 +3535,617 @@ struct rx_tpa_start_cmpl { * corresponds to. */ uint32_t opaque; + uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t v1; + #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 2 b */ + #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0) + #define RX_PKT_V2_CMPL_UNUSED1_SFT 6 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + uint16_t metadata1_payload_offset; + /* + * This is data from the CFA as indicated by the meta_format field. + * If truncation placement is not used, this value indicates the offset + * in bytes from the beginning of the packet where the inner payload + * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If + * truncation placement is used, this value represents the placed + * (truncated) length of the packet. + */ + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. When vee_cmpl_mode + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. + */ + uint32_t rss_hash; +} __rte_packed; + +/* Last 16 bytes of RX Packet V2 Completion Record */ +/* rx_pkt_v2_cmpl_hi (size:128b/16B) */ +struct rx_pkt_v2_cmpl_hi { + uint32_t flags2; + /* + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \ + RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_PKT_V2_CMPL_HI_V2 \ + UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 8 physical buffers + * (if fixed-size buffers are used), or that the packet could + * not be placed in the number of physical buffers configured + * for the VNIC (if variable-size buffers are used) + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. For regular placement, this error is + * not valid. For HDS and jumbo placement, this means that not + * enough agg BDs were posted to place the packet. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH + /* + * This indicates that there was an error in the outer tunnel + * portion of the packet when this field is non-zero. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \ + UINT32_C(0x70) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4 + /* + * No additional error occurred on the outer tunnel portion + * of the packet or the packet does not have a outer tunnel. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 4) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \ + (UINT32_C(0x1) << 4) + /* + * Indicates that header length is out of range in the outer + * tunnel header. Valid for IPv4. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 4) + /* + * Indicates that physical packet is shorter than that claimed + * by the outer tunnel l3 header length. Valid for IPv4, or + * IPv6 outer tunnel packets. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 4) + /* + * Indicates that the physical packet is shorter than that + * claimed by the outer tunnel UDP header length for a outer + * tunnel UDP packet that is not fragmented. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 4) + /* + * Indicates that the IPv4 TTL or IPv6 hop limit check have + * failed (e.g. TTL = 0) in the outer tunnel header. Valid for + * IPv4, and IPv6. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \ + (UINT32_C(0x5) << 4) + /* + * Indicates that the IP checksum failed its check in the outer + * tunnel header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \ + (UINT32_C(0x6) << 4) + /* + * Indicates that the L4 checksum failed its check in the outer + * tunnel header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \ + (UINT32_C(0x7) << 4) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR + /* + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \ + UINT32_C(0x100) + /* + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe00) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9 + /* + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 9) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 9) + /* + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 9) + /* + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 9) + /* + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 9) + /* + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 9) + /* + * Indicates that the IP checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 9) + /* + * Indicates that the L4 checksum failed its check in the tunnel + * header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 9) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12 + /* + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 12) + /* + * Indicates that the IP checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \ + (UINT32_C(0x9) << 12) + /* + * Indicates that the L4 checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \ + (UINT32_C(0xa) << 12) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13 + /* + * The timestamp field contains the 32b timestamp for the packet from + * the MAC. + */ + uint32_t timestamp; +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_start_cmpl (size:128b/16B) */ +struct rx_tpa_start_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA Start Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + */ + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + #define RX_TPA_START_CMPL_TYPE_LAST \ + RX_TPA_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. @@ -3288,9 +4319,11 @@ struct rx_tpa_start_cmpl_hi { /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte + * struct) */ -/* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { +/* rx_tpa_start_v2_cmpl (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -3299,27 +4332,33 @@ struct rx_tpa_end_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_END_CMPL_TYPE_SFT 0 + #define RX_TPA_START_V2_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. + * RX L2 TPA Start V2 Completion: + * Completion at the beginning of a TPA operation. * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. */ - #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_END_CMPL_TYPE_LAST \ - RX_TPA_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_END_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ + UINT32_C(0xd) + #define RX_TPA_START_V2_CMPL_TYPE_LAST \ + RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 + #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -3328,15 +4367,24 @@ struct rx_tpa_end_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* * GRO/Jumbo: * Packet will be placed using GRO/Jumbo where the first @@ -3345,7 +4393,7 @@ struct rx_tpa_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -3356,33 +4404,57 @@ struct rx_tpa_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10 + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. */ uint32_t opaque; /* @@ -3390,72 +4462,505 @@ struct rx_tpa_end_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t agg_bufs_v1; + uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 /* - * This value is the number of aggregation buffers that follow this - * entry in the completion ring that are a part of this aggregation - * packet. - * If the value is zero, then the packet is completely contained - * in the buffer space provided in the aggregation start completion. + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. */ - #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) - #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + uint8_t rss_hash_type; /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * - * A value of zero indicates an offset of 256 bytes. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - uint8_t payload_offset; - uint8_t agg_id; - /* unused2 is 1 b */ - #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + uint16_t agg_id; /* * This is the aggregation ID that the completion is associated * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ - #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) - #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V2_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V2_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. */ - uint32_t tsdelta; + uint32_t rss_hash; } __rte_packed; /* - * Last 16 bytes of rx_tpa_end_cmpl. + * Last 16 bytes of RX L2 TPA Start V2 Completion Record * * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { - uint32_t tpa_dup_acks; +/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl_hi { + uint32_t flags2; + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x4) /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. - */ - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet in the affregation. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + * CS status for TPA packets is always valid. This means that "all_ok" + * status will always be set. The ok count status will be set + * appropriately for the packet header, such that all existing CS + * values are ok. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_V2_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for the packetThe packet should be treated as + * invalid. + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13 + /* + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. + * + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. + */ + uint32_t hdr_offsets; +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl (size:128b/16B) */ +struct rx_tpa_end_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B + */ + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_END_CMPL_TYPE_LAST \ + RX_TPA_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* unused is 1 b */ + #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. + */ + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + /* + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t agg_bufs_v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. + */ + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; + /* + * This value indicates the offset in bytes from the beginning of the packet + * where the inner payload starts. This value is valid for TCP, UDP, + * FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t payload_offset; + uint8_t agg_id; + /* unused2 is 1 b */ + #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + /* + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. + */ + uint32_t tsdelta; +} __rte_packed; + +/* + * Last 16 bytes of rx_tpa_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* * This value is the valid when TPA completion is active. It @@ -4243,6 +5748,52 @@ struct rx_abuf_cmpl { uint32_t unused_2; } __rte_packed; +/* VEE FLUSH Completion Record (16 bytes) */ +/* vee_flush (size:128b/16B) */ +struct vee_flush { + uint32_t downstream_path_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f) + #define VEE_FLUSH_TYPE_SFT 0 + /* + * VEE Flush Completion: + * This completion is inserted manually by the Primate and processed + * by the VEE hardware to ensure that all completions on a VEE + * function have been processed by the VEE hardware before FLR + * process is completed. + */ + #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c) + #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH + /* downstream_path is 1 b */ + #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40) + /* This completion is associated with VEE Transmit */ + #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6) + /* This completion is associated with VEE Receive */ + #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6) + #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX + /* + * This is an opaque value that is passed through the completion + * to the VEE handler SW and is used to indicate what VEE VQ or + * function has completed FLR processing. + */ + uint32_t opaque; + uint32_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define VEE_FLUSH_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_3; +} __rte_packed; + /* eject_cmpl (size:128b/16B) */ struct eject_cmpl { uint16_t type; @@ -7397,6 +8948,23 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ UINT32_C(0x80) + /* + * If this bit is set to 1, the VF driver is requesting FW to enable + * PPP TX PUSH feature on all the TX rings specified in the + * num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the VF. This flag is ignored if + * the num_tx_rings field is not specified or the VF doesn't support + * PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x100) + /* + * If this bit is set to 1, the VF driver is requesting FW to disable + * PPP TX PUSH feature on all the TX rings of the VF. This flag is + * ignored if the VF doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x200) /* The number of RSS/COS contexts requested for the VF. */ uint16_t num_rsscos_ctxs; /* The number of completion rings requested for the VF. */ @@ -7476,6 +9044,8 @@ struct hwrm_func_qcaps_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ uint16_t fid; uint8_t unused_0[6]; @@ -7729,6 +9299,12 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ UINT32_C(0x40000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_QCAPS command + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \ + UINT32_C(0x80000000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -7854,7 +9430,43 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ UINT32_C(0x2) - uint8_t unused_1[3]; + /* + * If 1, the device can report extended hw statistics (including + * additional tpa statistics). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, then the core firmware has support to enable/ + * disable hot reset support for interface dynamically through + * HWRM_FUNC_CFG. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x8) + /* If 1, the proxy mode is supported on this function */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \ + UINT32_C(0x10) + /* + * If 1, the tx rings source interface override feature is supported + * on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \ + UINT32_C(0x20) + /* + * If 1, the device supports scheduler queues. SCHQs can be managed + * using RING_SCHQ_ALLOC/CFG/FREE commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \ + UINT32_C(0x40) + /* + * If set to 1, then this function supports the TX push mode that + * uses ping-pong buffers from the push pages. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ + UINT32_C(0x80) + /* The maximum number of SCHQs supported by this device. */ + uint8_t max_schqs; + uint8_t unused_1[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7904,6 +9516,8 @@ struct hwrm_func_qcfg_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ uint16_t fid; uint8_t unused_0[6]; @@ -8013,6 +9627,22 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ UINT32_C(0x100) + /* + * If set to 1, then the firmware and all currently registered driver + * instances support hot reset. The hot reset support will be updated + * dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * hot reset. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \ + UINT32_C(0x200) + /* + * If set to 1, then the PPP tx push mode is enabled for all the + * reserved TX rings of this function. If set to 0, then PPP tx push + * mode is disabled for all the reserved TX rings of this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \ + UINT32_C(0x400) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -8345,7 +9975,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:704b/88B) */ +/* hwrm_func_cfg_input (size:768b/96B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -8565,6 +10195,36 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ UINT32_C(0x2000000) + /* + * If this bit is set to 0, then the interface does not support hot + * reset capability which it advertised with the hot_reset_support + * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this + * flag to 0, adapter cannot do the hot reset. In this state, if the + * firmware receives a hot reset request, firmware must fail the + * request. If this bit is set to 1, then interface is renabling the + * hot reset capability. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \ + UINT32_C(0x4000000) + /* + * If this bit is set to 1, the PF driver is requesting FW + * to enable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the function. This flag is + * ignored if num_tx_rings field is not specified or the function + * doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x8000000) + /* + * If this bit is set to 1, the PF driver is requesting FW + * to disable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. This flag is ignored if num_tx_rings + * field is not specified or the function doesn't support PPP tx + * push feature. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x10000000) uint32_t enables; /* * This bit must be '1' for the mtu field to be @@ -8704,6 +10364,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ UINT32_C(0x400000) + /* + * This bit must be '1' for the hot_reset_if_en_dis field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x800000) + /* + * This bit must be '1' for the schq_id field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x1000000) /* * The maximum transmission unit of the function. * The HWRM should make sure that the mtu of @@ -8968,6 +10640,9 @@ struct hwrm_func_cfg_input { * be reserved for this function on the RX side. */ uint16_t num_mcast_filters; + /* Used by a PF driver to associate a SCHQ with a VF. */ + uint16_t schq_id; + uint8_t unused_0[6]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -9036,15 +10711,21 @@ struct hwrm_func_qstats_input { /* This flags indicates the type of statistics request. */ uint8_t flags; /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * flags should be set to 1 when request is for only RoCE statistics. * This will be honored only if the caller_fid is a privileged PF. * In all other cases FID and caller_fid should be the same. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY + HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK uint8_t unused_0[5]; } __rte_packed; @@ -9130,6 +10811,147 @@ struct hwrm_func_qstats_output { uint8_t valid; } __rte_packed; +/************************ + * hwrm_func_qstats_ext * + ************************/ + + +/* hwrm_func_qstats_ext_input (size:256b/32B) */ +struct hwrm_func_qstats_ext_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * A privileged PF can query for other function's statistics. + */ + uint16_t fid; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[1]; + uint32_t enables; + /* + * This bit must be '1' for the schq_id and traffic_class fields to + * be configured. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1) + /* Specifies the SCHQ for which to gather statistics */ + uint16_t schq_id; + /* + * Specifies the traffic class for which to gather statistics. Valid + * values are 0 through (max_configurable_queues - 1), where + * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG + */ + uint16_t traffic_class; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_qstats_ext_output (size:1472b/184B) */ +struct hwrm_func_qstats_ext_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on received path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_func_clr_stats * ***********************/ @@ -10116,7 +11938,7 @@ struct hwrm_func_backing_store_qcaps_output { * * TQM slowpath rings should be sized as follows: * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: * num_vnics is the number of VNICs allocated in the VNIC backing store @@ -11039,7 +12861,7 @@ struct hwrm_func_backing_store_cfg_input { * * TQM slowpath rings should be sized as follows: * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: * num_vnics is the number of VNICs allocated in the VNIC backing store @@ -13455,8 +15277,13 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ UINT32_C(0x2) /* - * When this bit is set to '1', the link shall be forced to - * the force_link_speed value. + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '0', the link shall be forced + * to the force_link_speed value. + * + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '1', the link shall be forced + * to the force_pam4_link_speed value. * * When this bit is set to '1', the HWRM client should * not enable any of the auto negotiation related @@ -13514,7 +15341,14 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x80) /* * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. + * on this port if supported. When enabled, at least one of the + * FEC modes must be advertised by enabling the fec_clause_74_enable, + * fec_clause_91_enable, fec_rs544_1xn_enable, or fec_rs544_2xn_enable + * flag. If none of the FEC mode is currently enabled, the HWRM + * shall choose a default advertisement setting. + * The default advertisement setting can be queried by calling + * hwrm_port_phy_qcfg. Note that the link speed must be + * in autonegotiation mode for FEC autonegotiation to take effect. * When set to 0, then this flag shall be ignored. * If FEC autonegotiation is not supported, then the HWRM shall ignore this * flag. @@ -13532,7 +15366,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x200) /* * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -13541,7 +15376,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x400) /* * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by not advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -13550,7 +15386,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x800) /* * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. + * on this port if supported, by advertising FEC CLAUSE 91 if + * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this * flag. @@ -13559,7 +15396,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x1000) /* * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. + * on this port if supported, by not advertising FEC CLAUSE 91 if + * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this * flag. @@ -13586,6 +15424,46 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ UINT32_C(0x4000) + /* + * When set to 1, then the HWRM shall enable FEC RS544_1XN + * on this port if supported, by advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \ + UINT32_C(0x8000) + /* + * When set to 1, then the HWRM shall disable FEC RS544_1XN + * on this port if supported, by not advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \ + UINT32_C(0x10000) + /* + * When set to 1, then the HWRM shall enable FEC RS544_2XN + * on this port if supported, by advertising FEC RS544_2XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_2XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_ENABLE \ + UINT32_C(0x20000) + /* + * When set to 1, then the HWRM shall disable FEC RS544_2XN + * on this port if supported, by not advertising FEC RS544_2XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_2XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_2XN_DISABLE \ + UINT32_C(0x40000) uint32_t enables; /* * This bit must be '1' for the auto_mode field to be @@ -13929,7 +15807,23 @@ struct hwrm_port_phy_cfg_input { /* 10Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \ UINT32_C(0x40) - uint8_t unused_2[2]; + /* + * This is the speed that will be used if the force and force_pam4 + * bits are '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_pam4_link_speed; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \ + UINT32_C(0x7d0) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB /* * Requested setting of TX LPI timer in microseconds. * This field is valid only when EEE is enabled and TX LPI is @@ -14796,9 +16690,6 @@ struct hwrm_port_phy_qcfg_output { * is set to 1, then all other FEC configuration flags shall be ignored. * When set to 0, then FEC is supported as indicated by other * configuration flags. - * If no cable is attached and the HWRM does not yet know the FEC - * capability, then the HWRM shall set this flag to 1 when reporting - * FEC capability. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \ UINT32_C(0x1) @@ -14822,7 +16713,9 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \ UINT32_C(0x8) /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port. + * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this + * port. This means that FEC CLAUSE 74 is either advertised if + * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled. * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. */ @@ -14835,12 +16728,84 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \ UINT32_C(0x20) /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port. + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this + * port. This means that FEC CLAUSE 91 is either advertised if + * FEC autonegotiation is enabled or FEC CLAUSE 91 is force enabled. * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported. * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \ UINT32_C(0x40) + /* + * When set to 1, then FEC RS544_1XN is supported on this port. + * When set to 0, then FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \ + UINT32_C(0x80) + /* + * When set to 1, then RS544_1XN is enabled on this + * port. This means that FEC RS544_1XN is either advertised if + * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled. + * When set to 0, then FEC RS544_1XN is disabled if supported. + * This flag should be ignored if FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \ + UINT32_C(0x100) + /* + * When set to 1, then FEC RS544_2XN is supported on this port. + * When set to 0, then FEC RS544_2XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_SUPPORTED \ + UINT32_C(0x200) + /* + * When set to 1, then RS544_2XN is enabled on this + * port. This means that FEC RS544_2XN is either advertised if + * FEC autonegotiation is enabled or FEC RS544_2XN is force enabled. + * When set to 0, then FEC RS544_2XN is disabled if supported. + * This flag should be ignored if FEC RS544_2XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ENABLED \ + UINT32_C(0x400) + /* + * When set to 1, then FEC CLAUSE 74 (Fire Code) is active on this + * port, either successfully autonegoatiated or forced. + * When set to 0, then FEC CLAUSE 74 (Fire Code) is not active. + * This flag is only valid when link is up on this port. + * At most only one active FEC flags (fec_clause74_active, + * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ACTIVE \ + UINT32_C(0x800) + /* + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is active on this + * port, either successfully autonegoatiated or forced. + * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not active. + * This flag is only valid when link is up on this port. + * At most only one active FEC flags (fec_clause74_active, + * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ACTIVE \ + UINT32_C(0x1000) + /* + * When set to 1, then FEC RS544_1XN is active on this + * port, either successfully autonegoatiated or forced. + * When set to 0, then FEC RS544_1XN is not active. + * This flag is only valid when link is up on this port. + * At most only one active FEC flags (fec_clause74_active, + * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ACTIVE \ + UINT32_C(0x2000) + /* + * When set to 1, then FEC RS544_2XN is active on this + * port, either successfully autonegoatiated or forced. + * When set to 0, then FEC RS544_2XN is not active. + * This flag is only valid when link is up on this port. + * At most only one active FEC flags (fec_clause74_active, + * fec_clause91_active, fec_rs544_1xn, fec_rs544_2xn) can be set. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_2XN_ACTIVE \ + UINT32_C(0x4000) /* * This value is indicates the duplex of the current * connection state. @@ -16149,7 +18114,18 @@ struct hwrm_port_qstats_input { uint64_t resp_addr; /* Port ID of port that is being queried. */ uint16_t port_id; - uint8_t unused_0[6]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; /* * This is the host address where * Tx port statistics will be stored @@ -16843,7 +18819,18 @@ struct hwrm_port_qstats_ext_input { * statistics block in bytes */ uint16_t rx_stat_size; - uint8_t unused_0[2]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for the counter mask, + * representing width of each of the stats counters, rather than + * counters themselves. + */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0; /* * This is the host address where * Tx port statistics will be stored @@ -17280,13 +19267,24 @@ struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ UINT32_C(0x8) + /* + * If set to 1, it indicates that the port counters and extended + * port counters will not reset when the firmware shuts down or + * resets the PHY. These counters will only be reset during power + * cycle or by calling HWRM_PORT_CLR_STATS. + * If set to 0, the state of the counters is unspecified when + * firmware shuts down or resets the PHY. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \ + UINT32_C(0x10) /* * Reserved field. The HWRM shall set this field to 0. * An HWRM client shall ignore this field. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xf0) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 + UINT32_C(0xe0) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \ + 5 /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -19452,7 +21450,7 @@ struct hwrm_queue_qportcfg_input { uint8_t unused_0; } __rte_packed; -/* hwrm_queue_qportcfg_output (size:256b/32B) */ +/* hwrm_queue_qportcfg_output (size:1344b/168B) */ struct hwrm_queue_qportcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -19828,6 +21826,28 @@ struct hwrm_queue_qportcfg_output { UINT32_C(0xff) #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN + uint8_t unused_0; + /* + * Up to 16 bytes of null padded ASCII string describing this queue. + * The queue name includes a CoS queue index and, in some cases, text + * that distinguishes the queue from other queues in the group. + */ + char qid0_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid1_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid2_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid3_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid4_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid5_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid6_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid7_name[16]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23612,6 +25632,9 @@ struct hwrm_vnic_cfg_input { /* This bit must be '1' for the queue_id field to be configured. */ #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \ UINT32_C(0x80) + /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \ + UINT32_C(0x100) /* Logical vnic ID */ uint16_t vnic_id; /* @@ -23669,7 +25692,41 @@ struct hwrm_vnic_cfg_input { * filter rules with destination VNIC specified. */ uint16_t queue_id; - uint8_t unused0[6]; + /* + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the two RX checksum modes supported by these + * completion records. + */ + uint8_t rx_csum_v2_mode; + /* + * When configured with this checksum mode, the number of header + * groups in the delivered packet with a valid IP checksum and + * the number of header groups in the delivered packet with a valid + * L4 checksum are reported. Valid checksums are counted from the + * outermost header group to the innermost header group, stopping at + * the first error. This is the default checksum mode supported if + * the driver doesn't explicitly configure the RX checksum mode. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this checksum mode, the checksum status is + * reported using 'all ok' mode. In the RX completion record, one + * bit indicates if the IP checksum is valid for all the parsed + * header groups with an IP checksum. Another bit indicates if the + * L4 checksum is valid for all the parsed header groups with an L4 + * checksum. The number of header groups that were parsed by the + * chip and passed in the delivered packet is also reported. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused0[5]; } __rte_packed; /* hwrm_vnic_cfg_output (size:128b/16B) */ @@ -23844,7 +25901,33 @@ struct hwrm_vnic_qcfg_output { * queue association. */ uint16_t queue_id; - uint8_t unused_1[5]; + /* + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the current RX checksum mode configured for all the + * RX rings of a VNIC. + */ + uint8_t rx_csum_v2_mode; + /* + * This value indicates that the VNIC is configured to use the + * default RX checksum mode for all the rings associated with this + * VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured to use the RX + * checksum ‘all_ok’ mode for all the rings associated with this + * VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused_1[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23981,6 +26064,17 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ UINT32_C(0x100) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V2 and RX TPA start V2 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. Additionally, two new RX + * checksum features supported by these ompletion records can be + * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \ + UINT32_C(0x200) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -24613,6 +26707,13 @@ struct hwrm_vnic_plcmodes_cfg_input { */ #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ UINT32_C(0x20) + /* + * When this bit is '1', the VNIC shall be configured use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x40) uint32_t enables; /* * This bit must be '1' for the jumbo_thresh_valid field to be @@ -24632,6 +26733,12 @@ struct hwrm_vnic_plcmodes_cfg_input { */ #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ UINT32_C(0x4) + /* + * This bit must be '1' for the max_bds_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \ + UINT32_C(0x8) /* Logical vnic ID */ uint32_t vnic_id; /* @@ -24659,7 +26766,21 @@ struct hwrm_vnic_plcmodes_cfg_input { * This value shall be in multiple of 4 bytes. */ uint16_t hds_threshold; - uint8_t unused_0[6]; + /* + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is + * supported on the function. + */ + uint16_t max_bds; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ @@ -24677,8 +26798,9 @@ struct hwrm_vnic_plcmodes_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -24776,6 +26898,13 @@ struct hwrm_vnic_plcmodes_qcfg_output { */ #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ UINT32_C(0x40) + /* + * When this bit is '1', the VNIC is configured to use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x80) /* * When jumbo placement algorithm is enabled, this value * is used to determine the threshold for jumbo placement. @@ -24801,13 +26930,28 @@ struct hwrm_vnic_plcmodes_qcfg_output { * This value shall be in multiple of 4 bytes. */ uint16_t hds_threshold; - uint8_t unused_0[5]; + /* + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is supported + * on the function + */ + uint16_t max_bds; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; @@ -25005,6 +27149,12 @@ struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ UINT32_C(0x100) + /* + * This bit must be '1' for the schq_id field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x200) /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ @@ -25070,7 +27220,8 @@ struct hwrm_ring_alloc_input { * element of the ring. */ uint8_t page_tbl_depth; - uint8_t unused_1[2]; + /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ + uint16_t schq_id; /* * Number of 16B units in the ring. Minimum size for * a ring is 16 16B entries. @@ -25390,17 +27541,26 @@ struct hwrm_ring_reset_input { /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* + * Rx Ring Group. This is to reset rx and aggregation in an atomic + * operation. Completion ring associated with this ring group is + * not reset. + */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6) #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ - HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL + HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP uint8_t unused_0; - /* Physical number of the ring. */ + /* + * Physical number of the ring. When ring type is rx_ring_grp, ring id + * actually refers to ring group id. + */ uint16_t ring_id; uint8_t unused_1[4]; } __rte_packed; @@ -25428,13 +27588,13 @@ struct hwrm_ring_reset_output { uint8_t valid; } __rte_packed; -/************************** - * hwrm_ring_aggint_qcaps * - **************************/ +/***************** + * hwrm_ring_cfg * + *****************/ -/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ -struct hwrm_ring_aggint_qcaps_input { +/* hwrm_ring_cfg_input (size:256b/32B) */ +struct hwrm_ring_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25463,163 +27623,96 @@ struct hwrm_ring_aggint_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; - -/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ -struct hwrm_ring_aggint_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t cmpl_params; - /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ - UINT32_C(0x1) + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_CFG_INPUT_RING_TYPE_RX + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + /* Ring config enable bits. */ + uint16_t enables; /* - * When this bit is set to '1', int_lat_tmr_max can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \ + UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \ UINT32_C(0x2) /* - * When this bit is set to '1', timer_reset can be enabled - * on completion rings. + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid + * is used as source interface of the transmitted packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ UINT32_C(0x4) - /* - * When this bit is set to '1', ring_idle can be enabled - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + /* The schq_id field is valid */ + #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \ UINT32_C(0x8) - /* - * When this bit is set to '1', num_cmpl_dma_aggr can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + /* Update completion ring ID associated with Tx or Rx ring. */ + #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \ UINT32_C(0x10) /* - * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ - UINT32_C(0x20) - /* - * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ - UINT32_C(0x40) - /* - * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured - * on completion rings. + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from + * the TX ring. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ - UINT32_C(0x80) + uint16_t proxy_fid; /* - * When this bit is set to '1', num_cmpl_aggr_int can be configured - * on completion rings. + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated + * with the default scheduler queue (SCHQ). */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ - UINT32_C(0x100) - uint32_t nq_params; + uint16_t schq_id; /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on notification queues. + * This field is valid for TX or Rx rings. This value identifies the + * new completion ring ID to associate with the TX or Rx ring. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ - UINT32_C(0x1) - /* Minimum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_min; - /* Maximum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_max; - /* Minimum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_min; - /* Maximum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_max; - /* Minimum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_min; - /* Maximum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_max; - /* Minimum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_min; - /* Maximum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_max; - /* Minimum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_min; - /* Maximum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_max; - /* Minimum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_min; - /* Maximum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_max; - /* Minimum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_min; - /* Maximum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_max; - /* The units for timer parameters, in nanoseconds. */ - uint16_t timer_units; - uint8_t unused_0[1]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/************************************** - * hwrm_ring_cmpl_ring_qaggint_params * - **************************************/ - - -/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; + uint16_t cmpl_ring_id; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. */ - uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint8_t unused_0[6]; + uint8_t rx_sop_pad_bytes; + uint8_t unused_1[3]; } __rte_packed; -/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_output { +/* hwrm_ring_cfg_output (size:128b/16B) */ +struct hwrm_ring_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25628,70 +27721,432 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* - * When this bit is set to '1', interrupt max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ - UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ - UINT32_C(0x2) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; - /* - * Number of completions to aggregate before DMA - * during the interrupt mode. - */ - uint16_t num_cmpl_dma_aggr_during_int; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). - */ - uint16_t cmpl_aggr_dma_tmr; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. - */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; - /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. - */ - uint16_t int_lat_tmr_max; - /* - * Minimum number of completions aggregated before signaling - * an interrupt. - */ - uint16_t num_cmpl_aggr_int; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/***************************************** - * hwrm_ring_cmpl_ring_cfg_aggint_params * - *****************************************/ +/****************** + * hwrm_ring_qcfg * + ******************/ -/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +/* hwrm_ring_qcfg_input (size:192b/24B) */ +struct hwrm_ring_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_QCFG_INPUT_RING_TYPE_RX + uint8_t unused_0[5]; + /* Physical number of the ring. */ + uint16_t ring_id; +} __rte_packed; + +/* hwrm_ring_qcfg_output (size:192b/24B) */ +struct hwrm_ring_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \ + UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \ + UINT32_C(0x2) + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid is + * used as source interface of the transmitted packets. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ + UINT32_C(0x4) + /* + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from the TX + * ring. + */ + uint16_t proxy_fid; + /* + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated with + * the default scheduler queue (SCHQ). + */ + uint16_t schq_id; + /* + * This field is used when ring_type is a TX or Rx ring. + * This value indicates what completion ring the TX or Rx ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_ring_aggint_qcaps * + **************************/ + + +/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ +struct hwrm_ring_aggint_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ +struct hwrm_ring_aggint_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t cmpl_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* + * When this bit is set to '1', int_lat_tmr_max can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + UINT32_C(0x2) + /* + * When this bit is set to '1', timer_reset can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + UINT32_C(0x4) + /* + * When this bit is set to '1', ring_idle can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + UINT32_C(0x8) + /* + * When this bit is set to '1', num_cmpl_dma_aggr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x10) + /* + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x40) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ + UINT32_C(0x80) + /* + * When this bit is set to '1', num_cmpl_aggr_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ + UINT32_C(0x100) + uint32_t nq_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on notification queues. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* Minimum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_min; + /* Maximum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_max; + /* Minimum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_min; + /* Maximum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_max; + /* Minimum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_min; + /* Maximum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_max; + /* Minimum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_min; + /* Maximum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_max; + /* Minimum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_min; + /* Maximum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_max; + /* Minimum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_min; + /* Maximum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_max; + /* Minimum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_min; + /* Maximum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_max; + /* The units for timer parameters, in nanoseconds. */ + uint16_t timer_units; + uint8_t unused_0[1]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************** + * hwrm_ring_cmpl_ring_qaggint_params * + **************************************/ + + +/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \ + UINT32_C(0x3) + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0 + /* + * Set this flag to 1 when querying parameters on a notification + * queue. Set this flag to 0 when querying parameters on a + * completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t flags; + /* + * When this bit is set to '1', interrupt max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA when in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************************** + * hwrm_ring_cmpl_ring_cfg_aggint_params * + *****************************************/ + + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25738,7 +28193,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { /* * Set this flag to 1 when configuring parameters on a * notification queue. Set this flag to 0 when configuring - * parameters on a completion queue. + * parameters on a completion queue or completion ring. */ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ UINT32_C(0x4) @@ -25753,20 +28208,20 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { */ uint16_t num_cmpl_dma_aggr_during_int; /* - * Timer in unit of 80-nsec used to aggregate completions before + * Timer used to aggregate completions before * DMA during the normal mode (not in interrupt mode). */ uint16_t cmpl_aggr_dma_tmr; /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. + * Timer used to aggregate completions before + * DMA while in interrupt mode. */ uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ + /* Minimum time between two interrupts. */ uint16_t int_lat_tmr_min; /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * cmpls before signaling the interrupt after the + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the * interrupt is enabled. */ uint16_t int_lat_tmr_max; @@ -25962,13 +28417,803 @@ struct hwrm_ring_grp_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the ring group ID value. */ - uint32_t ring_group_id; - uint8_t unused_0[4]; + /* This is the ring group ID value. */ + uint32_t ring_group_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_grp_free_output (size:128b/16B) */ +struct hwrm_ring_grp_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_ring_schq_alloc * + ************************/ + + +/* hwrm_ring_schq_alloc_input (size:1088b/136B) */ +struct hwrm_ring_schq_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) + /* Reserved for future use. */ + uint32_t reserved; + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring0_num_entries; + /* + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring1_num_entries; + /* + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring2_num_entries; + /* + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring3_num_entries; + /* + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring4_num_entries; + /* + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring5_num_entries; + /* + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring6_num_entries; + /* + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring7_num_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_ring_schq_alloc_output (size:128b/16B) */ +struct hwrm_ring_schq_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is an identifier for the SCHQ to be used in other HWRM commands + * that need to reference this SCHQ. This value is greater than zero + * (i.e. a schq_id of zero references the default SCHQ). + */ + uint16_t schq_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_ring_schq_cfg * + **********************/ + + +/* hwrm_ring_schq_cfg_input (size:768b/96B) */ +struct hwrm_ring_schq_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Identifies the SCHQ being configured. A schq_id of zero refers to + * the default SCHQ. + */ + uint16_t schq_id; + /* + * This field is an 8 bit bitmap that indicates which TCs are enabled + * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents + * traffic class 7. + */ + uint8_t tc_enabled; + uint8_t unused_0; + uint32_t flags; + /* The tc_max_bw array and the max_bw parameters are valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \ + UINT32_C(0x1) + /* The tc_min_bw array is valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \ + UINT32_C(0x2) + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc0; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc1; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc2; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc3; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc4; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc5; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc6; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc7; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc0; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc1; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc2; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc3; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc4; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc5; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc6; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc7; + /* + * Indicates the max bandwidth for all enabled traffic classes in + * this SCHQ, specified in Mbps. + */ + uint32_t max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_schq_cfg_output (size:128b/16B) */ +struct hwrm_ring_schq_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_ring_schq_free * + ***********************/ + + +/* hwrm_ring_schq_free_input (size:192b/24B) */ +struct hwrm_ring_schq_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Identifies the SCHQ being freed. */ + uint16_t schq_id; + uint8_t unused_0[6]; } __rte_packed; -/* hwrm_ring_grp_free_output (size:128b/16B) */ -struct hwrm_ring_grp_free_output { +/* hwrm_ring_schq_free_output (size:128b/16B) */ +struct hwrm_ring_schq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32119,6 +35364,144 @@ struct hwrm_cfa_pair_info_output { uint8_t valid; } __rte_packed; +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ + + +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vfr_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; +} __rte_packed; + +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vfr_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_cfa_vfr_free * + *********************/ + + +/* hwrm_cfa_vfr_free_input (size:448b/56B) */ +struct hwrm_cfa_vfr_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + uint16_t reserved; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +struct hwrm_cfa_vfr_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + + + /*************************************** * hwrm_cfa_redirect_query_tunnel_type * ***************************************/ @@ -33409,7 +36792,7 @@ struct hwrm_tf_session_open_input { uint8_t session_name[64]; } __rte_packed; -/* hwrm_tf_session_open_output (size:128b/16B) */ +/* hwrm_tf_session_open_output (size:192b/24B) */ struct hwrm_tf_session_open_output { /* The specific error status for the command. */ uint16_t error_code; @@ -33421,13 +36804,18 @@ struct hwrm_tf_session_open_output { uint16_t resp_len; /* * Unique session identifier for the session created by the - * firmware. It includes PCIe bus info to distinguish the PF - * and session info to identify the associated TruFlow - * session. + * firmware. */ uint32_t fw_session_id; + /* + * Unique session client identifier for the first client on + * the newly created session. + */ + uint32_t fw_session_client_id; /* unused. */ - uint8_t unused0[3]; + uint32_t unused0; + /* unused. */ + uint8_t unused1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -33522,6 +36910,155 @@ struct hwrm_tf_session_attach_output { uint8_t valid; } __rte_packed; +/**************************** + * hwrm_tf_session_register * + ****************************/ + + +/* hwrm_tf_session_register_input (size:704b/88B) */ +struct hwrm_tf_session_register_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session that the + * register request want to create a new client on. This + * value originates from the first open request. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. + */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session client. */ + uint8_t session_client_name[64]; +} __rte_packed; + +/* hwrm_tf_session_register_output (size:128b/16B) */ +struct hwrm_tf_session_register_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session client identifier for the session created + * by the firmware. It includes the session the client it + * attached to and session client info. + */ + uint32_t fw_session_client_id; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_unregister * + ******************************/ + + +/* hwrm_tf_session_unregister_input (size:192b/24B) */ +struct hwrm_tf_session_unregister_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session that the + * unregister request want to close a session client on. + */ + uint32_t fw_session_id; + /* + * Unique session client identifier for the session that the + * unregister request want to close. + */ + uint32_t fw_session_client_id; +} __rte_packed; + +/* hwrm_tf_session_unregister_output (size:128b/16B) */ +struct hwrm_tf_session_unregister_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /************************* * hwrm_tf_session_close * *************************/ @@ -33746,15 +37283,17 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX /* - * Defines the size, in bytes, of the provided qcaps_addr + * Defines the size of the provided qcaps_addr array * buffer. The size should be set to the Resource Manager - * provided max qcaps value that is device specific. This is - * the max size possible. + * provided max number of qcaps entries which is device + * specific. Resource Manager gets the max size from HCAPI + * RM. */ - uint16_t size; + uint16_t qcaps_size; /* - * This is the DMA address for the qcaps output data - * array. Array is of tf_rm_cap type and is device specific. + * This is the DMA address for the qcaps output data array + * buffer. Array is of tf_rm_resc_req_entry type and is + * device specific. */ uint64_t qcaps_addr; } __rte_packed; @@ -33772,29 +37311,28 @@ struct hwrm_tf_session_resc_qcaps_output { /* Control flags. */ uint32_t flags; /* Session reservation strategy. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \ UINT32_C(0x3) - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \ 0 /* Static partitioning. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \ UINT32_C(0x0) /* Strategy 1. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \ UINT32_C(0x1) /* Strategy 2. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \ UINT32_C(0x2) /* Strategy 3. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \ UINT32_C(0x3) - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \ - HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 /* - * Size of the returned tf_rm_cap data array. The value - * cannot exceed the size defined by the input msg. The data - * array is returned using the qcaps_addr specified DMA - * address also provided by the input msg. + * Size of the returned qcaps_addr data array buffer. The + * value cannot exceed the size defined by the input msg, + * qcaps_size. */ uint16_t size; /* unused. */ @@ -33817,7 +37355,7 @@ struct hwrm_tf_session_resc_qcaps_output { ******************************/ -/* hwrm_tf_session_resc_alloc_input (size:256b/32B) */ +/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ struct hwrm_tf_session_resc_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -33860,16 +37398,25 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX /* - * Defines the size, in bytes, of the provided num_addr - * buffer. + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. */ - uint16_t size; + uint64_t req_addr; /* - * This is the DMA address for the num input data array - * buffer. Array is of tf_rm_num type. Size of the buffer is - * provided by the 'size' field in this message. + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. */ - uint64_t num_addr; + uint64_t resc_addr; } __rte_packed; /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ @@ -33882,8 +37429,15 @@ struct hwrm_tf_session_resc_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -33946,11 +37500,12 @@ struct hwrm_tf_session_resc_free_input { * Defines the size, in bytes, of the provided free_addr * buffer. */ - uint16_t size; + uint16_t free_size; /* * This is the DMA address for the free input data array - * buffer. Array of tf_rm_res type. Size of the buffer is - * provided by the 'size field of this message. + * buffer. Array is of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'free_size' field of this + * message. */ uint64_t free_addr; } __rte_packed; @@ -34029,11 +37584,12 @@ struct hwrm_tf_session_resc_flush_input { * Defines the size, in bytes, of the provided flush_addr * buffer. */ - uint16_t size; + uint16_t flush_size; /* * This is the DMA address for the flush input data array - * buffer. Array of tf_rm_res type. Size of the buffer is - * provided by the 'size' field in this message. + * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'flush_size' field in this + * message. */ uint64_t flush_addr; } __rte_packed; @@ -34062,12 +37618,9 @@ struct hwrm_tf_session_resc_flush_output { } __rte_packed; /* TruFlow RM capability of a resource. */ -/* tf_rm_cap (size:64b/8B) */ -struct tf_rm_cap { - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ +/* tf_rm_resc_req_entry (size:64b/8B) */ +struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ uint32_t type; /* Minimum value. */ uint16_t min; @@ -34075,25 +37628,10 @@ struct tf_rm_cap { uint16_t max; } __rte_packed; -/* TruFlow RM number of a resource. */ -/* tf_rm_num (size:64b/8B) */ -struct tf_rm_num { - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Number of resources. */ - uint32_t num; -} __rte_packed; - /* TruFlow RM reservation information. */ -/* tf_rm_res (size:64b/8B) */ -struct tf_rm_res { - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ +/* tf_rm_resc_entry (size:64b/8B) */ +struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ uint32_t type; /* Start offset. */ uint16_t start; @@ -34863,19 +38401,567 @@ struct hwrm_tf_ext_em_qcfg_input { /* Control flags. */ uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* unused. */ + uint32_t unused0; +} __rte_packed; + +/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ +struct hwrm_tf_ext_em_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_em_insert * + *********************/ + + +/* hwrm_tf_em_insert_input (size:832b/104B) */ +struct hwrm_tf_em_insert_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX + /* Reported match strength. */ + uint16_t strength; + /* Index to action. */ + uint32_t action_ptr; + /* Index of EM record. */ + uint32_t em_record_idx; + /* EM Key value. */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + +/* hwrm_tf_em_insert_output (size:128b/16B) */ +struct hwrm_tf_em_insert_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; +} __rte_packed; + +/********************* + * hwrm_tf_em_delete * + *********************/ + + +/* hwrm_tf_em_delete_input (size:832b/104B) */ +struct hwrm_tf_em_delete_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX + /* Unused0 */ + uint16_t unused0; + /* EM internal flow hanndle. */ + uint64_t flow_handle; + /* EM Key value */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused1[3]; +} __rte_packed; + +/* hwrm_tf_em_delete_output (size:128b/16B) */ +struct hwrm_tf_em_delete_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Original stack allocation index. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; + +/******************** + * hwrm_tf_tcam_set * + ********************/ + + +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +struct hwrm_tf_tcam_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data is packing does not change. + */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[88]; +} __rte_packed; + +/* hwrm_tf_tcam_set_output (size:128b/16B) */ +struct hwrm_tf_tcam_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_tf_tcam_get * + ********************/ + + +/* hwrm_tf_tcam_get_input (size:256b/32B) */ +struct hwrm_tf_tcam_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; +} __rte_packed; + +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +struct hwrm_tf_tcam_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_tcam_move * + *********************/ + + +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +struct hwrm_tf_tcam_move_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; +} __rte_packed; + +/* hwrm_tf_tcam_move_output (size:128b/16B) */ +struct hwrm_tf_tcam_move_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_tcam_free * + *********************/ + + +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +struct hwrm_tf_tcam_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; /* unused. */ - uint32_t unused0; + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; } __rte_packed; -/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ -struct hwrm_tf_ext_em_qcfg_output { +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34884,36 +38970,8 @@ struct hwrm_tf_ext_em_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ - UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ - UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ - UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ - HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x2) - /* The number of entries the FW has configured for EXT EM. */ - uint32_t num_entries; - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; /* unused. */ - uint8_t unused0[5]; + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be @@ -34925,13 +38983,13 @@ struct hwrm_tf_ext_em_qcfg_output { uint8_t valid; } __rte_packed; -/******************** - * hwrm_tf_tcam_set * - ********************/ +/************************** + * hwrm_tf_global_cfg_set * + **************************/ -/* hwrm_tf_tcam_set_input (size:1024b/128B) */ -struct hwrm_tf_tcam_set_input { +/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ +struct hwrm_tf_global_cfg_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34965,47 +39023,29 @@ struct hwrm_tf_tcam_set_input { /* Control flags. */ uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX - /* - * Indicate device data is being sent via DMA, the device - * data is packing does not change. - */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) - /* - * TCAM type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ uint32_t type; - /* Index of TCAM entry. */ - uint16_t idx; - /* Number of bytes in the TCAM key. */ - uint8_t key_size; - /* Number of bytes in the TCAM result. */ - uint8_t result_size; - /* - * Offset from which the mask bytes start in the device data - * array, key offset is always 0. - */ - uint8_t mask_offset; - /* Offset from which the result bytes start in the device data array. */ - uint8_t result_offset; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; /* unused. */ uint8_t unused0[6]; - /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. - */ - uint8_t dev_data[88]; + /* Data to set */ + uint8_t data[8]; + /* Mask of data to set, 0 indicates no mask */ + uint8_t mask[8]; } __rte_packed; -/* hwrm_tf_tcam_set_output (size:128b/16B) */ -struct hwrm_tf_tcam_set_output { +/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ +struct hwrm_tf_global_cfg_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35027,13 +39067,13 @@ struct hwrm_tf_tcam_set_output { uint8_t valid; } __rte_packed; -/******************** - * hwrm_tf_tcam_get * - ********************/ +/************************** + * hwrm_tf_global_cfg_get * + **************************/ -/* hwrm_tf_tcam_get_input (size:256b/32B) */ -struct hwrm_tf_tcam_get_input { +/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ +struct hwrm_tf_global_cfg_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35067,26 +39107,25 @@ struct hwrm_tf_tcam_get_input { /* Control flags. */ uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX - /* - * TCAM type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ uint32_t type; - /* Index of a TCAM entry. */ - uint16_t idx; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; /* unused. */ - uint16_t unused0; + uint8_t unused0[6]; } __rte_packed; -/* hwrm_tf_tcam_get_output (size:2368b/296B) */ -struct hwrm_tf_tcam_get_output { +/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +struct hwrm_tf_global_cfg_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35095,41 +39134,21 @@ struct hwrm_tf_tcam_get_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of bytes in the TCAM key. */ - uint8_t key_size; - /* Number of bytes in the TCAM entry. */ - uint8_t result_size; - /* Offset from which the mask bytes start in the device data array. */ - uint8_t mask_offset; - /* Offset from which the result bytes start in the device data array. */ - uint8_t result_offset; - /* unused. */ - uint8_t unused0[4]; - /* - * TCAM key located at offset 0, mask located at mask_offsec - * and result at result_offsec for the device. - */ - uint8_t dev_data[272]; + /* Size of the data read in bytes */ + uint16_t size; /* unused. */ - uint8_t unused1[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[16]; } __rte_packed; -/********************* - * hwrm_tf_tcam_move * - *********************/ +/********************** + * hwrm_tf_if_tbl_get * + **********************/ -/* hwrm_tf_tcam_move_input (size:1024b/128B) */ -struct hwrm_tf_tcam_move_input { +/* hwrm_tf_if_tbl_get_input (size:256b/32B) */ +struct hwrm_tf_if_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35161,30 +39180,28 @@ struct hwrm_tf_tcam_move_input { /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Size of the data to set. */ + uint16_t size; /* - * TCAM type of the resource, defined globally in the + * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Number of TCAM index pairs to be swapped for the device. */ - uint16_t count; - /* unused. */ - uint16_t unused0; - /* TCAM index pairs to be swapped for the device. */ - uint16_t idx_pairs[48]; + /* Index of the type to retrieve. */ + uint32_t index; } __rte_packed; -/* hwrm_tf_tcam_move_output (size:128b/16B) */ -struct hwrm_tf_tcam_move_output { +/* hwrm_tf_if_tbl_get_output (size:256b/32B) */ +struct hwrm_tf_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35193,26 +39210,34 @@ struct hwrm_tf_tcam_move_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[8]; + /* unused */ + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; -/********************* - * hwrm_tf_tcam_free * - *********************/ +/*************************** + * hwrm_tf_if_tbl_type_set * + ***************************/ -/* hwrm_tf_tcam_free_input (size:1024b/128B) */ -struct hwrm_tf_tcam_free_input { +/* hwrm_tf_if_tbl_set_input (size:384b/48B) */ +struct hwrm_tf_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35244,30 +39269,34 @@ struct hwrm_tf_tcam_free_input { /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; /* - * TCAM type of the resource, defined globally in the + * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Number of TCAM index to be deleted for the device. */ - uint16_t count; - /* unused. */ - uint16_t unused0; - /* TCAM index list to be deleted for the device. */ - uint16_t idx_list[48]; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[8]; } __rte_packed; -/* hwrm_tf_tcam_free_output (size:128b/16B) */ -struct hwrm_tf_tcam_free_output { +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +struct hwrm_tf_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35279,12 +39308,12 @@ struct hwrm_tf_tcam_free_output { /* unused. */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; @@ -35582,10 +39611,10 @@ struct ctx_hw_stats { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -35598,10 +39627,10 @@ struct ctx_hw_stats { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -35618,7 +39647,11 @@ struct ctx_hw_stats { uint64_t tpa_aborts; } __rte_packed; -/* Periodic statistics context DMA to host. */ +/* + * Extended periodic statistics context DMA to host. On cards that + * support TPA v2, additional TPA related stats exist and can be retrieved + * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. + */ /* ctx_hw_stats_ext (size:1344b/168B) */ struct ctx_hw_stats_ext { /* Number of received unicast packets */ @@ -35627,10 +39660,10 @@ struct ctx_hw_stats_ext { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -35643,10 +39676,10 @@ struct ctx_hw_stats_ext { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -35912,7 +39945,14 @@ struct hwrm_stat_ctx_query_input { uint64_t resp_addr; /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; - uint8_t unused_0[4]; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[3]; } __rte_packed; /* hwrm_stat_ctx_query_output (size:1408b/176B) */ @@ -35949,7 +39989,7 @@ struct hwrm_stat_ctx_query_output { uint64_t rx_bcast_pkts; /* Number of received packets with error */ uint64_t rx_err_pkts; - /* Number of dropped packets on received path */ + /* Number of dropped packets on receive path */ uint64_t rx_drop_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; @@ -35976,6 +40016,117 @@ struct hwrm_stat_ctx_query_output { uint8_t valid; } __rte_packed; +/*************************** + * hwrm_stat_ext_ctx_query * + ***************************/ + + +/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ +struct hwrm_stat_ext_ctx_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* ID of the extended statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \ + UINT32_C(0x1) + uint8_t unused_0[3]; +} __rte_packed; + +/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */ +struct hwrm_stat_ext_ctx_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*************************** * hwrm_stat_ctx_eng_query * ***************************/ @@ -37565,6 +41716,13 @@ struct hwrm_nvm_install_update_input { */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) + /* + * If set to 1, FW will verify the package in the "UPDATE" NVM item + * without installing it. This flag is for FW internal use only. + * Users should not set this flag. The request will otherwise fail. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \ + UINT32_C(0x8) uint8_t unused_0[2]; } __rte_packed; @@ -38115,6 +42273,72 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/**************** + * hwrm_oem_cmd * + ****************/ + + +/* hwrm_oem_cmd_input (size:1024b/128B) */ +struct hwrm_oem_cmd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific command data. */ + uint32_t oem_data[26]; +} __rte_packed; + +/* hwrm_oem_cmd_output (size:768b/96B) */ +struct hwrm_oem_cmd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific response data. */ + uint32_t oem_data[18]; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /***************** * hwrm_fw_reset * ******************/ @@ -38338,6 +42562,55 @@ struct hwrm_port_ts_query_output { uint8_t valid; } __rte_packed; +/* + * This structure is fixed at the beginning of the ChiMP SRAM (GRC + * offset: 0x31001F0). Host software is expected to read from this + * location for a defined signature. If it exists, the software can + * assume the presence of this structure and the validity of the + * FW_STATUS location in the next field. + */ +/* hcomm_status (size:64b/8B) */ +struct hcomm_status { + uint32_t sig_ver; + /* + * This field defines the version of the structure. The latest + * version value is 1. + */ + #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) + #define HCOMM_STATUS_VER_SFT 0 + #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) + #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST + /* + * This field is to store the signature value to indicate the + * presence of the structure. + */ + #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) + #define HCOMM_STATUS_SIGNATURE_SFT 8 + #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) + #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL + uint32_t fw_status_loc; + #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) + #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 + /* PCIE configuration space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) + /* GRC space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) + /* BAR0 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) + /* BAR1 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \ + HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + /* + * This offset where the fw_status register is located. The value + * is generally 4-byte aligned. + */ + #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) + #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 +} __rte_packed; +/* This is the GRC offset where the hcomm_status struct resides. */ +#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + /************************** * hwrm_cfa_counter_qcaps * **************************/ @@ -38622,53 +42895,4 @@ struct hwrm_cfa_counter_qstats_output { uint8_t valid; } __rte_packed; -/* - * This structure is fixed at the beginning of the ChiMP SRAM (GRC - * offset: 0x31001F0). Host software is expected to read from this - * location for a defined signature. If it exists, the software can - * assume the presence of this structure and the validity of the - * FW_STATUS location in the next field. - */ -/* hcomm_status (size:64b/8B) */ -struct hcomm_status { - uint32_t sig_ver; - /* - * This field defines the version of the structure. The latest - * version value is 1. - */ - #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) - #define HCOMM_STATUS_VER_SFT 0 - #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) - #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST - /* - * This field is to store the signature value to indicate the - * presence of the structure. - */ - #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) - #define HCOMM_STATUS_SIGNATURE_SFT 8 - #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) - #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL - uint32_t fw_status_loc; - #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) - #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 - /* PCIE configuration space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) - /* GRC space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) - /* BAR0 space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) - /* BAR1 space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \ - HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 - /* - * This offset where the fw_status register is located. The value - * is generally 4-byte aligned. - */ - #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) - #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 -} __rte_packed; -/* This is the GRC offset where the hcomm_status struct resides. */ -#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL - #endif /* _HSI_STRUCT_DEF_DPDK_H_ */