X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=7e30c9ffcad3deeb278cb70d7ebb75bcf97395a2;hb=205b742952828afa26ca00c590cf00cb12939bea;hp=c45d0883acb7b627a3467835bc959c68a55bd94d;hpb=84d49664b5b2bf94264601ffca8de931dc91b8ec;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c45d0883ac..7e30c9ffca 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2019 Broadcom Inc. + * Copyright (c) 2014-2020 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -39,7 +39,7 @@ struct hwrm_cmd_hdr { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* This is the HWRM response header. */ /* hwrm_resp_hdr (size:64b/8B) */ @@ -52,7 +52,7 @@ struct hwrm_resp_hdr { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; -} __attribute__((packed)); +} __rte_packed; /* * TLV encapsulated message. Use the TLV type field of the @@ -80,16 +80,18 @@ struct hwrm_resp_hdr { #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004) /* Engine CKV - The encrypted data. */ #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005) -/* Engine CKV - Supported algorithms. */ -#define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006) +/* Engine CKV - Supported host_algorithms. */ +#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006) /* Engine CKV - The Host EC curve name and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007) /* Engine CKV - The ECDSA signature. */ #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008) -/* Engine CKV - The SRT EC curve name and ECC public key information. */ -#define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - The firmware EC curve name and ECC public key information. */ +#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - Supported firmware algorithms. */ +#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a) #define TLV_TYPE_LAST \ - TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY + TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS /* tlv (size:64b/8B) */ @@ -145,7 +147,7 @@ struct tlv { * and it must be an integer multiple of 8B. */ uint16_t length; -} __attribute__((packed)); +} __rte_packed; /* Input */ /* input (size:128b/16B) */ @@ -178,7 +180,7 @@ struct input { * and must be cleared to zero before the request is made. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* Output */ /* output (size:64b/8B) */ @@ -201,7 +203,7 @@ struct output { * memory. */ uint16_t resp_len; -} __attribute__((packed)); +} __rte_packed; /* Short Command Structure */ /* hwrm_short_input (size:128b/16B) */ @@ -237,7 +239,7 @@ struct hwrm_short_input { * This area must be 16B aligned. */ uint64_t req_addr; -} __attribute__((packed)); +} __rte_packed; /* * Command numbering @@ -319,11 +321,8 @@ struct cmd_nums { #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38) #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39) #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a) - /* Experimental */ #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d) #define HWRM_VNIC_ALLOC UINT32_C(0x40) #define HWRM_VNIC_FREE UINT32_C(0x41) @@ -351,6 +350,9 @@ struct cmd_nums { #define HWRM_RESERVED6 UINT32_C(0x65) #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70) #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71) + #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) + #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) + #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -382,11 +384,15 @@ struct cmd_nums { #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4) #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5) #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6) + #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) + #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) + #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) + #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) #define HWRM_FW_SYNC UINT32_C(0xc3) - #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4) + #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4) #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5) #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6) #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7) @@ -400,6 +406,8 @@ struct cmd_nums { #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb) /* Experimental */ #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) + #define HWRM_FW_ECN_CFG UINT32_C(0xcd) + #define HWRM_FW_ECN_QCFG UINT32_C(0xce) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -407,7 +415,15 @@ struct cmd_nums { #define HWRM_OEM_CMD UINT32_C(0xd4) /* Tells the fw to run PRBS test on a given port and lane. */ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5) + #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6) + #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7) + #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) + /* Tells the fw to collect dsc dump on a given port and lane. */ + #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) + #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) + #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) + #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -499,7 +515,7 @@ struct cmd_nums { #define HWRM_CFA_EEM_OP UINT32_C(0x123) /* Experimental */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) - /* Experimental */ + /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) @@ -561,6 +577,8 @@ struct cmd_nums { #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) + /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) /* Engine - Free an Engine RQ. */ @@ -616,6 +634,56 @@ struct cmd_nums { * to the host test. */ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209) + /* Tells the fw to program the fru memory */ + #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) + /* Tells the fw to read the fru memory */ + #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Experimental */ + #define HWRM_TF UINT32_C(0x2bc) + /* Experimental */ + #define HWRM_TF_VERSION_GET UINT32_C(0x2bd) + /* Experimental */ + #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) + /* Experimental */ + #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) + /* Experimental */ + #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2c8) + /* Experimental */ + #define HWRM_TF_SESSION_QCFG UINT32_C(0x2c9) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2ca) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cb) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2cc) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cd) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2d0) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2d1) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2da) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2db) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2dc) + /* Experimental */ + #define HWRM_TF_EXT_EM_OP UINT32_C(0x2dd) + /* Experimental */ + #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2de) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2df) + /* Experimental */ + #define HWRM_TF_TCAM_SET UINT32_C(0x2ee) + /* Experimental */ + #define HWRM_TF_TCAM_GET UINT32_C(0x2ef) + /* Experimental */ + #define HWRM_TF_TCAM_MOVE UINT32_C(0x2f0) + /* Experimental */ + #define HWRM_TF_TCAM_FREE UINT32_C(0x2f1) + /* Experimental */ + #define HWRM_SV UINT32_C(0x400) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -645,6 +713,8 @@ struct cmd_nums { #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d) /* Experimental */ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e) + /* Send driver debug information to firmware */ + #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -666,7 +736,7 @@ struct cmd_nums { #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff) #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK uint16_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* Return Codes */ /* ret_codes (size:64b/8B) */ @@ -731,7 +801,7 @@ struct ret_codes { #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb) /* * This error code is only reported by the firmware when during - * flow allocation when a requeest for a flow counter fails because + * flow allocation when a request for a flow counter fails because * the number of flow counters are exhausted. */ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) @@ -752,11 +822,16 @@ struct ret_codes { * internal error. */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) + /* + * Firmware is unable to service the request at the present time. Caller + * may try again later. + */ + #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the - * hwrm_resp_hdr TLV. This value is not an indicatation of any error - * by itself, just an indicatation that the response should be parsed + * hwrm_resp_hdr TLV. This value is not an indication of any error + * by itself, just an indication that the response should be parsed * as TLV and the actual error code will be in the hwrm_resp_hdr TLV. */ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000) @@ -767,7 +842,7 @@ struct ret_codes { #define HWRM_ERR_CODE_LAST \ HWRM_ERR_CODE_CMD_NOT_SUPPORTED uint16_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* Output */ /* hwrm_err_output (size:128b/16B) */ @@ -807,7 +882,7 @@ struct hwrm_err_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* * Following is the signature for HWRM message field that indicates not * applicable (All F's). Need to cast it the size of the field if needed. @@ -837,10 +912,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 0 +#define HWRM_VERSION_UPDATE 1 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 91 -#define HWRM_VERSION_STR "1.10.0.91" +#define HWRM_VERSION_RSVD 30 +#define HWRM_VERSION_STR "1.10.1.30" /**************** * hwrm_ver_get * @@ -905,7 +980,7 @@ struct hwrm_ver_get_input { */ uint8_t hwrm_intf_upd; uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ver_get_output (size:1408b/176B) */ struct hwrm_ver_get_output { @@ -1125,12 +1200,21 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \ UINT32_C(0x1000) /* + * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. * If set to 0, then the firmware doesn’t support TFLIB features. * By default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \ UINT32_C(0x2000) + /* + * If set to 1, the firmware is able to support TruFlow features. + * If set to 0, then the firmware doesn’t support TruFlow features. + * By default, this flag should be 0 for older version of + * core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ + UINT32_C(0x4000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1380,7 +1464,7 @@ struct hwrm_ver_get_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* bd_base (size:64b/8B) */ struct bd_base { @@ -1395,12 +1479,12 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) /* @@ -1426,7 +1510,7 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11) #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE uint8_t unused_1[7]; -} __attribute__((packed)); +} __rte_packed; /* tx_bd_short (size:128b/16B) */ struct tx_bd_short { @@ -1454,7 +1538,7 @@ struct tx_bd_short { #define TX_BD_SHORT_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40) @@ -1472,9 +1556,9 @@ struct tx_bd_short { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1535,7 +1619,7 @@ struct tx_bd_short { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* tx_bd_long (size:128b/16B) */ struct tx_bd_long { @@ -1562,7 +1646,7 @@ struct tx_bd_long { #define TX_BD_LONG_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40) @@ -1580,9 +1664,9 @@ struct tx_bd_long { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1642,7 +1726,7 @@ struct tx_bd_long { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* Last 16 bytes of tx_bd_long. */ /* tx_bd_long_hi (size:128b/16B) */ @@ -1663,7 +1747,7 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) /* - * If set to 1, the controller replaces the IP checksum of the + * If set to 1, the controller replaces the IP checksum of the * normal packets, or the inner IP checksum of the encapsulated * packets with the hardware calculated IP checksum for the * packet associated with this descriptor. @@ -1677,9 +1761,9 @@ struct tx_bd_long_hi { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not + * Packet must be 64B or longer when this flag is set. It is not * useful to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) @@ -1708,9 +1792,9 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* - * If set to 1, the device will treat this packet with LSO(Large + * If set to 1, the device will treat this packet with LSO(Large * Send Offload) processing for both normal or encapsulated - * packets, which is a form of TCP segmentation. When this bit + * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum * flags since the controller will replace the appropriate @@ -1743,19 +1827,19 @@ struct tx_bd_long_hi { #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t hdr_size; /* * When LSO is '1', this field must contain the offset of the * TCP payload from the beginning of the packet in as - * 16b words. In case of encapsulated/tunneling packet, this field + * 16b words. In case of encapsulated/tunneling packet, this field * contains the offset of the inner TCP payload from beginning of the * packet as 16-bit words. * @@ -1832,7 +1916,7 @@ struct tx_bd_long_hi { #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ TX_BD_LONG_CFA_META_KEY_VLAN_TAG -} __attribute__((packed)); +} __rte_packed; /* * This structure is used to inform the NIC of packet data that needs to be @@ -1862,7 +1946,7 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40) @@ -1967,12 +2051,12 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t unused2; @@ -2045,7 +2129,7 @@ struct tx_bd_long_inline { (UINT32_C(0x1) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG -} __attribute__((packed)); +} __rte_packed; /* tx_bd_empty (size:128b/16B) */ struct tx_bd_empty { @@ -2055,7 +2139,7 @@ struct tx_bd_empty { #define TX_BD_EMPTY_TYPE_SFT 0 /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1) #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY @@ -2063,7 +2147,7 @@ struct tx_bd_empty { uint8_t unused_2; uint8_t unused_3[3]; uint8_t unused_4[8]; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_pkt_bd (size:128b/16B) */ struct rx_prod_pkt_bd { @@ -2074,7 +2158,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_TYPE_SFT 0 /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4) #define RX_PROD_PKT_BD_TYPE_LAST \ @@ -2083,7 +2167,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_SFT 6 /* * If set to 1, the packet will be placed at the address plus - * 2B. The 2 Bytes of padding will be written as zero. + * 2B. The 2 Bytes of padding will be written as zero. */ #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40) /* @@ -2093,9 +2177,9 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* * This value is the number of additional buffers in the ring that - * describe the buffer space to be consumed for the this packet. + * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the - * space described by this BD. If this value is 1 or more, it + * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same * network packet. @@ -2118,10 +2202,10 @@ struct rx_prod_pkt_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_bfr_bd (size:128b/16B) */ struct rx_prod_bfr_bd { @@ -2147,10 +2231,10 @@ struct rx_prod_bfr_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_agg_bd (size:128b/16B) */ struct rx_prod_agg_bd { @@ -2186,10 +2270,10 @@ struct rx_prod_agg_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* cmpl_base (size:128b/16B) */ struct cmpl_base { @@ -2197,15 +2281,15 @@ struct cmpl_base { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f) #define CMPL_BASE_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) /* @@ -2216,7 +2300,7 @@ struct cmpl_base { /* * RX Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * TPA, HDS, or Jumbo packet completion. Length = 16B */ #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12) /* @@ -2265,8 +2349,8 @@ struct cmpl_base { uint32_t info2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint32_t info3_v; #define CMPL_BASE_V UINT32_C(0x1) @@ -2274,7 +2358,7 @@ struct cmpl_base { #define CMPL_BASE_INFO3_SFT 1 /* info4 is 32 b */ uint32_t info4; -} __attribute__((packed)); +} __rte_packed; /* tx_cmpl (size:128b/16B) */ struct tx_cmpl { @@ -2282,15 +2366,15 @@ struct tx_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define TX_CMPL_TYPE_MASK UINT32_C(0x3f) #define TX_CMPL_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0) #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2 @@ -2298,14 +2382,14 @@ struct tx_cmpl { #define TX_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet completed * was transmitted using the push acceleration data provided - * by the driver. When this bit is '0', it indicates that the + * by the driver. When this bit is '0', it indicates that the * packet had not push acceleration data written or was executed * as a normal packet even though push data was provided. */ @@ -2320,8 +2404,8 @@ struct tx_cmpl { uint16_t errors_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define TX_CMPL_V UINT32_C(0x1) #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -2343,7 +2427,7 @@ struct tx_cmpl { TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT /* * When this bit is '1', it indicates that the length of - * the packet was zero. No packet was transmitted. + * the packet was zero. No packet was transmitted. */ #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) /* @@ -2360,7 +2444,7 @@ struct tx_cmpl { #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet was longer - * than indicated by the hint. No packet was transmitted. + * than indicated by the hint. No packet was transmitted. */ #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) /* @@ -2373,7 +2457,7 @@ struct tx_cmpl { uint16_t unused_1; /* unused3 is 32 b */ uint32_t unused_2; -} __attribute__((packed)); +} __rte_packed; /* rx_pkt_cmpl (size:128b/16B) */ struct rx_pkt_cmpl { @@ -2381,8 +2465,8 @@ struct rx_pkt_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -2397,7 +2481,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -2498,9 +2582,9 @@ struct rx_pkt_cmpl { RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP /* * This is the length of the data for the packet stored in the - * buffer(s) identified by the opaque value. This includes - * the packet BD and any associated buffer BDs. This does not include - * the the length of any data places in aggregation BDs. + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -2511,8 +2595,8 @@ struct rx_pkt_cmpl { uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V1 UINT32_C(0x1) /* @@ -2527,7 +2611,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0) #define RX_PKT_CMPL_UNUSED1_SFT 6 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -2558,7 +2642,7 @@ struct rx_pkt_cmpl { uint8_t rss_hash_type; /* * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, + * where the inner payload starts. This value is valid for TCP, UDP, * FCoE, and RoCE packets. * * A value of zero indicates that header is 256B into the packet. @@ -2571,7 +2655,7 @@ struct rx_pkt_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; /* Last 16 bytes of rx_pkt_cmpl. */ /* rx_pkt_cmpl_hi (size:128b/16B) */ @@ -2604,7 +2688,7 @@ struct rx_pkt_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -2623,7 +2707,7 @@ struct rx_pkt_cmpl_hi { * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -2653,7 +2737,7 @@ struct rx_pkt_cmpl_hi { RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ @@ -2697,8 +2781,8 @@ struct rx_pkt_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V2 \ UINT32_C(0x1) @@ -2708,7 +2792,7 @@ struct rx_pkt_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -2721,7 +2805,7 @@ struct rx_pkt_cmpl_hi { * Did Not Fit: * Packet did not fit into packet buffer provided. * For regular placement, this means the packet did not fit - * in the buffer provided. For HDS and jumbo placement, this + * in the buffer provided. For HDS and jumbo placement, this * means that the packet could not be placed into 7 physical * buffers or less. */ @@ -2774,7 +2858,7 @@ struct rx_pkt_cmpl_hi { UINT32_C(0x80) /* * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * or RoCE packet. The itype indicates the packet type. */ #define RX_PKT_CMPL_ERRORS_CRC_ERROR \ UINT32_C(0x100) @@ -2912,12 +2996,12 @@ struct rx_pkt_cmpl_hi { * This value holds the reordering sequence number for the packet. * If the reordering sequence is not valid, then this value is zero. * The reordering domain for the packet is in the bottom 8 to 10b of - * the rss_hash value. The bottom 20b of this value contain the + * the rss_hash value. The bottom 20b of this value contain the * ordering domain value for the packet. */ #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff) #define RX_PKT_CMPL_REORDER_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the @@ -2929,8 +3013,8 @@ struct rx_tpa_start_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -2952,9 +3036,9 @@ struct rx_tpa_start_cmpl { #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3020,19 +3104,19 @@ struct rx_tpa_start_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3063,7 +3147,7 @@ struct rx_tpa_start_cmpl { uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3072,7 +3156,7 @@ struct rx_tpa_start_cmpl { #define RX_TPA_START_CMPL_UNUSED2_SFT 0 /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) @@ -3082,7 +3166,7 @@ struct rx_tpa_start_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; /* * Last 16 bytes of rx_tpa_start_cmpl. @@ -3120,7 +3204,7 @@ struct rx_tpa_start_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -3136,7 +3220,7 @@ struct rx_tpa_start_cmpl_hi { RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* @@ -3158,8 +3242,8 @@ struct rx_tpa_start_cmpl_hi { uint16_t v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) /* @@ -3175,7 +3259,7 @@ struct rx_tpa_start_cmpl_hi { uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this + * the outer L3 header. If there is no outer L3 header, then this * value is zero. */ #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) @@ -3199,7 +3283,7 @@ struct rx_tpa_start_cmpl_hi { */ #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the @@ -3211,8 +3295,8 @@ struct rx_tpa_end_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -3229,7 +3313,7 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -3238,9 +3322,9 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3283,7 +3367,7 @@ struct rx_tpa_end_cmpl { * This value indicates what the inner packet determined for the * packet was. * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates + * Indicates that the packet was IP and TCP. This indicates * that the ip_cs field is valid and that the tcp_udp_cs * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. @@ -3303,14 +3387,14 @@ struct rx_tpa_end_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) /* @@ -3326,7 +3410,7 @@ struct rx_tpa_end_cmpl { uint8_t tpa_segs; /* * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, + * where the inner payload starts. This value is valid for TCP, UDP, * FCoE, and RoCE packets. * * A value of zero indicates an offset of 256 bytes. @@ -3337,7 +3421,7 @@ struct rx_tpa_end_cmpl { #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) @@ -3351,12 +3435,12 @@ struct rx_tpa_end_cmpl { * For GRO packets, this field is zero except for the following * sub-fields. * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp * option is present in the packet. */ uint32_t tsdelta; -} __attribute__((packed)); +} __rte_packed; /* * Last 16 bytes of rx_tpa_end_cmpl. @@ -3374,13 +3458,13 @@ struct rx_tpa_end_cmpl_hi { #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* - * This value is the valid when TPA completion is active. It + * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation * for LRO mode and the length of the first segment in GRO mode. * * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; @@ -3389,8 +3473,8 @@ struct rx_tpa_end_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -3398,14 +3482,14 @@ struct rx_tpa_end_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ @@ -3414,7 +3498,7 @@ struct rx_tpa_end_cmpl_hi { /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. + * ring. All data for the TPA operation was not placed. * * This error can also be generated when the number of * segments is not programmed correctly in TPA and the @@ -3432,7 +3516,7 @@ struct rx_tpa_end_cmpl_hi { * completion that corresponds to this TPA end completion. */ uint32_t start_opaque; -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the @@ -3444,8 +3528,8 @@ struct rx_tpa_v2_start_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_START_CMPL_TYPE_MASK \ @@ -3472,9 +3556,9 @@ struct rx_tpa_v2_start_cmpl { #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3551,19 +3635,19 @@ struct rx_tpa_v2_start_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3594,7 +3678,7 @@ struct rx_tpa_v2_start_cmpl { uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3603,7 +3687,7 @@ struct rx_tpa_v2_start_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; /* * Last 16 bytes of rx_tpa_v2_start_cmpl. @@ -3646,7 +3730,7 @@ struct rx_tpa_v2_start_cmpl_hi { #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ UINT32_C(0xf0) #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata informtaion. Value is zero. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -3695,7 +3779,7 @@ struct rx_tpa_v2_start_cmpl_hi { RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ UINT32_C(0x100) @@ -3742,8 +3826,8 @@ struct rx_tpa_v2_start_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_START_CMPL_V2 \ UINT32_C(0x1) @@ -3753,7 +3837,7 @@ struct rx_tpa_v2_start_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -3794,7 +3878,7 @@ struct rx_tpa_v2_start_cmpl_hi { uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this + * the outer L3 header. If there is no outer L3 header, then this * value is zero. */ #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) @@ -3818,7 +3902,7 @@ struct rx_tpa_v2_start_cmpl_hi { */ #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the @@ -3830,8 +3914,8 @@ struct rx_tpa_v2_end_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -3848,7 +3932,7 @@ struct rx_tpa_v2_end_cmpl { #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -3857,9 +3941,9 @@ struct rx_tpa_v2_end_cmpl { #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ @@ -3902,7 +3986,7 @@ struct rx_tpa_v2_end_cmpl { * This value indicates what the inner packet determined for the * packet was. * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates + * Indicates that the packet was IP and TCP. This indicates * that the ip_cs field is valid and that the tcp_udp_cs * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. @@ -3923,15 +4007,15 @@ struct rx_tpa_v2_end_cmpl { uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) /* This value is the number of segments in the TPA operation. */ uint8_t tpa_segs; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; @@ -3944,12 +4028,12 @@ struct rx_tpa_v2_end_cmpl { * For GRO packets, this field is zero except for the following * sub-fields. * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp * option is present in the packet. */ uint32_t tsdelta; -} __attribute__((packed)); +} __rte_packed; /* * Last 16 bytes of rx_tpa_v2_end_cmpl. @@ -3986,13 +4070,13 @@ struct rx_tpa_v2_end_cmpl_hi { */ uint8_t tpa_agg_bufs; /* - * This value is the valid when TPA completion is active. It + * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation * for LRO mode and the length of the first segment in GRO mode. * * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; @@ -4000,8 +4084,8 @@ struct rx_tpa_v2_end_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ @@ -4010,7 +4094,7 @@ struct rx_tpa_v2_end_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -4021,7 +4105,7 @@ struct rx_tpa_v2_end_cmpl_hi { (UINT32_C(0x0) << 1) /* * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ @@ -4036,7 +4120,7 @@ struct rx_tpa_v2_end_cmpl_hi { /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. + * ring. All data for the TPA operation was not placed. * * This error can also be generated when the number of * segments is not programmed correctly in TPA and the @@ -4059,7 +4143,7 @@ struct rx_tpa_v2_end_cmpl_hi { * completion that corresponds to this TPA end completion. */ uint32_t start_opaque; -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the @@ -4071,8 +4155,8 @@ struct rx_tpa_v2_abuf_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4080,17 +4164,17 @@ struct rx_tpa_v2_abuf_cmpl { /* * RX TPA Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA packet completion. Length = 16B + * TPA packet completion. Length = 16B */ #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG /* * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not + * aggregation buffer identified by the opaque value. This does not * include the length of any * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to + * BDs. This length does not include any space added due to * hdr_offset register during HDS placement mode. */ uint16_t len; @@ -4102,8 +4186,8 @@ struct rx_tpa_v2_abuf_cmpl { uint16_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) /* @@ -4113,7 +4197,7 @@ struct rx_tpa_v2_abuf_cmpl { */ uint16_t agg_id; uint32_t unused_1; -} __attribute__((packed)); +} __rte_packed; /* rx_abuf_cmpl (size:128b/16B) */ struct rx_abuf_cmpl { @@ -4121,8 +4205,8 @@ struct rx_abuf_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4130,16 +4214,16 @@ struct rx_abuf_cmpl { /* * RX Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * TPA, HDS, or Jumbo packet completion. Length = 16B */ #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG /* * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not + * aggregation buffer identified by the opaque value. This does not * include the length of any * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to + * BDs. This length does not include any space added due to * hdr_offset register during HDS placement mode. */ uint16_t len; @@ -4151,13 +4235,13 @@ struct rx_abuf_cmpl { uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_ABUF_CMPL_V UINT32_C(0x1) /* unused3 is 32 b */ uint32_t unused_2; -} __attribute__((packed)); +} __rte_packed; /* eject_cmpl (size:128b/16B) */ struct eject_cmpl { @@ -4165,8 +4249,8 @@ struct eject_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4182,7 +4266,7 @@ struct eject_cmpl { #define EJECT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -4199,8 +4283,8 @@ struct eject_cmpl { uint16_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define EJECT_CMPL_V UINT32_C(0x1) #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) @@ -4239,7 +4323,7 @@ struct eject_cmpl { uint16_t reserved16; /* unused3 is 32 b */ uint32_t unused_2; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cmpl (size:128b/16B) */ struct hwrm_cmpl { @@ -4247,8 +4331,8 @@ struct hwrm_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4266,29 +4350,29 @@ struct hwrm_cmpl { uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_CMPL_V UINT32_C(0x1) /* unused4 is 32 b */ uint32_t unused_3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_req_cmpl (size:128b/16B) */ struct hwrm_fwd_req_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ uint16_t req_len_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4314,14 +4398,14 @@ struct hwrm_fwd_req_cmpl { uint32_t req_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) /* Address of forwarded request. */ #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_resp_cmpl (size:128b/16B) */ struct hwrm_fwd_resp_cmpl { @@ -4329,8 +4413,8 @@ struct hwrm_fwd_resp_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4355,14 +4439,14 @@ struct hwrm_fwd_resp_cmpl { uint32_t resp_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) /* Address of forwarded request. */ #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl (size:128b/16B) */ struct hwrm_async_event_cmpl { @@ -4370,8 +4454,8 @@ struct hwrm_async_event_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -4490,12 +4574,37 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ UINT32_C(0x3c) - /* TFLIB unique default VNIC Configuration Change */ + /* + * Deprecated. + * TFLIB unique default VNIC Configuration Change + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ UINT32_C(0x3d) - /* TFLIB unique link status changed */ + /* + * Deprecated. + * TFLIB unique link status changed + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ UINT32_C(0x3e) + /* + * An event signifying completion for HWRM_FW_STATE_QUIESCE + * (completion, timeout, or error) + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred. This event is used on crypto controllers + * only. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + /* + * An event signifying that a PFC WatchDog configuration + * has changed on any port / cos. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -4513,8 +4622,8 @@ struct hwrm_async_event_cmpl { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4526,7 +4635,7 @@ struct hwrm_async_event_cmpl { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_status_change { @@ -4534,8 +4643,8 @@ struct hwrm_async_event_cmpl_link_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ @@ -4558,8 +4667,8 @@ struct hwrm_async_event_cmpl_link_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -4605,7 +4714,7 @@ struct hwrm_async_event_cmpl_link_status_change { UINT32_C(0xff00000) #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ 20 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_mtu_change { @@ -4613,8 +4722,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ @@ -4637,8 +4746,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4655,7 +4764,7 @@ struct hwrm_async_event_cmpl_link_mtu_change { #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_change { @@ -4663,8 +4772,8 @@ struct hwrm_async_event_cmpl_link_speed_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ @@ -4687,8 +4796,8 @@ struct hwrm_async_event_cmpl_link_speed_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ UINT32_C(0x1) @@ -4750,7 +4859,7 @@ struct hwrm_async_event_cmpl_link_speed_change { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ struct hwrm_async_event_cmpl_dcb_config_change { @@ -4758,8 +4867,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ @@ -4791,8 +4900,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ UINT32_C(0x1) @@ -4831,7 +4940,7 @@ struct hwrm_async_event_cmpl_dcb_config_change { (UINT32_C(0xff) << 24) #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ struct hwrm_async_event_cmpl_port_conn_not_allowed { @@ -4839,8 +4948,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ @@ -4864,8 +4973,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4907,7 +5016,7 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { (UINT32_C(0x3) << 16) #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { @@ -4915,8 +5024,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ @@ -4940,8 +5049,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4960,7 +5069,7 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_cfg_change { @@ -4968,8 +5077,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ @@ -4993,8 +5102,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5029,7 +5138,7 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ UINT32_C(0x20000) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_port_phy_cfg_change { @@ -5037,8 +5146,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ @@ -5062,8 +5171,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5105,7 +5214,7 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ UINT32_C(0x40000) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ struct hwrm_async_event_cmpl_reset_notify { @@ -5113,8 +5222,8 @@ struct hwrm_async_event_cmpl_reset_notify { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ @@ -5137,8 +5246,8 @@ struct hwrm_async_event_cmpl_reset_notify { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5205,7 +5314,7 @@ struct hwrm_async_event_cmpl_reset_notify { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ struct hwrm_async_event_cmpl_error_recovery { @@ -5213,8 +5322,8 @@ struct hwrm_async_event_cmpl_error_recovery { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ @@ -5242,8 +5351,8 @@ struct hwrm_async_event_cmpl_error_recovery { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5274,7 +5383,7 @@ struct hwrm_async_event_cmpl_error_recovery { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ UINT32_C(0x2) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ struct hwrm_async_event_cmpl_func_drvr_unload { @@ -5282,8 +5391,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ @@ -5306,8 +5415,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5325,7 +5434,7 @@ struct hwrm_async_event_cmpl_func_drvr_unload { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ struct hwrm_async_event_cmpl_func_drvr_load { @@ -5333,8 +5442,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ @@ -5357,8 +5466,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5374,7 +5483,7 @@ struct hwrm_async_event_cmpl_func_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { @@ -5382,8 +5491,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ @@ -5407,8 +5516,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ UINT32_C(0x1) @@ -5427,7 +5536,7 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_drvr_unload { @@ -5435,8 +5544,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ @@ -5459,8 +5568,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5480,7 +5589,7 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_drvr_load { @@ -5488,8 +5597,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ @@ -5512,8 +5621,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5533,7 +5642,7 @@ struct hwrm_async_event_cmpl_pf_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_flr { @@ -5541,8 +5650,8 @@ struct hwrm_async_event_cmpl_vf_flr { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ @@ -5564,8 +5673,8 @@ struct hwrm_async_event_cmpl_vf_flr { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5585,7 +5694,7 @@ struct hwrm_async_event_cmpl_vf_flr { #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ UINT32_C(0xff0000) #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_mac_addr_change { @@ -5593,8 +5702,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ @@ -5617,8 +5726,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ UINT32_C(0x1) @@ -5637,7 +5746,7 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { @@ -5645,8 +5754,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ @@ -5670,8 +5779,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -5693,7 +5802,7 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ UINT32_C(0x1) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_cfg_change { @@ -5701,8 +5810,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ @@ -5725,8 +5834,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5778,7 +5887,7 @@ struct hwrm_async_event_cmpl_vf_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ UINT32_C(0x10) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ struct hwrm_async_event_cmpl_llfc_pfc_change { @@ -5786,8 +5895,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ @@ -5814,8 +5923,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5857,7 +5966,7 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { UINT32_C(0x1fffe0) #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 5 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ struct hwrm_async_event_cmpl_default_vnic_change { @@ -5865,8 +5974,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ @@ -5885,7 +5994,7 @@ struct hwrm_async_event_cmpl_default_vnic_change { 6 /* Identifiers of events. */ uint16_t event_id; - /* Notification of a default vnic allocaiton or free */ + /* Notification of a default vnic allocation or free */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ UINT32_C(0x35) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ @@ -5895,8 +6004,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ UINT32_C(0x1) @@ -5939,7 +6048,7 @@ struct hwrm_async_event_cmpl_default_vnic_change { UINT32_C(0x3fffc00) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ 10 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ struct hwrm_async_event_cmpl_hw_flow_aged { @@ -5947,8 +6056,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ @@ -5971,8 +6080,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6006,7 +6115,7 @@ struct hwrm_async_event_cmpl_hw_flow_aged { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cache_flush_req { @@ -6014,8 +6123,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ @@ -6039,8 +6148,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ UINT32_C(0x1) @@ -6054,7 +6163,7 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cache_flush_done { @@ -6062,8 +6171,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ @@ -6090,8 +6199,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ UINT32_C(0x1) @@ -6110,7 +6219,7 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ struct hwrm_async_event_cmpl_tcp_flag_action_change { @@ -6118,8 +6227,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ @@ -6143,8 +6252,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ UINT32_C(0x1) @@ -6158,7 +6267,7 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_flow_active { @@ -6166,8 +6275,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ @@ -6209,8 +6318,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6258,7 +6367,7 @@ struct hwrm_async_event_cmpl_eem_flow_active { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cfg_change { @@ -6266,8 +6375,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ @@ -6290,8 +6399,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6315,7 +6424,256 @@ struct hwrm_async_event_cmpl_eem_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ UINT32_C(0x2) -} __attribute__((packed)); +} __rte_packed; + +/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_quiesce_done { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* Event specific data */ + uint32_t event_data2; + /* Status of HWRM_FW_STATE_QUIESCE completion */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ + 0 + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * completed successfully. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ + UINT32_C(0x0) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed + * out. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + UINT32_C(0x1) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * encountered an error. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + /* opaque is 8 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ + 8 + /* + * Additional information about internal hardware state related to + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may + * inspect idle_state_flags to determine whether a retry is warranted. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ + 16 + /* + * Failure to quiesce is caused by host not updating the NQ consumer + * index. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ + UINT32_C(0x10000) + /* Flag 1 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ + UINT32_C(0x20000) + /* Flag 2 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ + UINT32_C(0x40000) + /* Flag 3 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ + UINT32_C(0x80000) + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ +struct hwrm_async_event_cmpl_deferred_response { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE + /* Event specific data */ + uint32_t event_data2; + /* + * The PF's mailbox is clear to issue another command. + * A command with this seq_id is still in progress + * and will return a regular HWRM completion when done. + * 'event_data1' field, if non-zero, contains the estimated + * execution time for the command. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Estimated remaining time of command execution in ms (if not zero) */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PFC watchdog configuration change for given port/cos */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * 1 in bit position X indicates PFC watchdog should + * be on for COSX + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ + 0 + /* 1 means PFC WD for COS0 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + UINT32_C(0x1) + /* 1 means PFC WD for COS1 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ + UINT32_C(0x2) + /* 1 means PFC WD for COS2 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ + UINT32_C(0x4) + /* 1 means PFC WD for COS3 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ + UINT32_C(0x8) + /* 1 means PFC WD for COS4 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ + UINT32_C(0x10) + /* 1 means PFC WD for COS5 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ + UINT32_C(0x20) + /* 1 means PFC WD for COS6 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ + UINT32_C(0x40) + /* 1 means PFC WD for COS7 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ + UINT32_C(0x80) + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff00) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 8 +} __rte_packed; /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { @@ -6323,8 +6681,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ @@ -6363,8 +6721,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6422,7 +6780,7 @@ struct hwrm_async_event_cmpl_fw_trace_msg { #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ UINT32_C(0xff000000) #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ struct hwrm_async_event_cmpl_hwrm_error { @@ -6430,8 +6788,8 @@ struct hwrm_async_event_cmpl_hwrm_error { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ @@ -6469,8 +6827,8 @@ struct hwrm_async_event_cmpl_hwrm_error { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6485,7 +6843,7 @@ struct hwrm_async_event_cmpl_hwrm_error { /* Time stamp for error event */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ UINT32_C(0x1) -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_func_reset * @@ -6568,7 +6926,7 @@ struct hwrm_func_reset_input { #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_reset_output (size:128b/16B) */ struct hwrm_func_reset_output { @@ -6589,7 +6947,7 @@ struct hwrm_func_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_getfid * @@ -6640,7 +6998,7 @@ struct hwrm_func_getfid_input { */ uint16_t pci_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_getfid_output (size:128b/16B) */ struct hwrm_func_getfid_output { @@ -6666,7 +7024,7 @@ struct hwrm_func_getfid_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_vf_alloc * @@ -6716,7 +7074,7 @@ struct hwrm_func_vf_alloc_input { uint16_t first_vf_id; /* The number of virtual functions requested. */ uint16_t num_vfs; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_alloc_output (size:128b/16B) */ struct hwrm_func_vf_alloc_output { @@ -6739,7 +7097,7 @@ struct hwrm_func_vf_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_func_vf_free * @@ -6792,7 +7150,7 @@ struct hwrm_func_vf_free_input { * 0xFFFF - Cleanup all children of this PF. */ uint16_t num_vfs; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_free_output (size:128b/16B) */ struct hwrm_func_vf_free_output { @@ -6813,7 +7171,7 @@ struct hwrm_func_vf_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_vf_cfg * @@ -7056,7 +7414,7 @@ struct hwrm_func_vf_cfg_input { /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ struct hwrm_func_vf_cfg_output { @@ -7077,7 +7435,7 @@ struct hwrm_func_vf_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_func_qcaps * @@ -7121,9 +7479,9 @@ struct hwrm_func_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_qcaps_output (size:640b/80B) */ +/* hwrm_func_qcaps_output (size:704b/88B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7335,6 +7693,42 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ UINT32_C(0x2000000) + /* + * If the query is for a VF, then this flag (always set to 0) shall + * be ignored. If this query is for a PF and this flag is set to 1, + * host, when registered for the default vnic change async event, + * receives async notification whenever a default vnic state is + * changed for any of child or adopted VFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ + UINT32_C(0x4000000) + /* If set to 1, then the vlan acceleration for TX is disabled. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_COREDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_CRASHDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ + UINT32_C(0x20000000) + /* + * If the query is for a VF, then this flag should be ignored. + * If the query is for a PF and this flag is set to 1, then + * the PF has the capability to support retrieval of + * rx_port_stats_ext_pfc_wd statistics (supported by the PFC + * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. + * If this flag is set to 1, only that (supported) command should + * be used for retrieval of PFC related statistics (rather than + * hwrm_port_qstats_ext command, which could previously be used). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + UINT32_C(0x40000000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -7445,7 +7839,22 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0; + uint8_t unused_0[2]; + uint32_t flags_ext; + /* + * If 1, the device can be configured to set the ECN bits in the + * IP header of received packets if the receive queue length + * exceeds a given threshold. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ + UINT32_C(0x1) + /* + * If 1, the device can report the number of received packets + * that it marked as having experienced congestion. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ + UINT32_C(0x2) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7454,7 +7863,7 @@ struct hwrm_func_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_func_qcfg * @@ -7498,9 +7907,9 @@ struct hwrm_func_qcfg_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_qcfg_output (size:704b/88B) */ +/* hwrm_func_qcfg_output (size:768b/96B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7905,7 +8314,22 @@ struct hwrm_func_qcfg_output { * after receiving the RESET Notify event. */ uint32_t reset_addr_poll; - uint8_t unused_2[3]; + /* + * This field specifies legacy L2 doorbell size in KBytes. Drivers should use + * this value to find out the doorbell page offset from the BAR. + */ + uint16_t legacy_l2_db_size_kb; + uint16_t svif_info; + /* + * This field specifies the source virtual interface of the function being + * queried. Drivers can use this to program svif field in the L2 context + * table + */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 + /* This field specifies whether svif is valid or not */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7914,7 +8338,7 @@ struct hwrm_func_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_func_cfg * @@ -8544,7 +8968,7 @@ struct hwrm_func_cfg_input { * be reserved for this function on the RX side. */ uint16_t num_mcast_filters; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ struct hwrm_func_cfg_output { @@ -8565,7 +8989,7 @@ struct hwrm_func_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_qstats * @@ -8606,10 +9030,23 @@ struct hwrm_func_qstats_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * A privileged PF can query for other function's statistics. */ uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY + uint8_t unused_0[5]; +} __rte_packed; /* hwrm_func_qstats_output (size:1408b/176B) */ struct hwrm_func_qstats_output { @@ -8691,7 +9128,7 @@ struct hwrm_func_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_func_clr_stats * @@ -8735,7 +9172,7 @@ struct hwrm_func_clr_stats_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_clr_stats_output (size:128b/16B) */ struct hwrm_func_clr_stats_output { @@ -8756,7 +9193,7 @@ struct hwrm_func_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_func_vf_resc_free * @@ -8799,7 +9236,7 @@ struct hwrm_func_vf_resc_free_input { */ uint16_t vf_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_resc_free_output (size:128b/16B) */ struct hwrm_func_vf_resc_free_output { @@ -8820,7 +9257,7 @@ struct hwrm_func_vf_resc_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_drv_rgtr * @@ -8928,12 +9365,11 @@ struct hwrm_func_drv_rgtr_input { UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select - * the Master function. The master function will be used to initiate - * designated functionality like error recovery etc. If none of the - * registered PFs or trusted VFs indicate this support, then - * firmware will select the 1st registered PF as Master capable - * instance. + * Master capability. The Firmware will use this capability to select the + * Master function. The master function will be used to initiate + * designated functionality like error recovery etc… If none of the + * registered PF’s or trusted VF’s indicate this support, then + * firmware will select the 1st registered PF as Master capable instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ UINT32_C(0x40) @@ -9045,7 +9481,7 @@ struct hwrm_func_drv_rgtr_input { uint16_t ver_upd; /* This is the 16bit patch version of the driver. */ uint16_t ver_patch; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_rgtr_output (size:128b/16B) */ struct hwrm_func_drv_rgtr_output { @@ -9073,7 +9509,7 @@ struct hwrm_func_drv_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_drv_unrgtr * @@ -9118,7 +9554,7 @@ struct hwrm_func_drv_unrgtr_input { #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ UINT32_C(0x1) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ struct hwrm_func_drv_unrgtr_output { @@ -9139,7 +9575,7 @@ struct hwrm_func_drv_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_buf_rgtr * @@ -9253,7 +9689,7 @@ struct hwrm_func_buf_rgtr_input { * HWRM. */ uint64_t resp_buf_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_buf_rgtr_output (size:128b/16B) */ struct hwrm_func_buf_rgtr_output { @@ -9274,7 +9710,7 @@ struct hwrm_func_buf_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_buf_unrgtr * @@ -9323,7 +9759,7 @@ struct hwrm_func_buf_unrgtr_input { */ uint16_t vf_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_buf_unrgtr_output (size:128b/16B) */ struct hwrm_func_buf_unrgtr_output { @@ -9344,7 +9780,7 @@ struct hwrm_func_buf_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_drv_qver * @@ -9390,7 +9826,7 @@ struct hwrm_func_drv_qver_input { */ uint16_t fid; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_qver_output (size:256b/32B) */ struct hwrm_func_drv_qver_output { @@ -9452,7 +9888,7 @@ struct hwrm_func_drv_qver_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_func_resource_qcaps * @@ -9496,7 +9932,7 @@ struct hwrm_func_resource_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_resource_qcaps_output (size:448b/56B) */ struct hwrm_func_resource_qcaps_output { @@ -9582,7 +10018,7 @@ struct hwrm_func_resource_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************* * hwrm_func_backing_store_qcaps * @@ -9619,9 +10055,9 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ +/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -9728,6 +10164,23 @@ struct hwrm_func_backing_store_qcaps_output { * limitations. */ uint8_t tqm_entries_multiple; + /* + * Initializer to be used by drivers + * to initialize context memory to ensure + * context subsystem flags an error for an attack + * before the first time context load. + */ + uint8_t ctx_kind_initializer; + /* Reserved for future. */ + uint32_t rsvd; + /* Reserved for future. */ + uint16_t rsvd1; + /* + * Count of TQM fastpath rings to be used for allocating backing store. + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9736,7 +10189,7 @@ struct hwrm_func_backing_store_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_backing_store_cfg * @@ -10750,7 +11203,7 @@ struct hwrm_func_backing_store_cfg_input { uint16_t mrav_entry_size; /* Number of bytes that have been allocated for each context entry. */ uint16_t tim_entry_size; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ struct hwrm_func_backing_store_cfg_output { @@ -10771,7 +11224,7 @@ struct hwrm_func_backing_store_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_func_backing_store_qcfg * @@ -10808,7 +11261,7 @@ struct hwrm_func_backing_store_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ struct hwrm_func_backing_store_qcfg_output { @@ -11685,7 +12138,7 @@ struct hwrm_func_backing_store_qcfg_output { * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_error_recovery_qcfg * @@ -11723,7 +12176,7 @@ struct hwrm_error_recovery_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ struct hwrm_error_recovery_qcfg_output { @@ -12042,7 +12495,54 @@ struct hwrm_error_recovery_qcfg_output { * this much time after writing reset_reg_val in reset_reg. */ uint8_t delay_after_reset[16]; - uint8_t unused_1[7]; + /* + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12052,7 +12552,7 @@ struct hwrm_error_recovery_qcfg_output { * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_func_vlan_qcfg * @@ -12097,7 +12597,7 @@ struct hwrm_func_vlan_qcfg_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vlan_qcfg_output (size:320b/40B) */ struct hwrm_func_vlan_qcfg_output { @@ -12143,7 +12643,7 @@ struct hwrm_func_vlan_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_vlan_cfg * @@ -12244,7 +12744,7 @@ struct hwrm_func_vlan_cfg_input { /* Future use. */ uint32_t rsvd2; uint8_t unused_3[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vlan_cfg_output (size:128b/16B) */ struct hwrm_func_vlan_cfg_output { @@ -12265,7 +12765,7 @@ struct hwrm_func_vlan_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_vf_vnic_ids_query * @@ -12312,7 +12812,7 @@ struct hwrm_func_vf_vnic_ids_query_input { uint32_t max_vnic_id_cnt; /* This is the address for VF VNIC ID table */ uint64_t vnic_id_tbl_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ struct hwrm_func_vf_vnic_ids_query_output { @@ -12339,7 +12839,7 @@ struct hwrm_func_vf_vnic_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_func_vf_bw_cfg * @@ -12443,7 +12943,7 @@ struct hwrm_func_vf_bw_cfg_input { (UINT32_C(0xf) << 12) #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ struct hwrm_func_vf_bw_cfg_output { @@ -12464,7 +12964,7 @@ struct hwrm_func_vf_bw_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_vf_bw_qcfg * @@ -12513,7 +13013,7 @@ struct hwrm_func_vf_bw_qcfg_input { /* The physical VF id of interest */ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ struct hwrm_func_vf_bw_qcfg_output { @@ -12602,7 +13102,7 @@ struct hwrm_func_vf_bw_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_func_drv_if_change * @@ -12655,7 +13155,7 @@ struct hwrm_func_drv_if_change_input { */ #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) uint32_t unused; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_if_change_output (size:128b/16B) */ struct hwrm_func_drv_if_change_output { @@ -12691,7 +13191,7 @@ struct hwrm_func_drv_if_change_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_host_pf_ids_query * @@ -12777,7 +13277,7 @@ struct hwrm_func_host_pf_ids_query_input { #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE uint8_t unused_1[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ struct hwrm_func_host_pf_ids_query_output { @@ -12897,7 +13397,7 @@ struct hwrm_func_host_pf_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_phy_cfg * @@ -13369,7 +13869,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -13431,7 +13931,7 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x40) uint8_t unused_2[2]; /* - * Reuested setting of TX LPI timer in microseconds. + * Requested setting of TX LPI timer in microseconds. * This field is valid only when EEE is enabled and TX LPI is * enabled. */ @@ -13439,7 +13939,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 uint32_t unused_3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_cfg_output (size:128b/16B) */ struct hwrm_port_phy_cfg_output { @@ -13460,7 +13960,7 @@ struct hwrm_port_phy_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ struct hwrm_port_phy_cfg_cmd_err { @@ -13489,7 +13989,7 @@ struct hwrm_port_phy_cfg_cmd_err { #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \ HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_phy_qcfg * @@ -13529,7 +14029,7 @@ struct hwrm_port_phy_qcfg_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_qcfg_output (size:768b/96B) */ struct hwrm_port_phy_qcfg_output { @@ -13861,7 +14361,7 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -13903,6 +14403,9 @@ struct hwrm_port_phy_qcfg_output { /* Module is not inserted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ UINT32_C(0x4) + /* Module is powered down because of over current fault. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \ + UINT32_C(0x5) /* Module status is not applicable. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ UINT32_C(0xff) @@ -14377,7 +14880,7 @@ struct hwrm_port_phy_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_mac_cfg * @@ -14500,7 +15003,7 @@ struct hwrm_port_mac_cfg_input { #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \ UINT32_C(0x100) /* - * When this bit is '1', the the Out-Of-Box WoL is requested to + * When this bit is '1', the Out-Of-Box WoL is requested to * be disabled on this port. */ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \ @@ -14670,7 +15173,7 @@ struct hwrm_port_mac_cfg_input { * This field shall be ignored if the ptp_tx_ts_capture_enable * flag is not set in this command. * Otherwise, if bit 'i' is set, then the HWRM is being - * requested to configure the transmit sied of the port to + * requested to configure the transmit side of the port to * capture the time stamp of every transmitted PTP message * with messageType field value set to i. */ @@ -14778,7 +15281,7 @@ struct hwrm_port_mac_cfg_input { */ int32_t ptp_freq_adj_ppb; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ struct hwrm_port_mac_cfg_output { @@ -14832,7 +15335,7 @@ struct hwrm_port_mac_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_mac_qcfg * @@ -14872,9 +15375,9 @@ struct hwrm_port_mac_qcfg_input { /* Port ID of port that is to be configured. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_port_mac_qcfg_output (size:192b/24B) */ +/* hwrm_port_mac_qcfg_output (size:256b/32B) */ struct hwrm_port_mac_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15114,6 +15617,20 @@ struct hwrm_port_mac_qcfg_output { UINT32_C(0xe0) #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ 5 + uint8_t unused_1; + uint16_t port_svif_info; + /* + * This field specifies the source virtual interface of the port being + * queried. Drivers can use this to program port svif field in the + * L2 context table + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \ + UINT32_C(0x7fff) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 + /* This field specifies whether port_svif is valid or not */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \ + UINT32_C(0x8000) + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15122,7 +15639,7 @@ struct hwrm_port_mac_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_port_mac_ptp_qcfg * @@ -15162,7 +15679,7 @@ struct hwrm_port_mac_ptp_qcfg_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ struct hwrm_port_mac_ptp_qcfg_output { @@ -15185,18 +15702,18 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ UINT32_C(0x1) - /* - * When this bit is set to '1', the PTP information is accessible - * via HWRM commands. - */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ - UINT32_C(0x2) /* * When this bit is set to '1', the device supports one-step * Tx timestamping. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \ UINT32_C(0x4) + /* + * When this bit is set to '1', the PTP information is accessible + * via HWRM commands. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ + UINT32_C(0x8) uint8_t unused_0[3]; /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ uint32_t rx_ts_reg_off_lower; @@ -15237,9 +15754,9 @@ struct hwrm_port_mac_ptp_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/* Port Tx Statistics Formats */ +/* Port Tx Statistics Format */ /* tx_port_stats (size:3264b/408B) */ struct tx_port_stats { /* Total Number of 64 Bytes frames transmitted */ @@ -15378,9 +15895,9 @@ struct tx_port_stats { uint64_t tx_stat_discard; /* Total Tx Error Drops per Port reported by STATS block */ uint64_t tx_stat_error; -} __attribute__((packed)); +} __rte_packed; -/* Port Rx Statistics Formats */ +/* Port Rx Statistics Format */ /* rx_port_stats (size:4224b/528B) */ struct rx_port_stats { /* Total Number of 64 Bytes frames received */ @@ -15593,7 +16110,7 @@ struct rx_port_stats { /* Total Rx Discards per Port reported by STATS block */ uint64_t rx_stat_discard; uint64_t rx_stat_err; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_port_qstats * @@ -15643,7 +16160,7 @@ struct hwrm_port_qstats_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_qstats_output (size:128b/16B) */ struct hwrm_port_qstats_output { @@ -15668,9 +16185,9 @@ struct hwrm_port_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/* Port Tx Statistics extended Formats */ +/* Port Tx Statistics extended Format */ /* tx_port_stats_ext (size:2048b/256B) */ struct tx_port_stats_ext { /* Total number of tx bytes count on cos queue 0 */ @@ -15737,9 +16254,9 @@ struct tx_port_stats_ext { uint64_t pfc_pri7_tx_duration_us; /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */ uint64_t pfc_pri7_tx_transitions; -} __attribute__((packed)); +} __rte_packed; -/* Port Rx Statistics extended Formats */ +/* Port Rx Statistics extended Format */ /* rx_port_stats_ext (size:3648b/456B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -15859,7 +16376,425 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; -} __attribute__((packed)); +} __rte_packed; + +/* + * Port Rx Statistics extended PFC WatchDog Format. + * StormDetect and StormRevert event determination is based + * on an integration period and a percentage threshold. + * StormDetect event - when percentage of XOFF frames received + * within an integration period exceeds the configured threshold. + * StormRevert event - when percentage of XON frames received + * within an integration period exceeds the configured threshold. + * Actual number of XOFF/XON frames for the events to be triggered + * depends on both configured integration period and sampling rate. + * The statistics in this structure represent counts of specified + * events from the moment the feature (PFC WatchDog) is enabled via + * hwrm_queue_pfc_enable_cfg call. + */ +/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */ +struct rx_port_stats_ext_pfc_wd { + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri0; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri1; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri2; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri3; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri4; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri5; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri6; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri7; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri0; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri1; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri2; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri3; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri4; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri5; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri6; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri7; + /* + * Total number of packets received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri0; + /* + * Total number of packets received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri1; + /* + * Total number of packets received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri2; + /* + * Total number of packets received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri3; + /* + * Total number of packets received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri4; + /* + * Total number of packets received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri5; + /* + * Total number of packets received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri6; + /* + * Total number of packets received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri7; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7; + /* + * Number of packets received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0; + /* + * Number of packets received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1; + /* + * Number of packets received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2; + /* + * Number of packets received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3; + /* + * Number of packets received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4; + /* + * Number of packets received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5; + /* + * Number of packets received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6; + /* + * Number of packets received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7; +} __rte_packed; /************************ * hwrm_port_qstats_ext * @@ -15919,7 +16854,7 @@ struct hwrm_port_qstats_ext_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_qstats_ext_output (size:128b/16B) */ struct hwrm_port_qstats_ext_output { @@ -15952,7 +16887,84 @@ struct hwrm_port_qstats_ext_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/******************************* + * hwrm_port_qstats_ext_pfc_wd * + *******************************/ + + +/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */ +struct hwrm_port_qstats_ext_pfc_wd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + /* + * The size of rx_port_stats_ext_pfc_wd + * block in bytes + */ + uint16_t pfc_wd_stat_size; + uint8_t unused_0[4]; + /* + * This is the host address where + * rx_port_stats_ext_pfc_wd will be stored + */ + uint64_t pfc_wd_stat_host_addr; +} __rte_packed; + +/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */ +struct hwrm_port_qstats_ext_pfc_wd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The size of rx_port_stats_ext_pfc_wd + * statistics block in bytes. + */ + uint16_t pfc_wd_stat_size; + uint8_t flags; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; + uint8_t unused_0[4]; +} __rte_packed; /************************* * hwrm_port_lpbk_qstats * @@ -15989,7 +17001,7 @@ struct hwrm_port_lpbk_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ struct hwrm_port_lpbk_qstats_output { @@ -16030,7 +17042,92 @@ struct hwrm_port_lpbk_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/************************ + * hwrm_port_ecn_qstats * + ************************/ + + +/* hwrm_port_ecn_qstats_input (size:192b/24B) */ +struct hwrm_port_ecn_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port that is being queried. Unused if NIC is in + * multi-host mode. + */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_ecn_qstats_output (size:384b/48B) */ +struct hwrm_port_ecn_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of packets marked in CoS queue 0. */ + uint32_t mark_cnt_cos0; + /* Number of packets marked in CoS queue 1. */ + uint32_t mark_cnt_cos1; + /* Number of packets marked in CoS queue 2. */ + uint32_t mark_cnt_cos2; + /* Number of packets marked in CoS queue 3. */ + uint32_t mark_cnt_cos3; + /* Number of packets marked in CoS queue 4. */ + uint32_t mark_cnt_cos4; + /* Number of packets marked in CoS queue 5. */ + uint32_t mark_cnt_cos5; + /* Number of packets marked in CoS queue 6. */ + uint32_t mark_cnt_cos6; + /* Number of packets marked in CoS queue 7. */ + uint32_t mark_cnt_cos7; + /* + * Bitmask that indicates which CoS queues have ECN marking enabled. + * Bit i corresponds to CoS queue i. + */ + uint8_t mark_en; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; /*********************** * hwrm_port_clr_stats * @@ -16081,7 +17178,7 @@ struct hwrm_port_clr_stats_input { */ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_clr_stats_output (size:128b/16B) */ struct hwrm_port_clr_stats_output { @@ -16102,7 +17199,7 @@ struct hwrm_port_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_phy_qcaps * @@ -16142,7 +17239,7 @@ struct hwrm_port_phy_qcaps_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_qcaps_output (size:192b/24B) */ struct hwrm_port_phy_qcaps_output { @@ -16168,13 +17265,28 @@ struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \ UINT32_C(0x2) + /* + * If set to 1, then this field indicates that the + * PHY is capable of supporting loopback in autoneg mode. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \ + UINT32_C(0x4) + /* + * Indicates if the configuration of shared PHY settings is supported. + * In cases where a physical port is shared by multiple functions + * (e.g. NPAR, multihost, etc), the configuration of PHY + * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will + * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ + UINT32_C(0x8) /* * Reserved field. The HWRM shall set this field to 0. * An HWRM client shall ignore this field. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xfc) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2 + UINT32_C(0xf0) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -16357,7 +17469,7 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ UINT32_C(0xff000000) #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_port_phy_mdio_write * @@ -16413,7 +17525,7 @@ struct hwrm_port_phy_mdio_write_input { uint8_t cl45_mdio; /* */ uint8_t unused_1[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ struct hwrm_port_phy_mdio_write_output { @@ -16434,7 +17546,7 @@ struct hwrm_port_phy_mdio_write_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_port_phy_mdio_read * @@ -16488,7 +17600,7 @@ struct hwrm_port_phy_mdio_read_input { uint8_t cl45_mdio; /* */ uint8_t unused_1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ struct hwrm_port_phy_mdio_read_output { @@ -16511,7 +17623,7 @@ struct hwrm_port_phy_mdio_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_led_cfg * @@ -16914,7 +18026,7 @@ struct hwrm_port_led_cfg_input { uint8_t led3_group_id; /* Reserved field. */ uint8_t rsvd3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_cfg_output (size:128b/16B) */ struct hwrm_port_led_cfg_output { @@ -16935,7 +18047,7 @@ struct hwrm_port_led_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_led_qcfg * @@ -16975,7 +18087,7 @@ struct hwrm_port_led_qcfg_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_qcfg_output (size:448b/56B) */ struct hwrm_port_led_qcfg_output { @@ -17241,7 +18353,7 @@ struct hwrm_port_led_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_led_qcaps * @@ -17281,7 +18393,7 @@ struct hwrm_port_led_qcaps_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_qcaps_output (size:384b/48B) */ struct hwrm_port_led_qcaps_output { @@ -17593,7 +18705,7 @@ struct hwrm_port_led_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_prbs_test * @@ -17700,7 +18812,7 @@ struct hwrm_port_prbs_test_input { * bit1 = lane1 ..bit31 = lane31 */ uint32_t rx_lane_map; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_prbs_test_output (size:128b/16B) */ struct hwrm_port_prbs_test_output { @@ -17724,7 +18836,554 @@ struct hwrm_port_prbs_test_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/********************** + * hwrm_port_dsc_dump * + **********************/ + + +/* hwrm_port_dsc_dump_input (size:320b/40B) */ +struct hwrm_port_dsc_dump_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Host address where response diagnostic data is returned. */ + uint64_t resp_data_addr; + /* + * Size of the buffer pointed to by resp_data_addr. The firmware + * may use this entire buffer or less than the entire buffer, but + * never more. + */ + uint16_t data_len; + uint16_t unused_0; + uint32_t unused_1; + /* Port ID of port where dsc dump to be collected. */ + uint16_t port_id; + /* Diag level specified by the user */ + uint16_t diag_level; + /* SRDS_DIAG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \ + UINT32_C(0x0) + /* SRDS_DIAG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \ + UINT32_C(0x1) + /* SRDS_DIAG_EVENT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \ + UINT32_C(0x2) + /* SRDS_DIAG_EYE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \ + UINT32_C(0x3) + /* SRDS_DIAG_REG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \ + UINT32_C(0x4) + /* SRDS_DIAG_REG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \ + UINT32_C(0x5) + /* SRDS_DIAG_UC_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \ + UINT32_C(0x6) + /* SRDS_DIAG_UC_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \ + UINT32_C(0x7) + /* SRDS_DIAG_LANE_DEBUG */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \ + UINT32_C(0x8) + /* SRDS_DIAG_BER_VERT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \ + UINT32_C(0x9) + /* SRDS_DIAG_BER_HORZ */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \ + UINT32_C(0xa) + /* SRDS_DIAG_EVENT_SAFE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \ + UINT32_C(0xb) + /* SRDS_DIAG_TIMESTAMP */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \ + UINT32_C(0xc) + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \ + HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP + /* + * This field is a lane number + * on which to collect the dsc dump + */ + uint16_t lane_number; + /* + * Configuration bits. + * Use enable bit to start dsc dump or retrieve dump + */ + uint16_t dsc_dump_config; + /* + * Set 0 to retrieve the dsc dump + * Set 1 to start the dsc dump + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_port_dsc_dump_output (size:128b/16B) */ +struct hwrm_port_dsc_dump_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of stored data. */ + uint16_t total_data_len; + uint16_t unused_0; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_port_sfp_sideband_cfg * + ******************************/ + + +/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */ +struct hwrm_port_sfp_sideband_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; + /* + * This bitfield is used to specify which bits from the 'flags' + * fields are being configured by the caller. + */ + uint32_t enables; + /* This bit must be '1' for rs0 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \ + UINT32_C(0x1) + /* This bit must be '1' for rs1 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \ + UINT32_C(0x2) + /* This bit must be '1' for tx_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \ + UINT32_C(0x4) + /* + * This bit must be '1' for mod_sel to be configured. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \ + UINT32_C(0x8) + /* This bit must be '1' for reset_l to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \ + UINT32_C(0x10) + /* This bit must be '1' for lp_mode to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \ + UINT32_C(0x20) + /* This bit must be '1' for pwr_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \ + UINT32_C(0x40) + /* + * Only bits that have corresponding bits in the 'enables' + * bitfield are processed by the firmware, all other bits + * of 'flags' are ignored. + */ + uint32_t flags; + /* + * This bit along with rs1 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ + UINT32_C(0x1) + /* + * This bit along with rs0 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ + UINT32_C(0x2) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, + * module PHY registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \ + UINT32_C(0x4) + /* + * When this bit is set to '1', this module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \ + UINT32_C(0x8) + /* + * If reset_l is set to 0, Module will be taken out of reset + * and other signals will be set to their requested state once + * the module is out of reset. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \ + UINT32_C(0x10) + /* + * When this bit is set to '1', the module will be configured + * in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \ + UINT32_C(0x20) + /* When this bit is set to '1', the module will be powered down. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \ + UINT32_C(0x40) +} __rte_packed; + +/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */ +struct hwrm_port_sfp_sideband_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_port_sfp_sideband_qcfg * + *******************************/ + + +/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which sideband signals are valid. + * This is based on the board and nvm cfg that is present on the board. + */ + uint32_t supported_mask; + uint32_t sideband_signals; + /* When this bit is set to '1', the Module is absent. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \ + UINT32_C(0x1) + /* + * When this bit is set to '1', there is no valid signal on RX. + * This signal is a filtered version of Signal Detect. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ + UINT32_C(0x2) + /* + * This bit along with rs1 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ + UINT32_C(0x4) + /* + * This bit along with rs0 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ + UINT32_C(0x8) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, module PHY + * registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \ + UINT32_C(0x10) + /* When this bit is set to '1', tx_fault is set. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \ + UINT32_C(0x40) + /* + * When this bit is set to '0', the module is held in reset. + * if reset_l is set to 1,first module is taken out of reset + * and other signals will be set to their requested state. + * Valid only on QSFP modules. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \ + UINT32_C(0x80) + /* + * When this bit is set to '1', the module is in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \ + UINT32_C(0x100) + /* When this bit is set to '1', module is in power down state. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \ + UINT32_C(0x200) + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_port_phy_mdio_bus_acquire * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_acquire_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS access. + * Any value from 0x10 to 0xFFFF can be used. + * Client should make sure that the returned client_id + * in response matches the client_id in request. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + /* + * Timeout in milli seconds, MDIO BUS will be released automatically + * after this time, if another mdio acquire command is not received + * within the timeout window from the same client. + * A 0xFFFF will hold the bus until this bus is released. + */ + uint16_t mdio_bus_timeout; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_acquire_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* + * client_id of the module holding the BUS. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_port_phy_mdio_bus_release * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_release_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS release. + * A client should not release any other clients BUS. + */ + uint16_t client_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_release_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* The BUS is released if client_id matches the client_id in request. */ + uint16_t clients_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; /*********************** * hwrm_queue_qportcfg * @@ -17776,7 +19435,7 @@ struct hwrm_queue_qportcfg_input { HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX /* * Port ID of port for which the queue configuration is being - * queried. This field is only required when sent by IPC. + * queried. This field is only required when sent by IPC. */ uint16_t port_id; /* @@ -17791,7 +19450,7 @@ struct hwrm_queue_qportcfg_input { #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \ HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_qportcfg_output (size:256b/32B) */ struct hwrm_queue_qportcfg_output { @@ -18171,13 +19830,13 @@ struct hwrm_queue_qportcfg_output { HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_queue_qcfg * @@ -18229,7 +19888,7 @@ struct hwrm_queue_qcfg_input { HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX /* Queue ID of the queue. */ uint32_t queue_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_qcfg_output (size:128b/16B) */ struct hwrm_queue_qcfg_output { @@ -18242,7 +19901,7 @@ struct hwrm_queue_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This value is a the estimate packet length used in the + * This value is the estimate packet length used in the * TX arbiter. */ uint32_t queue_len; @@ -18269,13 +19928,13 @@ struct hwrm_queue_qcfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_queue_cfg * @@ -18358,7 +20017,7 @@ struct hwrm_queue_cfg_input { #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cfg_output (size:128b/16B) */ struct hwrm_queue_cfg_output { @@ -18373,13 +20032,13 @@ struct hwrm_queue_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_queue_pfcenable_qcfg * @@ -18423,7 +20082,7 @@ struct hwrm_queue_pfcenable_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ struct hwrm_queue_pfcenable_qcfg_output { @@ -18460,16 +20119,40 @@ struct hwrm_queue_pfcenable_qcfg_output { /* If set to 1, then PFC is enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_queue_pfcenable_cfg * @@ -18513,24 +20196,48 @@ struct hwrm_queue_pfcenable_cfg_input { /* If set to 1, then PFC is requested to be enabled on PRI 1. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ UINT32_C(0x2) - /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ UINT32_C(0x4) - /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ UINT32_C(0x8) - /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ UINT32_C(0x10) - /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ UINT32_C(0x20) - /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ UINT32_C(0x40) - /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed @@ -18538,7 +20245,7 @@ struct hwrm_queue_pfcenable_cfg_input { */ uint16_t port_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ struct hwrm_queue_pfcenable_cfg_output { @@ -18553,13 +20260,13 @@ struct hwrm_queue_pfcenable_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_queue_pri2cos_qcfg * @@ -18611,9 +20318,9 @@ struct hwrm_queue_pri2cos_qcfg_input { HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX /* * When this bit is set to '0', the query is - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the query is - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) /* @@ -18623,7 +20330,7 @@ struct hwrm_queue_pri2cos_qcfg_input { */ uint8_t port_id; uint8_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ struct hwrm_queue_pri2cos_qcfg_output { @@ -18636,56 +20343,56 @@ struct hwrm_queue_pri2cos_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri1_cos_queue_id; /* - * CoS Queue assigned to priority 2 This value can only + * CoS Queue assigned to priority 2. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. @@ -18704,13 +20411,13 @@ struct hwrm_queue_pri2cos_qcfg_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_queue_pri2cos_cfg * @@ -18765,9 +20472,9 @@ struct hwrm_queue_pri2cos_cfg_input { HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR /* * When this bit is set to '0', the mapping is requested - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the mapping is requested - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) uint32_t enables; @@ -18826,12 +20533,12 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t port_id; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. */ uint8_t pri1_cos_queue_id; @@ -18841,32 +20548,32 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. */ uint8_t pri7_cos_queue_id; uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ struct hwrm_queue_pri2cos_cfg_output { @@ -18881,13 +20588,13 @@ struct hwrm_queue_pri2cos_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_queue_cos2bw_qcfg * @@ -18931,7 +20638,7 @@ struct hwrm_queue_cos2bw_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ struct hwrm_queue_cos2bw_qcfg_output { @@ -19924,13 +21631,13 @@ struct hwrm_queue_cos2bw_qcfg_output { uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_queue_cos2bw_cfg * @@ -21001,7 +22708,7 @@ struct hwrm_queue_cos2bw_cfg_input { */ uint8_t queue_id7_bw_weight; uint8_t unused_1[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ struct hwrm_queue_cos2bw_cfg_output { @@ -21016,21 +22723,174 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************* - * hwrm_vnic_alloc * - *******************/ +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ -/* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ + + +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; + /* + * This is the default PRI which un-initialized DSCP values are + * mapped to. + */ + uint8_t default_pri; + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ + + +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21059,17 +22919,43 @@ struct hwrm_vnic_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. + */ + uint64_t src_data_addr; uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + UINT32_C(0x1) + uint32_t enables; /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. + * This bit must be '1' for the default_pri field to be + * configured. */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + UINT32_C(0x1) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + /* + * This is the default PRI which un-initialized DSCP values will be + * mapped to. + */ + uint8_t default_pri; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. + */ + uint16_t entry_cnt; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21078,26 +22964,24 @@ struct hwrm_vnic_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************** - * hwrm_vnic_free * - ******************/ +/************************* + * hwrm_queue_mpls_qcaps * + *************************/ -/* hwrm_vnic_free_input (size:192b/24B) */ -struct hwrm_vnic_free_input { +/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ +struct hwrm_queue_mpls_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21126,13 +23010,17 @@ struct hwrm_vnic_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_vnic_free_output (size:128b/16B) */ -struct hwrm_vnic_free_output { +/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ +struct hwrm_queue_mpls_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21141,24 +23029,445 @@ struct hwrm_vnic_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * Bitmask indicating which queues can be configured by the + * hwrm_queue_mplstc2pri_cfg command. + * + * Each bit represents a specific pri where bit 0 represents + * pri 0 and bit 7 represents pri 7. + * # A value of 0 indicates that the pri is not configurable + * by the hwrm_queue_mplstc2pri_cfg command. + * # A value of 1 indicates that the pri is configurable. + * # A hwrm_queue_mplstc2pri_cfg command shall return error when + * trying to configure a pri that is not configurable. + */ + uint8_t queue_mplstc2pri_cfg_allowed; + /* + * This is the default PRI which un-initialized MPLS values will be + * mapped to. + */ + uint8_t hw_default_pri; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_mplstc2pri_qcfg * + ******************************/ + + +/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 0. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 1. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 2. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 3. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 4. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 5. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 6. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 7. + */ + uint8_t tc7_pri_queue_id; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/***************** - * hwrm_vnic_cfg * - *****************/ +/***************************** + * hwrm_queue_mplstc2pri_cfg * + *****************************/ -/* hwrm_vnic_cfg_input (size:384b/48B) */ -struct hwrm_vnic_cfg_input { +/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_mplstc2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the mplstc0_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mplstc1_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the mplstc2_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the mplstc3_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the mplstc4_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the mplstc5_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the mplstc6_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the mplstc7_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP)to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only + * be changed before traffic has started. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only + * be changed before traffic has started. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2 This value can only + * be changed before traffic has started. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only + * be changed before traffic has started. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only + * be changed before traffic has started. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only + * be changed before traffic has started. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + */ + uint8_t tc7_pri_queue_id; +} __rte_packed; + +/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_mplstc2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_vnic_alloc * + *******************/ + + +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_vnic_free * + ******************/ + + +/* hwrm_vnic_free_input (size:192b/24B) */ +struct hwrm_vnic_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_free_output (size:128b/16B) */ +struct hwrm_vnic_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_vnic_cfg * + *****************/ + + +/* hwrm_vnic_cfg_input (size:384b/48B) */ +struct hwrm_vnic_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21361,7 +23670,7 @@ struct hwrm_vnic_cfg_input { */ uint16_t queue_id; uint8_t unused0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_cfg_output (size:128b/16B) */ struct hwrm_vnic_cfg_output { @@ -21382,7 +23691,7 @@ struct hwrm_vnic_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_vnic_qcfg * @@ -21430,7 +23739,7 @@ struct hwrm_vnic_qcfg_input { /* ID of Virtual Function whose VNIC resource is being queried. */ uint16_t vf_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_qcfg_output (size:256b/32B) */ struct hwrm_vnic_qcfg_output { @@ -21529,7 +23838,13 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) - uint8_t unused_1[7]; + /* + * When returned with a valid CoS Queue id, the CoS Queue/VNIC association + * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS + * queue association. + */ + uint16_t queue_id; + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21538,7 +23853,7 @@ struct hwrm_vnic_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_vnic_qcaps * @@ -21577,7 +23892,7 @@ struct hwrm_vnic_qcaps_input { uint64_t resp_addr; uint32_t enables; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_qcaps_output (size:192b/24B) */ struct hwrm_vnic_qcaps_output { @@ -21681,7 +23996,7 @@ struct hwrm_vnic_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_vnic_tpa_cfg * @@ -21866,7 +24181,7 @@ struct hwrm_vnic_tpa_cfg_input { * and can be queried using hwrm_vnic_tpa_qcfg. */ uint32_t min_agg_len; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ struct hwrm_vnic_tpa_cfg_output { @@ -21887,7 +24202,7 @@ struct hwrm_vnic_tpa_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_vnic_rss_cfg * @@ -22017,7 +24332,7 @@ struct hwrm_vnic_rss_cfg_input { /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; uint8_t unused_1[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ struct hwrm_vnic_rss_cfg_output { @@ -22038,7 +24353,28 @@ struct hwrm_vnic_rss_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ +struct hwrm_vnic_rss_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* + * Unable to change global RSS mode to outer due to all active + * interfaces are not ready to support outer RSS hashing. + */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \ + UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ + HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY + uint8_t unused_0[7]; +} __rte_packed; /********************** * hwrm_vnic_rss_qcfg * @@ -22078,7 +24414,7 @@ struct hwrm_vnic_rss_qcfg_input { /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ struct hwrm_vnic_rss_qcfg_output { @@ -22181,7 +24517,7 @@ struct hwrm_vnic_rss_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_vnic_plcmodes_cfg * @@ -22308,7 +24644,7 @@ struct hwrm_vnic_plcmodes_cfg_input { /* * This value is used to determine the offset into * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. + * placed according to one of HDS placement algorithm. * * The lengths of packet buffers provided for split data * shall be larger than this value. @@ -22324,7 +24660,7 @@ struct hwrm_vnic_plcmodes_cfg_input { */ uint16_t hds_threshold; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ struct hwrm_vnic_plcmodes_cfg_output { @@ -22345,7 +24681,7 @@ struct hwrm_vnic_plcmodes_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_vnic_plcmodes_qcfg * @@ -22385,7 +24721,7 @@ struct hwrm_vnic_plcmodes_qcfg_input { /* Logical vnic ID */ uint32_t vnic_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ struct hwrm_vnic_plcmodes_qcfg_output { @@ -22450,7 +24786,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { /* * This value is used to determine the offset into * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. + * placed according to one of HDS placement algorithm. * * The lengths of packet buffers provided for split data * shall be larger than this value. @@ -22474,7 +24810,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************** * hwrm_vnic_rss_cos_lb_ctx_alloc * @@ -22511,7 +24847,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { @@ -22534,7 +24870,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************* * hwrm_vnic_rss_cos_lb_ctx_free * @@ -22574,7 +24910,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input { /* rss_cos_lb_ctx_id is 16 b */ uint16_t rss_cos_lb_ctx_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ struct hwrm_vnic_rss_cos_lb_ctx_free_output { @@ -22595,7 +24931,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_ring_alloc * @@ -22908,7 +25244,7 @@ struct hwrm_ring_alloc_input { * record. */ uint64_t cq_handle; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_alloc_output (size:128b/16B) */ struct hwrm_ring_alloc_output { @@ -22936,7 +25272,7 @@ struct hwrm_ring_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_ring_free * @@ -22993,7 +25329,7 @@ struct hwrm_ring_free_input { /* Physical number of ring allocated. */ uint16_t ring_id; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_free_output (size:128b/16B) */ struct hwrm_ring_free_output { @@ -23014,7 +25350,7 @@ struct hwrm_ring_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_ring_reset * @@ -23067,7 +25403,7 @@ struct hwrm_ring_reset_input { /* Physical number of the ring. */ uint16_t ring_id; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_reset_output (size:128b/16B) */ struct hwrm_ring_reset_output { @@ -23090,7 +25426,7 @@ struct hwrm_ring_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_ring_aggint_qcaps * @@ -23127,7 +25463,7 @@ struct hwrm_ring_aggint_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ struct hwrm_ring_aggint_qcaps_output { @@ -23240,7 +25576,7 @@ struct hwrm_ring_aggint_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************************** * hwrm_ring_cmpl_ring_qaggint_params * @@ -23280,7 +25616,7 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input { /* Physical number of completion ring. */ uint16_t ring_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ struct hwrm_ring_cmpl_ring_qaggint_params_output { @@ -23347,7 +25683,7 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************************** * hwrm_ring_cmpl_ring_cfg_aggint_params * @@ -23483,7 +25819,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ UINT32_C(0x20) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { @@ -23504,7 +25840,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_ring_grp_alloc * @@ -23562,7 +25898,7 @@ struct hwrm_ring_grp_alloc_input { * with the ring group. */ uint16_t sc; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_grp_alloc_output (size:128b/16B) */ struct hwrm_ring_grp_alloc_output { @@ -23589,7 +25925,7 @@ struct hwrm_ring_grp_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_ring_grp_free * @@ -23629,7 +25965,7 @@ struct hwrm_ring_grp_free_input { /* This is the ring group ID value. */ uint32_t ring_group_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ring_grp_free_output (size:128b/16B) */ struct hwrm_ring_grp_free_output { @@ -23650,7 +25986,7 @@ struct hwrm_ring_grp_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* * special reserved flow ID to identify per function default * flows for vSwitch offload @@ -23768,7 +26104,7 @@ struct hwrm_cfa_l2_filter_alloc_input { UINT32_C(0x40) /* * Setting this flag to 1 indicate the L2 fields in this command - * pertain to source fields. Setting this flag to 0 indicate the + * pertain to source fields. Setting this flag to 0 indicate the * L2 fields in this command pertain to the destination fields * and this is the default/legacy behavior. */ @@ -24010,7 +26346,7 @@ struct hwrm_cfa_l2_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -24082,7 +26418,7 @@ struct hwrm_cfa_l2_filter_alloc_input { * 2 - Below the given filter */ uint64_t l2_filter_id_hint; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ struct hwrm_cfa_l2_filter_alloc_output { @@ -24142,13 +26478,13 @@ struct hwrm_cfa_l2_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_cfa_l2_filter_free * @@ -24190,7 +26526,7 @@ struct hwrm_cfa_l2_filter_free_input { * context. */ uint64_t l2_filter_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ struct hwrm_cfa_l2_filter_free_output { @@ -24205,13 +26541,13 @@ struct hwrm_cfa_l2_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_cfa_l2_filter_cfg * @@ -24318,7 +26654,7 @@ struct hwrm_cfa_l2_filter_cfg_input { * mirrored. */ uint32_t new_mirror_vnic_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ struct hwrm_cfa_l2_filter_cfg_output { @@ -24333,13 +26669,13 @@ struct hwrm_cfa_l2_filter_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_cfa_l2_set_rx_mask * @@ -24500,7 +26836,7 @@ struct hwrm_cfa_l2_set_rx_mask_input { */ uint32_t num_vlan_tags; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ struct hwrm_cfa_l2_set_rx_mask_output { @@ -24515,13 +26851,13 @@ struct hwrm_cfa_l2_set_rx_mask_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ struct hwrm_cfa_l2_set_rx_mask_cmd_err { @@ -24539,7 +26875,7 @@ struct hwrm_cfa_l2_set_rx_mask_cmd_err { #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_vlan_antispoof_cfg * @@ -24593,7 +26929,7 @@ struct hwrm_cfa_vlan_antispoof_cfg_input { * for the 12-bit VLAN ID. */ uint64_t vlan_tag_mask_tbl_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ struct hwrm_cfa_vlan_antispoof_cfg_output { @@ -24608,13 +26944,13 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_vlan_antispoof_qcfg * @@ -24671,7 +27007,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input { * the mask value should be 0xfff for the 12-bit VLAN ID. */ uint64_t vlan_tag_mask_tbl_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ struct hwrm_cfa_vlan_antispoof_qcfg_output { @@ -24688,13 +27024,13 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_tunnel_filter_alloc * @@ -24863,7 +27199,7 @@ struct hwrm_cfa_tunnel_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -24941,7 +27277,7 @@ struct hwrm_cfa_tunnel_filter_alloc_input { * mirrored. */ uint32_t mirror_vnic_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ struct hwrm_cfa_tunnel_filter_alloc_output { @@ -24998,13 +27334,13 @@ struct hwrm_cfa_tunnel_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_tunnel_filter_free * @@ -25043,7 +27379,7 @@ struct hwrm_cfa_tunnel_filter_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t tunnel_filter_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ struct hwrm_cfa_tunnel_filter_free_output { @@ -25058,13 +27394,13 @@ struct hwrm_cfa_tunnel_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************************** * hwrm_cfa_redirect_tunnel_type_alloc * @@ -25123,7 +27459,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25155,7 +27491,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ UINT32_C(0x1) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ struct hwrm_cfa_redirect_tunnel_type_alloc_output { @@ -25170,13 +27506,13 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************************** * hwrm_cfa_redirect_tunnel_type_free * @@ -25235,7 +27571,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25262,7 +27598,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ struct hwrm_cfa_redirect_tunnel_type_free_output { @@ -25277,13 +27613,13 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************************** * hwrm_cfa_redirect_tunnel_type_info * @@ -25342,7 +27678,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -25369,7 +27705,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ struct hwrm_cfa_redirect_tunnel_type_info_output { @@ -25386,13 +27722,13 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ struct hwrm_vxlan_ipv4_hdr { @@ -25418,7 +27754,7 @@ struct hwrm_vxlan_ipv4_hdr { uint32_t src_ip_addr; /* IPv4 destination address. */ uint32_t dest_ip_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ struct hwrm_vxlan_ipv6_hdr { @@ -25454,7 +27790,7 @@ struct hwrm_vxlan_ipv6_hdr { uint32_t src_ip_addr[4]; /* IPv6 destination address. */ uint32_t dest_ip_addr[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ struct hwrm_cfa_encap_data_vxlan { @@ -25499,7 +27835,7 @@ struct hwrm_cfa_encap_data_vxlan { /* VXLAN header flags field. */ uint8_t hdr_flags; uint8_t unused[3]; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_encap_record_alloc * @@ -25564,7 +27900,7 @@ struct hwrm_cfa_encap_record_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ UINT32_C(0x6) /* VLAN */ @@ -25590,7 +27926,7 @@ struct hwrm_cfa_encap_record_alloc_input { uint8_t unused_0[3]; /* This value is encap data used for the given encap type. */ uint32_t encap_data[20]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ struct hwrm_cfa_encap_record_alloc_output { @@ -25607,13 +27943,13 @@ struct hwrm_cfa_encap_record_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_cfa_encap_record_free * @@ -25653,7 +27989,7 @@ struct hwrm_cfa_encap_record_free_input { /* This value is an opaque id into CFA data structures. */ uint32_t encap_record_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ struct hwrm_cfa_encap_record_free_output { @@ -25668,20 +28004,20 @@ struct hwrm_cfa_encap_record_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_ntuple_filter_alloc * ********************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */ +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -25729,11 +28065,25 @@ struct hwrm_cfa_ntuple_filter_alloc_input { #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ UINT32_C(0x4) /* - * Setting of this flag indicates that the dest_id field contains function ID. + * Setting of this flag indicates that the dst_id field contains function ID. * If this is not set it indicates dest_id is VNIC or VPORT. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ UINT32_C(0x8) + /* + * Setting of this flag indicates match on arp reply when ethertype is 0x0806. + * If this is not set it indicates no specific arp opcode matching. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ + UINT32_C(0x10) + /* + * Setting of this flag indicates that the dst_id field contains RFS ring + * table index. If this is not set it indicates dst_id is VNIC or VPORT + * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at + * the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x20) uint32_t enables; /* * This bit must be '1' for the l2_filter_id field to be @@ -25849,10 +28199,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x40000) - /* - * This bit must be '1' for the rfs_ring_tbl_idx field to be - * configured. - */ + /* This flag is deprecated. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ UINT32_C(0x80000) /* @@ -25942,7 +28289,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -26038,14 +28385,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * the pri_hint. */ uint64_t ntuple_filter_id_hint; - /* - * The value of rfs_ring_tbl_idx to be used for RFS for this filter. - * This index is used in lieu of the RSS hash when selecting the - * index into the RSS table to determine the rx ring. - */ - uint16_t rfs_ring_tbl_idx; - uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ struct hwrm_cfa_ntuple_filter_alloc_output { @@ -26102,13 +28442,13 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ struct hwrm_cfa_ntuple_filter_alloc_cmd_err { @@ -26126,7 +28466,7 @@ struct hwrm_cfa_ntuple_filter_alloc_cmd_err { #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_ntuple_filter_free * @@ -26165,7 +28505,7 @@ struct hwrm_cfa_ntuple_filter_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ struct hwrm_cfa_ntuple_filter_free_output { @@ -26180,13 +28520,13 @@ struct hwrm_cfa_ntuple_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_cfa_ntuple_filter_cfg * @@ -26249,6 +28589,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input { */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ UINT32_C(0x1) + /* + * Setting of this flag indicates that the new_dst_id field contains + * RFS ring table index. If this is not set it indicates new_dst_id is + * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x2) /* This value is an opaque id into CFA data structures. */ uint64_t ntuple_filter_id; /* @@ -26278,7 +28626,7 @@ struct hwrm_cfa_ntuple_filter_cfg_input { #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID uint8_t unused_1[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ struct hwrm_cfa_ntuple_filter_cfg_output { @@ -26293,13 +28641,13 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_cfa_em_flow_alloc * @@ -26508,7 +28856,7 @@ struct hwrm_cfa_em_flow_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -26642,7 +28990,7 @@ struct hwrm_cfa_em_flow_alloc_input { /* Logical ID of the encapsulation record. */ uint32_t encap_record_id; uint8_t unused_2[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ struct hwrm_cfa_em_flow_alloc_output { @@ -26699,13 +29047,13 @@ struct hwrm_cfa_em_flow_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_cfa_em_flow_free * @@ -26744,7 +29092,7 @@ struct hwrm_cfa_em_flow_free_input { uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ uint64_t em_filter_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_em_flow_free_output (size:128b/16B) */ struct hwrm_cfa_em_flow_free_output { @@ -26759,13 +29107,13 @@ struct hwrm_cfa_em_flow_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_cfa_meter_qcaps * @@ -26802,7 +29150,7 @@ struct hwrm_cfa_meter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ struct hwrm_cfa_meter_qcaps_output { @@ -26872,13 +29220,13 @@ struct hwrm_cfa_meter_qcaps_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_meter_profile_alloc * @@ -27125,7 +29473,7 @@ struct hwrm_cfa_meter_profile_alloc_input { (UINT32_C(0x7) << 29) #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ struct hwrm_cfa_meter_profile_alloc_output { @@ -27150,13 +29498,13 @@ struct hwrm_cfa_meter_profile_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_meter_profile_free * @@ -27220,7 +29568,7 @@ struct hwrm_cfa_meter_profile_free_input { #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ struct hwrm_cfa_meter_profile_free_output { @@ -27235,13 +29583,13 @@ struct hwrm_cfa_meter_profile_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_cfa_meter_profile_cfg * @@ -27491,7 +29839,7 @@ struct hwrm_cfa_meter_profile_cfg_input { (UINT32_C(0x7) << 29) #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ struct hwrm_cfa_meter_profile_cfg_output { @@ -27506,13 +29854,13 @@ struct hwrm_cfa_meter_profile_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************* * hwrm_cfa_meter_instance_alloc * @@ -27577,7 +29925,7 @@ struct hwrm_cfa_meter_instance_alloc_input { #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ struct hwrm_cfa_meter_instance_alloc_output { @@ -27602,13 +29950,13 @@ struct hwrm_cfa_meter_instance_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_meter_instance_cfg * @@ -27680,7 +30028,7 @@ struct hwrm_cfa_meter_instance_cfg_input { */ uint16_t meter_instance_id; uint8_t unused_1[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ struct hwrm_cfa_meter_instance_cfg_output { @@ -27695,13 +30043,13 @@ struct hwrm_cfa_meter_instance_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_meter_instance_free * @@ -27765,7 +30113,7 @@ struct hwrm_cfa_meter_instance_free_input { #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ struct hwrm_cfa_meter_instance_free_output { @@ -27780,13 +30128,13 @@ struct hwrm_cfa_meter_instance_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_cfa_decap_filter_alloc * @@ -27958,7 +30306,7 @@ struct hwrm_cfa_decap_filter_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28088,7 +30436,7 @@ struct hwrm_cfa_decap_filter_alloc_input { * information of the decap filter. */ uint16_t l2_ctxt_ref_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ struct hwrm_cfa_decap_filter_alloc_output { @@ -28105,13 +30453,13 @@ struct hwrm_cfa_decap_filter_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_cfa_decap_filter_free * @@ -28151,7 +30499,7 @@ struct hwrm_cfa_decap_filter_free_input { /* This value is an opaque id into CFA data structures. */ uint32_t decap_filter_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ struct hwrm_cfa_decap_filter_free_output { @@ -28166,13 +30514,13 @@ struct hwrm_cfa_decap_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_cfa_flow_alloc * @@ -28326,7 +30674,7 @@ struct hwrm_cfa_flow_alloc_input { UINT32_C(0x800) /* * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be + * most optimal flow table resource. If set to 0, the flow will be * placed to the default flow table resource. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ @@ -28335,7 +30683,7 @@ struct hwrm_cfa_flow_alloc_input { * If set to 1 there will be no attempt to allocate an on-chip try to * offload this flow. If set to 0, which will keep compatibility with the * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior + * counter for the newly created flow. This will keep the existing behavior * with EM flows which always had an associated flow counter. */ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ @@ -28428,7 +30776,7 @@ struct hwrm_cfa_flow_alloc_input { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28454,7 +30802,7 @@ struct hwrm_cfa_flow_alloc_input { UINT32_C(0xff) #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ struct hwrm_cfa_flow_alloc_output { @@ -28515,13 +30863,13 @@ struct hwrm_cfa_flow_alloc_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ struct hwrm_cfa_flow_alloc_cmd_err { @@ -28549,7 +30897,7 @@ struct hwrm_cfa_flow_alloc_cmd_err { #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_cfa_flow_free * @@ -28593,7 +30941,7 @@ struct hwrm_cfa_flow_free_input { uint32_t flow_counter_id; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_free_output (size:256b/32B) */ struct hwrm_cfa_flow_free_output { @@ -28612,13 +30960,13 @@ struct hwrm_cfa_flow_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_action_data (size:960b/120B) */ struct hwrm_cfa_flow_action_data { @@ -28651,10 +30999,10 @@ struct hwrm_cfa_flow_action_data { /* If set to 1, flow aging is enabled for this flow. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ UINT32_C(0x80) - /* Setting of this flag indicates encap action.. */ + /* Setting of this flag indicates encap action. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ UINT32_C(0x100) - /* Setting of this flag indicates decap action.. */ + /* Setting of this flag indicates decap action. */ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ UINT32_C(0x200) /* Meter id. */ @@ -28680,7 +31028,7 @@ struct hwrm_cfa_flow_action_data { #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) /* VLAN */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) @@ -28699,7 +31047,7 @@ struct hwrm_cfa_flow_action_data { uint8_t unused[7]; /* This value is encap data for the associated encap type. */ uint32_t encap_data[20]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ struct hwrm_cfa_flow_tunnel_hdr_data { @@ -28723,7 +31071,7 @@ struct hwrm_cfa_flow_tunnel_hdr_data { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ @@ -28755,7 +31103,7 @@ struct hwrm_cfa_flow_tunnel_hdr_data { * Virtual Network Identifier (VNI). */ uint32_t tunnel_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ struct hwrm_cfa_flow_l4_key_data { @@ -28764,7 +31112,7 @@ struct hwrm_cfa_flow_l4_key_data { /* The value of destination port. */ uint16_t l4_dst_port; uint32_t unused; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ struct hwrm_cfa_flow_l3_key_data { @@ -28778,7 +31126,7 @@ struct hwrm_cfa_flow_l3_key_data { /* NAT IPv4/IPv6 address. */ uint32_t nat_ip_address[4]; uint32_t unused[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ struct hwrm_cfa_flow_l2_key_data { @@ -28811,7 +31159,7 @@ struct hwrm_cfa_flow_l2_key_data { /* Inner VLAN TCI. */ uint16_t ivlan_tci; uint8_t unused[8]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_key_data (size:4160b/520B) */ struct hwrm_cfa_flow_key_data { @@ -28841,7 +31189,7 @@ struct hwrm_cfa_flow_key_data { uint32_t l4_key_data[2]; /* Flow associated L4 header mask info. */ uint32_t l4_key_mask[2]; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_cfa_flow_info * @@ -28899,7 +31247,7 @@ struct hwrm_cfa_flow_info_input { uint8_t unused_0[6]; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_info_output (size:5632b/704B) */ struct hwrm_cfa_flow_info_output { @@ -28946,13 +31294,13 @@ struct hwrm_cfa_flow_info_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_cfa_flow_flush * @@ -29001,7 +31349,7 @@ struct hwrm_cfa_flow_flush_input { UINT32_C(0x1) /* * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables..etc. This flag is set to 0 by older driver. For older firmware, + * context memory tables etc. This flag is set to 0 by older driver. For older firmware, * setting this flag has no effect. */ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ @@ -29065,7 +31413,7 @@ struct hwrm_cfa_flow_flush_input { uint16_t num_flows; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_flush_output (size:128b/16B) */ struct hwrm_cfa_flow_flush_output { @@ -29080,13 +31428,13 @@ struct hwrm_cfa_flow_flush_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_cfa_flow_stats * @@ -29166,7 +31514,7 @@ struct hwrm_cfa_flow_stats_input { uint32_t flow_id_8; /* Flow ID of a flow. */ uint32_t flow_id_9; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ struct hwrm_cfa_flow_stats_output { @@ -29221,13 +31569,13 @@ struct hwrm_cfa_flow_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************************** * hwrm_cfa_flow_aging_timer_reset * @@ -29274,7 +31622,7 @@ struct hwrm_cfa_flow_aging_timer_reset_input { uint32_t flow_timer; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ struct hwrm_cfa_flow_aging_timer_reset_output { @@ -29289,13 +31637,13 @@ struct hwrm_cfa_flow_aging_timer_reset_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_cfa_flow_aging_cfg * @@ -29399,7 +31747,7 @@ struct hwrm_cfa_flow_aging_cfg_input { #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ struct hwrm_cfa_flow_aging_cfg_output { @@ -29414,13 +31762,13 @@ struct hwrm_cfa_flow_aging_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_cfa_flow_aging_qcfg * @@ -29468,7 +31816,7 @@ struct hwrm_cfa_flow_aging_qcfg_input { #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ struct hwrm_cfa_flow_aging_qcfg_output { @@ -29499,13 +31847,13 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_cfa_flow_aging_qcaps * @@ -29553,7 +31901,7 @@ struct hwrm_cfa_flow_aging_qcaps_input { #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ struct hwrm_cfa_flow_aging_qcaps_output { @@ -29576,13 +31924,13 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************** * hwrm_cfa_tcp_flag_process_qcfg * @@ -29619,7 +31967,7 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ struct hwrm_cfa_tcp_flag_process_qcfg_output { @@ -29642,13 +31990,13 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_cfa_pair_info * @@ -29698,7 +32046,7 @@ struct hwrm_cfa_pair_info_input { uint8_t pair_vfid; /* Pair name (32 byte string). */ char pair_name[32]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_pair_info_output (size:576b/72B) */ struct hwrm_cfa_pair_info_output { @@ -29763,13 +32111,13 @@ struct hwrm_cfa_pair_info_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************************** * hwrm_cfa_redirect_query_tunnel_type * @@ -29809,7 +32157,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_input { /* The source function id. */ uint16_t src_fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ struct hwrm_cfa_redirect_query_tunnel_type_output { @@ -29841,7 +32189,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { /* Generic Network Virtualization Encapsulation (Geneve) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ UINT32_C(0x20) - /* Multi-Protocol Lable Switching (MPLS) */ + /* Multi-Protocol Label Switching (MPLS) */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ UINT32_C(0x40) /* Stateless Transport Tunnel (STT) */ @@ -29868,13 +32216,13 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_cfa_ctx_mem_rgtr * @@ -29945,7 +32293,7 @@ struct hwrm_cfa_ctx_mem_rgtr_input { uint32_t unused_0; /* Pointer to the PBL, or PDL depending on number of levels */ uint64_t page_dir; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ struct hwrm_cfa_ctx_mem_rgtr_output { @@ -29958,20 +32306,20 @@ struct hwrm_cfa_ctx_mem_rgtr_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_cfa_ctx_mem_unrgtr * @@ -30009,12 +32357,12 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ struct hwrm_cfa_ctx_mem_unrgtr_output { @@ -30029,13 +32377,13 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_cfa_ctx_mem_qctx * @@ -30073,12 +32421,12 @@ struct hwrm_cfa_ctx_mem_qctx_input { */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is passed + * Id/Handle to the recently register context memory. This handle is passed * to the CFA feature. */ uint16_t ctx_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ struct hwrm_cfa_ctx_mem_qctx_output { @@ -30127,13 +32475,13 @@ struct hwrm_cfa_ctx_mem_qctx_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_cfa_ctx_mem_qcaps * @@ -30170,7 +32518,7 @@ struct hwrm_cfa_ctx_mem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ struct hwrm_cfa_ctx_mem_qcaps_output { @@ -30187,13 +32535,13 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_cfa_eem_qcaps * @@ -30249,7 +32597,7 @@ struct hwrm_cfa_eem_qcaps_input { #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x4) uint32_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ struct hwrm_cfa_eem_qcaps_output { @@ -30278,15 +32626,15 @@ struct hwrm_cfa_eem_qcaps_output { UINT32_C(0x2) /* * When set to 1, indicates the the FW supports the Centralized - * Memory Model. The concept designates one entity for the + * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* * When set to 1, indicates the the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of * which can interfere with the management of the memory. */ @@ -30326,7 +32674,7 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ UINT32_C(0x10) /* - * The maximum number of entries supported by EEM. When configuring the host memory + * The maximum number of entries supported by EEM. When configuring the host memory * the number of numbers of entries that can supported are - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. * Any value that are not these values, the FW will round down to the closest support @@ -30344,13 +32692,13 @@ struct hwrm_cfa_eem_qcaps_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_cfa_eem_cfg * @@ -30415,9 +32763,9 @@ struct hwrm_cfa_eem_cfg_input { uint16_t group_id; uint16_t unused_0; /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, + * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * using this value. Current minimum value is 32k. Current maximum value is 128M. */ uint32_t num_entries; uint32_t unused_1; @@ -30433,7 +32781,7 @@ struct hwrm_cfa_eem_cfg_input { uint16_t fid_ctx_id; uint16_t unused_2; uint32_t unused_3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ struct hwrm_cfa_eem_cfg_output { @@ -30448,13 +32796,13 @@ struct hwrm_cfa_eem_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_cfa_eem_qcfg * @@ -30497,7 +32845,7 @@ struct hwrm_cfa_eem_qcfg_input { /* When set to 1, indicates the configuration is the RX flow. */ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) uint32_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ struct hwrm_cfa_eem_qcfg_output { @@ -30534,13 +32882,13 @@ struct hwrm_cfa_eem_qcfg_output { uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_cfa_eem_op * @@ -30597,7 +32945,7 @@ struct hwrm_cfa_eem_op_input { #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) /* * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will + * must disable EEM for the given PF, using this call. This will * safely disable EEM and ensure that all DMA'ed to the * keys/records/efc have been completed. */ @@ -30605,7 +32953,7 @@ struct hwrm_cfa_eem_op_input { /* * Once the EEM host memory has been configured, EEM options have * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism + * PF. Note once this call has been made, then the EEM mechanism * will be active and DMA's will occur as packets are processed. */ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) @@ -30616,7 +32964,7 @@ struct hwrm_cfa_eem_op_input { #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP -} __attribute__((packed)); +} __rte_packed; /* hwrm_cfa_eem_op_output (size:128b/16B) */ struct hwrm_cfa_eem_op_output { @@ -30631,13 +32979,13 @@ struct hwrm_cfa_eem_op_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_cfa_adv_flow_mgnt_qcaps * @@ -30674,160 +33022,2252 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint32_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + UINT32_C(0x1) + /* + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + UINT32_C(0x2) + /* + * Value of 1 to indicate firmware support flow batch delete operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow batch delete + * operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + UINT32_C(0x4) + /* + * Value of 1 to indicate that the firmware support flow reset all operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + UINT32_C(0x8) + /* + * Value of 1 to indicate that firmware supports use of FID as dest_id in + * HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as dest_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + UINT32_C(0x10) + /* + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x20) + /* + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x40) + /* + * Value of 1 to indicate that firmware supports the dynamic allocation of an + * on-chip flow counter which can be used for EEM flows. + * Value of 0 indicates firmware does not support the dynamic allocation of an + * on-chip flow counter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + UINT32_C(0x80) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + UINT32_C(0x100) + /* + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + UINT32_C(0x200) + /* + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ + UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_cfa_tflib * + ******************/ + + +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} __rte_packed; + +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********** + * hwrm_tf * + ***********/ + + +/* hwrm_tf_input (size:1024b/128B) */ +struct hwrm_tf_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* unused. */ + uint8_t unused0[4]; + /* TF request data. */ + uint32_t req[26]; +} __rte_packed; + +/* hwrm_tf_output (size:5632b/704B) */ +struct hwrm_tf_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* TF response code */ + uint32_t resp_code; + /* TF response data. */ + uint32_t resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tf_version_get * + ***********************/ + + +/* hwrm_tf_version_get_input (size:128b/16B) */ +struct hwrm_tf_version_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_tf_version_get_output (size:128b/16B) */ +struct hwrm_tf_version_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Version Major number. */ + uint8_t major; + /* Version Minor number. */ + uint8_t minor; + /* Version Update number. */ + uint8_t update; + /* unused. */ + uint8_t unused0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tf_session_open * + ************************/ + + +/* hwrm_tf_session_open_input (size:640b/80B) */ +struct hwrm_tf_session_open_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Name of the session. */ + uint8_t session_name[64]; +} __rte_packed; + +/* hwrm_tf_session_open_output (size:128b/16B) */ +struct hwrm_tf_session_open_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. + */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tf_session_attach * + **************************/ + + +/* hwrm_tf_session_attach_input (size:704b/88B) */ +struct hwrm_tf_session_attach_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session that the attach + * request want to attach to. This value originates from the + * shared session memory that the attach request opened by + * way of the 'attach name' that was passed in to the core + * attach API. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. + */ + uint32_t attach_fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session it self. */ + uint8_t session_name[64]; +} __rte_packed; + +/* hwrm_tf_session_attach_output (size:128b/16B) */ +struct hwrm_tf_session_attach_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. This fw_session_id is unique to the attach + * request. + */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_tf_session_close * + *************************/ + + +/* hwrm_tf_session_close_input (size:192b/24B) */ +struct hwrm_tf_session_close_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; + +/* hwrm_tf_session_close_output (size:128b/16B) */ +struct hwrm_tf_session_close_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tf_session_qcfg * + ************************/ + + +/* hwrm_tf_session_qcfg_input (size:192b/24B) */ +struct hwrm_tf_session_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; + +/* hwrm_tf_session_qcfg_output (size:128b/16B) */ +struct hwrm_tf_session_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* RX action control settings flags. */ + uint8_t rx_act_flags; + /* + * A value of 1 in this field indicates that Global Flow ID + * reporting into cfa_code and cfa_metadata is enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \ + UINT32_C(0x1) + /* + * A value of 1 in this field indicates that both inner and outer + * are stripped and inner tag is passed. + * Enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \ + UINT32_C(0x2) + /* + * A value of 1 in this field indicates that the re-use of + * existing tunnel L2 header SMAC is enabled for + * Non-tunnel L2, L2-L3 and IP-IP tunnel. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \ + UINT32_C(0x4) + /* TX Action control settings flags. */ + uint8_t tx_act_flags; + /* Disabled. */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \ + UINT32_C(0x1) + /* + * When set to 1 any GRE tunnels will include the + * optional Key field. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \ + UINT32_C(0x2) + /* + * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap + * record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \ + UINT32_C(0x4) + /* + * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \ + UINT32_C(0x8) + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_resc_qcaps * + ******************************/ + + +/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ +struct hwrm_tf_session_resc_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided qcaps_addr + * buffer. The size should be set to the Resource Manager + * provided max qcaps value that is device specific. This is + * the max size possible. + */ + uint16_t size; + /* + * This is the DMA address for the qcaps output data + * array. Array is of tf_rm_cap type and is device specific. + */ + uint64_t qcaps_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ +struct hwrm_tf_session_resc_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Session reservation strategy. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \ + 0 + /* Static partitioning. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \ + UINT32_C(0x0) + /* Strategy 1. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \ + UINT32_C(0x1) + /* Strategy 2. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \ + UINT32_C(0x2) + /* Strategy 3. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 + /* + * Size of the returned tf_rm_cap data array. The value + * cannot exceed the size defined by the input msg. The data + * array is returned using the qcaps_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint16_t unused0; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_resc_alloc * + ******************************/ + + +/* hwrm_tf_session_resc_alloc_input (size:256b/32B) */ +struct hwrm_tf_session_resc_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided num_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the num input data array + * buffer. Array is of tf_rm_num type. Size of the buffer is + * provided by the 'size' field in this message. + */ + uint64_t num_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ +struct hwrm_tf_session_resc_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tf_session_resc_free * + *****************************/ + + +/* hwrm_tf_session_resc_free_input (size:256b/32B) */ +struct hwrm_tf_session_resc_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided free_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the free input data array + * buffer. Array of tf_rm_res type. Size of the buffer is + * provided by the 'size field of this message. + */ + uint64_t free_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_free_output (size:128b/16B) */ +struct hwrm_tf_session_resc_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_resc_flush * + ******************************/ + + +/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ +struct hwrm_tf_session_resc_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided flush_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_res type. Size of the buffer is + * provided by the 'size' field in this message. + */ + uint64_t flush_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +struct hwrm_tf_session_resc_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* TruFlow RM capability of a resource. */ +/* tf_rm_cap (size:64b/8B) */ +struct tf_rm_cap { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __rte_packed; + +/* TruFlow RM number of a resource. */ +/* tf_rm_num (size:64b/8B) */ +struct tf_rm_num { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of resources. */ + uint32_t num; +} __rte_packed; + +/* TruFlow RM reservation information. */ +/* tf_rm_res (size:64b/8B) */ +struct tf_rm_res { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __rte_packed; + +/************************ + * hwrm_tf_tbl_type_get * + ************************/ + + +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} __rte_packed; + +/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +struct hwrm_tf_tbl_type_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tf_tbl_type_set * + ************************/ + + +/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ +struct hwrm_tf_tbl_type_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} __rte_packed; + +/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_tf_ctxt_mem_rgtr * + *************************/ + + +/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ +struct hwrm_tf_ctxt_mem_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G + /* unused. */ + uint32_t unused0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} __rte_packed; + +/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_tf_ctxt_mem_unrgtr * + ***************************/ + + +/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tf_ext_em_qcaps * + ************************/ + + +/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; +} __rte_packed; + +/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */ +struct hwrm_tf_ext_em_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When set to 1, indicates the the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x1) + /* + * When set to 1, indicates the the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; + /* Support flags. */ + uint32_t supported; + /* + * If set to 1, then EXT EM KEY0 table is supported using + * crc32 hash. + * If set to 0, EXT EM KEY0 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EXT EM KEY1 table is supported using + * lookup3 hash. + * If set to 0, EXT EM KEY1 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EXT EM External Record table is supported. + * If set to 0, EXT EM External Record table is not + * supported. (This table includes action record, EFC + * pointers, encap pointers) + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EXT EM External Flow Counters table is + * supported. + * If set to 0, EXT EM External Flow Counters table is not + * supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush + * is supported. + * If set to 0, then FID table used for implicit flow flush + * is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * The maximum number of entries supported by EXT EM. When + * configuring the host memory the number of numbers of + * entries that can supported are - + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, + * 128M entries. + * Any value that are not these values, the FW will round + * down to the closest support number of entries. + */ + uint32_t max_entries_supported; + /* + * The entry size in bytes of each entry in the EXT EM + * KEY0/KEY1 tables. + */ + uint16_t key_entry_size; + /* + * The entry size in bytes of each entry in the EXT EM RECORD + * tables. + */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EXT EM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EXT EM FID tables. */ + uint16_t fid_entry_size; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_ext_em_op * + *********************/ + + +/* hwrm_tf_ext_em_op_input (size:192b/24B) */ +struct hwrm_tf_ext_em_op_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX + /* unused. */ + uint16_t unused0; + /* The number of EXT EM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EXT EM and ensure there are no DMA's, + * the caller must disable EXT EM for the given PF, using + * this call. This will safely disable EXT EM and ensure + * that all DMA'ed to the keys/records/efc have been + * completed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) + /* + * Once the EXT EM host memory has been configured, EXT EM + * options have been configured. Then the caller should + * enable EXT EM for the given PF. Note once this call has + * been made, then the EXT EM mechanism will be active and + * DMA's will occur as packets are processed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) + /* + * Clear EXT EM settings for the given PF so that the + * register values are reset back to their initial state. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) + #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP + /* unused. */ + uint16_t unused1; +} __rte_packed; + +/* hwrm_tf_ext_em_op_output (size:128b/16B) */ +struct hwrm_tf_ext_em_op_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_tf_ext_em_cfg * + **********************/ + + +/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */ +struct hwrm_tf_ext_em_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x4) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* + * Dynamically reconfigure EEM pending cache every 1/10th of second. + * If set to 0 it will disable the EEM HW flush of the pending cache. + */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused0; + /* + * Configured EXT EM with the given number of entries. All + * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the + * same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current + * maximum value is 128M. + */ + uint32_t num_entries; + /* unused. */ + uint32_t unused1; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint16_t unused2; + /* unused. */ + uint32_t unused3; +} __rte_packed; + +/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +struct hwrm_tf_ext_em_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tf_ext_em_qcfg * + ***********************/ + + +/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* unused. */ + uint32_t unused0; +} __rte_packed; + +/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ +struct hwrm_tf_ext_em_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_tf_tcam_set * + ********************/ + + +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +struct hwrm_tf_tcam_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data is packing does not change. + */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[88]; +} __rte_packed; + +/* hwrm_tf_tcam_set_output (size:128b/16B) */ +struct hwrm_tf_tcam_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_tf_tcam_get * + ********************/ + + +/* hwrm_tf_tcam_get_input (size:256b/32B) */ +struct hwrm_tf_tcam_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; +} __rte_packed; + +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +struct hwrm_tf_tcam_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_tcam_move * + *********************/ + + +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +struct hwrm_tf_tcam_move_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; +} __rte_packed; + +/* hwrm_tf_tcam_move_output (size:128b/16B) */ +struct hwrm_tf_tcam_move_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tf_tcam_free * + *********************/ + + +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +struct hwrm_tf_tcam_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ - UINT32_C(0x1) - /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ - UINT32_C(0x2) - /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ - UINT32_C(0x4) - /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ - UINT32_C(0x8) - /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ - UINT32_C(0x10) - /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x20) - /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x40) - /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ - UINT32_C(0x80) - /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ - UINT32_C(0x100) - /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ - UINT32_C(0x200) - /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ - UINT32_C(0x400) - /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/****************** - * hwrm_cfa_tflib * - ******************/ - - -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; -} __attribute__((packed)); + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; +} __rte_packed; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30836,25 +35276,18 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; /* unused. */ - uint8_t unused1[7]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_tunnel_dst_port_query * @@ -30914,7 +35347,7 @@ struct hwrm_tunnel_dst_port_query_input { #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_query_output { @@ -30953,7 +35386,7 @@ struct hwrm_tunnel_dst_port_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_tunnel_dst_port_alloc * @@ -31025,7 +35458,7 @@ struct hwrm_tunnel_dst_port_alloc_input { */ uint16_t tunnel_dst_port_val; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_alloc_output { @@ -31051,7 +35484,7 @@ struct hwrm_tunnel_dst_port_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_tunnel_dst_port_free * @@ -31117,7 +35550,7 @@ struct hwrm_tunnel_dst_port_free_input { */ uint16_t tunnel_dst_port_id; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_free_output { @@ -31138,7 +35571,7 @@ struct hwrm_tunnel_dst_port_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* Periodic statistics context DMA to host. */ /* ctx_hw_stats (size:1280b/160B) */ @@ -31183,7 +35616,7 @@ struct ctx_hw_stats { uint64_t tpa_events; /* Number of TPA aborts */ uint64_t tpa_aborts; -} __attribute__((packed)); +} __rte_packed; /* Periodic statistics context DMA to host. */ /* ctx_hw_stats_ext (size:1344b/168B) */ @@ -31230,7 +35663,7 @@ struct ctx_hw_stats_ext { uint64_t rx_tpa_bytes; /* Number of TPA errors */ uint64_t rx_tpa_errors; -} __attribute__((packed)); +} __rte_packed; /* Periodic Engine statistics context DMA to host. */ /* ctx_eng_stats (size:512b/64B) */ @@ -31276,7 +35709,7 @@ struct ctx_eng_stats { * the unit is count of clock cycles */ uint64_t cdd_engine_usage; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_stat_ctx_alloc * @@ -31354,7 +35787,7 @@ struct hwrm_stat_ctx_alloc_input { * for the periodic DMA updates. */ uint16_t stats_dma_length; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ struct hwrm_stat_ctx_alloc_output { @@ -31377,7 +35810,7 @@ struct hwrm_stat_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_stat_ctx_free * @@ -31417,7 +35850,7 @@ struct hwrm_stat_ctx_free_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_free_output (size:128b/16B) */ struct hwrm_stat_ctx_free_output { @@ -31440,7 +35873,7 @@ struct hwrm_stat_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_stat_ctx_query * @@ -31480,7 +35913,7 @@ struct hwrm_stat_ctx_query_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_query_output (size:1408b/176B) */ struct hwrm_stat_ctx_query_output { @@ -31541,7 +35974,7 @@ struct hwrm_stat_ctx_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_stat_ctx_eng_query * @@ -31581,7 +36014,7 @@ struct hwrm_stat_ctx_eng_query_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */ struct hwrm_stat_ctx_eng_query_output { @@ -31643,7 +36076,7 @@ struct hwrm_stat_ctx_eng_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_stat_ctx_clr_stats * @@ -31683,7 +36116,7 @@ struct hwrm_stat_ctx_clr_stats_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ struct hwrm_stat_ctx_clr_stats_output { @@ -31704,7 +36137,7 @@ struct hwrm_stat_ctx_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_pcie_qstats * @@ -31753,7 +36186,7 @@ struct hwrm_pcie_qstats_input { * PCIe statistics will be stored */ uint64_t pcie_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_pcie_qstats_output (size:128b/16B) */ struct hwrm_pcie_qstats_output { @@ -31776,7 +36209,7 @@ struct hwrm_pcie_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* PCIe Statistics Formats */ /* pcie_ctx_hw_stats (size:768b/96B) */ @@ -31792,11 +36225,11 @@ struct pcie_ctx_hw_stats { uint64_t pcie_tl_signal_integrity; /* Number of times LTSSM entered Recovery state */ uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been trasmitted */ + /* Report number of TLP bits that have been transmitted in Mbps */ uint64_t pcie_tx_traffic_rate; - /* Number of TLP bytes that have been received */ + /* Report number of TLP bits that have been received in Mbps */ uint64_t pcie_rx_traffic_rate; - /* Number of DLLP bytes that have been trasmitted */ + /* Number of DLLP bytes that have been transmitted */ uint64_t pcie_tx_dllp_statistics; /* Number of DLLP bytes that have been received */ uint64_t pcie_rx_dllp_statistics; @@ -31812,7 +36245,7 @@ struct pcie_ctx_hw_stats { * to Recovery */ uint64_t pcie_recovery_histogram; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_exec_fwd_resp * @@ -31865,7 +36298,7 @@ struct hwrm_exec_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_exec_fwd_resp_output (size:128b/16B) */ struct hwrm_exec_fwd_resp_output { @@ -31886,7 +36319,7 @@ struct hwrm_exec_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_reject_fwd_resp * @@ -31939,7 +36372,7 @@ struct hwrm_reject_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_reject_fwd_resp_output (size:128b/16B) */ struct hwrm_reject_fwd_resp_output { @@ -31960,7 +36393,7 @@ struct hwrm_reject_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_fwd_resp * @@ -32028,7 +36461,7 @@ struct hwrm_fwd_resp_input { uint64_t encap_resp_addr; /* This is an encapsulated response. */ uint32_t encap_resp[24]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_resp_output (size:128b/16B) */ struct hwrm_fwd_resp_output { @@ -32049,7 +36482,7 @@ struct hwrm_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_fwd_async_event_cmpl * @@ -32098,7 +36531,7 @@ struct hwrm_fwd_async_event_cmpl_input { uint8_t unused_0[6]; /* This is an encapsulated asynchronous event completion. */ uint32_t encap_async_event_cmpl[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ struct hwrm_fwd_async_event_cmpl_output { @@ -32119,7 +36552,7 @@ struct hwrm_fwd_async_event_cmpl_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_raw_write_blk * @@ -32158,7 +36591,7 @@ struct hwrm_nvm_raw_write_blk_input { uint64_t resp_addr; /* * 64-bit Host Source Address. - * This is the loation of the source data to be written. + * This is the location of the source data to be written. */ uint64_t host_src_addr; /* @@ -32168,7 +36601,7 @@ struct hwrm_nvm_raw_write_blk_input { uint32_t dest_addr; /* Length of data to be written, in bytes. */ uint32_t len; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ struct hwrm_nvm_raw_write_blk_output { @@ -32189,7 +36622,7 @@ struct hwrm_nvm_raw_write_blk_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_nvm_read * @@ -32239,7 +36672,7 @@ struct hwrm_nvm_read_input { /* The length of the data to be read, in bytes. */ uint32_t len; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_read_output (size:128b/16B) */ struct hwrm_nvm_read_output { @@ -32260,7 +36693,7 @@ struct hwrm_nvm_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_nvm_raw_dump * @@ -32306,7 +36739,7 @@ struct hwrm_nvm_raw_dump_input { uint32_t offset; /* Total length of NVRAM contents to be read, in bytes. */ uint32_t len; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_raw_dump_output (size:128b/16B) */ struct hwrm_nvm_raw_dump_output { @@ -32327,7 +36760,7 @@ struct hwrm_nvm_raw_dump_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_get_dir_entries * @@ -32369,7 +36802,7 @@ struct hwrm_nvm_get_dir_entries_input { * This is the host address where the directory will be written. */ uint64_t host_dest_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ struct hwrm_nvm_get_dir_entries_output { @@ -32390,7 +36823,7 @@ struct hwrm_nvm_get_dir_entries_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_dir_info * @@ -32427,7 +36860,7 @@ struct hwrm_nvm_get_dir_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ struct hwrm_nvm_get_dir_info_output { @@ -32452,7 +36885,7 @@ struct hwrm_nvm_get_dir_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_nvm_write * @@ -32491,134 +36924,150 @@ struct hwrm_nvm_write_input { uint64_t resp_addr; /* * 64-bit Host Source Address. - * This is where the source data is. + * This is where the source data is. + */ + uint64_t host_src_addr; + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ + uint16_t dir_type; + /* + * Directory ordinal. + * The 0-based instance of the combined Directory Entry Type and Extension. + */ + uint16_t dir_ordinal; + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + uint16_t dir_ext; + /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + uint16_t dir_attr; + /* + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. + */ + uint32_t dir_data_length; + /* Option. */ + uint16_t option; + uint16_t flags; + /* + * When this bit is '1', the original active image + * will not be removed. TBD: what purpose is this? + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ + UINT32_C(0x1) + /* + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). + * If this value is less than the specified data length, it will be ignored. + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). + */ + uint32_t dir_item_length; + uint32_t unused_0; +} __rte_packed; + +/* hwrm_nvm_write_output (size:128b/16B) */ +struct hwrm_nvm_write_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. + */ + uint32_t dir_item_length; + /* The directory index of the created or modified item. */ + uint16_t dir_idx; + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_write_cmd_err (size:64b/8B) */ +struct hwrm_nvm_write_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to fragmentation */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + /* nvm is completely full. */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ + HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE + uint8_t unused_0[7]; +} __rte_packed; + +/******************* + * hwrm_nvm_modify * + *******************/ + + +/* hwrm_nvm_modify_input (size:320b/40B) */ +struct hwrm_nvm_modify_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * 64-bit Host Source Address. + * This is where the modified data is. */ uint64_t host_src_addr; - /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ - uint16_t dir_type; - /* - * Directory ordinal. - * The 0-based instance of the combined Directory Entry Type and Extension. - */ - uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ - uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ - uint16_t dir_attr; - /* - * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to reflect this value once the write is complete. - */ - uint32_t dir_data_length; - /* Option. */ - uint16_t option; - uint16_t flags; - /* - * When this bit is '1', the original active image - * will not be removed. TBD: what purpose is this? - */ - #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ - UINT32_C(0x1) - /* - * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). - * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate - * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). - */ - uint32_t dir_item_length; - uint32_t unused_0; -} __attribute__((packed)); - -/* hwrm_nvm_write_output (size:128b/16B) */ -struct hwrm_nvm_write_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. - */ - uint32_t dir_item_length; - /* The directory index of the created or modified item. */ + /* 16-bit directory entry index. */ uint16_t dir_idx; - uint8_t unused_0; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/* hwrm_nvm_write_cmd_err (size:64b/8B) */ -struct hwrm_nvm_write_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) - /* nvm is completely full. */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) - #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ - HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE - uint8_t unused_0[7]; -} __attribute__((packed)); - -/******************* - * hwrm_nvm_modify * - *******************/ - - -/* hwrm_nvm_modify_input (size:320b/40B) */ -struct hwrm_nvm_modify_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; + uint16_t flags; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This flag indicates the sender wants to modify a continuous NVRAM + * area using a batch of this HWRM requests. The offset of a request + * must be continuous to the end of previous request's. Firmware does + * not update the directory entry until receiving the last request, + * which is indicated by the batch_last flag. + * This flag is set usually when a sender does not have a block of + * memory that is big enough to hold the entire NVRAM data for send + * at one time. */ - uint16_t seq_id; + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This flag can be used only when the batch_mode flag is set. + * It indicates this request is the last of batch requests. */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * 64-bit Host Source Address. - * This is where the modified data is. - */ - uint64_t host_src_addr; - /* 16-bit directory entry index. */ - uint16_t dir_idx; - uint8_t unused_0[2]; + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) /* 32-bit NVRAM byte-offset to modify content from. */ uint32_t offset; /* @@ -32627,7 +37076,7 @@ struct hwrm_nvm_modify_input { */ uint32_t len; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_modify_output (size:128b/16B) */ struct hwrm_nvm_modify_output { @@ -32648,7 +37097,7 @@ struct hwrm_nvm_modify_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_nvm_find_dir_entry * @@ -32717,7 +37166,7 @@ struct hwrm_nvm_find_dir_entry_input { #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT uint8_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ struct hwrm_nvm_find_dir_entry_output { @@ -32751,7 +37200,7 @@ struct hwrm_nvm_find_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_erase_dir_entry * @@ -32791,7 +37240,7 @@ struct hwrm_nvm_erase_dir_entry_input { /* Directory Entry Index */ uint16_t dir_idx; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ struct hwrm_nvm_erase_dir_entry_output { @@ -32812,7 +37261,7 @@ struct hwrm_nvm_erase_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_dev_info * @@ -32849,7 +37298,7 @@ struct hwrm_nvm_get_dev_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ struct hwrm_nvm_get_dev_info_output { @@ -32886,7 +37335,7 @@ struct hwrm_nvm_get_dev_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_mod_dir_entry * @@ -32945,7 +37394,7 @@ struct hwrm_nvm_mod_dir_entry_input { * value of the content in the directory entry. */ uint32_t checksum; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ struct hwrm_nvm_mod_dir_entry_output { @@ -32966,7 +37415,7 @@ struct hwrm_nvm_mod_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_verify_update * @@ -33019,7 +37468,7 @@ struct hwrm_nvm_verify_update_input { */ uint16_t dir_ext; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_verify_update_output (size:128b/16B) */ struct hwrm_nvm_verify_update_output { @@ -33040,7 +37489,7 @@ struct hwrm_nvm_verify_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_nvm_install_update * @@ -33105,7 +37554,7 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecifed images, images not in the package file, will be safely deleted. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ @@ -33117,7 +37566,7 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_install_update_output (size:192b/24B) */ struct hwrm_nvm_install_update_output { @@ -33186,7 +37635,7 @@ struct hwrm_nvm_install_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ struct hwrm_nvm_install_update_cmd_err { @@ -33204,7 +37653,7 @@ struct hwrm_nvm_install_update_cmd_err { #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_nvm_flush * @@ -33241,7 +37690,7 @@ struct hwrm_nvm_flush_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_flush_output (size:128b/16B) */ struct hwrm_nvm_flush_output { @@ -33262,7 +37711,7 @@ struct hwrm_nvm_flush_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_flush_cmd_err (size:64b/8B) */ struct hwrm_nvm_flush_cmd_err { @@ -33278,7 +37727,7 @@ struct hwrm_nvm_flush_cmd_err { #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \ HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_variable * @@ -33355,7 +37804,7 @@ struct hwrm_nvm_get_variable_input { #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \ UINT32_C(0x1) uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_variable_output (size:128b/16B) */ struct hwrm_nvm_get_variable_output { @@ -33394,7 +37843,7 @@ struct hwrm_nvm_get_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ struct hwrm_nvm_get_variable_cmd_err { @@ -33414,7 +37863,7 @@ struct hwrm_nvm_get_variable_cmd_err { #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_set_variable * @@ -33512,7 +37961,7 @@ struct hwrm_nvm_set_variable_input { #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \ UINT32_C(0x80) uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_set_variable_output (size:128b/16B) */ struct hwrm_nvm_set_variable_output { @@ -33533,7 +37982,7 @@ struct hwrm_nvm_set_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ struct hwrm_nvm_set_variable_cmd_err { @@ -33551,7 +38000,7 @@ struct hwrm_nvm_set_variable_cmd_err { #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_validate_option * @@ -33622,7 +38071,7 @@ struct hwrm_nvm_validate_option_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_validate_option_output (size:128b/16B) */ struct hwrm_nvm_validate_option_output { @@ -33650,7 +38099,7 @@ struct hwrm_nvm_validate_option_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ struct hwrm_nvm_validate_option_cmd_err { @@ -33664,7 +38113,7 @@ struct hwrm_nvm_validate_option_cmd_err { #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \ HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_fw_reset * @@ -33764,7 +38213,7 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fw_reset_output (size:128b/16B) */ struct hwrm_fw_reset_output { @@ -33801,7 +38250,7 @@ struct hwrm_fw_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_ts_query * @@ -33859,7 +38308,7 @@ struct hwrm_port_ts_query_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_ts_query_output (size:192b/24B) */ struct hwrm_port_ts_query_output { @@ -33887,6 +38336,339 @@ struct hwrm_port_ts_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/************************** + * hwrm_cfa_counter_qcaps * + **************************/ + + +/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_counter_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ +struct hwrm_cfa_counter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* Enumeration denoting the supported CFA counter format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \ + UINT32_C(0x1) + /* CFA counter types are not supported. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \ + UINT32_C(0x0) + /* 64-bit packet counters followed by 64-bit byte counters format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \ + HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT + uint32_t unused_0; + /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */ + uint32_t min_rx_fc; + /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */ + uint32_t max_rx_fc; + /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */ + uint32_t min_tx_fc; + /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */ + uint32_t max_tx_fc; + /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */ + uint32_t min_rx_efc; + /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */ + uint32_t max_rx_efc; + /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */ + uint32_t min_tx_efc; + /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */ + uint32_t max_tx_efc; + /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */ + uint32_t min_rx_mdc; + /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */ + uint32_t max_rx_mdc; + /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */ + uint32_t min_tx_mdc; + /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */ + uint32_t max_tx_mdc; + /* Maximum guaranteed number of flow counters which can be used during flow alloc. */ + uint32_t max_flow_alloc_fc; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_cfa_counter_cfg * + ************************/ + + +/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ +struct hwrm_cfa_counter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \ + UINT32_C(0x1) + /* Disable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \ + UINT32_C(0x0) + /* Enable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x2) + /* Tx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \ + (UINT32_C(0x0) << 1) + /* Rx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 + /* Push mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \ + (UINT32_C(0x0) << 2) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \ + (UINT32_C(0x1) << 2) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + /* Flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) + /* Extended flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) + /* Meter drop counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC + /* Ctx memory handle to be used for the counter. */ + uint16_t ctx_id; + /* Counter update cadence hint (only in Push mode). */ + uint16_t update_tmr_ms; + /* Total number of entries. */ + uint32_t num_entries; + uint32_t unused_0; +} __rte_packed; + +/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_counter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_counter_qstats * + ***************************/ + + +/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ +struct hwrm_cfa_counter_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX + uint16_t counter_type; + uint16_t input_flow_ctx_id; + uint16_t num_entries; + uint16_t delta_time_ms; + uint16_t meter_instance_id; + uint16_t mdc_ctx_id; + uint8_t unused_0[2]; + uint64_t expected_count; +} __rte_packed; + +/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ +struct hwrm_cfa_counter_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* + * This structure is fixed at the beginning of the ChiMP SRAM (GRC + * offset: 0x31001F0). Host software is expected to read from this + * location for a defined signature. If it exists, the software can + * assume the presence of this structure and the validity of the + * FW_STATUS location in the next field. + */ +/* hcomm_status (size:64b/8B) */ +struct hcomm_status { + uint32_t sig_ver; + /* + * This field defines the version of the structure. The latest + * version value is 1. + */ + #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) + #define HCOMM_STATUS_VER_SFT 0 + #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) + #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST + /* + * This field is to store the signature value to indicate the + * presence of the structure. + */ + #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) + #define HCOMM_STATUS_SIGNATURE_SFT 8 + #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) + #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL + uint32_t fw_status_loc; + #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) + #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 + /* PCIE configuration space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) + /* GRC space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) + /* BAR0 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) + /* BAR1 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \ + HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + /* + * This offset where the fw_status register is located. The value + * is generally 4-byte aligned. + */ + #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) + #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 +} __rte_packed; +/* This is the GRC offset where the hcomm_status struct resides. */ +#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL #endif /* _HSI_STRUCT_DEF_DPDK_H_ */