X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=aea930548671da0b53d36ab3cabdd2ebcc108097;hb=b25987fa7e25b3ba852f9433d22761c006884205;hp=e5fd5d109d6b77ea7de6d2a88ec9b5b126aab3bf;hpb=ef5baf3486e03004b6d807f731f0d9936504511d;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index e5fd5d109d..aea9305486 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2019 Broadcom Inc. + * Copyright (c) 2014-2021 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -269,6 +269,7 @@ struct cmd_nums { */ uint16_t req_type; #define HWRM_VER_GET UINT32_C(0x0) + #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb) #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc) #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd) #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe) @@ -336,14 +337,21 @@ struct cmd_nums { #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48) #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49) #define HWRM_VNIC_QCAPS UINT32_C(0x4a) + /* Updates specific fields in RX VNIC structure */ + #define HWRM_VNIC_UPDATE UINT32_C(0x4b) #define HWRM_RING_ALLOC UINT32_C(0x50) #define HWRM_RING_FREE UINT32_C(0x51) #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53) #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54) + #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55) + #define HWRM_RING_SCHQ_CFG UINT32_C(0x56) + #define HWRM_RING_SCHQ_FREE UINT32_C(0x57) #define HWRM_RING_RESET UINT32_C(0x5e) #define HWRM_RING_GRP_ALLOC UINT32_C(0x60) #define HWRM_RING_GRP_FREE UINT32_C(0x61) + #define HWRM_RING_CFG UINT32_C(0x62) + #define HWRM_RING_QCFG UINT32_C(0x63) /* Reserved for future use. */ #define HWRM_RESERVED5 UINT32_C(0x64) /* Reserved for future use. */ @@ -353,6 +361,9 @@ struct cmd_nums { #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) + #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83) + #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84) + #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -386,6 +397,14 @@ struct cmd_nums { #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6) #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) + #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) + /* Reserved. */ + #define HWRM_RESERVED7 UINT32_C(0xba) + #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb) + #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc) + #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd) + #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe) + #define HWRM_FW_LIVEPATCH UINT32_C(0xbf) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) @@ -404,6 +423,9 @@ struct cmd_nums { #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb) /* Experimental */ #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) + #define HWRM_FW_ECN_CFG UINT32_C(0xcd) + #define HWRM_FW_ECN_QCFG UINT32_C(0xce) + #define HWRM_FW_SECURE_CFG UINT32_C(0xcf) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -419,6 +441,7 @@ struct cmd_nums { #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) + #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -510,7 +533,7 @@ struct cmd_nums { #define HWRM_CFA_EEM_OP UINT32_C(0x123) /* Experimental */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) - /* Experimental */ + /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) @@ -606,6 +629,14 @@ struct cmd_nums { #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196) /* Queries pf ids belong to specified host(s) */ #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197) + /* Queries extended stats per function */ + #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198) + /* Queries extended statistics context */ + #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199) + /* Configure SoC packet DMA settings */ + #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a) + /* Query SoC packet DMA settings */ + #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -629,6 +660,90 @@ struct cmd_nums { * to the host test. */ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209) + /* Tells the fw to program the fru memory */ + #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) + /* Tells the fw to read the fru memory */ + #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Used to provision SoC software images */ + #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) + /* Retrieves the SoC status and image provisioning information */ + #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) + /* Tells the fw to program the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) + /* Tells the fw to read the seeprom memory */ + #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) + /* Tells the fw to get the health of seeprom data */ + #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* Experimental */ + #define HWRM_TF UINT32_C(0x2bc) + /* Experimental */ + #define HWRM_TF_VERSION_GET UINT32_C(0x2bd) + /* Experimental */ + #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) + /* Experimental */ + #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) + /* Experimental */ + #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) + /* Experimental */ + #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) + /* Experimental */ + #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca) + /* Experimental */ + #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) + /* Experimental */ + #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) + /* Experimental */ + #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) + /* Experimental */ + #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) + /* Experimental */ + #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) + /* Experimental */ + #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec) + /* Experimental */ + #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) + /* Experimental */ + #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) + /* Experimental */ + #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa) + /* Experimental */ + #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd) + /* Experimental */ + #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) + /* Experimental */ + #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* Experimental */ + #define HWRM_SV UINT32_C(0x400) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -658,6 +773,15 @@ struct cmd_nums { #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d) /* Experimental */ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e) + /* Send driver debug information to firmware */ + #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f) + /* Query debug capabilities of firmware */ + #define HWRM_DBG_QCAPS UINT32_C(0xff20) + /* Retrieve debug settings of firmware */ + #define HWRM_DBG_QCFG UINT32_C(0xff21) + /* Set destination parameters for crashdump medium */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -770,6 +894,11 @@ struct ret_codes { * may try again later. */ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) + /* + * This error code is reported by Firmware when an operation requested + * by the host is not allowed due to a secure lock violation. + */ + #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -855,10 +984,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 1 +#define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 6 -#define HWRM_VERSION_STR "1.10.1.6" +#define HWRM_VERSION_RSVD 15 +#define HWRM_VERSION_STR "1.10.2.15" /**************** * hwrm_ver_get * @@ -1143,12 +1272,21 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \ UINT32_C(0x1000) /* + * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. * If set to 0, then the firmware doesn’t support TFLIB features. * By default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \ UINT32_C(0x2000) + /* + * If set to 1, the firmware is able to support TruFlow features. + * If set to 0, then the firmware doesn’t support TruFlow features. + * By default, this flag should be 0 for older version of + * core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ + UINT32_C(0x4000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1236,18 +1374,34 @@ struct hwrm_ver_get_output { * If set to 1, it will indicate to host drivers that firmware is * not ready to start full blown HWRM commands. Host drivers should * re-try HWRM_VER_GET with some timeout period. The timeout period - * can be selected up to 5 seconds. + * can be selected up to 5 seconds. Host drivers should also check + * for dev_not_rdy_backing_store to identify if flag is set due to + * backing store not been available. * For Example, PCIe hot-plug: * Hot plug timing is system dependent. It generally takes up to * 600 miliseconds for firmware to clear DEV_NOT_RDY flag. * If set to 0, device is ready to accept all HWRM commands. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1) + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \ + UINT32_C(0x1) /* * If set to 1, external version present. * If set to 0, external version not present. */ - #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2) + #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \ + UINT32_C(0x2) + /* + * Firmware sets this flag along with dev_not_rdy flag to indicate + * host drivers that it has not completed resource initialization + * required for data path operations. Host drivers should not send + * any HWRM command that requires data path resources. Firmware will + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry + * those commands once both the flags are cleared. + * If this flag and dev_not_rdy flag are set to 0, device is ready + * to accept all HWRM commands. + */ + #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \ + UINT32_C(0x4) uint8_t unused_0[2]; /* * For backward compatibility this field must be set to 1. @@ -1400,6 +1554,657 @@ struct hwrm_ver_get_output { uint8_t valid; } __rte_packed; +/* cfa_bds_read_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_read_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is read command. From 32 to 128B can be read from a table + * using this command. + */ + #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0) + #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + * this command is read from. The bottom two bits of this value must be + * zero. The size of the write is controlled by the data_size field. + */ + uint64_t host_address; +} __rte_packed; + +/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */ +struct cfa_bds_write_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is write command. From 32 to 128B can be written to a table + * using this command. + */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1) + #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE + /* This value selects the table type to be acted upon. */ + uint8_t write_thru_table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + uint32_t unused0; + uint32_t unused1; + /* + * This is the data to be written. Data length is determined by the + * data_size field. The bd_cnt in the encapsulating BD must also be set + * correctly to ensure that the BD is processed correctly and the full + * WRITE_CMD message is extracted from the BD. + */ + uint32_t dta[32]; +} __rte_packed; + +/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */ +struct cfa_bds_read_clr_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * This is read-clear command. 32B can be read from a table and + * a 16b mask can be used to clear specific 16b units after the + * read as an atomic operation. + */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. + * Always set the value to 1. + */ + uint8_t data_size; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + * this command is read from. The bottom two bits of this value must be + * zero. The size of the write is controlled by the data_size field. + */ + uint64_t host_address; + /* + * This is active high clear mask for the 32B of data that this command + * can read. Bit 0 of the field will clear bits 15:0 of the first word + * of data read when set to '1'. + */ + uint16_t clear_mask; + uint16_t unused0[3]; + uint16_t unused1[4]; +} __rte_packed; + +/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */ +struct cfa_bds_em_insert_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * An exact match table insert will be attempted into the table. + * If there is a free location in the bucket, the payload will + * be written to the bucket. + */ + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + uint8_t write_thru; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0 + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; + /* + * This is the Exact Match Lookup Record. Data length is determined by + * the data_size field. The bd_cnt in the encapsulating BD must also be + */ + uint32_t dta[32]; +} __rte_packed; + +/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */ +struct cfa_bds_em_delete_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* An exact match table delete will be attempted. */ + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + uint8_t write_thru; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0 + /* + * Indicates write-through control. Indicates write-through when set, + * or write back when cleared. + */ + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10) + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + uint32_t unused0; + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; + /* + * This is the Exact Match Lookup Record. Data length is determined by + * the data_size field. The bd_cnt in the encapsulating BD must also be + */ + uint64_t dta; + uint32_t unused1[2]; +} __rte_packed; + +/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_invalidate_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* + * The specified table area will be invalidated. If it is needed. + * again, it will be read from the backing store. + */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE + /* This value selects the table type to be acted upon. */ + uint8_t table_type; + /* This value selects the table type to be acted upon. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0 + /* This command acts on the action table of the specified scope. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \ + UINT32_C(0x0) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \ + UINT32_C(0x1) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \ + CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* This value specifies the number of cache lines to invalidate. */ + uint8_t data_size; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0 + /* This is the 32B index into the selected table to access. */ + uint32_t table_index; + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \ + UINT32_C(0x3ffffff) + #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0 + uint32_t unused[2]; +} __rte_packed; + +/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */ +struct cfa_bds_event_collect_cmd_data_msg { + /* This value selects the format for the mid-path command for the CFA. */ + uint8_t opcode; + /* Reads notification messages from the Host Notification Queue. */ + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \ + UINT32_C(0x6) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \ + CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT + uint8_t unused0; + /* This value selects which table scope will be accessed. */ + uint8_t table_scope; + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \ + UINT32_C(0x1f) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0 + /* + * This value identifies the number of 32B units will be accessed. A + * value of zero is invalid. Maximum value is 4. + */ + uint8_t data_size; + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7) + #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0 + uint32_t unused1; + /* + * This is the 64b host address where you want the data returned to. The + * data will be written to the same function as the one that owns the SQ + */ + uint64_t host_address; +} __rte_packed; + +/* ce_bds_add_data_msg (size:512b/64B) */ +struct ce_bds_add_data_msg { + uint32_t version_algorithm_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0 + /* + * This is the add command. Using this opcode, Host Driver can add + * information required for kTLS processing. The information is + * updated in the CFCK context. + */ + #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1) + #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \ + CE_BDS_ADD_DATA_MSG_OPCODE_ADD + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_ADD_DATA_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_ADD_DATA_MSG_KID_SFT 4 + /* + * Currently only two algorithms are supported, AES_GCM_128 and + * AES_GCM_256. Additional bits for future growth. + */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \ + UINT32_C(0xf000000) + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24 + /* AES_GCM_128 Algorithm */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \ + UINT32_C(0x1000000) + /* AES_GCM_256 Algorithm */ + #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \ + UINT32_C(0x2000000) + /* + * Version number of TLS connection. HW will provide registers that + * converts the 4b encoded version number to 16b of actual version + * number in the TLS Header. * Initialized --> By mid-path command * + * Updated --> Never though another mid-path command will result in an + * update. + */ + #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \ + UINT32_C(0xf0000000) + #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28 + /* TLS1.2 Version */ + #define CE_BDS_ADD_DATA_MSG__TLS1_2 \ + (UINT32_C(0x0) << 28) + /* TLS1.3 Version */ + #define CE_BDS_ADD_DATA_MSG__TLS1_3 \ + (UINT32_C(0x1) << 28) + #define CE_BDS_ADD_DATA_MSG__LAST \ + CE_BDS_ADD_DATA_MSG__TLS1_3 + /* + * Command Type in the TLS header. HW will provide registers that + * converts the 3b encoded command type to 8b of actual command type in + * the TLS Header. * Initialized --> By mid-path command * Updated --> + * Never though another mid-path command will result in an update + */ + uint8_t cmd_type; + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7) + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 + /* Application */ + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) + #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \ + CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP + uint8_t unused0[3]; + /* + * Salt is part of the nonce that is used as the Initial Vector (IV) in + * AES-GCM cipher suites. These are exchanged as part of the handshake + * process and is either the client_write_iv (when the client is + * sending) or server_write_iv (when the server is sending). In + * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to + * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number + * is zero padded to 12B and then xor'ed with the 4B of salt to generate + * the 12B of IV. This value is initialized by this mid-path command. + */ + uint32_t salt; + uint32_t unused1; + /* + * This field keeps track of the TCP sequence number that is expected as + * the first byte in the next TCP packet. This field is calculated by HW + * using the output of the parser. The field is initialized as part of + * the Mid-path BD download/update of a kTLS connection. For every TCP + * packet processed, TCE HW will update the value to Current packet TCP + * sequence number + Current packet TCP Payload Length. + */ + uint32_t pkt_tcp_seq_num; + /* + * This field maintains the TCP sequence number of the first byte in the + * header of the active TLS record. This field is initialized as part of + * the Mid-path BD download/update of a kTLS connection. For every + * record that is processed, TCE HW copies the value from the + * next_tls_header_tcp_seq_num field. + */ + uint32_t tls_header_tcp_seq_num; + /* + * This is sequence number for the TLS record in a particular session. + * In TLS1.2, record sequence number is part of the Associated Data (AD) + * in the AEAD algorithm. In TLS1.3, record sequence number is part of + * the Initial Vector (IV). The field is initialized as part of the + * mid-path BD download/update of a kTLS connection. TCE HW increments + * the field after that for every record processed as it parses the TCP + * packet. + */ + uint32_t record_seq_num[2]; + /* + * Key used for encrypting or decrypting TLS records. The Key is + * exchanged during the hand-shake protocol by the client-server and + * provided to HW through this mid-path BD. + */ + uint32_t session_key[8]; +} __rte_packed; + +/* ce_bds_delete_data_msg (size:64b/8B) */ +struct ce_bds_delete_data_msg { + uint32_t kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0 + /* + * This is the delete command. Using this opcode, the host Driver + * can remove a key context from the CFCK. If context is deleted + * and packets with the same KID come through the pipeline, the + * following actions are taken. For transmit packets, no crypto + * operation will be performed, payload will be zero'ed out. For + * receive packets, no crypto operation will be performed, + * payload will be unmodified. + */ + #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2) + #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \ + CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0) + #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4 + uint32_t unused0; +} __rte_packed; + +/* ce_bds_resync_resp_ack_msg (size:128b/16B) */ +struct ce_bds_resync_resp_ack_msg { + uint32_t resync_status_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0 + /* + * This command is used by the driver as a response to the resync + * request sent by the crypto engine. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3) + #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \ + CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0) + #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4 + /* + * This field indicates if the resync request resulted in a success or + * a failure. + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \ + UINT32_C(0x1000000) + /* + * An ACK indicates that the driver was able to find the TLS record + * associated with TCP sequence number provided by the HW + */ + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \ + (UINT32_C(0x0) << 24) + #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \ + CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK + /* + * This field is the echo of the TCP sequence number provided in the + * resync request by the HW. If HW sent multiple resync requests, it + * only tracks the latest TCP sequence number. When the response from + * the Driver doesn't match the latest request, HW will drop the resync + * response. + */ + uint32_t resync_record_tcp_seq_num; + /* + * This field indicates the TLS record sequence number associated with + * the resync request. HW will take this number and add the delta records + * it has found since sending the resync request, update the context and + * resume decrypting records. + */ + uint32_t resync_record_seq_num[2]; +} __rte_packed; + +/* ce_bds_resync_resp_nack_msg (size:64b/8B) */ +struct ce_bds_resync_resp_nack_msg { + uint32_t resync_status_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0 + /* + * This command is used by the driver as a response to the resync + * request sent by the crypto engine. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3) + #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \ + CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4 + /* + * This field indicates if the resync request resulted in a success or + * a failure. + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \ + UINT32_C(0x1000000) + /* + * An NAK indicates that the driver wasn't able to find the TLS + * record associated with TCP sequence number provided by the HW + */ + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \ + (UINT32_C(0x1) << 24) + #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \ + CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK + /* + * This field is the echo of the TCP sequence number provided in the + * resync request by the HW. If HW sent multiple resync requests, it + * only tracks the latest TCP sequence number. When the response from + * the Driver doesn't match the latest request, HW will drop the resync + * response. + */ + uint32_t resync_record_tcp_seq_num; +} __rte_packed; + +/* crypto_presync_bd_cmd (size:256b/32B) */ +struct crypto_presync_bd_cmd { + uint8_t flags; + /* + * Typically, presync BDs are used for packet retransmissions. Source + * port sends all the packets in order over the network to destination + * port and packets get dropped in the network. The destination port + * will request retranmission of dropped packets and source port driver + * will send presync BD to setup the transmitter appropriately. It will + * provide the start and end TCP sequence number of the data to be + * transmitted. HW keeps two sets of context variable, one for in order + * traffic and one for retransmission traffic. HW is designed to + * transmit everything posted in the presync BD and return to in order + * mode after that. No inorder context variables are updated in the + * process. There is a special case where packets can be dropped + * between the TCP stack and Device Driver (Berkeley Packet Filter for + * ex) and HW still needs to transmit rest of the traffic. In this + * mode, driver will send a presync BD as if it is a retransmission but + * at the end of the transmission, the in order variables need to be + * updated. This flag is used by driver to indicate that in order + * variables needs to be updated at the end of completing the task + * associated with the presync BD. + */ + #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \ + UINT32_C(0x1) + uint8_t unused0; + uint16_t unused1; + /* + * This field maintains the TCP sequence number of the first byte in the + * Header of the active TLS record. This field is set to 0 during + * mid-path BD updates, but is set to correct value when a presync BD is + * detected. For every record that is processed, the value from the + * next_tls_header_tcp_seq_num field is copied. + */ + uint32_t header_tcp_seq_num; + /* + * When a retransmitted packet has a TLS authentication TAG present and + * the data spans multiple TCP Packets, HW is required to read the entire + * record to recalculate the TAG but only transmit what is required. This + * field is the start TCP sequence number of the packet(s) that need to + * be re-transmitted. This field is initialized to 0 during Mid-path BD + * add command and initialized to value provided by the driver when + * Pre-sync BD is detected. This field is never updated unless another + * Pre-sync BD signaling a new retransmission is scheduled. + */ + uint32_t start_tcp_seq_num; + /* + * When a retransmitted packet has a TLS authentication TAG present and + * the data spans multiple TCP Packets, HW is required to read the + * entire record to recalculate the TAG but only transmit what is + * required. This field is the end TCP sequence number of the packet(s) + * that need to be re-transmitted. This field is initialized to 0 during + * Mid-path BD add command and initialized to value provided by the + * driver when Pre-sync BD is detected. This field is never updated + * unless another Pre-sync BD signaling a new retransmission is + * scheduled. + */ + uint32_t end_tcp_seq_num; + /* + * For TLS1.2, an explicit nonce is used as part of the IV (concatenated + * with the SALT). For retans packets, this field is extracted from the + * TLS record, field right after the TLS Header and stored in the + * context. This field needs to be stored in context as TCP segmentation + * could have split the field into multiple TCP packets. This value is + * initialized to 0 when presync BD is detected by taking the value from + * the first TLS header. When subsequent TLS Headers are detected, the + * value is extracted from packet. + */ + uint32_t explicit_nonce[2]; + /* + * This is sequence number for the TLS record in a particular session. In + * TLS1.2, record sequence number is part of the Associated Data (AD) in + * the AEAD algorithm. In TLS1.3, record sequence number is part of the + * Initial Vector (IV). The field is initialized to 0 during Mid-path BD + * download. Is initialized to correct value when a pre-sync BD is + * detected. TCE HW increments the field after that for every record + * processed as it parses the TCP packet. Subsequent pre-sync BDs + * delivering more retransmission instruction will also update this + * field. + */ + uint32_t record_seq_num[2]; +} __rte_packed; + /* bd_base (size:64b/8B) */ struct bd_base { uint8_t type; @@ -1431,6 +2236,16 @@ struct bd_base { * RX Producer Assembly Buffer Descriptor. */ #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6) + /* + * Indicates that this BD is used to issue a command to one of + * the mid-path destinations. + */ + #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8) + /* + * Indicates that this BD is used to issue a cryptographic pre- + * sync command through the fast path and destined for TCE. + */ + #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9) /* * Indicates that this BD is 32B long and is used for * normal L2 packet transmission. @@ -1543,7 +2358,12 @@ struct tx_bd_short { * used for any data that the driver wants to associate with the * transmit BD. * - * This field must be valid on the first BD of a packet. + * This field must be valid on the first BD of a packet. If completion + * coalescing is enabled on the TX ring, it is suggested that the driver + * populate the opaque field to indicate the specific TX ring with which + * the completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. */ uint32_t opaque; /* @@ -1646,11 +2466,16 @@ struct tx_bd_long { */ uint16_t len; /* - * The opaque data field is pass through to the completion and can be + * The opaque data field is passed through to the completion and can be * used for any data that the driver wants to associate with the * transmit BD. * - * This field must be valid on the first BD of a packet. + * This field must be valid on the first BD of a packet. If completion + * coalescing is enabled on the TX ring, it is suggested that the driver + * populate the opaque field to indicate the specific TX ring with which + * the completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. */ uint32_t opaque; /* @@ -1703,7 +2528,7 @@ struct tx_bd_long_hi { #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) /* * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. + * was actually transmitted at the TX MAC for 2-step time sync. * * This bit must be valid on the first BD of a packet. */ @@ -1730,9 +2555,9 @@ struct tx_bd_long_hi { * Send Offload) processing for both normal or encapsulated * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver - * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum - * flags since the controller will replace the appropriate - * checksum fields for segmented packets. + * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and + * tcp_udp_chksum flags since the controller will replace the + * appropriate checksum fields for segmented packets. * * When this bit is 1, the hdr_size and mss fields must be valid. */ @@ -1769,7 +2594,47 @@ struct tx_bd_long_hi { * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) - uint16_t hdr_size; + /* + * If set to '1', then the timestamp from the BD is used. If cleared + * to 0, then TWE provides the timestamp. + */ + #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400) + /* + * If set to '1', this operation will cause a trace capture in each + * block it passes through. + */ + #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800) + /* + * If set to '1', the device will record the time at which the packet + * was actually transmitted at the TX MAC for 1-step time sync. This + * bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000) + /* + * If set to '1', the controller replaces the Outer-tunnel IP checksum + * field with hardware calculated IP checksum for the IP header of the + * packet associated with this descriptor. For outer UDP checksum, it + * will be the following behavior for all cases independent of settings + * of inner LSO and checksum offload BD flags. If outer UDP checksum + * is 0, then do not update it. If outer UDP checksum is non zero, then + * the hardware should compute and update it. + */ + #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) + /* + * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP + * header will not be modified during LSO operations. If set to one + * when LSO is '1', then the IPID of the Outer-tunnel IP header will be + * incremented for each subsequent segment of an LSO operation. The + * flag is ignored if the LSO packet is a normal (non-tunneled) TCP + * packet. + */ + #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000) + /* + * If set to '1', When set to 1, KTLS encryption will be enabled for + * the packet. + */ + #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000) + uint16_t kid_or_ts_low_hdr_size; /* * When LSO is '1', this field must contain the offset of the * TCP payload from the beginning of the packet in as @@ -1779,9 +2644,16 @@ struct tx_bd_long_hi { * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff) - #define TX_BD_LONG_HDR_SIZE_SFT 0 - uint32_t mss; + #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff) + #define TX_BD_LONG_HDR_SIZE_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the + * 20-bit KID. + */ + #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00) + #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9 + uint32_t kid_or_ts_high_mss; /* * This is the MSS value that will be used to do the LSO processing. * The value is the length in bytes of the TCP payload for each @@ -1789,9 +2661,22 @@ struct tx_bd_long_hi { * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff) - #define TX_BD_LONG_MSS_SFT 0 - uint16_t unused2; + #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff) + #define TX_BD_LONG_MSS_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, the least significant 13 bits + * of this field contain the upper 13 bits of the 20-bit KID. + */ + #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000) + #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15 + /* + * This value selects bits 25:16 of the CFA action to perform on the + * packet. See the cfa_action field for more information. + */ + uint16_t cfa_action_high; + #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0 /* * This value selects a CFA action to perform on the packet. * Set this value to zero if no CFA action is desired. @@ -1805,51 +2690,69 @@ struct tx_bd_long_hi { */ uint32_t cfa_meta; /* When key=1, This is the VLAN tag VID value. */ - #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 /* When key=1, This is the VLAN tag DE value. */ - #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) /* When key=1, This is the VLAN tag PRI value. */ - #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \ + (UINT32_C(0x0) << 16) /* 0x8100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \ + (UINT32_C(0x1) << 16) /* 0x9100 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \ + (UINT32_C(0x2) << 16) /* 0x9200 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \ + (UINT32_C(0x3) << 16) /* 0x9300 */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \ + (UINT32_C(0x4) << 16) /* Value programmed in CFA VLANTPID register. */ - #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \ + (UINT32_C(0x5) << 16) #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \ TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG /* When key=1, This is the VLAN tag TPID select value. */ - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) - #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. * * This value must be valid on the first BD of a packet. */ - #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) - #define TX_BD_LONG_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define TX_BD_LONG_CFA_META_KEY_SFT 28 /* No editing */ - #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + #define TX_BD_LONG_CFA_META_KEY_NONE \ + (UINT32_C(0x0) << 28) /* * - meta[17:16] - TPID select value (0 = 0x8100). * - meta[15:12] - PRI/DE value. * - meta[11:0] - VID value. */ - #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \ + (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ - TX_BD_LONG_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* @@ -1926,7 +2829,12 @@ struct tx_bd_long_inline { /* * The opaque data field is passed through to the completion and can be * used for any data that the driver wants to associate with the transmit - * BD. + * BD. This field must be valid on the first BD of a packet. If + * completion coalescing is enabled on the TX ring, it is suggested that + * the driver populate the opaque field to indicate the specific TX ring + * with which the completion is associated, then utilize the opaque and + * sq_cons_idx fields in the coalesced completion record to determine + * the specific packets that are to be completed on that ring. * * This field must be valid on the first BD of a packet. */ @@ -1964,7 +2872,8 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4) /* * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. + * was actually transmitted at the TX MAC for 2-step time sync. This + * bit must be valid on the first BD of a packet. */ #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8) /* @@ -1993,9 +2902,73 @@ struct tx_bd_long_inline { * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) - uint16_t unused2; - uint32_t unused3; - uint16_t unused4; + /* + * If set to '1', then the timestamp from the BD is used. If cleared + * to 0, then TWE provides the timestamp. + */ + #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400) + /* + * If set to '1', this operation will cause a trace capture in each + * block it passes through. + */ + #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800) + /* + * If set to '1', the device will record the time at which the packet + * was actually transmitted at the TX MAC for 1-step time sync. This + * bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000) + /* + * If set to '1', the controller replaces the Outer-tunnel IP checksum + * field with hardware calculated IP checksum for the IP header of the + * packet associated with this descriptor. For outer UDP checksum, it + * will be the following behavior for all cases independent of settings + * of inner LSO and checksum offload BD flags. If outer UDP checksum + * is 0, then do not update it. If outer UDP checksum is non zero, then + * the hardware should compute and update it. + */ + #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) + /* + * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP + * header will not be modified during LSO operations. If set to one + * when LSO is '1', then the IPID of the Outer-tunnel IP header will be + * incremented for each subsequent segment of an LSO operation. The + * flag is ignored if the LSO packet is a normal (non-tunneled) TCP + * packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000) + /* + * If set to '1', When set to 1, KTLS encryption will be enabled for + * the packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000) + uint8_t unused2; + uint8_t kid_or_ts_low; + #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1) + /* + * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of + * the 20-bit KID. + */ + #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe) + #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1 + uint32_t kid_or_ts_high; + #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff) + #define TX_BD_LONG_INLINE_UNUSED_SFT 0 + /* + * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit + * timestamp. If lflags.crypto_en is 1, the least significant 13 bits + * of this field contain the upper 13 bits of the 20-bit KID. + */ + #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000) + #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15 + /* + * This value selects bits 25:16 of the CFA action to perform on the + * packet. See the cfa_action field for more information. + */ + uint16_t cfa_action_high; + #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0 /* * This value selects a CFA action to perform on the packet. * Set this value to zero if no CFA action is desired. @@ -2009,16 +2982,19 @@ struct tx_bd_long_inline { */ uint32_t cfa_meta; /* When key = 1, this is the VLAN tag VID value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 /* When key = 1, this is the VLAN tag DE value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \ + UINT32_C(0x1000) /* When key = 1, this is the VLAN tag PRI value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \ + UINT32_C(0xe000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 /* When key = 1, this is the VLAN tag TPID select value. */ - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \ + UINT32_C(0x70000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 /* 0x88a8 */ #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \ (UINT32_C(0x0) << 16) @@ -2041,7 +3017,7 @@ struct tx_bd_long_inline { TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \ UINT32_C(0xff80000) - #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 + #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 /* * This field identifies the type of edit to be performed * on the packet. @@ -2050,7 +3026,7 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \ UINT32_C(0xf0000000) - #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 + #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 /* No editing */ #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \ (UINT32_C(0x0) << 28) @@ -2061,8 +3037,18 @@ struct tx_bd_long_inline { */ #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \ (UINT32_C(0x1) << 28) + /* + * Provide metadata + * - Wh+/SR - this option is not supported. + * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta + * is set in the Lookup Table. + * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * en_bd_meta is set in the Lookup Table. + */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \ + (UINT32_C(0x2) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ - TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG + TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER } __rte_packed; /* tx_bd_empty (size:128b/16B) */ @@ -2083,6 +3069,97 @@ struct tx_bd_empty { uint8_t unused_4[8]; } __rte_packed; +/* tx_bd_mp_cmd (size:128b/16B) */ +struct tx_bd_mp_cmd { + /* Unless otherwise stated, sub-fields of this field are always valid. */ + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_MP_CMD_TYPE_SFT 0 + /* + * Indicates that this BD is used to issue a command to one of + * the mid-path destinations. + */ + #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8) + #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD + #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_MP_CMD_FLAGS_SFT 6 + /* */ + #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0) + #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6 + /* + * This value indicates the number of 16B BD locations (slots) + * consumed in the ring by this mid-path command BD, including the + * BD header and the command field. + */ + #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8 + /* + * This value defines the length of command field in bytes. The maximum + * value shall be 496. + */ + uint16_t len; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with this + * Tx mid-path command. + */ + uint32_t opaque; + uint64_t unused1; +} __rte_packed; + +/* tx_bd_presync_cmd (size:128b/16B) */ +struct tx_bd_presync_cmd { + /* Unless otherwise stated, sub-fields of this field are always valid. */ + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_PRESYNC_CMD_TYPE_SFT 0 + /* + * Indicates that this BD is used to issue a cryptographic pre- + * sync command through the fast path and destined for TCE. + */ + #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9) + #define TX_BD_PRESYNC_CMD_TYPE_LAST \ + TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD + #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6 + /* */ + #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0) + #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6 + /* + * This value indicates the number of 16B BD locations (slots) + * consumed in the ring by this pre-sync command BD, including the + * BD header and the command field. + */ + #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8 + /* + * This value defines the length of command field in bytes. The maximum + * value shall be 496. + */ + uint16_t len; + /* + * The opaque data field is pass through to TCE and can be used for + * debug. + */ + uint32_t opaque; + /* + * This field is the Crypto Context ID to which the retransmit packet is + * applied. The KID references the context fields used by the + * associated kTLS offloaded connection. + */ + uint32_t kid; + /* + * The KID value of all-ones is reserved for non-KTLS packets, which + * only implies that this value must not be used when filling this + * field for crypto packets. + */ + #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff) + #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0 + uint32_t unused_1; +} __rte_packed; + /* rx_prod_pkt_bd (size:128b/16B) */ struct rx_prod_pkt_bd { /* This value identifies the type of buffer descriptor. */ @@ -2110,16 +3187,18 @@ struct rx_prod_pkt_bd { */ #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* + * This field has been deprecated. There can be no additional + * BDs for this packet from this ring. + * + * Old definition: * This value is the number of additional buffers in the ring that * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same - * network packet. - * - * Even if the packet to be placed does not need all the - * additional buffers, they will be consumed anyway. + * network packet. Even if the packet to be placed does not need + * all the additional buffers, they will be consumed anyway. */ #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300) #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8 @@ -2209,6 +3288,297 @@ struct rx_prod_agg_bd { uint64_t address; } __rte_packed; +/* cfa_cmpls_cmp_data_msg (size:128b/16B) */ +struct cfa_cmpls_cmp_data_msg { + uint32_t mp_client_dma_length_opcode_status_type; + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f) + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0 + /* Mid Path Short Completion with length = 16B. */ + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \ + UINT32_C(0x1e) + #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + /* This value indicates the status for the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0) + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6 + /* Completed without error. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \ + (UINT32_C(0x0) << 6) + /* Indicates an unsupported CFA opcode in the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \ + (UINT32_C(0x1) << 6) + /* + * Indicates a CFA command formatting error. This error can occur on + * any of the supported CFA commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \ + (UINT32_C(0x2) << 6) + /* + * Indicates an SVIF-Table scope error. This error can occur on any + * of the supported CFA commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \ + (UINT32_C(0x3) << 6) + /* + * Indicates that the table_index is either outside of the + * table_scope range set by its EM_SIZE or, for EM Insert, it is in + * the static bucket range. This error can occur on EM Insert + * commands. It can also occur on Read, Read Clear, Write, and + * Invalidate commands if the table_type is EM. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \ + (UINT32_C(0x4) << 6) + /* + * Cache operation responded with an error. This error can occur on + * Read, Read Clear, Write, EM Insert, and EM Delete commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \ + (UINT32_C(0x5) << 6) + /* + * Indicates failure on EM Insert or EM Delete Command. Hash index + * and hash msb are returned in table_index and hash_msb fields. + * Dma_length is set to 1 if the bucket is also returned (as dma + * data). + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \ + (UINT32_C(0x6) << 6) + /* + * Indicates no notifications were available on an Event Collection + * command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \ + (UINT32_C(0x7) << 6) + #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \ + CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10 + /* This is the opcode from the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \ + UINT32_C(0xff000) + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12 + /* + * This is read command. From 32 to 128B can be read from a table + * using this command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \ + (UINT32_C(0x0) << 12) + /* + * This is write command. From 32 to 128B can be written to a table + * using this command. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \ + (UINT32_C(0x1) << 12) + /* + * This is read-clear command. 32B can be read from a table and a 16b + * mask can be used to clear specific 16b units after the read as an + * atomic operation. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \ + (UINT32_C(0x2) << 12) + /* + * An exact match table insert will be attempted into the table. If + * there is a free location in the bucket, the payload will be + * written to the bucket. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \ + (UINT32_C(0x3) << 12) + /* An exact match table delete will be attempted. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \ + (UINT32_C(0x4) << 12) + /* + * The specified table area will be invalidated. If it is needed + * again, it will be read from the backing store. + */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \ + (UINT32_C(0x5) << 12) + /* Reads notification messages from the Host Notification Queue. */ + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \ + (UINT32_C(0x6) << 12) + #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT + /* + * This field indicates the length of the DMA that accompanies the + * completion. Specified in units of DWords (32b). Valid values are + * between 0 and 128. A value of zero indicates that there is no DMA + * that accompanies the completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \ + UINT32_C(0xff00000) + #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \ + UINT32_C(0xf0000000) + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28 + /* TX configrable flow processing block. */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \ + (UINT32_C(0x2) << 28) + /* RX configrable flow processing block. */ + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \ + (UINT32_C(0x3) << 28) + #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ + CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque; + uint16_t hash_msb_v; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1 + /* + * This is the upper 12b of the hash, returned on Exact Match + * Insertion/Deletion Commands. + */ + #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0) + #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4 + /* This is the table type from the command. */ + uint8_t table_type; + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf) + #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0 + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4 + /* This command acts on the action table of the specified scope. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4) + /* This command acts on the exact match table of the specified scope. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \ + CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM + uint8_t table_scope; + /* This is the table scope from the command. */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0 + uint32_t table_index; + /* + * This is the table index from the command (if it exists). However, if + * an Exact Match Insertion/Deletion command failed, then this is the + * table index of the calculated static hash bucket. + */ + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff) + #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0 +} __rte_packed; + +/* CFA Mid-Path 32B DMA Message */ +/* cfa_dma32b_data_msg (size:256b/32B) */ +struct cfa_dma32b_data_msg { + /* DMA data value. */ + uint32_t dta[8]; +} __rte_packed; + +/* CFA Mid-Path 64B DMA Message */ +/* cfa_dma64b_data_msg (size:512b/64B) */ +struct cfa_dma64b_data_msg { + /* DMA data value. */ + uint32_t dta[16]; +} __rte_packed; + +/* CFA Mid-Path 96B DMA Message */ +/* cfa_dma96b_data_msg (size:768b/96B) */ +struct cfa_dma96b_data_msg { + /* DMA data value. */ + uint32_t dta[24]; +} __rte_packed; + +/* CFA Mid-Path 128B DMA Message */ +/* cfa_dma128b_data_msg (size:1024b/128B) */ +struct cfa_dma128b_data_msg { + /* DMA data value. */ + uint32_t dta[32]; +} __rte_packed; + +/* ce_cmpls_cmp_data_msg (size:128b/16B) */ +struct ce_cmpls_cmp_data_msg { + uint16_t status_subtype_type; + /* + * This field indicates the exact type of the completion. By + * convention, the LSB identifies the length of the record in 16B + * units. Even values indicate 16B records. Odd values indicate 32B + * records. + */ + #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f) + #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0 + /* Completion of a Mid Path Command. Length = 16B */ + #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e) + #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \ + CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + /* + * This value indicates the CE sub-type operation that is being + * completed. + */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6 + /* Completion Response for a Solicited Command. */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6) + /* Error Completion (Unsolicited). */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6) + /* Re-Sync Completion (Unsolicited) */ + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \ + CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC + /* This value indicates the status for the command. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10 + /* Completed without error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \ + (UINT32_C(0x0) << 10) + /* CFCK load error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \ + (UINT32_C(0x1) << 10) + /* FID check error. */ + #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \ + (UINT32_C(0x2) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \ + CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR + uint8_t unused0; + uint8_t mp_clients; + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0 + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4 + /* TX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4) + /* RX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \ + CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE + /* + * This is a copy of the opaque field from the mid path BD of this + * command. + */ + uint32_t opaque; + /* */ + uint32_t kid_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated kTLS offloaded connection. + */ + #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe) + #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1 + uint32_t unused2; +} __rte_packed; + /* cmpl_base (size:128b/16B) */ struct cmpl_base { uint16_t type; @@ -2226,6 +3596,35 @@ struct cmpl_base { * Completion of TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) + /* + * NO-OP completion: + * Completion of NO-OP. Length = 16B + */ + #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1) + /* + * TX L2 coalesced completion: + * Completion of coalesced TX packet. Length = 16B + */ + #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2) + /* + * TX L2 PTP completion: + * Completion of PTP TX packet. Length = 32B + */ + #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) + /* + * RX L2 TPA Start V2 Completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd) + /* + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. + */ + #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf) /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B @@ -2255,6 +3654,24 @@ struct cmpl_base { * Length = 16B */ #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a) + /* + * VEE Flush Completion: + * This completion is inserted manually by + * the Primate and processed by the VEE hardware to ensure that + * all completions on a VEE function have been processed by the + * VEE hardware before FLR process is completed. + */ + #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c) + /* + * Mid Path Short Completion : + * Completion of a Mid Path Command. Length = 16B + */ + #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e) + /* + * Mid Path Long Completion : + * Completion of a Mid Path Command. Length = 32B + */ + #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f) /* * HWRM Command Completion: * Completion of an HWRM command. @@ -2332,7 +3749,9 @@ struct tx_cmpl { uint16_t unused_0; /* * This is a copy of the opaque field from the first TX BD of this - * transmitted packet. + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. */ uint32_t opaque; uint16_t errors_v; @@ -2341,58 +3760,352 @@ struct tx_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define TX_CMPL_V UINT32_C(0x1) - #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define TX_CMPL_ERRORS_SFT 1 + #define TX_CMPL_V UINT32_C(0x1) + #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem * with the BDs for the packet. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No error */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \ TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT /* * When this bit is '1', it indicates that the length of * the packet was zero. No packet was transmitted. */ - #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) /* * When this bit is '1', it indicates that the packet * was longer than the programmed limit in TDI. No * packet was transmitted. */ - #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) /* * When this bit is '1', it indicates that one or more of the * BDs associated with this packet generated a PCI error. * This probably means the address was not valid. */ - #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) + #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet was longer * than indicated by the hint. No packet was transmitted. */ - #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) /* * When this bit is '1', it indicates that the packet was * dropped due to Poison TLP error on one or more of the * TLPs in the PXP completion. */ - #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such completions + * are PTP completions or other TX completions. + */ + #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) /* unused2 is 16 b */ uint16_t unused_1; /* unused3 is 32 b */ uint32_t unused_2; } __rte_packed; +/* tx_cmpl_coal (size:128b/16B) */ +struct tx_cmpl_coal { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_COAL_TYPE_SFT 0 + /* + * TX L2 coalesced completion: + * Completion of TX packet. Length = 16B + */ + #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2) + #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL + #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_COAL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of the packet + * which corresponds with the reported sq_cons_idx. Note that, with + * coalesced completions, completions are generated for only some of the + * packets. The driver will see the opaque field for only those packets. + * Note that, if the packet was described by a short CSO or short CSO + * inline BD, then the 16-bit opaque field from the short CSO BD will + * appear in the bottom 16 bits of this field. For TX rings with + * completion coalescing enabled (which would use the coalesced + * completion record), it is suggested that the driver populate the + * opaque field to indicate the specific TX ring with which the + * completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_COAL_V UINT32_C(0x1) + #define TX_CMPL_COAL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define TX_CMPL_COAL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \ + UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \ + UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + uint32_t sq_cons_idx; + /* + * This value is SQ index for the start of the packet following the + * last completed packet. + */ + #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff) + #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 +} __rte_packed; + +/* tx_cmpl_ptp (size:128b/16B) */ +struct tx_cmpl_ptp { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_PTP_TYPE_SFT 0 + /* + * TX L2 PTP completion: + * Completion of TX packet. Length = 32B + */ + #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2) + #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP + #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_PTP_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of this + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_PTP_V UINT32_C(0x1) + #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_PTP_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped due + * to a transient internal error in TDC. The packet or LSO can be + * retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint32_t timestamp_lo; +} __rte_packed; + +/* tx_cmpl_ptp_hi (size:128b/16B) */ +struct tx_cmpl_ptp_hi { + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint16_t timestamp_hi[3]; + uint16_t reserved16; + uint64_t v2; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue.The even passes will write 1. + * The odd passes will write 0 + */ + #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) +} __rte_packed; + /* rx_pkt_cmpl (size:128b/16B) */ struct rx_pkt_cmpl { uint16_t flags_type; @@ -2937,12 +4650,8 @@ struct rx_pkt_cmpl_hi { #define RX_PKT_CMPL_REORDER_SFT 0 } __rte_packed; -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +/* rx_pkt_v2_cmpl (size:128b/16B) */ +struct rx_pkt_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -2951,84 +4660,143 @@ struct rx_tpa_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_START_CMPL_TYPE_SFT 0 + #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_V2_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. */ - #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) - #define RX_TPA_START_CMPL_TYPE_LAST \ - RX_TPA_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_START_CMPL_FLAGS_SFT 6 - /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf) + #define RX_PKT_V2_CMPL_TYPE_LAST \ + RX_PKT_V2_CMPL_TYPE_RX_L2_V2 + #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Normal: + * Packet was placed using normal algorithm. + */ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Packet was placed using jumbo algorithm. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Truncation: + * Packet was placed using truncation algorithm. The + * placed (truncated) length is indicated in the payload_offset + * field. The original length is indicated in the len field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \ + (UINT32_C(0x3) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* * TCP Packet: * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -3036,19 +4804,24 @@ struct rx_tpa_start_cmpl { * corresponds to. */ uint32_t opaque; + uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - uint8_t v1; + #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 2 b */ + #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0) + #define RX_PKT_V2_CMPL_UNUSED1_SFT 6 /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. @@ -3079,385 +4852,463 @@ struct rx_tpa_start_cmpl { * corresponding to 4-tuples are only valid for TCP traffic. */ uint8_t rss_hash_type; - /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. - */ - uint16_t agg_id; - /* unused2 is 9 b */ - #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_UNUSED2_SFT 0 - /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. - */ - #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) - #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + uint16_t metadata1_payload_offset; + /* + * This is data from the CFA as indicated by the meta_format field. + * If truncation placement is not used, this value indicates the offset + * in bytes from the beginning of the packet where the inner payload + * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If + * truncation placement is used, this value represents the placed + * (truncated) length of the packet. + */ + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) /* * This value is the RSS hash value calculated for the packet - * based on the mode bits and key value in the VNIC. + * based on the mode bits and key value in the VNIC. When vee_cmpl_mode + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. */ uint32_t rss_hash; } __rte_packed; -/* - * Last 16 bytes of rx_tpa_start_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_cmpl_hi { +/* Last 16 bytes of RX Packet V2 Completion Record */ +/* rx_pkt_v2_cmpl_hi (size:128b/16B) */ +struct rx_pkt_v2_cmpl_hi { uint32_t flags2; /* - * This indicates that the ip checksum was calculated for the - * inner packet and that the sum passed for all segments - * included in the aggregation. - */ - #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * This indicates that the TCP, UDP or ICMP checksum was - * calculated for the inner packet and that the sum passed - * for all segments included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) /* - * This indicates that the ip checksum was calculated for the - * tunnel header and that the sum passed for all segments - * included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) /* - * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the sum passed for - * all segments included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). */ - #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) - /* This value indicates what format the metadata field is. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ - (UINT32_C(0x0) << 4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) /* - * The metadata field contains the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. - * - metadata[31:16] contains the vlan TPID value. - */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ - (UINT32_C(0x1) << 4) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \ + RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. - */ - uint32_t metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 - uint16_t v2; + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_V2 \ + UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1 /* - * This field identifies the CFA action rule that was used for this - * packet. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - uint16_t cfa_code; + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 8 physical buffers + * (if fixed-size buffers are used), or that the packet could + * not be placed in the number of physical buffers configured + * for the VNIC (if variable-size buffers are used) */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. For regular placement, this error is + * not valid. For HDS and jumbo placement, this means that not + * enough agg BDs were posted to place the packet. */ - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. + * Bad Format: + * BDs were not formatted correctly. */ - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. + * Flush: + * There was a bad_format error on the previous operation */ - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * This indicates that there was an error in the outer tunnel + * portion of the packet when this field is non-zero. */ - #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 -} __rte_packed; - -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { - uint16_t flags_type; + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \ + UINT32_C(0x70) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * No additional error occurred on the outer tunnel portion + * of the packet or the packet does not have a outer tunnel. */ - #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_END_CMPL_TYPE_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 4) /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. - * Length = 32B + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header. */ - #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_END_CMPL_TYPE_LAST \ - RX_TPA_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_END_CMPL_FLAGS_SFT 6 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \ + (UINT32_C(0x1) << 4) /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * Indicates that header length is out of range in the outer + * tunnel header. Valid for IPv4. */ - #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) - /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 4) /* - * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Indicates that physical packet is shorter than that claimed + * by the outer tunnel l3 header length. Valid for IPv4, or + * IPv6 outer tunnel packets. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ - (UINT32_C(0x1) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 4) /* - * Header/Data Separation: - * Packet was placed using Header/Data separation algorithm. - * The separation location is indicated by the itype field. + * Indicates that the physical packet is shorter than that + * claimed by the outer tunnel UDP header length for a outer + * tunnel UDP packet that is not fragmented. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ - (UINT32_C(0x2) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 4) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that the IPv4 TTL or IPv6 hop limit check have + * failed (e.g. TTL = 0) in the outer tunnel header. Valid for + * IPv4, and IPv6. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \ + (UINT32_C(0x5) << 4) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that the IP checksum failed its check in the outer + * tunnel header. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \ + (UINT32_C(0x6) << 4) /* - * This value indicates what the inner packet determined for the - * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. + * Indicates that the L4 checksum failed its check in the outer + * tunnel header. */ - #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \ + (UINT32_C(0x7) << 4) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - uint16_t len; + #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \ + UINT32_C(0x100) /* - * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. */ - uint32_t opaque; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe00) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. */ - uint8_t agg_bufs_v1; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 9) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. */ - #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 9) /* - * This value is the number of aggregation buffers that follow this - * entry in the completion ring that are a part of this aggregation - * packet. - * If the value is zero, then the packet is completely contained - * in the buffer space provided in the aggregation start completion. + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. */ - #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) - #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 9) /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * - * A value of zero indicates an offset of 256 bytes. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. */ - uint8_t payload_offset; - uint8_t agg_id; - /* unused2 is 1 b */ - #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 9) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. */ - #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) - #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 9) /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. */ - uint32_t tsdelta; -} __rte_packed; - -/* - * Last 16 bytes of rx_tpa_end_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { - uint32_t tpa_dup_acks; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 9) /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * Indicates that the IP checksum failed its check in the tunnel + * header. */ - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 9) /* - * This value is the valid when TPA completion is active. It - * indicates the length of the longest segment of the TPA operation - * for LRO mode and the length of the first segment in GRO mode. - * - * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used - * to indicate MSS size to the stack. + * Indicates that the L4 checksum failed its check in the tunnel + * header. */ - uint16_t tpa_seg_len; - /* unused4 is 16 b */ - uint16_t unused3; - uint16_t errors_v2; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 9) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. */ - #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define RX_TPA_END_CMPL_ERRORS_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12 /* - * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as - * invalid. + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 12) /* - * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not - * BDs on chip but that there was adequate reservation. - * provided by the TPA block. + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ - (UINT32_C(0x2) << 1) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 12) /* - * This error occurs when TPA block was not configured to - * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. - * - * This error can also be generated when the number of - * segments is not programmed correctly in TPA and the - * 33 total aggregation buffers allowed for the TPA - * operation has been exceeded. + * indicates that header length is out of range. Valid for + * IPv4 and RoCE */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ - (UINT32_C(0x4) << 1) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR - /* unused5 is 16 b */ - uint16_t unused_4; + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 12) /* - * This is the opaque value that was completed for the TPA start - * completion that corresponds to this TPA end completion. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 */ - uint32_t start_opaque; + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 12) + /* + * Indicates that the IP checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \ + (UINT32_C(0x9) << 12) + /* + * Indicates that the L4 checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \ + (UINT32_C(0xa) << 12) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13 + /* + * The timestamp field contains the 32b timestamp for the packet from + * the MAC. + */ + uint32_t timestamp; } __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl { +/* rx_tpa_start_cmpl (size:128b/16B) */ +struct rx_tpa_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -3466,28 +5317,23 @@ struct rx_tpa_v2_start_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_START_CMPL_TYPE_MASK \ - UINT32_C(0x3f) - #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 /* * RX L2 TPA Start Completion: * Completion at the beginning of a TPA operation. * Length = 32B */ - #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ - UINT32_C(0x13) - #define RX_TPA_V2_START_CMPL_TYPE_LAST \ - RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ - UINT32_C(0xffc0) - #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + #define RX_TPA_START_CMPL_TYPE_LAST \ + RX_TPA_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ - UINT32_C(0x40) + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ - UINT32_C(0x380) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -3496,14 +5342,14 @@ struct rx_tpa_v2_start_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* * GRO/Jumbo: @@ -3513,7 +5359,7 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -3524,39 +5370,28 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ - UINT32_C(0x400) - /* - * For devices that support timestamps, when this bit is cleared the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the 32b timestamp for - * the packet from the MAC. When this bit is set, the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the outer_l3_offset, inner_l2_offset, - * inner_l3_offset, and inner_l4_size. - */ - #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ - UINT32_C(0x800) + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ - UINT32_C(0xf000) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 /* * TCP Packet: * Indicates that the packet was IP and TCP. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* * This value indicates the amount of packet data written to the * buffer the opaque field in this completion corresponds to. @@ -3578,8 +5413,8 @@ struct rx_tpa_v2_start_cmpl { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. @@ -3616,6 +5451,16 @@ struct rx_tpa_v2_start_cmpl { * with the TPA end completion. */ uint16_t agg_id; + /* unused2 is 9 b */ + #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) + #define RX_TPA_START_CMPL_AGG_ID_SFT 9 /* * This value is the RSS hash value calculated for the packet * based on the mode bits and key value in the VNIC. @@ -3624,48 +5469,43 @@ struct rx_tpa_v2_start_cmpl { } __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_start_cmpl. + * Last 16 bytes of rx_tpa_start_cmpl. * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl_hi { +/* rx_tpa_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the * inner packet and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ - UINT32_C(0x1) + #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) /* * This indicates that the TCP, UDP or ICMP checksum was * calculated for the inner packet and that the sum passed * for all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ - UINT32_C(0x2) + #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* * This indicates that the ip checksum was calculated for the * tunnel header and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ - UINT32_C(0x4) + #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* * This indicates that the UDP checksum was * calculated for the tunnel packet and that the sum passed for * all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ - UINT32_C(0x8) + #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) /* This value indicates what format the metadata field is. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ - UINT32_C(0xf0) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Value is zero. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* * The metadata field contains the VLAN tag and TPID value. @@ -3674,62 +5514,427 @@ struct rx_tpa_v2_start_cmpl_hi { * - metadata[15:13] contains the vlan PRI value. * - metadata[31:16] contains the vlan TPID value. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ (UINT32_C(0x1) << 4) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN /* - * If ext_meta_format is equal to 1, the metadata field - * contains the lower 16b of the tunnel ID value, justified - * to LSB + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + */ + #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint32_t metadata; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 + uint16_t v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + /* + * This field identifies the CFA action rule that was used for this + * packet. + */ + uint16_t cfa_code; + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + /* + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. + */ + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. + */ + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. + */ + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte + * struct) + */ +/* rx_tpa_start_v2_cmpl (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_START_V2_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA Start V2 Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ + UINT32_C(0xd) + #define RX_TPA_START_V2_CMPL_TYPE_LAST \ + RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 + #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + uint16_t agg_id; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V2_CMPL_METADATA1_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \ + UINT32_C(0x7000) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* 0x88a8 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \ + (UINT32_C(0x0) << 12) + /* 0x8100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \ + (UINT32_C(0x1) << 12) + /* 0x9100 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \ + (UINT32_C(0x2) << 12) + /* 0x9200 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \ + (UINT32_C(0x3) << 12) + /* 0x9300 */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \ + (UINT32_C(0x4) << 12) + /* Value programmed in CFA VLANTPID register. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \ + (UINT32_C(0x5) << 12) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \ + RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V2_CMPL_METADATA1_VALID \ + UINT32_C(0x8000) + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. + */ + uint32_t rss_hash; +} __rte_packed; + +/* + * Last 16 bytes of RX L2 TPA Start V2 Completion Record + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl_hi { + uint32_t flags2; + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x4) + /* + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] * - MPLs = Outer label[19:0] * - UPAR = Selected[31:0] with bit mask */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ (UINT32_C(0x2) << 4) /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ (UINT32_C(0x3) << 4) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset, inner_l2_offset, inner_l3_offset and - * inner_l4_size. - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[17:9] contains the inner_l2_offset. - * - metadata[26:18] contains the inner_l3_offset. - * - metadata[31:27] contains the inner_l4_size. - */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ (UINT32_C(0x4) << 4) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ + #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \ UINT32_C(0x100) /* * This indicates that the complete 1's complement checksum was - * calculated for the packet. + * calculated for the packet in the affregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ UINT32_C(0x200) /* - * The combination of this value and meta_format indicated what - * format the metadata field is. + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + * CS status for TPA packets is always valid. This means that "all_ok" + * status will always be set. The ok count status will be set + * appropriately for the packet header, such that all existing CS + * values are ok. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ - UINT32_C(0xc00) - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10 /* * This value is the complete 1's complement checksum calculated from * the start of the outer L3 header to the end of the packet (not @@ -3738,112 +5943,101 @@ struct rx_tpa_v2_start_cmpl_hi { * the complete checksum is calculated for the first packet in the * aggregation only. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. - */ - uint32_t metadata; - /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ - #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ - #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ - #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ - #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V2 \ + #define RX_TPA_START_V2_CMPL_V2 \ UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ + #define RX_TPA_START_V2_CMPL_ERRORS_MASK \ UINT32_C(0xfffe) - #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * the BDs for the packetThe packet should be treated as * invalid. */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \ UINT32_C(0xe) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * This field identifies the CFA action rule that was used for this - * packet. + * This is data from the CFA block as indicated by the meta_format + * field. */ - uint16_t cfa_code; - /* - * For devices that support timestamps this field is overridden - * with the timestamp value. When `flags.timestamp_fld_format` is - * cleared, this field contains the 32b timestamp for the packet from the - * MAC. + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13 + /* + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. * - * When `flags.timestamp_fld_format` is set, this field contains the - * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size - * as defined below. - */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; - /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. - */ - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 - /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. - */ - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 - /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. - */ - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 - /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. */ - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 + uint32_t hdr_offsets; } __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_end_cmpl (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl { +/* rx_tpa_end_cmpl (size:128b/16B) */ +struct rx_tpa_end_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. @@ -3852,27 +6046,27 @@ struct rx_tpa_v2_end_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 /* * RX L2 TPA End Completion: * Completion at the end of a TPA operation. * Length = 32B */ - #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_V2_END_CMPL_TYPE_LAST \ - RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_END_CMPL_TYPE_LAST \ + RX_TPA_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an * error of some type. Type of error is indicated in * error_flags. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: * TPA Packet was placed using jumbo algorithm. This means @@ -3881,15 +6075,24 @@ struct rx_tpa_v2_end_cmpl { * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* * GRO/Jumbo: * Packet will be placed using GRO/Jumbo where the first @@ -3898,7 +6101,7 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -3909,13 +6112,30 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10 + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* unused is 1 b */ + #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. @@ -3925,8 +6145,9 @@ struct rx_tpa_v2_end_cmpl { * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 /* * This value is zero for TPA End completions. * There is no data in the buffer that corresponds to the opaque @@ -3938,21 +6159,47 @@ struct rx_tpa_v2_end_cmpl { * corresponds to. */ uint32_t opaque; - uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) + uint8_t agg_bufs_v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. + */ + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 /* This value is the number of segments in the TPA operation. */ uint8_t tpa_segs; + /* + * This value indicates the offset in bytes from the beginning of the packet + * where the inner payload starts. This value is valid for TCP, UDP, + * FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t payload_offset; + uint8_t agg_id; + /* unused2 is 1 b */ + #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) /* * This is the aggregation ID that the completion is associated * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ - uint16_t agg_id; + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 /* * For non-GRO packets, this value is the * timestamp delta between earliest and latest timestamp values for @@ -3970,39 +6217,20 @@ struct rx_tpa_v2_end_cmpl { } __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_end_cmpl. + * Last 16 bytes of rx_tpa_end_cmpl. * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl_hi { - /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. - */ - uint16_t tpa_dup_acks; +/* rx_tpa_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; /* * This value is the number of duplicate ACKs that have been * received as part of the TPA operation. */ - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 - /* - * This value indicated the offset in bytes from the beginning of - * the packet where the inner payload starts. This value is valid - * for TCP, UDP, FCoE and RoCE packets - */ - uint8_t payload_offset; - /* - * The value is the total number of aggregation buffers that were - * used in the TPA operation. All TPA aggregation buffer completions - * precede the TPA End completion. If the value is zero, then the - * aggregation is completely contained in the buffer space provided - * in the aggregation start completion. - * Note that the field is simply provided as a cross check. - */ - uint8_t tpa_agg_bufs; + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation @@ -4014,43 +6242,33 @@ struct rx_tpa_v2_end_cmpl_hi { * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; - uint16_t unused_1; + /* unused4 is 16 b */ + uint16_t unused3; uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ - UINT32_C(0xfffe) - #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 + #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_TPA_END_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the * packet was already placed. The packet should be treated as * invalid. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ - UINT32_C(0xe) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 - /* No buffer error */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ - (UINT32_C(0x0) << 1) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* * This error occurs when there is a fatal HW problem in * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ (UINT32_C(0x2) << 1) - /* - * Bad Format: - * BDs were not formatted correctly. - */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ - (UINT32_C(0x3) << 1) /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX @@ -4061,17 +6279,12 @@ struct rx_tpa_v2_end_cmpl_hi { * 33 total aggregation buffers allowed for the TPA * operation has been exceeded. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ (UINT32_C(0x4) << 1) - /* - * Flush: - * There was a bad_format error on the previous operation - */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ - (UINT32_C(0x5) << 1) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH - uint16_t unused_2; + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR + /* unused5 is 16 b */ + uint16_t unused_4; /* * This is the opaque value that was completed for the TPA start * completion that corresponds to this TPA end completion. @@ -4083,9 +6296,9 @@ struct rx_tpa_v2_end_cmpl_hi { * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ -/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ -struct rx_tpa_v2_abuf_cmpl { - uint16_t type; +/* rx_tpa_v2_start_cmpl (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -4093,257 +6306,385 @@ struct rx_tpa_v2_abuf_cmpl { * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 /* - * RX TPA Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA packet completion. Length = 16B - */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) - #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ - RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + * RX L2 TPA Start Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + */ + #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ + UINT32_C(0x13) + #define RX_TPA_V2_START_CMPL_TYPE_LAST \ + RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * For devices that support timestamps, when this bit is cleared the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the 32b timestamp for + * the packet from the MAC. When this bit is set, the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. */ uint32_t opaque; - uint16_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) + uint8_t v1; /* - * This is the aggregation ID that the completion is associated with. Use - * this number to correlate the TPA agg completion with the TPA start - * completion and the TPA end completion. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ uint16_t agg_id; - uint32_t unused_1; + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + */ + uint32_t rss_hash; } __rte_packed; -/* rx_abuf_cmpl (size:128b/16B) */ -struct rx_abuf_cmpl { - uint16_t type; +/* + * Last 16 bytes of rx_tpa_v2_start_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl_hi { + uint32_t flags2; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates that the ip checksum was calculated for the + * inner packet and that the sum passed for all segments + * included in the aggregation. */ - #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * RX Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the sum passed + * for all segments included in the aggregation. */ - #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) - #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * This indicates that the ip checksum was calculated for the + * tunnel header and that the sum passed for all segments + * included in the aggregation. */ - uint16_t len; + #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the sum passed for + * all segments included in the aggregation. */ - uint32_t opaque; - uint32_t v; + #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata informtaion. Value is zero. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The metadata field contains the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. + * - metadata[31:16] contains the vlan TPID value. */ - #define RX_ABUF_CMPL_V UINT32_C(0x1) - /* unused3 is 32 b */ - uint32_t unused_2; -} __rte_packed; - -/* eject_cmpl (size:128b/16B) */ -struct eject_cmpl { - uint16_t type; + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + (UINT32_C(0x1) << 4) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * If ext_meta_format is equal to 1, the metadata field + * contains the lower 16b of the tunnel ID value, justified + * to LSB + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define EJECT_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) /* - * Statistics Ejection Completion: - * Completion of statistics data ejection buffer. - * Length = 16B + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). */ - #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) - #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT - #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define EJECT_CMPL_FLAGS_SFT 6 + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset, inner_l2_offset, inner_l3_offset and + * inner_l4_size. + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[17:9] contains the inner_l2_offset. + * - metadata[26:18] contains the inner_l3_offset. + * - metadata[31:27] contains the inner_l4_size. */ - #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* - * This is the length of the statistics data stored in this - * buffer. + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ - uint16_t len; + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) /* - * This is a copy of the opaque field from the RX BD this ejection - * buffer corresponds to. + * This indicates that the complete 1's complement checksum was + * calculated for the packet. */ - uint32_t opaque; - uint16_t v; + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * The combination of this value and meta_format indicated what + * format the metadata field is. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ + UINT32_C(0xc00) + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint32_t metadata; + /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ + #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ + #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ + #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ + #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define EJECT_CMPL_V UINT32_C(0x1) - #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define EJECT_CMPL_ERRORS_SFT 1 + #define RX_TPA_V2_START_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for statistics ejection. The statistics ejection should - * be treated as invalid + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) - /* - * Did Not Fit: - * Statistics did not fit into aggregation buffer provided. - */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ - (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ - EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH - /* reserved16 is 16 b */ - uint16_t reserved16; - /* unused3 is 32 b */ - uint32_t unused_2; -} __rte_packed; - -/* hwrm_cmpl (size:128b/16B) */ -struct hwrm_cmpl { - uint16_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * HWRM Command Completion: - * Completion of an HWRM command. + * This field identifies the CFA action rule that was used for this + * packet. */ - #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) - #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE - /* This is the sequence_id of the HWRM command that has completed. */ - uint16_t sequence_id; - /* unused2 is 32 b */ - uint32_t unused_1; - uint32_t v; + uint16_t cfa_code; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * For devices that support timestamps this field is overridden + * with the timestamp value. When `flags.timestamp_fld_format` is + * cleared, this field contains the 32b timestamp for the packet from the + * MAC. + * + * When `flags.timestamp_fld_format` is set, this field contains the + * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size + * as defined below. */ - #define HWRM_CMPL_V UINT32_C(0x1) - /* unused4 is 32 b */ - uint32_t unused_3; -} __rte_packed; - -/* hwrm_fwd_req_cmpl (size:128b/16B) */ -struct hwrm_fwd_req_cmpl { + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. */ - uint16_t req_len_type; + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. */ - #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Request */ - #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) - #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ - HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ - /* Length of forwarded request in bytes. */ - #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) - #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 /* - * Source ID of this request. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. */ - uint16_t source_id; - /* unused1 is 32 b */ - uint32_t unused0; - /* Address of forwarded request. */ - uint32_t req_buf_addr_v[2]; + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. */ - #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 } __rte_packed; -/* hwrm_fwd_resp_cmpl (size:128b/16B) */ -struct hwrm_fwd_resp_cmpl { - uint16_t type; +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -4351,288 +6692,264 @@ struct hwrm_fwd_resp_cmpl { * records. Odd values indicate 32B * records. */ - #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Response */ - #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) - #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ - HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + #define RX_TPA_V2_END_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 /* - * Source ID of this response. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B */ - uint16_t source_id; - /* Length of forwarded response in bytes. */ - uint16_t resp_len; - /* unused2 is 16 b */ - uint16_t unused_1; - /* Address of forwarded request. */ - uint32_t resp_buf_addr_v[2]; + #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \ + UINT32_C(0x15) + #define RX_TPA_V2_END_CMPL_TYPE_LAST \ + RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_V2_END_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. */ - #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 -} __rte_packed; - -/* hwrm_async_event_cmpl (size:128b/16B) */ -struct hwrm_async_event_cmpl { - uint16_t type; + #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ - UINT32_C(0x0) - /* Link MTU changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \ - UINT32_C(0x1) - /* Link speed changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \ - UINT32_C(0x2) - /* DCB Configuration changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \ - UINT32_C(0x3) - /* Port connection not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \ - UINT32_C(0x4) - /* Link speed configuration was not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ - UINT32_C(0x5) - /* Link speed configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \ - UINT32_C(0x6) - /* Port PHY configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \ - UINT32_C(0x7) - /* Reset notification to clients */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \ - UINT32_C(0x8) - /* Master function selection event */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \ - UINT32_C(0x9) - /* Function driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \ - UINT32_C(0x10) - /* Function driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \ - UINT32_C(0x11) - /* Function FLR related processing has completed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \ - UINT32_C(0x12) - /* PF driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \ - UINT32_C(0x20) - /* PF driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \ - UINT32_C(0x21) - /* VF Function Level Reset (FLR) */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \ - UINT32_C(0x30) - /* VF MAC Address Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \ - UINT32_C(0x31) - /* PF-VF communication channel status change. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ - UINT32_C(0x32) - /* VF Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \ - UINT32_C(0x33) - /* LLFC/PFC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \ - UINT32_C(0x34) - /* Default VNIC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \ - UINT32_C(0x35) - /* HW flow aged */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \ - UINT32_C(0x36) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * A debug notification being posted to the driver. These - * notifications are purely for diagnostic purpose and should not be - * used for functional purpose. The driver is not supposed to act - * on these messages except to log/record it. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \ - UINT32_C(0x37) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * An EEM flow cached memory flush for all flows request event being - * posted to the PF driver. + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \ - UINT32_C(0x38) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) /* - * An EEM flow cache memory flush completion event being posted to the - * firmware by the PF driver. This is indication that host EEM flush - * has completed by the PF. + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \ - UINT32_C(0x39) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) /* - * A tcp flag action change event being posted to the PF or trusted VF - * driver by the firmware. The PF or trusted VF driver should query - * the firmware for the new TCP flag action update after receiving - * this async event. + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ - UINT32_C(0x3a) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* unused is 1 b */ + #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \ + UINT32_C(0x400) /* - * An EEM flow active event being posted to the PF or trusted VF driver - * by the firmware. The PF or trusted VF driver should update the - * flow's aging timer after receiving this async event. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \ - UINT32_C(0x3b) + #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) /* - * A eem cfg change event being posted to the trusted VF driver by the - * firmware if the parent PF EEM configuration changed. + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ - UINT32_C(0x3c) - /* TFLIB unique default VNIC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ - UINT32_C(0x3d) - /* TFLIB unique link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ - UINT32_C(0x3e) + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 /* - * An event signifying completion for HWRM_FW_STATE_QUIESCE - * (completion, timeout, or error) + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ - UINT32_C(0x3f) + uint16_t len; /* - * A trace log message. This contains firmware trace logs string - * embedded in the asynchronous message. This is an experimental - * event, not meant for production use at this time. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \ - UINT32_C(0xfe) - /* HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint32_t opaque; + uint8_t v1; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; + #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + uint16_t agg_id; + /* + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. + */ + uint32_t tsdelta; } __rte_packed; -/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_status_change { - uint16_t type; +/* + * Last 16 bytes of rx_tpa_v2_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl_hi { /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \ - UINT32_C(0x0) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint16_t tpa_dup_acks; + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 + /* + * This value indicated the offset in bytes from the beginning of + * the packet where the inner payload starts. This value is valid + * for TCP, UDP, FCoE and RoCE packets + */ + uint8_t payload_offset; + /* + * The value is the total number of aggregation buffers that were + * used in the TPA operation. All TPA aggregation buffer completions + * precede the TPA End completion. If the value is zero, then the + * aggregation is completely contained in the buffer space provided + * in the aggregation start completion. + * Note that the field is simply provided as a cross check. + */ + uint8_t tpa_agg_bufs; + /* + * This value is the valid when TPA completion is active. It + * indicates the length of the longest segment of the TPA operation + * for LRO mode and the length of the first segment in GRO mode. + * + * This value may be used by GRO software to re-construct the original + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used + * to indicate MSS size to the stack. + */ + uint16_t tpa_seg_len; + uint16_t unused_1; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates link status change */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \ - UINT32_C(0x1) + #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 /* - * If this bit set to 0, then it indicates that the link - * was up and it went down. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \ - UINT32_C(0x0) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * If this bit is set to 1, then it indicates that the link - * was down and it went up. + * This error occurs when there is a fatal HW problem in + * the chip only. It indicates that there were not + * BDs on chip but that there was adequate reservation. + * provided by the TPA block. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP - /* Indicates the physical port this link status change occur */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \ - UINT32_C(0xe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \ - 1 - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff0) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 4 - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0xff00000) - #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ - 20 + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * This error occurs when TPA block was not configured to + * reserve adequate BDs for TPA operations on this RX + * ring. All data for the TPA operation was not placed. + * + * This error can also be generated when the number of + * segments is not programmed correctly in TPA and the + * 33 total aggregation buffers allowed for the TPA + * operation has been exceeded. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + (UINT32_C(0x4) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH + uint16_t unused_2; + /* + * This is the opaque value that was completed for the TPA start + * completion that corresponds to this TPA end completion. + */ + uint32_t start_opaque; } __rte_packed; -/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_mtu_change { +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ +struct rx_tpa_v2_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -4641,48 +6958,48 @@ struct hwrm_async_event_cmpl_link_mtu_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link MTU changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + /* + * RX TPA Aggregation Buffer completion : + * Completion of an L2 aggregation buffer in support of + * TPA packet completion. Length = 16B + */ + #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) + #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ + RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* The new MTU of the link in bytes. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 + #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) + /* + * This is the aggregation ID that the completion is associated with. Use + * this number to correlate the TPA agg completion with the TPA start + * completion and the TPA end completion. + */ + uint16_t agg_id; + uint32_t unused_1; } __rte_packed; -/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_change { +/* rx_abuf_cmpl (size:128b/16B) */ +struct rx_abuf_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -4691,94 +7008,44 @@ struct hwrm_async_event_cmpl_link_speed_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed changed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_ABUF_CMPL_TYPE_SFT 0 + /* + * RX Aggregation Buffer completion : + * Completion of an L2 aggregation buffer in support of + * TPA, HDS, or Jumbo packet completion. Length = 16B + */ + #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) + #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* - * When this bit is '1', the link was forced to the - * force_link_speed value. - */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \ - UINT32_C(0x1) - /* The new link speed in 100 Mbps units. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \ - UINT32_C(0xfffe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \ - 1 - /* 100Mb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \ - (UINT32_C(0x1) << 1) - /* 1Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \ - (UINT32_C(0xa) << 1) - /* 2Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \ - (UINT32_C(0x14) << 1) - /* 25Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \ - (UINT32_C(0x19) << 1) - /* 10Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \ - (UINT32_C(0x64) << 1) - /* 20Mb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \ - (UINT32_C(0xc8) << 1) - /* 25Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \ - (UINT32_C(0xfa) << 1) - /* 40Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \ - (UINT32_C(0x190) << 1) - /* 50Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \ - (UINT32_C(0x1f4) << 1) - /* 100Gb link speed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \ - (UINT32_C(0x3e8) << 1) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff0000) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 16 + #define RX_ABUF_CMPL_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_2; } __rte_packed; -/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_dcb_config_change { - uint16_t type; +/* VEE FLUSH Completion Record (16 bytes) */ +/* vee_flush (size:128b/16B) */ +struct vee_flush { + uint32_t downstream_path_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -4786,79 +7053,43 @@ struct hwrm_async_event_cmpl_dcb_config_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* DCB Configuration changed */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE - /* Event specific data */ - uint32_t event_data2; - /* ETS configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \ - UINT32_C(0x1) - /* PFC configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \ - UINT32_C(0x2) - /* APP configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ - UINT32_C(0x4) - uint8_t opaque_v; + #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f) + #define VEE_FLUSH_TYPE_SFT 0 + /* + * VEE Flush Completion: + * This completion is inserted manually by the Primate and processed + * by the VEE hardware to ensure that all completions on a VEE + * function have been processed by the VEE hardware before FLR + * process is completed. + */ + #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c) + #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH + /* downstream_path is 1 b */ + #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40) + /* This completion is associated with VEE Transmit */ + #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6) + /* This completion is associated with VEE Receive */ + #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6) + #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX + /* + * This is an opaque value that is passed through the completion + * to the VEE handler SW and is used to indicate what VEE VQ or + * function has completed FLR processing. + */ + uint32_t opaque; + uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 - /* Priority recommended for RoCE traffic */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \ - 16 - /* none is 255 */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \ - (UINT32_C(0xff) << 16) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE - /* Priority recommended for L2 traffic */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \ - 24 - /* none is 255 */ - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \ - (UINT32_C(0xff) << 24) - #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE + #define VEE_FLUSH_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_3; } __rte_packed; -/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_conn_not_allowed { +/* eject_cmpl (size:128b/16B) */ +struct eject_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -4867,74 +7098,80 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Port connection not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \ - UINT32_C(0x4) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define EJECT_CMPL_TYPE_SFT 0 + /* + * Statistics Ejection Completion: + * Completion of statistics data ejection buffer. + * Length = 16B + */ + #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) + #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT + #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define EJECT_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* + * This is the length of the statistics data stored in this + * buffer. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this ejection + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ - 0 + #define EJECT_CMPL_V UINT32_C(0x1) + #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define EJECT_CMPL_ERRORS_SFT 1 /* - * This value indicates the current port level enforcement policy - * for the optics module when there is an optical module mismatch - * and port is not connected. + * This error indicates that there was some sort of problem with + * the BDs for statistics ejection. The statistics ejection should + * be treated as invalid */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \ - 16 - /* No enforcement */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \ - (UINT32_C(0x0) << 16) - /* Disable Transmit side Laser. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \ - (UINT32_C(0x1) << 16) - /* Raise a warning message. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \ - (UINT32_C(0x2) << 16) - /* Power down the module. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \ - (UINT32_C(0x3) << 16) - #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Statistics did not fit into aggregation buffer provided. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ + EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH + /* reserved16 is 16 b */ + uint16_t reserved16; + /* unused3 is 32 b */ + uint32_t unused_2; } __rte_packed; -/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { +/* hwrm_cmpl (size:128b/16B) */ +struct hwrm_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -4943,52 +7180,31 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed configuration was not allowed */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ - UINT32_C(0x5) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_CMPL_TYPE_SFT 0 + /* + * HWRM Command Completion: + * Completion of an HWRM command. + */ + #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) + #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE + /* This is the sequence_id of the HWRM command that has completed. */ + uint16_t sequence_id; + /* unused2 is 32 b */ + uint32_t unused_1; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ - 0 + #define HWRM_CMPL_V UINT32_C(0x1) + /* unused4 is 32 b */ + uint32_t unused_3; } __rte_packed; -/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_link_speed_cfg_change { - uint16_t type; +/* hwrm_fwd_req_cmpl (size:128b/16B) */ +struct hwrm_fwd_req_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the @@ -4996,67 +7212,48 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link speed configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \ - UINT32_C(0x6) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + uint16_t req_len_type; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 + #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Request */ + #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) + #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ + HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ + /* Length of forwarded request in bytes. */ + #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) + #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 /* - * If set to 1, it indicates that the supported link speeds - * configuration on the port has changed. - * If set to 0, then there is no change in supported link speeds - * configuration. + * Source ID of this request. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \ - UINT32_C(0x10000) + uint16_t source_id; + /* unused1 is 32 b */ + uint32_t unused0; + /* Address of forwarded request. */ + uint32_t req_buf_addr_v[2]; /* - * If set to 1, it indicates that the link speed configuration - * on the port has become illegal or invalid. - * If set to 0, then the link speed configuration on the port is - * legal or valid. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ - UINT32_C(0x20000) + #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 } __rte_packed; -/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_port_phy_cfg_change { +/* hwrm_fwd_resp_cmpl (size:128b/16B) */ +struct hwrm_fwd_resp_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5065,74 +7262,39 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \ - 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Port PHY configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \ - UINT32_C(0x7) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; + #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Response */ + #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) + #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ + HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + /* + * Source ID of this response. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t source_id; + /* Length of forwarded response in bytes. */ + uint16_t resp_len; + /* unused2 is 16 b */ + uint16_t unused_1; + /* Address of forwarded request. */ + uint32_t resp_buf_addr_v[2]; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ - UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ - uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 0 - /* - * If set to 1, it indicates that the FEC - * configuration on the port has changed. - * If set to 0, then there is no change in FEC configuration. - */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \ - UINT32_C(0x10000) - /* - * If set to 1, it indicates that the EEE configuration - * on the port has changed. - * If set to 0, then there is no change in EEE configuration - * on the port. - */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \ - UINT32_C(0x20000) - /* - * If set to 1, it indicates that the pause configuration - * on the PHY has changed. - * If set to 0, then there is no change in the pause - * configuration on the PHY. - */ - #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ - UINT32_C(0x40000) + #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 } __rte_packed; -/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ -struct hwrm_async_event_cmpl_reset_notify { +/* hwrm_async_event_cmpl (size:128b/16B) */ +struct hwrm_async_event_cmpl { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5141,98 +7303,202 @@ struct hwrm_async_event_cmpl_reset_notify { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \ - UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notify clients of imminent reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \ - UINT32_C(0x8) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY - /* Event specific data */ - uint32_t event_data2; - uint8_t opaque_v; - /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ + UINT32_C(0x0) + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \ + UINT32_C(0x1) + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \ + UINT32_C(0x2) + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \ + UINT32_C(0x3) + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \ + UINT32_C(0x4) + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ + UINT32_C(0x5) + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \ + UINT32_C(0x6) + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \ + UINT32_C(0x7) + /* Reset notification to clients */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) + /* Master function selection event */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \ + UINT32_C(0x9) + /* + * An event signifying that a ring has been disabled by + * hw due to error. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) - /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \ + UINT32_C(0xa) + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \ + UINT32_C(0x10) + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \ + UINT32_C(0x11) + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \ + UINT32_C(0x12) + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \ + UINT32_C(0x20) + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \ + UINT32_C(0x21) + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \ + UINT32_C(0x30) + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \ + UINT32_C(0x31) + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ + UINT32_C(0x32) + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \ + UINT32_C(0x33) + /* LLFC/PFC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \ + UINT32_C(0x34) + /* Default VNIC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \ + UINT32_C(0x35) + /* HW flow aged */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \ + UINT32_C(0x36) /* - * 8-lsb timestamp (100-msec resolution) - * The Minimum time required for the Firmware readiness after sending this - * notification to the driver instances. + * A debug notification being posted to the driver. These + * notifications are purely for diagnostic purpose and should not be + * used for functional purpose. The driver is not supposed to act + * on these messages except to log/record it. */ - uint8_t timestamp_lo; + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \ + UINT32_C(0x37) /* - * 16-lsb timestamp (100-msec resolution) - * The Maximum Firmware Reset bail out value in the order of 100 - * milli seconds. The driver instances will use this value to re-initiate the - * registration process again if the core firmware didn’t set the ready - * state bit. + * An EEM flow cached memory flush for all flows request event being + * posted to the PF driver. */ - uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates driver action requested */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \ + UINT32_C(0x38) /* - * If set to 1, it indicates that the l2 client should - * stop sending in band traffic to Nitro. - * if set to 0, there is no change in L2 client behavior. + * An EEM flow cache memory flush completion event being posted to the + * firmware by the PF driver. This is indication that host EEM flush + * has completed by the PF. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \ + UINT32_C(0x39) /* - * If set to 1, it indicates that the L2 client should - * bring down the interface. - * If set to 0, then there is no change in L2 client behavior. + * A tcp flag action change event being posted to the PF or trusted VF + * driver by the firmware. The PF or trusted VF driver should query + * the firmware for the new TCP flag action update after receiving + * this async event. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN - /* Indicates reason for reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \ - 8 - /* A management client has requested reset. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \ - (UINT32_C(0x1) << 8) - /* A fatal firmware exception has occurred. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \ - (UINT32_C(0x2) << 8) - /* A non-fatal firmware exception has occurred. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ - (UINT32_C(0x3) << 8) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ + UINT32_C(0x3a) /* - * Minimum time before driver should attempt access - units 100ms ticks. - * Range 0-65535 + * An EEM flow active event being posted to the PF or trusted VF driver + * by the firmware. The PF or trusted VF driver should update the + * flow's aging timer after receiving this async event. */ - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ - UINT32_C(0xffff0000) - #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ - 16 + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \ + UINT32_C(0x3b) + /* + * A eem cfg change event being posted to the trusted VF driver by the + * firmware if the parent PF EEM configuration changed. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ + UINT32_C(0x3c) + /* + * Deprecated. + * TFLIB unique default VNIC Configuration Change + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ + UINT32_C(0x3d) + /* + * Deprecated. + * TFLIB unique link status changed + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ + UINT32_C(0x3e) + /* + * An event signifying completion for HWRM_FW_STATE_QUIESCE + * (completion, timeout, or error) + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred. This event is used on crypto controllers + * only. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + /* + * An event signifying that a PFC WatchDog configuration + * has changed on any port / cos. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + /* + * An echo request from the firmware. An echo response is expected by + * the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + /* Maximum Registrable event id. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ + UINT32_C(0x43) + /* + * A trace log message. This contains firmware trace logs string + * embedded in the asynchronous message. This is an experimental + * event, not meant for production use at this time. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \ + UINT32_C(0xfe) + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; } __rte_packed; -/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ -struct hwrm_async_event_cmpl_error_recovery { +/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_status_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5241,26 +7507,21 @@ struct hwrm_async_event_cmpl_error_recovery { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* - * This async notification message can be used for selecting or - * deselecting master function for error recovery, - * and to communicate to all the functions whether error recovery - * was enabled/disabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \ - UINT32_C(0x9) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \ + UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5269,39 +7530,54 @@ struct hwrm_async_event_cmpl_error_recovery { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 - /* 8-lsb timestamp (100-msec resolution) */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; - /* 16-lsb timestamp (100-msec resolution) */ + /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Indicates driver action requested */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \ - 0 + /* Indicates link status change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \ + UINT32_C(0x1) /* - * If set to 1, this function is selected as Master function. - * This function has responsibility to do 'chip reset' when it - * detects a fatal error. If set to 0, master function functionality - * is disabled on this function. + * If this bit set to 0, then it indicates that the link + * was up and it went down. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \ + UINT32_C(0x0) /* - * If set to 1, error recovery is enabled. - * If set to 0, error recovery is disabled. + * If this bit is set to 1, then it indicates that the link + * was down and it went up. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP + /* Indicates the physical port this link status change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \ + UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \ + 1 + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 4 + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0xff00000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ + 20 } __rte_packed; -/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_unload { +/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_mtu_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5310,21 +7586,21 @@ struct hwrm_async_event_cmpl_func_drvr_unload { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Function driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \ - UINT32_C(0x10) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5333,26 +7609,25 @@ struct hwrm_async_event_cmpl_func_drvr_unload { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + /* The new MTU of the link in bytes. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 } __rte_packed; -/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_drvr_load { +/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5361,21 +7636,21 @@ struct hwrm_async_event_cmpl_func_drvr_load { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Function driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \ - UINT32_C(0x11) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5384,24 +7659,70 @@ struct hwrm_async_event_cmpl_func_drvr_load { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ - UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* + * When this bit is '1', the link was forced to the + * force_link_speed value. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \ + UINT32_C(0x1) + /* The new link speed in 100 Mbps units. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \ + UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \ + 1 + /* 100Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \ + (UINT32_C(0x1) << 1) + /* 1Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \ + (UINT32_C(0xa) << 1) + /* 2Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \ + (UINT32_C(0x14) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \ + (UINT32_C(0x19) << 1) + /* 10Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \ + (UINT32_C(0x64) << 1) + /* 20Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \ + (UINT32_C(0xc8) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \ + (UINT32_C(0xfa) << 1) + /* 40Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \ + (UINT32_C(0x190) << 1) + /* 50Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \ + (UINT32_C(0x1f4) << 1) + /* 100Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \ + (UINT32_C(0x3e8) << 1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 16 } __rte_packed; -/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ -struct hwrm_async_event_cmpl_func_flr_proc_cmplt { +/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_dcb_config_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5410,51 +7731,79 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Function FLR related processing has completed */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \ - UINT32_C(0x12) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE /* Event specific data */ uint32_t event_data2; + /* ETS configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \ + UINT32_C(0x1) + /* PFC configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \ + UINT32_C(0x2) + /* APP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ + UINT32_C(0x4) uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Function ID */ - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 0 + /* Priority recommended for RoCE traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \ + 16 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \ + (UINT32_C(0xff) << 16) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE + /* Priority recommended for L2 traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \ + 24 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \ + (UINT32_C(0xff) << 24) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE } __rte_packed; -/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_unload { +/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_conn_not_allowed { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5463,21 +7812,22 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* PF driver unloaded */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \ - UINT32_C(0x20) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5486,28 +7836,50 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* PF ID */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 - /* Indicates the physical port this pf belongs to */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x70000) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 + /* + * This value indicates the current port level enforcement policy + * for the optics module when there is an optical module mismatch + * and port is not connected. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \ + 16 + /* No enforcement */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \ + (UINT32_C(0x0) << 16) + /* Disable Transmit side Laser. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \ + (UINT32_C(0x1) << 16) + /* Raise a warning message. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \ + (UINT32_C(0x2) << 16) + /* Power down the module. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \ + (UINT32_C(0x3) << 16) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN } __rte_packed; -/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_drvr_load { +/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5516,21 +7888,22 @@ struct hwrm_async_event_cmpl_pf_drvr_load { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* PF driver loaded */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \ - UINT32_C(0x21) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5539,28 +7912,27 @@ struct hwrm_async_event_cmpl_pf_drvr_load { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* PF ID */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 - /* Indicates the physical port this pf belongs to */ - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x70000) - #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 } __rte_packed; -/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_flr { +/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5569,20 +7941,22 @@ struct hwrm_async_event_cmpl_vf_flr { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* VF Function Level Reset (FLR) */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \ + UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5591,28 +7965,43 @@ struct hwrm_async_event_cmpl_vf_flr { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* VF ID */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 + /* + * If set to 1, it indicates that the supported link speeds + * configuration on the port has changed. + * If set to 0, then there is no change in supported link speeds + * configuration. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \ + UINT32_C(0x10000) + /* + * If set to 1, it indicates that the link speed configuration + * on the port has become illegal or invalid. + * If set to 0, then the link speed configuration on the port is + * legal or valid. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ + UINT32_C(0x20000) } __rte_packed; -/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_mac_addr_change { +/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_phy_cfg_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5621,21 +8010,22 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* VF MAC Address Change */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \ - UINT32_C(0x31) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \ + UINT32_C(0x7) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5644,27 +8034,50 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* VF ID */ - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 0 + /* + * If set to 1, it indicates that the FEC + * configuration on the port has changed. + * If set to 0, then there is no change in FEC configuration. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \ + UINT32_C(0x10000) + /* + * If set to 1, it indicates that the EEE configuration + * on the port has changed. + * If set to 0, then there is no change in EEE configuration + * on the port. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \ + UINT32_C(0x20000) + /* + * If set to 1, it indicates that the pause configuration + * on the PHY has changed. + * If set to 0, then there is no change in the pause + * configuration on the PHY. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ + UINT32_C(0x40000) } __rte_packed; -/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_pf_vf_comm_status_change { +/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ +struct hwrm_async_event_cmpl_reset_notify { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5673,54 +8086,113 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* PF-VF communication channel status change. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ - UINT32_C(0x32) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE - /* Event specific data */ + /* Notify clients of imminent reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY + /* Event specific data. The data is for internal debug use only. */ uint32_t event_data2; + /* + * These bits indicate the status as being reported by the firmware. + * This value is exactly the same as status code in fw_status register. + * If the status code is equal to 0x8000, then the reset is initiated + * by the Host using the FW_RESET command when the FW is in a healthy + * state. If the status code is not equal to 0x8000, then the reset is + * initiated by the FW to recover from the error or FATAL state. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \ + 0 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 + /* + * 8-lsb timestamp (100-msec resolution) + * The Minimum time required for the Firmware readiness after sending this + * notification to the driver instances. + */ uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ + /* + * 16-lsb timestamp (100-msec resolution) + * The Maximum Firmware Reset bail out value in the order of 100 + * milli seconds. The driver instances will use this value to re-initiate the + * registration process again if the core firmware didn’t set the ready + * state bit. + */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; + /* Indicates driver action requested */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \ + 0 /* - * If this bit is set to 1, then it indicates that the PF-VF - * communication was lost and it is established. - * If this bit set to 0, then it indicates that the PF-VF - * communication was established and it is lost. + * If set to 1, it indicates that the l2 client should + * stop sending in band traffic to Nitro. + * if set to 0, there is no change in L2 client behavior. */ - #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \ UINT32_C(0x1) + /* + * If set to 1, it indicates that the L2 client should + * bring down the interface. + * If set to 0, then there is no change in L2 client behavior. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN + /* Indicates reason for reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \ + 8 + /* A management client has requested reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \ + (UINT32_C(0x1) << 8) + /* A fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \ + (UINT32_C(0x2) << 8) + /* A non-fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ + (UINT32_C(0x3) << 8) + /* Fast reset */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ + (UINT32_C(0x4) << 8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + /* + * Minimum time before driver should attempt access - units 100ms ticks. + * Range 0-65535 + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ + 16 } __rte_packed; -/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_vf_cfg_change { +/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_recovery { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5729,21 +8201,26 @@ struct hwrm_async_event_cmpl_vf_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* VF Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \ - UINT32_C(0x33) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE + /* + * This async notification message can be used for selecting or + * deselecting master function for error recovery, + * and to communicate to all the functions whether error recovery + * was enabled/disabled. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \ + UINT32_C(0x9) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5752,60 +8229,39 @@ struct hwrm_async_event_cmpl_vf_cfg_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 - /* 8-lsb timestamp from POR (100-msec resolution) */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ uint8_t timestamp_lo; - /* 16-lsb timestamp from POR (100-msec resolution) */ + /* 16-lsb timestamp (100-msec resolution) */ uint16_t timestamp_hi; - /* - * Each flag provided in this field indicates a specific VF - * configuration change. At least one of these flags shall be set to 1 - * when an asynchronous event completion of this type is provided - * by the HWRM. - */ + /* Event specific data */ uint32_t event_data1; + /* Indicates driver action requested */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \ + 0 /* - * If this bit is set to 1, then the value of MTU - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * If set to 1, this function is selected as Master function. + * This function has responsibility to do 'chip reset' when it + * detects a fatal error. If set to 0, master function functionality + * is disabled on this function. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \ UINT32_C(0x1) /* - * If this bit is set to 1, then the value of MRU - * was changed on this VF. - * If set to 0, then this bit should be ignored. + * If set to 1, error recovery is enabled. + * If set to 0, error recovery is disabled. */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ UINT32_C(0x2) - /* - * If this bit is set to 1, then the value of default MAC - * address was changed on this VF. - * If set to 0, then this bit should be ignored. - */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \ - UINT32_C(0x4) - /* - * If this bit is set to 1, then the value of default VLAN - * was changed on this VF. - * If set to 0, then this bit should be ignored. - */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ - UINT32_C(0x8) - /* - * If this bit is set to 1, then the value of trusted VF enable - * was changed on this VF. - * If set to 0, then this bit should be ignored. - */ - #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ - UINT32_C(0x10) } __rte_packed; -/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_llfc_pfc_change { +/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ +struct hwrm_async_event_cmpl_ring_monitor_msg { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5814,77 +8270,63 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* unused1 is 10 b */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \ - UINT32_C(0xffc0) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6 + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* LLFC/PFC Configuration Change */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \ - UINT32_C(0x34) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE + /* Ring Monitor Message. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \ + UINT32_C(0xa) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG /* Event specific data */ uint32_t event_data2; + /* Type of Ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \ + 0 + /* tx ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \ + UINT32_C(0x0) + /* rx ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \ + UINT32_C(0x1) + /* cmpl ring disabled. */ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; - /* Event specific data */ - uint32_t event_data1; - /* Indicates llfc pfc status change */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \ - 0 - /* - * If this field set to 1, then it indicates that llfc is - * enabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \ - UINT32_C(0x1) /* - * If this field is set to 2, then it indicates that pfc - * is enabled. + * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl + * then this field will indicate the ring id. */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \ - HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC - /* Indicates the physical port this llfc pfc change occur */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \ - UINT32_C(0x1c) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \ - 2 - /* PORT ID */ - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \ - UINT32_C(0x1fffe0) - #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ - 5 + uint32_t event_data1; } __rte_packed; -/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_default_vnic_change { +/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_unload { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5893,27 +8335,21 @@ struct hwrm_async_event_cmpl_default_vnic_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT - /* unused1 is 10 b */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \ - UINT32_C(0xffc0) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \ - 6 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of a default vnic allocation or free */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ - UINT32_C(0x35) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \ + UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5922,51 +8358,26 @@ struct hwrm_async_event_cmpl_default_vnic_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Indicates default vnic configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \ - UINT32_C(0x3) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \ + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ 0 - /* - * If this field is set to 1, then it indicates that - * a default VNIC has been allocate. - */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \ - UINT32_C(0x1) - /* - * If this field is set to 2, then it indicates that - * a default VNIC has been freed. - */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \ - HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE - /* Indicates the physical function this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \ - UINT32_C(0x3fc) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \ - 2 - /* Indicates the virtual function this event occurred on */ - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \ - UINT32_C(0x3fffc00) - #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ - 10 } __rte_packed; -/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ -struct hwrm_async_event_cmpl_hw_flow_aged { +/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_load { uint16_t type; /* * This field indicates the exact type of the completion. @@ -5975,21 +8386,21 @@ struct hwrm_async_event_cmpl_hw_flow_aged { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of a hw flow aged */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \ - UINT32_C(0x36) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \ + UINT32_C(0x11) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -5998,42 +8409,24 @@ struct hwrm_async_event_cmpl_hw_flow_aged { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Indicates flow ID this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \ - UINT32_C(0x7fffffff) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \ - 0 - /* Indicates flow direction this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \ - UINT32_C(0x80000000) - /* - * If this bit set to 0, then it indicates that the aged - * event was rx flow. - */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 31) - /* - * If this bit is set to 1, then it indicates that the aged - * event was tx flow. - */ - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 } __rte_packed; -/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_req { +/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_flr_proc_cmplt { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6042,22 +8435,22 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \ 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of a eem_cache_flush request */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \ - UINT32_C(0x38) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \ + UINT32_C(0x12) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -6066,22 +8459,27 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \ UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ + 0 } __rte_packed; -/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cache_flush_done { +/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_unload { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6090,25 +8488,21 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* - * Notification of a host eem_cache_flush has completed. This event - * is generated by the host driver. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \ - UINT32_C(0x39) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \ + UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -6117,27 +8511,28 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Indicates function ID that this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \ + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ UINT32_C(0xffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 } __rte_packed; -/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_tcp_flag_action_change { +/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_load { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6146,22 +8541,21 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \ - 0 + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of tcp flag action change */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ - UINT32_C(0x3a) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \ + UINT32_C(0x21) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -6170,22 +8564,28 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ - UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 } __rte_packed; -/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_flow_active { +/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_flr { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6194,98 +8594,50 @@ struct hwrm_async_event_cmpl_eem_flow_active { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of an active eem flow */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \ - UINT32_C(0x3b) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR /* Event specific data */ uint32_t event_data2; - /* Indicates the 2nd global id this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \ - 0 - /* - * Indicates flow direction of the flow identified by - * the global_id_2. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \ - UINT32_C(0x40000000) - /* If this bit is set to 0, then it indicates that this rx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 30) - /* If this bit is set to 1, then it indicates that this tx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 30) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Indicates the 1st global id this event occurred on. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \ - 0 - /* - * Indicates flow direction of the flow identified by the - * global_id_1. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \ - UINT32_C(0x40000000) - /* If this bit is set to 0, then it indicates that this is rx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \ - (UINT32_C(0x0) << 30) - /* If this bit is set to 1, then it indicates that this is tx flow. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \ - (UINT32_C(0x1) << 30) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX - /* - * Indicates EEM flow aging mode this event occurred on. If - * this bit is set to 0, the event_data1 is the EEM global - * ID. If this bit is set to 1, the event_data1 is the number - * of global ID in the context memory. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \ - UINT32_C(0x80000000) - /* EEM flow aging mode 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \ - (UINT32_C(0x0) << 31) - /* EEM flow aging mode 1. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \ - (UINT32_C(0x1) << 31) - #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 } __rte_packed; -/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ -struct hwrm_async_event_cmpl_eem_cfg_change { +/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_mac_addr_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6294,21 +8646,21 @@ struct hwrm_async_event_cmpl_eem_cfg_change { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* Notification of EEM configuration change */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \ - UINT32_C(0x3c) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \ + UINT32_C(0x31) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE /* Event specific data */ uint32_t event_data2; uint8_t opaque_v; @@ -6317,32 +8669,27 @@ struct hwrm_async_event_cmpl_eem_cfg_change { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* - * Value of 1 to indicate EEM TX configuration is enabled. Value of - * 0 to indicate the EEM TX configuration is disabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \ - UINT32_C(0x1) - /* - * Value of 1 to indicate EEM RX configuration is enabled. Value of 0 - * to indicate the EEM RX configuration is disabled. - */ - #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ - UINT32_C(0x2) + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ + 0 } __rte_packed; -/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ -struct hwrm_async_event_cmpl_quiesce_done { +/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_vf_comm_status_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6351,71 +8698,139 @@ struct hwrm_async_event_cmpl_quiesce_done { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT /* Identifiers of events. */ uint16_t event_id; - /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ - UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ + UINT32_C(0x32) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE /* Event specific data */ uint32_t event_data2; - /* Status of HWRM_FW_STATE_QUIESCE completion */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ - 0 + uint8_t opaque_v; /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE - * completed successfully. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ - UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed - * out. + * If this bit is set to 1, then it indicates that the PF-VF + * communication was lost and it is established. + * If this bit set to 0, then it indicates that the PF-VF + * communication was established and it is lost. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_cfg_change { + uint16_t type; /* - * The quiesce operation started by HWRM_FW_STATE_QUIESCE - * encountered an error. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ - HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \ + UINT32_C(0x33) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; - /* Event specific data */ + /* + * Each flag provided in this field indicates a specific VF + * configuration change. At least one of these flags shall be set to 1 + * when an asynchronous event completion of this type is provided + * by the HWRM. + */ uint32_t event_data1; - /* Time stamp for error event */ - #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + /* + * If this bit is set to 1, then the value of MTU + * was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \ UINT32_C(0x1) + /* + * If this bit is set to 1, then the value of MRU + * was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \ + UINT32_C(0x2) + /* + * If this bit is set to 1, then the value of default MAC + * address was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \ + UINT32_C(0x4) + /* + * If this bit is set to 1, then the value of default VLAN + * was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ + UINT32_C(0x8) + /* + * If this bit is set to 1, then the value of trusted VF enable + * was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ + UINT32_C(0x10) } __rte_packed; -/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ -struct hwrm_async_event_cmpl_fw_trace_msg { +/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_llfc_pfc_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6424,105 +8839,77 @@ struct hwrm_async_event_cmpl_fw_trace_msg { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* unused1 is 10 b */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \ + UINT32_C(0xffc0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6 /* Identifiers of events. */ uint16_t event_id; - /* Firmware trace log message */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \ - UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG - /* Trace byte 0 to 3 */ + /* LLFC/PFC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \ + UINT32_C(0x34) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE + /* Event specific data */ uint32_t event_data2; - /* Trace byte0 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0 - /* Trace byte1 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8 - /* Trace byte2 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16 - /* Trace byte3 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24 uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1 - /* Trace flags */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; - /* Indicates if the string is partial or complete. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \ - UINT32_C(0x1) - /* Complete string */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \ - UINT32_C(0x0) - /* Partial string */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \ - UINT32_C(0x1) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL - /* Indicates the firmware that sent the trace message. */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \ - UINT32_C(0x2) - /* Primary firmware */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \ - (UINT32_C(0x0) << 1) - /* Secondary firmware */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \ - (UINT32_C(0x1) << 1) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \ - HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY - /* Trace byte 4 to 5 */ + /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; - /* Trace byte4 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0 - /* Trace byte5 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8 - /* Trace byte 6 to 9 */ + /* Event specific data */ uint32_t event_data1; - /* Trace byte6 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0 - /* Trace byte7 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \ - UINT32_C(0xff00) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8 - /* Trace byte8 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \ - UINT32_C(0xff0000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16 - /* Trace byte9 */ - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ - UINT32_C(0xff000000) - #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 + /* Indicates llfc pfc status change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \ + 0 + /* + * If this field set to 1, then it indicates that llfc is + * enabled. + */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \ + UINT32_C(0x1) + /* + * If this field is set to 2, then it indicates that pfc + * is enabled. + */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC + /* Indicates the physical port this llfc pfc change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x1c) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \ + 2 + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0x1fffe0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 5 } __rte_packed; -/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ -struct hwrm_async_event_cmpl_hwrm_error { +/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_default_vnic_change { uint16_t type; /* * This field indicates the exact type of the completion. @@ -6531,1027 +8918,1474 @@ struct hwrm_async_event_cmpl_hwrm_error { * records. Odd values indicate 32B * records. */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \ + 0 /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* unused1 is 10 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \ + UINT32_C(0xffc0) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \ + 6 /* Identifiers of events. */ uint16_t event_id; - /* HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR + /* Notification of a default vnic allocation or free */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ + UINT32_C(0x35) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION /* Event specific data */ uint32_t event_data2; - /* Severity of HWRM Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \ - UINT32_C(0xff) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 - /* Warning */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \ - UINT32_C(0x0) - /* Non-fatal Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \ - UINT32_C(0x1) - /* Fatal Error */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \ - UINT32_C(0x2) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \ - HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL uint8_t opaque_v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ + UINT32_C(0x1) /* opaque is 7 b */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 /* 8-lsb timestamp from POR (100-msec resolution) */ uint8_t timestamp_lo; /* 16-lsb timestamp from POR (100-msec resolution) */ uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; - /* Time stamp for error event */ - #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ + /* Indicates default vnic configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \ + 0 + /* + * If this field is set to 1, then it indicates that + * a default VNIC has been allocate. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \ UINT32_C(0x1) -} __rte_packed; - -/******************* - * hwrm_func_reset * - *******************/ - - -/* hwrm_func_reset_input (size:192b/24B) */ -struct hwrm_func_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * If this field is set to 2, then it indicates that + * a default VNIC has been freed. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE + /* Indicates the physical function this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \ + UINT32_C(0x3fc) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \ + 2 + /* Indicates the virtual function this event occurred on */ + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0x3fffc00) + #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ + 10 +} __rte_packed; + +/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ +struct hwrm_async_event_cmpl_hw_flow_aged { + uint16_t type; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of a hw flow aged */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \ + UINT32_C(0x36) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates flow ID this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \ + UINT32_C(0x7fffffff) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \ + 0 + /* Indicates flow direction this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \ + UINT32_C(0x80000000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If this bit set to 0, then it indicates that the aged + * event was rx flow. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 31) /* - * This bit must be '1' for the vf_id_valid field to be - * configured. + * If this bit is set to 1, then it indicates that the aged + * event was tx flow. */ - #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cache_flush_req { + uint16_t type; /* - * The ID of the VF that this PF is trying to reset. - * Only the parent PF shall be allowed to reset a child VF. - * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t vf_id; - /* This value indicates the level of a function reset. */ - uint8_t func_reset_level; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of a eem_cache_flush request */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \ + UINT32_C(0x38) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * Reset the caller function and its children VFs (if any). If no - * children functions exist, then reset the caller function only. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ - UINT32_C(0x0) - /* Reset the caller function only */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cache_flush_done { + uint16_t type; /* - * Reset all children VFs of the caller function driver if the - * caller is a PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver with - * no children VFs. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * Reset a specific VF of the caller function driver if the caller - * is the parent PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver that is not - * the parent of the VF that is being requested to reset. + * Notification of a host eem_cache_flush has completed. This event + * is generated by the host driver. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ - UINT32_C(0x3) - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ - HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF - uint8_t unused_0; -} __rte_packed; - -/* hwrm_func_reset_output (size:128b/16B) */ -struct hwrm_func_reset_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \ + UINT32_C(0x39) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates function ID that this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ + 0 } __rte_packed; -/******************** - * hwrm_func_getfid * - ********************/ - - -/* hwrm_func_getfid_input (size:192b/24B) */ -struct hwrm_func_getfid_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_tcp_flag_action_change { + uint16_t type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of tcp flag action change */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \ + UINT32_C(0x3a) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_flow_active { + uint16_t type; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of an active eem flow */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \ + UINT32_C(0x3b) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE + /* Event specific data */ + uint32_t event_data2; + /* Indicates the 2nd global id this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \ + 0 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Indicates flow direction of the flow identified by + * the global_id_2. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \ + UINT32_C(0x40000000) + /* If this bit is set to 0, then it indicates that this rx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 30) + /* If this bit is set to 1, then it indicates that this tx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 30) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX + uint8_t opaque_v; /* - * This bit must be '1' for the pci_id field to be - * configured. - */ - #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) - /* - * This value is the PCI ID of the queried function. - * If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (5b):Function Number(3b). + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t pci_id; - uint8_t unused_0[2]; -} __rte_packed; - -/* hwrm_func_getfid_output (size:128b/16B) */ -struct hwrm_func_getfid_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the 1st global id this event occurred on. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \ + 0 /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * Indicates flow direction of the flow identified by the + * global_id_1. */ - uint16_t fid; - uint8_t unused_0[5]; + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \ + UINT32_C(0x40000000) + /* If this bit is set to 0, then it indicates that this is rx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \ + (UINT32_C(0x0) << 30) + /* If this bit is set to 1, then it indicates that this is tx flow. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \ + (UINT32_C(0x1) << 30) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Indicates EEM flow aging mode this event occurred on. If + * this bit is set to 0, the event_data1 is the EEM global + * ID. If this bit is set to 1, the event_data1 is the number + * of global ID in the context memory. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \ + UINT32_C(0x80000000) + /* EEM flow aging mode 0. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \ + (UINT32_C(0x0) << 31) + /* EEM flow aging mode 1. */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \ + (UINT32_C(0x1) << 31) + #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 } __rte_packed; -/********************** - * hwrm_func_vf_alloc * - **********************/ - - -/* hwrm_func_vf_alloc_input (size:192b/24B) */ -struct hwrm_func_vf_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; +/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_eem_cfg_change { + uint16_t type; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notification of EEM configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \ + UINT32_C(0x3c) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the first_vf_id field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * Value of 1 to indicate EEM TX configuration is enabled. Value of + * 0 to indicate the EEM TX configuration is disabled. */ - uint16_t first_vf_id; - /* The number of virtual functions requested. */ - uint16_t num_vfs; -} __rte_packed; - -/* hwrm_func_vf_alloc_output (size:128b/16B) */ -struct hwrm_func_vf_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The ID of the first VF allocated. */ - uint16_t first_vf_id; - uint8_t unused_0[5]; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \ + UINT32_C(0x1) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Value of 1 to indicate EEM RX configuration is enabled. Value of 0 + * to indicate the EEM RX configuration is disabled. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ + UINT32_C(0x2) } __rte_packed; -/********************* - * hwrm_func_vf_free * - *********************/ - - -/* hwrm_func_vf_free_input (size:192b/24B) */ -struct hwrm_func_vf_free_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_quiesce_done { + uint16_t type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* Event specific data */ + uint32_t event_data2; + /* Status of HWRM_FW_STATE_QUIESCE completion */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ + 0 /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * completed successfully. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ + UINT32_C(0x0) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed + * out. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + UINT32_C(0x1) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * encountered an error. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + /* opaque is 8 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ + 8 /* - * This bit must be '1' for the first_vf_id field to be - * configured. + * Additional information about internal hardware state related to + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may + * inspect idle_state_flags to determine whether a retry is warranted. */ - #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ + 16 /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * Failure to quiesce is caused by host not updating the NQ consumer + * index. */ - uint16_t first_vf_id; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ + UINT32_C(0x10000) + /* Flag 1 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ + UINT32_C(0x20000) + /* Flag 2 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ + UINT32_C(0x40000) + /* Flag 3 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ + UINT32_C(0x80000) + uint8_t opaque_v; /* - * The number of virtual functions requested. - * 0xFFFF - Cleanup all children of this PF. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t num_vfs; + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) } __rte_packed; -/* hwrm_func_vf_free_output (size:128b/16B) */ -struct hwrm_func_vf_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ +struct hwrm_async_event_cmpl_deferred_response { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __rte_packed; - -/******************** - * hwrm_func_vf_cfg * - ********************/ - - -/* hwrm_func_vf_cfg_input (size:448b/56B) */ -struct hwrm_func_vf_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * An event signifying a HWRM command is in progress and its + * response will be deferred */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE + /* Event specific data */ + uint32_t event_data2; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The PF's mailbox is clear to issue another command. + * A command with this seq_id is still in progress + * and will return a regular HWRM completion when done. + * 'event_data1' field, if non-zero, contains the estimated + * execution time for the command. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ + 0 + uint8_t opaque_v; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Estimated remaining time of command execution in ms (if not zero) */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { + uint16_t type; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PFC watchdog configuration change for given port/cos */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the mtu field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * This bit must be '1' for the guest_vlan field to be - * configured. + * 1 in bit position X indicates PFC watchdog should + * be on for COSX */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ + 0 + /* 1 means PFC WD for COS0 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + UINT32_C(0x1) + /* 1 means PFC WD for COS1 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ UINT32_C(0x2) - /* - * This bit must be '1' for the async_event_cr field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + /* 1 means PFC WD for COS2 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ UINT32_C(0x4) - /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + /* 1 means PFC WD for COS3 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ UINT32_C(0x8) - /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + /* 1 means PFC WD for COS4 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ UINT32_C(0x10) - /* - * This bit must be '1' for the num_cmpl_rings field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + /* 1 means PFC WD for COS5 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ UINT32_C(0x20) - /* - * This bit must be '1' for the num_tx_rings field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + /* 1 means PFC WD for COS6 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ UINT32_C(0x40) - /* - * This bit must be '1' for the num_rx_rings field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + /* 1 means PFC WD for COS7 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ UINT32_C(0x80) + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff00) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 8 +} __rte_packed; + +/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ +struct hwrm_async_event_cmpl_echo_request { + uint16_t type; /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ - UINT32_C(0x100) - /* - * This bit must be '1' for the num_vnics field to be - * configured. - */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ - UINT32_C(0x200) - /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ - UINT32_C(0x400) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. + * An echo request from the firmware. An echo response is expected by + * the firmware. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x800) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \ + UINT32_C(0x42) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST + /* Event specific data that should be provided in the echo response */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The maximum transmission unit requested on the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to requesting mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t mtu; + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data that should be provided in the echo response */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ +struct hwrm_async_event_cmpl_fw_trace_msg { + uint16_t type; /* - * The guest VLAN for the function being configured. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t guest_vlan; - /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. - */ - uint16_t async_event_cr; - /* - * This value is the current MAC address requested by the VF - * driver to be configured on this VF. A value of - * 00-00-00-00-00-00 indicates no MAC address configuration - * is requested by the VF driver. - * The parent PF driver may reject or overwrite this - * MAC address. - */ - uint8_t dflt_mac_addr[6]; - uint32_t flags; + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Firmware trace log message */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG + /* Trace byte 0 to 3 */ + uint32_t event_data2; + /* Trace byte0 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0 + /* Trace byte1 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8 + /* Trace byte2 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16 + /* Trace byte3 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24 + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1 + /* Trace flags */ + uint8_t timestamp_lo; + /* Indicates if the string is partial or complete. */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \ UINT32_C(0x1) - /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. - */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + /* Complete string */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \ + UINT32_C(0x0) + /* Partial string */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL + /* Indicates the firmware that sent the trace message. */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \ UINT32_C(0x2) + /* Primary firmware */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \ + (UINT32_C(0x0) << 1) + /* Secondary firmware */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \ + (UINT32_C(0x1) << 1) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY + /* Trace byte 4 to 5 */ + uint16_t timestamp_hi; + /* Trace byte4 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0 + /* Trace byte5 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8 + /* Trace byte 6 to 9 */ + uint32_t event_data1; + /* Trace byte6 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0 + /* Trace byte7 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8 + /* Trace byte8 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16 + /* Trace byte9 */ + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 +} __rte_packed; + +/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_hwrm_error { + uint16_t type; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. - */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ - UINT32_C(0x4) - /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ - UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Severity of HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 + /* Warning */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \ + UINT32_C(0x0) + /* Non-fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \ + UINT32_C(0x1) + /* Fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ - UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __rte_packed; + +/* metadata_base_msg (size:64b/8B) */ +struct metadata_base_msg { + uint16_t md_type_link; + /* This field classifies the data present in the meta-data. */ + #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f) + #define METADATA_BASE_MSG_MD_TYPE_SFT 0 + /* Meta data fields are not valid */ + #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ - UINT32_C(0x20) + #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ - UINT32_C(0x40) + #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2) + #define METADATA_BASE_MSG_MD_TYPE_LAST \ + METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ - UINT32_C(0x80) - /* The number of RSS/COS contexts requested for the VF. */ - uint16_t num_rsscos_ctxs; - /* The number of completion rings requested for the VF. */ - uint16_t num_cmpl_rings; - /* The number of transmit rings requested for the VF. */ - uint16_t num_tx_rings; - /* The number of receive rings requested for the VF. */ - uint16_t num_rx_rings; - /* The number of L2 contexts requested for the VF. */ - uint16_t num_l2_ctxs; - /* The number of vnics requested for the VF. */ - uint16_t num_vnics; - /* The number of statistic contexts requested for the VF. */ - uint16_t num_stat_ctxs; - /* The number of HW ring groups requested for the VF. */ - uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0) + #define METADATA_BASE_MSG_LINK_SFT 5 + uint16_t unused0; + uint32_t unused1; } __rte_packed; -/* hwrm_func_vf_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* tls_metadata_base_msg (size:64b/8B) */ +struct tls_metadata_base_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0 /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. */ - uint8_t valid; -} __rte_packed; - -/******************* - * hwrm_func_qcaps * - *******************/ - - -/* hwrm_func_qcaps_input (size:192b/24B) */ -struct hwrm_func_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \ + UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. */ - uint16_t cmpl_ring; + #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \ + UINT32_C(0x2) + #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \ + TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - uint16_t seq_id; + #define TLS_METADATA_BASE_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_BASE_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_BASE_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9 /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - uint16_t target_id; + #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \ + UINT32_C(0x200) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - uint64_t resp_addr; + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10 /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This enumeration states that the ghash is not valid in the + * meta-data. */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_qcaps_output (size:640b/80B) */ -struct hwrm_func_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * This enumeration indicates that this pkt contains the record's + * tag and this pkt was received ooo, the partial_ghash field + * contains the ghash. */ - uint16_t fid; + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \ + (UINT32_C(0x1) << 10) /* - * Port ID of port that this function is associated with. - * Valid only for the PF. - * 0xFF... (All Fs) if this function is not associated with - * any port. - * 0xFF... (All Fs) if this function is called from a VF. + * This enumeration indicates that the current record's tag wasn't + * seen and the chip is moving on to the next record, the + * partial_ghash field contains the ghash. */ - uint16_t port_id; - uint32_t flags; - /* If 1, then Push mode is supported on this function. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ - UINT32_C(0x1) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \ + (UINT32_C(0x2) << 10) + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * If 1, then the global MSI-X auto-masking is enabled for the - * device. + * This enumeration is set when there is no tags present in the + * packet. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ - UINT32_C(0x2) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) /* - * If 1, then the Precision Time Protocol (PTP) processing - * is supported on this function. - * The HWRM should enable PTP on only a single Physical - * Function (PF) per port. + * This enumeration states that there is at least one tag in the + * packet and every tag is valid. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ - UINT32_C(0x4) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \ + (UINT32_C(0x1) << 12) /* - * If 1, then RDMA over Converged Ethernet (RoCE) v1 - * is supported on this function. + * This enumeration states that there is at least one tag in the + * packet and at least one of the tag is invalid. The entire packet + * is sent decrypted to the host. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ - UINT32_C(0x8) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \ + (UINT32_C(0x2) << 12) + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE /* - * If 1, then RDMA over Converged Ethernet (RoCE) v2 - * is supported on this function. + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ - UINT32_C(0x10) + #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \ + UINT32_C(0x4000) /* - * If 1, then control and configuration of WoL magic packet - * are supported on this function. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ - UINT32_C(0x20) + #define TLS_METADATA_BASE_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * If 1, then control and configuration of bitmap pattern - * packet are supported on this function. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ - UINT32_C(0x40) + #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0 + uint16_t unused0; +} __rte_packed; + +/* tls_metadata_insync_msg (size:192b/24B) */ +struct tls_metadata_insync_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0 /* - * If set to 1, then the control and configuration of rate limit - * of an allocated TX ring on the queried function is supported. + * This setting is used when packets are coming in-order. Depending on + * the state of the receive context, the meta-data will carry different + * information. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ - UINT32_C(0x80) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \ + UINT32_C(0x1) + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \ + TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC /* - * If 1, then control and configuration of minimum and - * maximum bandwidths are supported on the queried function. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ - UINT32_C(0x100) + #define TLS_METADATA_INSYNC_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9 /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the rate limits - * on the TX rings of its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the rate limits - * on the TX rings of its children VFs. + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ + #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \ UINT32_C(0x200) /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the minimum and/or - * maximum bandwidths for its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the minimum or - * maximum bandwidths for its children VFs. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ - UINT32_C(0x400) - /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is supported - * on the queried function. - * If set to 0, then standard TX ring mode is not available - * on the queried function. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ - UINT32_C(0x800) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10 /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GENEVE tunnel - * flags. + * This enumeration states that the ghash is not valid in the + * meta-data. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x1000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect NVGRE tunnel - * flags. + * This enumeration indicates that this pkt contains the record's + * tag and this pkt was received ooo, the partial_ghash field + * contains the ghash. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x2000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \ + (UINT32_C(0x1) << 10) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GRE tunnel - * flags. + * This enumeration indicates that the current record's tag wasn't + * seen and the chip is moving on to the next record, the + * partial_ghash field contains the ghash. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x4000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \ + (UINT32_C(0x2) << 10) + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect MPLS tunnel - * flags. + * This enumeration is set when there is no tags present in the + * packet. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x8000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to support pcie stats. + * This enumeration states that there is at least one tag in the + * packet and every tag is valid. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ - UINT32_C(0x10000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \ + (UINT32_C(0x1) << 12) /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to adopt the VF's belonging - * to another PF. + * This enumeration states that there is at least one tag in the + * packet and at least one of the tag is invalid. The entire packet + * is sent decrypted to the host. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \ - UINT32_C(0x20000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \ + (UINT32_C(0x2) << 12) + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the administrative privilege to configure another PF + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ - UINT32_C(0x40000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \ + UINT32_C(0x4000) /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then - * the PF will know that the firmware has the capability to track - * the virtual link status. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \ - UINT32_C(0x80000) + #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * If 1, then this function supports the push mode that uses - * write combine buffers and the long inline tx buffer descriptor. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \ - UINT32_C(0x100000) + #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0 /* - * If 1, then FW has capability to allocate TX rings dynamically - * in ring alloc even if PF reserved pool is zero. - * This bit will be used only for PFs. + * This field is only valid when md_type is set to tls_insync. This field + * indicates the offset within the current TCP packet where the TLS header + * starts. If there are multiple TLS headers in the packet, this provides + * the offset of the last TLS header. + * + * The field is calculated by subtracting TCP sequence number of the first + * byte of the TCP payload of the packet from the TCP sequence number of + * the last TLS header in the packet. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ - UINT32_C(0x200000) + uint16_t tls_header_offset; /* - * When this bit is '1', it indicates that core firmware is - * capable of Hot Reset. + * This is the sequence Number of the record that was processed by the HW. + * If there are multiple records in a packet, this would be the sequence + * number of the last record. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \ - UINT32_C(0x400000) + uint64_t record_seq_num; /* - * This flag will be set to 1 by the FW if FW supports adapter error - * recovery. + * This field contains cumulative partial GHASH value of all the packets + * decrypted by the HW associated with a TLS record. This field is valid + * on when packets belonging to have arrived out-of-order and HW could + * not decrypt every packet and authenticate the record. Partial GHASH is + * only sent out with packet having the TAG field. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \ - UINT32_C(0x800000) + uint64_t partial_ghash; +} __rte_packed; + +/* tls_metadata_resync_msg (size:256b/32B) */ +struct tls_metadata_resync_msg { + uint32_t md_type_link_flags_kid_lo; + /* This field classifies the data present in the meta-data. */ + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \ + UINT32_C(0x1f) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0 /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then - * the PF has the capability to support extended stats. + * With this setting HW passes the TCP sequence number of the TLS + * record that it is requesting a resync on in the meta data. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \ - UINT32_C(0x1000000) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \ + UINT32_C(0x2) + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \ + TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, then host - * must initiate reset or reload (or fastboot) the firmware image - * upon detection of device shutdown state. + * This field indicates where the next metadata block starts. It is + * counted in 16B units. A value of zero indicates that there is no + * metadata. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ - UINT32_C(0x2000000) + #define TLS_METADATA_RESYNC_MSG_LINK_MASK \ + UINT32_C(0x1e0) + #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5 + /* These are flags present in the metadata. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \ + UINT32_C(0x1fffe00) + #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9 /* - * If the query is for a VF, then this flag (always set to 0) shall - * be ignored. If this query is for a PF and this flag is set to 1, - * host, when registered for the default vnic change async event, - * receives async notification whenever a default vnic state is - * changed for any of child or adopted VFs. + * A value of 1 implies that the packet was decrypted by HW. Otherwise + * the packet is passed on as it came in on the wire. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ - UINT32_C(0x4000000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \ + UINT32_C(0x200) /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. + * This field indicates the state of the ghash field passed in the + * meta-data. */ - uint8_t mac_address[6]; + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \ + UINT32_C(0xc00) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10 /* - * The maximum number of RSS/COS contexts that can be - * allocated to the function. + * This enumeration states that the ghash is not valid in the + * meta-data. */ - uint16_t max_rsscos_ctx; + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \ + (UINT32_C(0x0) << 10) + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID + /* This field indicates the status of tag authentication. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ + UINT32_C(0x3000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 /* - * The maximum number of completion rings that can be - * allocated to the function. + * This enumeration is set when there is no tags present in the + * packet. */ - uint16_t max_cmpl_rings; + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + (UINT32_C(0x0) << 12) + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE /* - * The maximum number of transmit rings that can be - * allocated to the function. + * A value of 1 indicates that this packet contains a record that + * starts in the packet and extends beyond the packet. */ - uint16_t max_tx_rings; + #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \ + UINT32_C(0x4000) /* - * The maximum number of receive rings that can be - * allocated to the function. + * This value indicates the lower 7-bit of the Crypto Key ID + * associated with this operation. */ - uint16_t max_rx_rings; + #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \ + UINT32_C(0xfe000000) + #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25 + uint16_t kid_hi; /* - * The maximum number of L2 contexts that can be - * allocated to the function. + * This value indicates the upper 13-bit of the Crypto Key ID + * associated with this operation. */ - uint16_t max_l2_ctxs; + #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) + #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0 + /* This field is unused in this context. */ + uint16_t metadata_0; /* - * The maximum number of VNICs that can be - * allocated to the function. + * This field indicates the TCP sequence number of the TLS record that HW + * is requesting a resync on from the Driver. HW will keep a count of the + * TLS records it found after this record (delta_records). Driver will + * provide the TLS Record Sequence Number associated with the record. HW + * will add the delta_records to the Record Sequence Number provided by + * the driver and get back on sync. */ - uint16_t max_vnics; + uint32_t resync_record_tcp_seq_num; + uint32_t unused0; + /* This field is unused in this context. */ + uint64_t metadata_2; + /* This field is unused in this context. */ + uint64_t metadata_3; +} __rte_packed; + +/******************* + * hwrm_func_reset * + *******************/ + + +/* hwrm_func_reset_input (size:192b/24B) */ +struct hwrm_func_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The identifier for the first VF enabled on a PF. This - * is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t first_vf_id; + uint16_t cmpl_ring; /* - * The maximum number of VFs that can be - * allocated to the function. This is valid only on the - * PF with SR-IOV enabled. 0xFF... (All Fs) if this - * command is called on a PF with SR-IOV disabled or - * on a VF. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_vfs; + uint16_t seq_id; /* - * The maximum number of statistic contexts that can be - * allocated to the function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t max_stat_ctx; + uint16_t target_id; /* - * The maximum number of Encapsulation records that can be - * offloaded by this function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t max_encap_records; + uint64_t resp_addr; + uint32_t enables; /* - * The maximum number of decapsulation records that can - * be offloaded by this function. + * This bit must be '1' for the vf_id_valid field to be + * configured. */ - uint32_t max_decap_records; + #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the TX side. + * The ID of the VF that this PF is trying to reset. + * Only the parent PF shall be allowed to reset a child VF. + * + * A parent PF driver shall use this field only when a specific child VF + * is requested to be reset. */ - uint32_t max_tx_em_flows; + uint16_t vf_id; + /* This value indicates the level of a function reset. */ + uint8_t func_reset_level; /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the TX side. + * Reset the caller function and its children VFs (if any). If no + * children functions exist, then reset the caller function only. */ - uint32_t max_tx_wm_flows; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ + UINT32_C(0x0) + /* Reset the caller function only */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ + UINT32_C(0x1) /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the RX side. + * Reset all children VFs of the caller function driver if the + * caller is a PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver with + * no children VFs. */ - uint32_t max_rx_em_flows; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ + UINT32_C(0x2) /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the RX side. + * Reset a specific VF of the caller function driver if the caller + * is the parent PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver that is not + * the parent of the VF that is being requested to reset. */ - uint32_t max_rx_wm_flows; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ + UINT32_C(0x3) + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ + HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF + uint8_t unused_0; +} __rte_packed; + +/* hwrm_func_reset_output (size:128b/16B) */ +struct hwrm_func_reset_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * The maximum number of multicast filters that can - * be supported by this function on the RX side. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t max_mcast_filters; + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_func_getfid * + ********************/ + + +/* hwrm_func_getfid_input (size:192b/24B) */ +struct hwrm_func_getfid_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The maximum value of flow_id that can be supported - * in completion records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t max_flow_id; + uint16_t cmpl_ring; /* - * The maximum number of HW ring groups that can be - * supported on this function. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t max_hw_ring_grps; + uint16_t seq_id; /* - * The maximum number of strict priority transmit rings - * that can be allocated to the function. - * This number indicates the maximum number of TX rings - * that can be assigned strict priorities out of the - * maximum number of TX rings that can be allocated - * (max_tx_rings) to the function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t max_sp_tx_rings; - uint8_t unused_0; + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the pci_id field to be + * configured. + */ + #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) + /* + * This value is the PCI ID of the queried function. + * If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (5b):Function Number(3b). + */ + uint16_t pci_id; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_getfid_output (size:128b/16B) */ +struct hwrm_func_getfid_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. + */ + uint16_t fid; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7562,13 +10396,13 @@ struct hwrm_func_qcaps_output { uint8_t valid; } __rte_packed; -/****************** - * hwrm_func_qcfg * - ******************/ +/********************** + * hwrm_func_vf_alloc * + **********************/ -/* hwrm_func_qcfg_input (size:192b/24B) */ -struct hwrm_func_qcfg_input { +/* hwrm_func_vf_alloc_input (size:192b/24B) */ +struct hwrm_func_vf_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -7597,17 +10431,23 @@ struct hwrm_func_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit must be '1' for the first_vf_id field to be + * configured. */ - uint16_t fid; - uint8_t unused_0[6]; + #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t first_vf_id; + /* The number of virtual functions requested. */ + uint16_t num_vfs; } __rte_packed; -/* hwrm_func_qcfg_output (size:704b/88B) */ -struct hwrm_func_qcfg_output { +/* hwrm_func_vf_alloc_output (size:128b/16B) */ +struct hwrm_func_vf_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -7616,407 +10456,364 @@ struct hwrm_func_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* The ID of the first VF allocated. */ + uint16_t first_vf_id; + uint8_t unused_0[5]; /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t fid; + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_func_vf_free * + *********************/ + + +/* hwrm_func_vf_free_input (size:192b/24B) */ +struct hwrm_func_vf_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Port ID of port that this function is associated with. - * 0xFF... (All Fs) if this function is not associated with - * any port. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t port_id; + uint16_t cmpl_ring; /* - * This value is the current VLAN setting for this - * function. The value of 0 for this field indicates - * no priority tagging or VLAN is used. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t vlan; - uint16_t flags; + uint16_t seq_id; /* - * If 1, then magic packet based Out-Of-Box WoL is enabled on - * the port associated with this function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ - UINT32_C(0x1) + uint16_t target_id; /* - * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled - * on the port associated with this function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ - UINT32_C(0x2) + uint64_t resp_addr; + uint32_t enables; /* - * If set to 1, then FW based DCBX agent is enabled and running on - * the port associated with this function. - * If set to 0, then DCBX agent is not running in the firmware. + * This bit must be '1' for the first_vf_id field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ - UINT32_C(0x4) + #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is enabled - * on the queried function. - * If set to 0, then the standard TX ring mode is disabled - * on the queried function. In this extended TX ring resource - * mode, the minimum and maximum bandwidth settings are not - * supported to allow the allocation of TX rings to span multiple - * scheduler nodes. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ - UINT32_C(0x8) + uint16_t first_vf_id; /* - * If set to 1 then FW based LLDP agent is enabled and running on - * the port associated with this function. - * If set to 0 then the LLDP agent is not running in the firmware. + * The number of virtual functions requested. + * 0xFFFF - Cleanup all children of this PF. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ - UINT32_C(0x10) + uint16_t num_vfs; +} __rte_packed; + +/* hwrm_func_vf_free_output (size:128b/16B) */ +struct hwrm_func_vf_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * If set to 1, then multi-host mode is active for this function. - * If set to 0, then multi-host mode is inactive for this function - * or not applicable for this device. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ - UINT32_C(0x20) + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_func_vf_cfg * + ********************/ + + +/* hwrm_func_vf_cfg_input (size:448b/56B) */ +struct hwrm_func_vf_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If the function that is being queried is a PF, then the HWRM shall - * set this field to 0 and the HWRM client shall ignore this field. - * If the function that is being queried is a VF, then the HWRM shall - * set this field to 1 if the queried VF is trusted, otherwise the HWRM - * shall set this field to 0. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ - UINT32_C(0x40) + uint16_t cmpl_ring; /* - * If set to 1, then secure mode is enabled for this function or device. - * If set to 0, then secure mode is disabled (or normal mode) for this - * function or device. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \ - UINT32_C(0x80) + uint16_t seq_id; /* - * If set to 1, then this PF is enabled with a preboot driver that - * requires access to the legacy L2 ring model and legacy 32b - * doorbells. If set to 0, then this PF is not allowed to use - * the legacy L2 rings. This feature is not allowed on VFs and - * is only relevant for devices that require a context backing - * store. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ - UINT32_C(0x100) + uint16_t target_id; /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t mac_address[6]; + uint64_t resp_addr; + uint32_t enables; /* - * This value is current PCI ID of this - * function. If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (4b):Function Number(4b). - * If multi-host mode is active, the 4 lsb will indicate - * the PF index for this function. + * This bit must be '1' for the mtu field to be + * configured. */ - uint16_t pci_id; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + UINT32_C(0x1) /* - * The number of RSS/COS contexts currently - * allocated to the function. + * This bit must be '1' for the guest_vlan field to be + * configured. */ - uint16_t alloc_rsscos_ctx; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ + UINT32_C(0x2) /* - * The number of completion rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * This bit must be '1' for the async_event_cr field to be + * configured. */ - uint16_t alloc_cmpl_rings; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4) /* - * The number of transmit rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * This bit must be '1' for the dflt_mac_addr field to be + * configured. */ - uint16_t alloc_tx_rings; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x8) /* - * The number of receive rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * This bit must be '1' for the num_rsscos_ctxs field to be + * configured. */ - uint16_t alloc_rx_rings; - /* The allocated number of L2 contexts to the function. */ - uint16_t alloc_l2_ctx; - /* The allocated number of vnics to the function. */ - uint16_t alloc_vnics; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + UINT32_C(0x10) /* - * The maximum transmission unit of the function. - * If the reported mtu value is non-zero then it will used for the - * rings allocated on this function. otherwise the default - * value is used if ring MTU is not specified. + * This bit must be '1' for the num_cmpl_rings field to be + * configured. */ - uint16_t mtu; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + UINT32_C(0x20) /* - * The maximum receive unit of the function. - * For vnics allocated on this function, this default - * value is used if vnic MRU is not specified. + * This bit must be '1' for the num_tx_rings field to be + * configured. */ - uint16_t mru; - /* The statistics context assigned to a function. */ - uint16_t stat_ctx_id; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + UINT32_C(0x40) /* - * The HWRM shall return Unknown value for this field - * when this command is used to query VF's configuration. + * This bit must be '1' for the num_rx_rings field to be + * configured. */ - uint8_t port_partition_type; - /* Single physical function */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) - /* Multiple physical functions */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) - /* Network Partitioning 1.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) - /* Network Partitioning 1.5 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) - /* Network Partitioning 2.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) - /* Unknown */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + UINT32_C(0x80) /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * This bit must be '1' for the num_l2_ctxs field to be + * configured. */ - uint8_t port_pf_cnt; - /* number of PFs is not available */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + UINT32_C(0x100) /* - * The default VNIC ID assigned to a function that is - * being queried. + * This bit must be '1' for the num_vnics field to be + * configured. */ - uint16_t dflt_vnic_id; - uint16_t max_mtu_configured; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x200) /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates the minimum bandwidth is not + * This bit must be '1' for the num_stat_ctxs field to be * configured. */ - uint32_t min_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x400) /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates that the maximum bandwidth is not + * This bit must be '1' for the num_hw_ring_grps field to be * configured. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x800) /* - * This value indicates the Edge virtual bridge mode for the - * domain that this function belongs to. + * The maximum transmission unit requested on the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to requesting mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. */ - uint8_t evb_mode; - /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) - /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) - /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA - uint8_t options; + uint16_t mtu; /* - * This value indicates the PCIE device cache line size. - * The cache line size allows the DMA writes to terminate and - * start at the cache boundary. + * The guest VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ - UINT32_C(0x3) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 - /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ - UINT32_C(0x0) - /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ - UINT32_C(0x1) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 - /* This value is the virtual link admin state setting. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ - UINT32_C(0xc) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 - /* Admin link state is in forced down mode. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ - (UINT32_C(0x0) << 2) - /* Admin link state is in forced up mode. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ - (UINT32_C(0x1) << 2) - /* Admin link state is in auto mode - follows the physical link state. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ - (UINT32_C(0x2) << 2) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO - /* Reserved for future. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4 + uint16_t guest_vlan; /* - * The number of VFs that are allocated to the function. - * This is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. */ - uint16_t alloc_vfs; + uint16_t async_event_cr; /* - * The number of allocated multicast filters for this - * function on the RX side. + * This value is the current MAC address requested by the VF + * driver to be configured on this VF. A value of + * 00-00-00-00-00-00 indicates no MAC address configuration + * is requested by the VF driver. + * The parent PF driver may reject or overwrite this + * MAC address. */ - uint32_t alloc_mcast_filters; + uint8_t dflt_mac_addr[6]; + uint32_t flags; /* - * The number of allocated HW ring groups for this - * function. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint32_t alloc_hw_ring_grps; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x1) /* - * The number of strict priority transmit rings out of - * currently allocated TX rings to the function - * (alloc_tx_rings). + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t alloc_sp_tx_rings; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x2) /* - * The number of statistics contexts - * currently reserved for the function. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t alloc_stat_ctx; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x4) /* - * This field specifies how many NQs are reserved for the PF. - * Remaining NQs that belong to the PF are available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t alloc_msix; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x8) /* - * The number of registered VF’s associated with the PF. This field - * should be ignored when the request received on the VF interface. - * This field will be updated on the PF interface to initiate - * the unregister request on PF in the HOT Reset Process. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t registered_vfs; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x10) /* - * The size of the doorbell BAR in KBytes reserved for L2 including - * any area that is shared between L2 and RoCE. The L2 driver - * should only map the L2 portion of the doorbell BAR. Any rounding - * of the BAR size to the native CPU page size should be performed - * by the driver. If the value is zero, no special partitioning - * of the doorbell BAR between L2 and RoCE is required. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t l2_doorbell_bar_size_kb; - uint8_t unused_1; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x20) /* - * For backward compatibility this field must be set to 1. - * Older drivers might look for this field to be 1 before - * processing the message. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint8_t always_1; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x40) /* - * This GRC address location is used by the Host driver interfaces to poll - * the adapter ready state to re-initiate the registration process again - * after receiving the RESET Notify event. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint32_t reset_addr_poll; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x80) /* - * This field specifies legacy L2 doorbell size in KBytes. Drivers should use - * this value to find out the doorbell page offset from the BAR. + * If this bit is set to 1, the VF driver is requesting FW to enable + * PPP TX PUSH feature on all the TX rings specified in the + * num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the VF. This flag is ignored if + * the num_tx_rings field is not specified or the VF doesn't support + * PPP tx push feature. */ - uint16_t legacy_l2_db_size_kb; - uint8_t unused_2[1]; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x100) + /* + * If this bit is set to 1, the VF driver is requesting FW to disable + * PPP TX PUSH feature on all the TX rings of the VF. This flag is + * ignored if the VF doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x200) + /* The number of RSS/COS contexts requested for the VF. */ + uint16_t num_rsscos_ctxs; + /* The number of completion rings requested for the VF. */ + uint16_t num_cmpl_rings; + /* The number of transmit rings requested for the VF. */ + uint16_t num_tx_rings; + /* The number of receive rings requested for the VF. */ + uint16_t num_rx_rings; + /* The number of L2 contexts requested for the VF. */ + uint16_t num_l2_ctxs; + /* The number of vnics requested for the VF. */ + uint16_t num_vnics; + /* The number of statistic contexts requested for the VF. */ + uint16_t num_stat_ctxs; + /* The number of HW ring groups requested for the VF. */ + uint16_t num_hw_ring_grps; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_vf_cfg_output (size:128b/16B) */ +struct hwrm_func_vf_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8027,13 +10824,13 @@ struct hwrm_func_qcfg_output { uint8_t valid; } __rte_packed; -/***************** - * hwrm_func_cfg * - *****************/ +/******************* + * hwrm_func_qcaps * + *******************/ -/* hwrm_func_cfg_input (size:704b/88B) */ -struct hwrm_func_cfg_input { +/* hwrm_func_qcaps_input (size:192b/24B) */ +struct hwrm_func_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -8063,611 +10860,1069 @@ struct hwrm_func_cfg_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the the configuration is - * for the requesting function. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_qcaps_output (size:704b/88B) */ +struct hwrm_func_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This field specifies how many NQs will be reserved for the PF. - * Remaining NQs that belong to the PF become available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint16_t num_msix; - uint32_t flags; + uint16_t fid; /* - * When this bit is '1', the function is disabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to disallow - * transmission of frames with the source MAC address that - * is configured for this function. + * Port ID of port that this function is associated with. + * Valid only for the PF. + * 0xFF... (All Fs) if this function is not associated with + * any port. + * 0xFF... (All Fs) if this function is called from a VF. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ + uint16_t port_id; + uint32_t flags; + /* If 1, then Push mode is supported on this function. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ UINT32_C(0x1) /* - * When this bit is '1', the function is enabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to allow - * transmission of frames with the source MAC address that - * is configured for this function. + * If 1, then the global MSI-X auto-masking is enabled for the + * device. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ - UINT32_C(0x1fc) - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is requested to be - * enabled on the function being configured. + * If 1, then the Precision Time Protocol (PTP) processing + * is supported on this function. + * The HWRM should enable PTP on only a single Physical + * Function (PF) per port. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ + UINT32_C(0x4) + /* + * If 1, then RDMA over Converged Ethernet (RoCE) v1 + * is supported on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ + UINT32_C(0x8) + /* + * If 1, then RDMA over Converged Ethernet (RoCE) v2 + * is supported on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ + UINT32_C(0x10) + /* + * If 1, then control and configuration of WoL magic packet + * are supported on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ + UINT32_C(0x20) + /* + * If 1, then control and configuration of bitmap pattern + * packet are supported on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ + UINT32_C(0x40) + /* + * If set to 1, then the control and configuration of rate limit + * of an allocated TX ring on the queried function is supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ + UINT32_C(0x80) + /* + * If 1, then control and configuration of minimum and + * maximum bandwidths are supported on the queried function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ + UINT32_C(0x100) + /* + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the rate limits + * on the TX rings of its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the rate limits + * on the TX rings of its children VFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ UINT32_C(0x200) /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then the standard TX ring mode is requested to - * be disabled on the function being configured. In this extended - * TX ring resource mode, the minimum and maximum bandwidth settings - * are not supported to allow the allocation of TX rings to - * span multiple scheduler nodes. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the minimum and/or + * maximum bandwidths for its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the minimum or + * maximum bandwidths for its children VFs. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ UINT32_C(0x400) /* - * If this bit is set, virtual mac address configured - * in this command will be persistent over warm boot. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is supported + * on the queried function. + * If set to 0, then standard TX ring mode is not available + * on the queried function. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ UINT32_C(0x800) /* - * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GENEVE tunnel + * flags. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ UINT32_C(0x1000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect NVGRE tunnel + * flags. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ UINT32_C(0x2000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GRE tunnel + * flags. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ UINT32_C(0x4000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect MPLS tunnel + * flags. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ UINT32_C(0x8000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to support pcie stats. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ UINT32_C(0x10000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to adopt the VF's belonging + * to another PF. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \ UINT32_C(0x20000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the administrative privilege to configure another PF */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ UINT32_C(0x40000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then + * the PF will know that the firmware has the capability to track + * the virtual link status. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \ UINT32_C(0x80000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * If 1, then this function supports the push mode that uses + * write combine buffers and the long inline tx buffer descriptor. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \ UINT32_C(0x100000) /* - * This configuration change can be initiated by a PF driver. This - * configuration request shall be targeted to a VF. From local host - * resident HWRM clients, only the parent PF driver shall be allowed - * to initiate this change on one of its children VFs. If this bit is - * set to 1, then the VF that is being configured is requested to be - * trusted. + * If 1, then FW has capability to allocate TX rings dynamically + * in ring alloc even if PF reserved pool is zero. + * This bit will be used only for PFs. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ UINT32_C(0x200000) /* - * When this bit it set, even if PF reserved pool size is zero, - * FW will allow driver to create TX rings in ring alloc, - * by reserving TX ring, S3 node dynamically. + * When this bit is '1', it indicates that core firmware is + * capable of Hot Reset. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \ UINT32_C(0x400000) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of NQ rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This flag will be set to 1 by the FW if FW supports adapter error + * recovery. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \ UINT32_C(0x800000) /* - * This configuration change can be initiated by a PF driver. This - * configuration request shall be targeted to a VF. From local host - * resident HWRM clients, only the parent PF driver shall be allowed - * to initiate this change on one of its children VFs. If this bit is - * set to 1, then the VF that is being configured is requested to be - * untrusted. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then + * the PF has the capability to support extended stats. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \ UINT32_C(0x1000000) /* - * This bit is used by preboot drivers on a PF that require access - * to the legacy L2 ring model and legacy 32b doorbells. This - * feature is not allowed on VFs and is only relevant for devices - * that require a context backing store. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then host + * must initiate reset or reload (or fastboot) the firmware image + * upon detection of device shutdown state. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ UINT32_C(0x2000000) - uint32_t enables; /* - * This bit must be '1' for the mtu field to be - * configured. + * If the query is for a VF, then this flag (always set to 0) shall + * be ignored. If this query is for a PF and this flag is set to 1, + * host, when registered for the default vnic change async event, + * receives async notification whenever a default vnic state is + * changed for any of child or adopted VFs. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ + UINT32_C(0x4000000) + /* If set to 1, then the vlan acceleration for TX is disabled. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_COREDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_CRASHDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ + UINT32_C(0x20000000) + /* + * If the query is for a VF, then this flag should be ignored. + * If the query is for a PF and this flag is set to 1, then + * the PF has the capability to support retrieval of + * rx_port_stats_ext_pfc_wd statistics (supported by the PFC + * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. + * If this flag is set to 1, only that (supported) command should + * be used for retrieval of PFC related statistics (rather than + * hwrm_port_qstats_ext command, which could previously be used). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + UINT32_C(0x40000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_QCAPS command + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \ + UINT32_C(0x80000000) + /* + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. + */ + uint8_t mac_address[6]; + /* + * The maximum number of RSS/COS contexts that can be + * allocated to the function. + */ + uint16_t max_rsscos_ctx; + /* + * The maximum number of completion rings that can be + * allocated to the function. + */ + uint16_t max_cmpl_rings; + /* + * The maximum number of transmit rings that can be + * allocated to the function. + */ + uint16_t max_tx_rings; + /* + * The maximum number of receive rings that can be + * allocated to the function. + */ + uint16_t max_rx_rings; + /* + * The maximum number of L2 contexts that can be + * allocated to the function. + */ + uint16_t max_l2_ctxs; + /* + * The maximum number of VNICs that can be + * allocated to the function. + */ + uint16_t max_vnics; + /* + * The identifier for the first VF enabled on a PF. This + * is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t first_vf_id; + /* + * The maximum number of VFs that can be + * allocated to the function. This is valid only on the + * PF with SR-IOV enabled. 0xFF... (All Fs) if this + * command is called on a PF with SR-IOV disabled or + * on a VF. + */ + uint16_t max_vfs; + /* + * The maximum number of statistic contexts that can be + * allocated to the function. + */ + uint16_t max_stat_ctx; + /* + * The maximum number of Encapsulation records that can be + * offloaded by this function. + */ + uint32_t max_encap_records; + /* + * The maximum number of decapsulation records that can + * be offloaded by this function. + */ + uint32_t max_decap_records; + /* + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the TX side. + */ + uint32_t max_tx_em_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the TX side. + */ + uint32_t max_tx_wm_flows; + /* + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the RX side. + */ + uint32_t max_rx_em_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the RX side. + */ + uint32_t max_rx_wm_flows; + /* + * The maximum number of multicast filters that can + * be supported by this function on the RX side. + */ + uint32_t max_mcast_filters; + /* + * The maximum value of flow_id that can be supported + * in completion records. + */ + uint32_t max_flow_id; + /* + * The maximum number of HW ring groups that can be + * supported on this function. + */ + uint32_t max_hw_ring_grps; + /* + * The maximum number of strict priority transmit rings + * that can be allocated to the function. + * This number indicates the maximum number of TX rings + * that can be assigned strict priorities out of the + * maximum number of TX rings that can be allocated + * (max_tx_rings) to the function. + */ + uint16_t max_sp_tx_rings; + uint8_t unused_0[2]; + uint32_t flags_ext; + /* + * If 1, the device can be configured to set the ECN bits in the + * IP header of received packets if the receive queue length + * exceeds a given threshold. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ UINT32_C(0x1) /* - * This bit must be '1' for the mru field to be - * configured. + * If 1, the device can report the number of received packets + * that it marked as having experienced congestion. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ UINT32_C(0x2) /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. + * If 1, the device can report extended hw statistics (including + * additional tpa statistics). */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \ UINT32_C(0x4) /* - * This bit must be '1' for the num_cmpl_rings field to be - * configured. + * If set to 1, then the core firmware has support to enable/ + * disable hot reset support for interface dynamically through + * HWRM_FUNC_CFG. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \ UINT32_C(0x8) - /* - * This bit must be '1' for the num_tx_rings field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + /* If 1, the proxy mode is supported on this function */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \ UINT32_C(0x10) /* - * This bit must be '1' for the num_rx_rings field to be - * configured. + * If 1, the tx rings source interface override feature is supported + * on this function. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \ UINT32_C(0x20) /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. + * If 1, the device supports scheduler queues. SCHQs can be managed + * using RING_SCHQ_ALLOC/CFG/FREE commands. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \ UINT32_C(0x40) /* - * This bit must be '1' for the num_vnics field to be - * configured. + * If set to 1, then this function supports the TX push mode that + * uses ping-pong buffers from the push pages. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ UINT32_C(0x80) /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. + * If set to 1, then this function doesn't have the privilege to + * configure the EVB mode of the port it uses. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \ UINT32_C(0x100) /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. + * If set to 1, then the HW and FW support the SoC packet DMA + * datapath between SoC and NIC. This function can act as the + * HWRM communication transport agent on behalf of the SoC SPD + * software module. This capability is only advertised to the + * SoC PFs. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \ UINT32_C(0x200) /* - * This bit must be '1' for the dflt_vlan field to be - * configured. + * If set to 1, then this function supports FW_LIVEPATCH for + * firmware livepatch commands. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \ UINT32_C(0x400) /* - * This bit must be '1' for the dflt_ip_addr field to be - * configured. + * When this bit is '1', it indicates that core firmware is + * capable of fast Reset. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \ UINT32_C(0x800) /* - * This bit must be '1' for the min_bw field to be - * configured. + * When this bit is '1', it indicates that firmware and hardware + * are capable of updating tx_metadata via hwrm_ring_cfg command. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \ UINT32_C(0x1000) /* - * This bit must be '1' for the max_bw field to be - * configured. + * If set to 1, then the device can report the action + * needed to activate set nvm options. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \ UINT32_C(0x2000) /* - * This bit must be '1' for the async_event_cr field to be - * configured. + * When this bit is '1', it indicates that the BD metadata feature + * is supported for this function. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \ UINT32_C(0x4000) /* - * This bit must be '1' for the vlan_antispoof_mode field to be - * configured. + * When this bit is '1', it indicates that the echo request feature + * is supported for this function. If the driver registers for the + * echo request asynchronous event, then the firmware can send an + * unsolicited echo request to the driver and expect an echo + * response. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \ UINT32_C(0x8000) + /* The maximum number of SCHQs supported by this device. */ + uint8_t max_schqs; + uint8_t mpc_chnls_cap; /* - * This bit must be '1' for the allowed_vlan_pris field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the evb_mode field to be - * configured. + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the TX crypto engine block. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ - UINT32_C(0x20000) + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1) /* - * This bit must be '1' for the num_mcast_filters field to be - * configured. + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the RX crypto engine block. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ - UINT32_C(0x40000) + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2) /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the TX configurable flow processing block. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x80000) + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4) /* - * This bit must be '1' for the cache_linesize field to be - * configured. + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the RX configurable flow processing block. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ - UINT32_C(0x100000) + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8) /* - * This bit must be '1' for the num_msix field to be - * configured. + * When this bit is '1', it indicates that HW and firmware + * supports the use of a MPC channel with destination set + * to the primate processor block. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ - UINT32_C(0x200000) + #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) + uint8_t unused_1; /* - * This bit must be '1' for the link admin state field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ - UINT32_C(0x400000) + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_func_qcfg * + ******************/ + + +/* hwrm_func_qcfg_input (size:192b/24B) */ +struct hwrm_func_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The maximum transmission unit of the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to configuring mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t mtu; + uint16_t cmpl_ring; /* - * The maximum receive unit of the function. - * The HWRM should make sure that the mru of - * the function does not exceed the mru of the physical - * port that this function is associated with. - * - * In addition to configuring mru per function, it is - * possible to configure mru per vnic. - * By default, the mru of each vnic associated - * with a function is equal to the mru of the function. - * The HWRM should make sure that the mru of each vnic - * that is assigned to a function has a valid mru. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t mru; + uint16_t seq_id; /* - * The number of RSS/COS contexts requested for the - * function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t num_rsscos_ctxs; + uint16_t target_id; /* - * The number of completion rings requested for the - * function. This does not include the rings allocated - * to any children functions if any. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t num_cmpl_rings; + uint64_t resp_addr; /* - * The number of transmit rings requested for the function. - * This does not include the rings allocated to any - * children functions if any. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ - uint16_t num_tx_rings; + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_qcfg_output (size:768b/96B) */ +struct hwrm_func_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * The number of receive rings requested for the function. - * This does not include the rings allocated - * to any children functions if any. + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint16_t num_rx_rings; - /* The requested number of L2 contexts for the function. */ - uint16_t num_l2_ctxs; - /* The requested number of vnics for the function. */ - uint16_t num_vnics; - /* The requested number of statistic contexts for the function. */ - uint16_t num_stat_ctxs; + uint16_t fid; /* - * The number of HW ring groups that should - * be reserved for this function. + * Port ID of port that this function is associated with. + * 0xFF... (All Fs) if this function is not associated with + * any port. */ - uint16_t num_hw_ring_grps; - /* The default MAC address for the function being configured. */ - uint8_t dflt_mac_addr[6]; + uint16_t port_id; /* - * The default VLAN for the function being configured. + * This value is the current VLAN setting for this + * function. The value of 0 for this field indicates + * no priority tagging or VLAN is used. * This field's format is same as 802.1Q Tag's * Tag Control Information (TCI) format that includes both * Priority Code Point (PCP) and VLAN Identifier (VID). */ - uint16_t dflt_vlan; + uint16_t vlan; + uint16_t flags; /* - * The default IP address for the function being configured. - * This address is only used in enabling source property check. + * If 1, then magic packet based Out-Of-Box WoL is enabled on + * the port associated with this function. */ - uint32_t dflt_ip_addr[4]; + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ + UINT32_C(0x1) /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled + * on the port associated with this function. */ - uint32_t min_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ + UINT32_C(0x2) /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. + * If set to 1, then FW based DCBX agent is enabled and running on + * the port associated with this function. + * If set to 0, then DCBX agent is not running in the firmware. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ + UINT32_C(0x4) + /* + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is enabled + * on the queried function. + * If set to 0, then the standard TX ring mode is disabled + * on the queried function. In this extended TX ring resource + * mode, the minimum and maximum bandwidth settings are not + * supported to allow the allocation of TX rings to span multiple + * scheduler nodes. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ + UINT32_C(0x8) + /* + * If set to 1 then FW based LLDP agent is enabled and running on + * the port associated with this function. + * If set to 0 then the LLDP agent is not running in the firmware. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ + UINT32_C(0x10) + /* + * If set to 1, then multi-host mode is active for this function. + * The NIC is attached to two or more independent host systems + * through two or more PCIe endpoints. + * If set to 0, then multi-host mode is inactive for this function + * or not applicable for this device. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ + UINT32_C(0x20) + /* + * If the function that is being queried is a PF, then the HWRM shall + * set this field to 0 and the HWRM client shall ignore this field. + * If the function that is being queried is a VF, then the HWRM shall + * set this field to 1 if the queried VF is trusted, otherwise the HWRM + * shall set this field to 0. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ + UINT32_C(0x40) + /* + * If set to 1, then secure mode is enabled for this function or device. + * If set to 0, then secure mode is disabled (or normal mode) for this + * function or device. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \ + UINT32_C(0x80) + /* + * If set to 1, then this PF is enabled with a preboot driver that + * requires access to the legacy L2 ring model and legacy 32b + * doorbells. If set to 0, then this PF is not allowed to use + * the legacy L2 rings. This feature is not allowed on VFs and + * is only relevant for devices that require a context backing + * store. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ + UINT32_C(0x100) + /* + * If set to 1, then the firmware and all currently registered driver + * instances support hot reset. The hot reset support will be updated + * dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * hot reset. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \ + UINT32_C(0x200) + /* + * If set to 1, then the PPP tx push mode is enabled for all the + * reserved TX rings of this function. If set to 0, then PPP tx push + * mode is disabled for all the reserved TX rings of this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \ + UINT32_C(0x400) + /* + * If set to 1, then the firmware will notify driver using async + * event when a ring is disabled due to a Hardware error. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \ + UINT32_C(0x800) + /* + * If set to 1, then the firmware and all currently registered driver + * instances support fast reset. The fast reset support will be + * updated dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * fast reset. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \ + UINT32_C(0x1000) + /* + * If set to 1, then multi-root mode is active for this function. + * The NIC is attached to a single host with a single operating + * system, but through two or more PCIe endpoints. + * If set to 0, then multi-root mode is inactive for this function + * or not applicable for this device. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \ + UINT32_C(0x2000) + /* + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. + */ + uint8_t mac_address[6]; + /* + * This value is current PCI ID of this + * function. If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (4b):Function Number(4b). + * If multi-host mode is active, the 4 lsb will indicate + * the PF index for this function. + */ + uint16_t pci_id; + /* + * The number of RSS/COS contexts currently + * allocated to the function. + */ + uint16_t alloc_rsscos_ctx; + /* + * The number of completion rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. + */ + uint16_t alloc_cmpl_rings; + /* + * The number of transmit rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. + */ + uint16_t alloc_tx_rings; + /* + * The number of receive rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. + */ + uint16_t alloc_rx_rings; + /* The allocated number of L2 contexts to the function. */ + uint16_t alloc_l2_ctx; + /* The allocated number of vnics to the function. */ + uint16_t alloc_vnics; + /* + * The maximum transmission unit of the function. + * If the reported mtu value is non-zero then it will used for the + * rings allocated on this function. otherwise the default + * value is used if ring MTU is not specified. + */ + uint16_t mtu; + /* + * The maximum receive unit of the function. + * For vnics allocated on this function, this default + * value is used if vnic MRU is not specified. + */ + uint16_t mru; + /* The statistics context assigned to a function. */ + uint16_t stat_ctx_id; + /* + * The HWRM shall return Unknown value for this field + * when this command is used to query VF's configuration. + */ + uint8_t port_partition_type; + /* Single physical function */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) + /* Multiple physical functions */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) + /* Network Partitioning 1.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) + /* Network Partitioning 1.5 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) + /* Network Partitioning 2.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Unknown */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN + /* + * This field will indicate number of physical functions on this port_partition. + * HWRM shall return unavail (i.e. value of 0) for this field + * when this command is used to query VF's configuration or + * from older firmware that doesn't support this field. + */ + uint8_t port_pf_cnt; + /* number of PFs is not available */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL + /* + * The default VNIC ID assigned to a function that is + * being queried. + */ + uint16_t dflt_vnic_id; + uint16_t max_mtu_configured; + /* + * Minimum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. + * A value of 0 indicates the minimum bandwidth is not + * configured. + */ + uint32_t min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID - /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. - */ - uint16_t async_event_cr; - /* VLAN Anti-spoofing mode. */ - uint8_t vlan_antispoof_mode; - /* No VLAN anti-spoofing checks are enabled */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ - UINT32_C(0x0) - /* Validate VLAN against the configured VLAN(s) */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ - UINT32_C(0x1) - /* Insert VLAN if it does not exist, otherwise discard */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ - UINT32_C(0x2) - /* Insert VLAN if it does not exist, override VLAN if it exists */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ - UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This bit field defines VLAN PRIs that are allowed on - * this function. - * If nth bit is set, then VLAN PRI n is allowed on this - * function. + * Maximum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. + * A value of 0 indicates that the maximum bandwidth is not + * configured. */ - uint8_t allowed_vlan_pris; + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID /* - * The HWRM shall allow a PF driver to change EVB mode for the - * partition it belongs to. - * The HWRM shall not allow a VF driver to change the EVB mode. - * The HWRM shall take into account the switching of EVB mode - * from one to another and reconfigure hardware resources as - * appropriately. - * The switching from VEB to VEPA mode requires - * the disabling of the loopback traffic. Additionally, - * source knock outs are handled differently in VEB and VEPA - * modes. + * This value indicates the Edge virtual bridge mode for the + * domain that this function belongs to. */ uint8_t evb_mode; /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA uint8_t options; /* * This value indicates the PCIE device cache line size. * The cache line size allows the DMA writes to terminate and * start at the cache boundary. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ UINT32_C(0x0) /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ UINT32_C(0x1) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 /* This value is the virtual link admin state setting. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ UINT32_C(0xc) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 - /* Admin state is forced down. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin link state is in forced down mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ (UINT32_C(0x0) << 2) - /* Admin state is forced up. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + /* Admin link state is in forced up mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ (UINT32_C(0x1) << 2) - /* Admin state is in auto mode - is to follow the physical link state. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + /* Admin link state is in auto mode - follows the physical link state. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ (UINT32_C(0x2) << 2) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ - HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4 /* - * The number of multicast filters that should - * be reserved for this function on the RX side. + * The number of VFs that are allocated to the function. + * This is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. */ - uint16_t num_mcast_filters; -} __rte_packed; - -/* hwrm_func_cfg_output (size:128b/16B) */ -struct hwrm_func_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t alloc_vfs; + /* + * The number of allocated multicast filters for this + * function on the RX side. + */ + uint32_t alloc_mcast_filters; + /* + * The number of allocated HW ring groups for this + * function. + */ + uint32_t alloc_hw_ring_grps; + /* + * The number of strict priority transmit rings out of + * currently allocated TX rings to the function + * (alloc_tx_rings). + */ + uint16_t alloc_sp_tx_rings; + /* + * The number of statistics contexts + * currently reserved for the function. + */ + uint16_t alloc_stat_ctx; + /* + * This field specifies how many NQs are reserved for the PF. + * Remaining NQs that belong to the PF are available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). + */ + uint16_t alloc_msix; + /* + * The number of registered VF’s associated with the PF. This field + * should be ignored when the request received on the VF interface. + * This field will be updated on the PF interface to initiate + * the unregister request on PF in the HOT Reset Process. + */ + uint16_t registered_vfs; + /* + * The size of the doorbell BAR in KBytes reserved for L2 including + * any area that is shared between L2 and RoCE. The L2 driver + * should only map the L2 portion of the doorbell BAR. Any rounding + * of the BAR size to the native CPU page size should be performed + * by the driver. If the value is zero, no special partitioning + * of the doorbell BAR between L2 and RoCE is required. + */ + uint16_t l2_doorbell_bar_size_kb; + uint8_t unused_1; + /* + * For backward compatibility this field must be set to 1. + * Older drivers might look for this field to be 1 before + * processing the message. + */ + uint8_t always_1; + /* + * This GRC address location is used by the Host driver interfaces to poll + * the adapter ready state to re-initiate the registration process again + * after receiving the RESET Notify event. + */ + uint32_t reset_addr_poll; + /* + * This field specifies legacy L2 doorbell size in KBytes. Drivers should use + * this value to find out the doorbell page offset from the BAR. + */ + uint16_t legacy_l2_db_size_kb; + uint16_t svif_info; + /* + * This field specifies the source virtual interface of the function being + * queried. Drivers can use this to program svif field in the L2 context + * table + */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 + /* This field specifies whether svif is valid or not */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) + uint8_t mpc_chnls; + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the TX crypto engine block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the RX crypto engine block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the TX configurable flow processing block is + * enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the RX configurable flow processing block is + * enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that a MPC channel with + * destination set to the primate processor block is enabled. + */ + #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ + UINT32_C(0x10) + uint8_t unused_2[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8678,13 +11933,13 @@ struct hwrm_func_cfg_output { uint8_t valid; } __rte_packed; -/******************** - * hwrm_func_qstats * - ********************/ +/***************** + * hwrm_func_cfg * + *****************/ -/* hwrm_func_qstats_input (size:192b/24B) */ -struct hwrm_func_qstats_input { +/* hwrm_func_cfg_input (size:768b/96B) */ +struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -8714,464 +11969,745 @@ struct hwrm_func_qstats_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. - * A privileged PF can query for other function's statistics. + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. */ uint16_t fid; - /* This flags indicates the type of statistics request. */ - uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This field specifies how many NQs will be reserved for the PF. + * Remaining NQs that belong to the PF become available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY - uint8_t unused_0[5]; -} __rte_packed; - -/* hwrm_func_qstats_output (size:1408b/176B) */ -struct hwrm_func_qstats_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Number of transmitted unicast packets on the function. */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets on the function. */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets on the function. */ - uint64_t tx_bcast_pkts; + uint16_t num_msix; + uint32_t flags; /* - * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this - * can only happen if TMP is configured to allow dropping - * in HOL blocking conditions, which is not a normal - * configuration. + * When this bit is '1', the function is disabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to disallow + * transmission of frames with the source MAC address that + * is configured for this function. */ - uint64_t tx_discard_pkts; + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ + UINT32_C(0x1) /* - * Number of dropped packets on transmit path on the function. - * These are packets that have been marked for drop by - * the TE CFA block or are packets that exceeded the - * transmit MTU limit for the function. - */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic on the function. */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic on the function. */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic on the function. */ - uint64_t tx_bcast_bytes; - /* Number of received unicast packets on the function. */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets on the function. */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets on the function. */ - uint64_t rx_bcast_pkts; + * When this bit is '1', the function is enabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to allow + * transmission of frames with the source MAC address that + * is configured for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ + UINT32_C(0x1fc) + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 /* - * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. - * # The BD used for the packet has a bad format. - * # There were no BDs available in the ring for the packet. - * # There were no BDs available on-chip for the packet. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is requested to be + * enabled on the function being configured. */ - uint64_t rx_discard_pkts; + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ + UINT32_C(0x200) /* - * Number of dropped packets on received path on the function. - * These are packets that have been marked for drop by the - * RE CFA. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then the standard TX ring mode is requested to + * be disabled on the function being configured. In this extended + * TX ring resource mode, the minimum and maximum bandwidth settings + * are not supported to allow the allocation of TX rings to + * span multiple scheduler nodes. */ - uint64_t rx_drop_pkts; - /* Number of received bytes for unicast traffic on the function. */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic on the function. */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic on the function. */ - uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets on the function. */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes on the function. */ - uint64_t rx_agg_bytes; - /* Number of aggregation events on the function. */ - uint64_t rx_agg_events; - /* Number of aborted aggregations on the function. */ - uint64_t rx_agg_aborts; - uint8_t unused_0[7]; + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ + UINT32_C(0x400) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If this bit is set, virtual mac address configured + * in this command will be persistent over warm boot. */ - uint8_t valid; -} __rte_packed; - -/*********************** - * hwrm_func_clr_stats * - ***********************/ - - -/* hwrm_func_clr_stats_input (size:192b/24B) */ -struct hwrm_func_clr_stats_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ + UINT32_C(0x800) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit only applies to the VF. If this bit is set, the statistic + * context counters will not be cleared when the statistic context is freed + * or a function reset is called on VF. This bit will be cleared when the PF + * is unloaded or a function reset is called on the PF. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ + UINT32_C(0x1000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x2000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x4000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint64_t resp_addr; + #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x8000) /* - * Function ID of the function. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_clr_stats_output (size:128b/16B) */ -struct hwrm_func_clr_stats_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x10000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint8_t valid; -} __rte_packed; - -/************************** - * hwrm_func_vf_resc_free * - **************************/ - - -/* hwrm_func_vf_resc_free_input (size:192b/24B) */ -struct hwrm_func_vf_resc_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x20000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x40000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x80000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x100000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This configuration change can be initiated by a PF driver. This + * configuration request shall be targeted to a VF. From local host + * resident HWRM clients, only the parent PF driver shall be allowed + * to initiate this change on one of its children VFs. If this bit is + * set to 1, then the VF that is being configured is requested to be + * trusted. */ - uint64_t resp_addr; + #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \ + UINT32_C(0x200000) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * When this bit it set, even if PF reserved pool size is zero, + * FW will allow driver to create TX rings in ring alloc, + * by reserving TX ring, S3 node dynamically. */ - uint16_t vf_id; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_func_vf_resc_free_output (size:128b/16B) */ -struct hwrm_func_vf_resc_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \ + UINT32_C(0x400000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of NQ rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint8_t valid; -} __rte_packed; - -/********************** - * hwrm_func_drv_rgtr * - **********************/ - - -/* hwrm_func_drv_rgtr_input (size:896b/112B) */ -struct hwrm_func_drv_rgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ + UINT32_C(0x800000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This configuration change can be initiated by a PF driver. This + * configuration request shall be targeted to a VF. From local host + * resident HWRM clients, only the parent PF driver shall be allowed + * to initiate this change on one of its children VFs. If this bit is + * set to 1, then the VF that is being configured is requested to be + * untrusted. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \ + UINT32_C(0x1000000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit is used by preboot drivers on a PF that require access + * to the legacy L2 ring model and legacy 32b doorbells. This + * feature is not allowed on VFs and is only relevant for devices + * that require a context backing store. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ + UINT32_C(0x2000000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If this bit is set to 0, then the interface does not support hot + * reset capability which it advertised with the hot_reset_support + * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this + * flag to 0, adapter cannot do the hot reset. In this state, if the + * firmware receives a hot reset request, firmware must fail the + * request. If this bit is set to 1, then interface is renabling the + * hot reset capability. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \ + UINT32_C(0x4000000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If this bit is set to 1, the PF driver is requesting FW + * to enable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the function. This flag is + * ignored if num_tx_rings field is not specified or the function + * doesn't support PPP tx push feature. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x8000000) /* - * When this bit is '1', the function driver is requesting - * all requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * If this bit is set to 1, the PF driver is requesting FW + * to disable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. This flag is ignored if num_tx_rings + * field is not specified or the function doesn't support PPP tx + * push feature. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \ + UINT32_C(0x10000000) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \ + UINT32_C(0x20000000) + /* + * If this bit is set to 1, the driver is requesting FW to disable + * the BD_METADATA feature for this function. The FW returns error + * on this request if the TX_METADATA is enabled for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \ + UINT32_C(0x40000000) + uint32_t enables; + /* + * This bit must be '1' for the mtu field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ UINT32_C(0x1) /* - * When this bit is '1', the function is requesting none of - * the requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * This bit must be '1' for the mru field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ UINT32_C(0x2) /* - * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be ignored and ver_maj, ver_min, ver_upd - * and ver_patch shall be used for the driver version information. - * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be used for the driver version information and - * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. + * This bit must be '1' for the num_rsscos_ctxs field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ UINT32_C(0x4) /* - * When this bit is '1', the function is indicating support of - * 64bit flow handle. The firmware that only supports 64bit flow - * handle should check this bit before allowing processing of - * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware - * with 64bit flow handle support can only be compatible with drivers - * that support 64bit flow handle. The legacy drivers that don't support - * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when - * running with new firmware that only supports 64bit flow handle. The new - * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED - * status to the legacy driver when encounters these commands. + * This bit must be '1' for the num_cmpl_rings field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ UINT32_C(0x8) /* - * When this bit is '1', the function is indicating support of - * Hot Reset. The driver interface will destroy the resources, - * unregister the function and register again up on receiving - * the RESET_NOTIFY Async notification from the core firmware. - * The core firmware will this use flag and trigger the Hot Reset - * process only if all the registered driver instances are capable - * of this support. + * This bit must be '1' for the num_tx_rings field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ UINT32_C(0x10) /* - * When this bit is 1, the function is indicating the support of the - * error recovery capability. Error recovery support will be used by - * firmware only if all the driver instances support error recovery - * process. By setting this bit, driver is indicating support for - * corresponding async event completion message. These will be - * delivered to the driver even if they did not register for it. - * If supported, after receiving reset notify async event with fatal - * flag set in event data1, then all the drivers have to tear down - * their resources without sending any HWRM commands to FW. + * This bit must be '1' for the num_rx_rings field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ UINT32_C(0x20) /* - * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select the - * Master function. The master function will be used to initiate - * designated functionality like error recovery etc… If none of the - * registered PF’s or trusted VF’s indicate this support, then - * firmware will select the 1st registered PF as Master capable instance. + * This bit must be '1' for the num_l2_ctxs field to be + * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ UINT32_C(0x40) - uint32_t enables; /* - * This bit must be '1' for the os_type field to be + * This bit must be '1' for the num_vnics field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ - UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x80) /* - * This bit must be '1' for the ver field to be + * This bit must be '1' for the num_stat_ctxs field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ - UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x100) /* - * This bit must be '1' for the timestamp field to be + * This bit must be '1' for the dflt_mac_addr field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ - UINT32_C(0x4) + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x200) /* - * This bit must be '1' for the vf_req_fwd field to be + * This bit must be '1' for the dflt_vlan field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ - UINT32_C(0x8) + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ + UINT32_C(0x400) /* - * This bit must be '1' for the async_event_fwd field to be + * This bit must be '1' for the dflt_ip_addr field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ - UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ - uint16_t os_type; - /* Unknown */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) - /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) - /* MSDOS OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) - /* Windows OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) - /* Solaris OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) - /* Linux OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) - /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) - /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) - /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) - /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) - /* UEFI driver. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI - /* This is the 8bit major version of the driver. */ - uint8_t ver_maj_8b; - /* This is the 8bit minor version of the driver. */ - uint8_t ver_min_8b; - /* This is the 8bit update version of the driver. */ - uint8_t ver_upd_8b; - uint8_t unused_0[3]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ + UINT32_C(0x800) /* - * This is a 32-bit timestamp provided by the driver for - * keep alive. - * The timestamp is in multiples of 1ms. + * This bit must be '1' for the min_bw field to be + * configured. */ - uint32_t timestamp; - uint8_t unused_1[4]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ + UINT32_C(0x1000) /* - * This is a 256-bit bit mask provided by the PF driver for - * letting the HWRM know what commands issued by the VF driver - * to the HWRM should be forwarded to the PF driver. - * Nth bit refers to the Nth req_type. - * - * Setting Nth bit to 1 indicates that requests from the - * VF driver with req_type equal to N shall be forwarded to - * the parent PF driver. - * - * This field is not valid for the VF driver. + * This bit must be '1' for the max_bw field to be + * configured. */ - uint32_t vf_req_fwd[8]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ + UINT32_C(0x2000) /* - * This is a 256-bit bit mask provided by the function driver - * (PF or VF driver) to indicate the list of asynchronous event - * completions to be forwarded. - * - * Nth bit refers to the Nth event_id. - * - * Setting Nth bit to 1 by the function driver shall result in - * the HWRM forwarding asynchronous event completion with - * event_id equal to N. - * - * If all bits are set to 0 (value of 0), then the HWRM shall - * not forward any asynchronous event completion to this - * function driver. + * This bit must be '1' for the async_event_cr field to be + * configured. */ - uint32_t async_event_fwd[8]; - /* This is the 16bit major version of the driver. */ - uint16_t ver_maj; - /* This is the 16bit minor version of the driver. */ - uint16_t ver_min; - /* This is the 16bit update version of the driver. */ - uint16_t ver_upd; - /* This is the 16bit patch version of the driver. */ - uint16_t ver_patch; -} __rte_packed; - -/* hwrm_func_drv_rgtr_output (size:128b/16B) */ -struct hwrm_func_drv_rgtr_output { + #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the vlan_antispoof_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the allowed_vlan_pris field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the evb_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the num_mcast_filters field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the num_hw_ring_grps field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the cache_linesize field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ + UINT32_C(0x100000) + /* + * This bit must be '1' for the num_msix field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ + UINT32_C(0x200000) + /* + * This bit must be '1' for the link admin state field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ + UINT32_C(0x400000) + /* + * This bit must be '1' for the hot_reset_if_en_dis field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x800000) + /* + * This bit must be '1' for the schq_id field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x1000000) + /* + * This bit must be '1' for the mpc_chnls field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \ + UINT32_C(0x2000000) + /* + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. + */ + uint16_t mtu; + /* + * The maximum receive unit of the function. + * The HWRM should make sure that the mru of + * the function does not exceed the mru of the physical + * port that this function is associated with. + * + * In addition to configuring mru per function, it is + * possible to configure mru per vnic. + * By default, the mru of each vnic associated + * with a function is equal to the mru of the function. + * The HWRM should make sure that the mru of each vnic + * that is assigned to a function has a valid mru. + */ + uint16_t mru; + /* + * The number of RSS/COS contexts requested for the + * function. + */ + uint16_t num_rsscos_ctxs; + /* + * The number of completion rings requested for the + * function. This does not include the rings allocated + * to any children functions if any. + */ + uint16_t num_cmpl_rings; + /* + * The number of transmit rings requested for the function. + * This does not include the rings allocated to any + * children functions if any. + */ + uint16_t num_tx_rings; + /* + * The number of receive rings requested for the function. + * This does not include the rings allocated + * to any children functions if any. + */ + uint16_t num_rx_rings; + /* The requested number of L2 contexts for the function. */ + uint16_t num_l2_ctxs; + /* The requested number of vnics for the function. */ + uint16_t num_vnics; + /* The requested number of statistic contexts for the function. */ + uint16_t num_stat_ctxs; + /* + * The number of HW ring groups that should + * be reserved for this function. + */ + uint16_t num_hw_ring_grps; + /* The default MAC address for the function being configured. */ + uint8_t dflt_mac_addr[6]; + /* + * The default VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). + */ + uint16_t dflt_vlan; + /* + * The default IP address for the function being configured. + * This address is only used in enabling source property check. + */ + uint32_t dflt_ip_addr[4]; + /* + * Minimum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. + */ + uint32_t min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. + */ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. + */ + uint16_t async_event_cr; + /* VLAN Anti-spoofing mode. */ + uint8_t vlan_antispoof_mode; + /* No VLAN anti-spoofing checks are enabled */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ + UINT32_C(0x0) + /* Validate VLAN against the configured VLAN(s) */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ + UINT32_C(0x1) + /* Insert VLAN if it does not exist, otherwise discard */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ + UINT32_C(0x2) + /* Insert VLAN if it does not exist, override VLAN if it exists */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN + /* + * This bit field defines VLAN PRIs that are allowed on + * this function. + * If nth bit is set, then VLAN PRI n is allowed on this + * function. + */ + uint8_t allowed_vlan_pris; + /* + * The evb_mode is configured on a per port basis. The default evb_mode + * is configured based on the NVM EVB mode setting upon firmware + * initialization. The HWRM allows a PF driver to change EVB mode for a + * port used by the PF only when one of the following conditions is + * satisfied. + * 1. The current operating mode is single function mode. + * (ie. one PF per port) + * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the + * EVB mode of the port used by the PAXC PF. None of the X86 PFs + * should have privileges. + * The HWRM doesn't permit any PFs to change the underlying EVB mode + * when running as MHB or NPAR mode in performance NIC configuration. + * The HWRM doesn't permit a VF driver to change the EVB mode. + * Once the HWRM determines a function doesn't meet the conditions + * to configure the EVB mode, it sets the evb_mode_cfg_not_supported + * flag in HWRM_FUNC_QCAPS command response for the function. + * The HWRM takes into account the switching of EVB mode from one to + * another and reconfigure hardware resources as reqiured. The + * switching from VEB to VEPA mode requires the disabling of the + * loopback traffic. Additionally, source knockouts are handled + * differently in VEB and VEPA modes. + */ + uint8_t evb_mode; + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA + uint8_t options; + /* + * This value indicates the PCIE device cache line size. + * The cache line size allows the DMA writes to terminate and + * start at the cache boundary. + */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + /* Cache Line Size 64 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ + UINT32_C(0x0) + /* Cache Line Size 128 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ + UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* This value is the virtual link admin state setting. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + UINT32_C(0xc) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin state is forced down. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + (UINT32_C(0x0) << 2) + /* Admin state is forced up. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + (UINT32_C(0x1) << 2) + /* Admin state is in auto mode - is to follow the physical link state. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + (UINT32_C(0x2) << 2) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO + /* Reserved for future. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4 + /* + * The number of multicast filters that should + * be reserved for this function on the RX side. + */ + uint16_t num_mcast_filters; + /* Used by a PF driver to associate a SCHQ with a VF. */ + uint16_t schq_id; + uint16_t mpc_chnls; + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the TX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the TX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the RX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the RX crypto engine block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the TX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \ + UINT32_C(0x10) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the TX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ + UINT32_C(0x20) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the RX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \ + UINT32_C(0x40) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the RX configurable flow processing + * block. When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ + UINT32_C(0x80) + /* + * When this bit is '1', the caller requests to enable a MPC + * channel with destination to the primate processor block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \ + UINT32_C(0x100) + /* + * When this bit is '1', the caller requests to disable a MPC + * channel with destination to the primate processor block. + * When this bit is ‘0’, this flag has no effect. + */ + #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \ + UINT32_C(0x200) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_cfg_output (size:128b/16B) */ +struct hwrm_func_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9180,14 +12716,7 @@ struct hwrm_func_drv_rgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When this bit is '1', it indicates that the - * HWRM_FUNC_DRV_IF_CHANGE call is supported. - */ - #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \ - UINT32_C(0x1) - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9198,13 +12727,13 @@ struct hwrm_func_drv_rgtr_output { uint8_t valid; } __rte_packed; -/************************ - * hwrm_func_drv_unrgtr * - ************************/ +/******************** + * hwrm_func_qstats * + ********************/ -/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ -struct hwrm_func_drv_unrgtr_input { +/* hwrm_func_qstats_input (size:192b/24B) */ +struct hwrm_func_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9233,18 +12762,36 @@ struct hwrm_func_drv_unrgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When this bit is '1', the function driver is notifying - * the HWRM to prepare for the shutdown. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * A privileged PF can query for other function's statistics. */ - #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ - UINT32_C(0x1) - uint8_t unused_0[4]; + uint16_t fid; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; } __rte_packed; -/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ -struct hwrm_func_drv_unrgtr_output { +/* hwrm_func_qstats_output (size:1408b/176B) */ +struct hwrm_func_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9253,6 +12800,67 @@ struct hwrm_func_drv_unrgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Number of transmitted unicast packets on the function. */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets on the function. */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets on the function. */ + uint64_t tx_bcast_pkts; + /* + * Number of transmitted packets that were discarded due to + * internal NIC resource problems. For transmit, this + * can only happen if TMP is configured to allow dropping + * in HOL blocking conditions, which is not a normal + * configuration. + */ + uint64_t tx_discard_pkts; + /* + * Number of dropped packets on transmit path on the function. + * These are packets that have been marked for drop by + * the TE CFA block or are packets that exceeded the + * transmit MTU limit for the function. + */ + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic on the function. */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic on the function. */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic on the function. */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets on the function. */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets on the function. */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets on the function. */ + uint64_t rx_bcast_pkts; + /* + * Number of received packets that were discarded on the function + * due to resource limitations. This can happen for 3 reasons. + * # The BD used for the packet has a bad format. + * # There were no BDs available in the ring for the packet. + * # There were no BDs available on-chip for the packet. + */ + uint64_t rx_discard_pkts; + /* + * Number of dropped packets on received path on the function. + * These are packets that have been marked for drop by the + * RE CFA. + */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic on the function. */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic on the function. */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic on the function. */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets on the function. */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes on the function. */ + uint64_t rx_agg_bytes; + /* Number of aggregation events on the function. */ + uint64_t rx_agg_events; + /* Number of aborted aggregations on the function. */ + uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -9264,13 +12872,13 @@ struct hwrm_func_drv_unrgtr_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_buf_rgtr * - **********************/ +/************************ + * hwrm_func_qstats_ext * + ************************/ -/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ -struct hwrm_func_buf_rgtr_input { +/* hwrm_func_qstats_ext_input (size:256b/32B) */ +struct hwrm_func_qstats_ext_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9299,87 +12907,51 @@ struct hwrm_func_buf_rgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; /* - * This bit must be '1' for the vf_id field to be - * configured. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + * A privileged PF can query for other function's statistics. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + uint16_t fid; + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * This bit must be '1' for the err_buf_addr field to be - * configured. + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * flags should be set to 2 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. */ - uint16_t vf_id; + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[1]; + uint32_t enables; /* - * This field represents the number of pages used for request - * buffer(s). + * This bit must be '1' for the schq_id and traffic_class fields to + * be configured. */ - uint16_t req_buf_num_pages; + #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1) + /* Specifies the SCHQ for which to gather statistics */ + uint16_t schq_id; /* - * This field represents the page size used for request - * buffer(s). + * Specifies the traffic class for which to gather statistics. Valid + * values are 0 through (max_configurable_queues - 1), where + * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG */ - uint16_t req_buf_page_size; - /* 16 bytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) - /* 4 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) - /* 8 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) - /* 64 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) - /* 2 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) - /* 4 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) - /* 1 Gbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ - HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G - /* The length of the request buffer per VF in bytes. */ - uint16_t req_buf_len; - /* The length of the response buffer in bytes. */ - uint16_t resp_buf_len; - uint8_t unused_0[2]; - /* This field represents the page address of page #0. */ - uint64_t req_buf_page_addr0; - /* This field represents the page address of page #1. */ - uint64_t req_buf_page_addr1; - /* This field represents the page address of page #2. */ - uint64_t req_buf_page_addr2; - /* This field represents the page address of page #3. */ - uint64_t req_buf_page_addr3; - /* This field represents the page address of page #4. */ - uint64_t req_buf_page_addr4; - /* This field represents the page address of page #5. */ - uint64_t req_buf_page_addr5; - /* This field represents the page address of page #6. */ - uint64_t req_buf_page_addr6; - /* This field represents the page address of page #7. */ - uint64_t req_buf_page_addr7; - /* This field represents the page address of page #8. */ - uint64_t req_buf_page_addr8; - /* This field represents the page address of page #9. */ - uint64_t req_buf_page_addr9; - /* - * This field is used to receive the error reporting from - * the chipset. Only applicable for PFs. - */ - uint64_t error_buf_addr; - /* - * This field is used to receive the response forwarded by the - * HWRM. - */ - uint64_t resp_buf_addr; + uint16_t traffic_class; + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_func_buf_rgtr_output (size:128b/16B) */ -struct hwrm_func_buf_rgtr_output { +/* hwrm_func_qstats_ext_output (size:1536b/192B) */ +struct hwrm_func_qstats_ext_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9388,6 +12960,50 @@ struct hwrm_func_buf_rgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on received path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + /* Number of TPA errors */ + uint64_t rx_tpa_events; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -9399,13 +13015,13 @@ struct hwrm_func_buf_rgtr_output { uint8_t valid; } __rte_packed; -/************************ - * hwrm_func_buf_unrgtr * - ************************/ +/*********************** + * hwrm_func_clr_stats * + ***********************/ -/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ -struct hwrm_func_buf_unrgtr_input { +/* hwrm_func_clr_stats_input (size:192b/24B) */ +struct hwrm_func_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9434,22 +13050,17 @@ struct hwrm_func_buf_unrgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vf_id field to be - * configured. - */ - #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * Function ID of the function. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ - uint16_t vf_id; - uint8_t unused_0[2]; + uint16_t fid; + uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ -struct hwrm_func_buf_unrgtr_output { +/* hwrm_func_clr_stats_output (size:128b/16B) */ +struct hwrm_func_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9469,13 +13080,13 @@ struct hwrm_func_buf_unrgtr_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_drv_qver * - **********************/ +/************************** + * hwrm_func_vf_resc_free * + **************************/ -/* hwrm_func_drv_qver_input (size:192b/24B) */ -struct hwrm_func_drv_qver_input { +/* hwrm_func_vf_resc_free_input (size:192b/24B) */ +struct hwrm_func_vf_resc_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9504,19 +13115,16 @@ struct hwrm_func_drv_qver_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Reserved for future use. */ - uint32_t reserved; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - uint16_t fid; - uint8_t unused_0[2]; + uint16_t vf_id; + uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_drv_qver_output (size:256b/32B) */ -struct hwrm_func_drv_qver_output { +/* hwrm_func_vf_resc_free_output (size:128b/16B) */ +struct hwrm_func_vf_resc_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9525,32 +13133,201 @@ struct hwrm_func_drv_qver_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_drv_rgtr * + **********************/ + + +/* hwrm_func_drv_rgtr_input (size:896b/112B) */ +struct hwrm_func_drv_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the function driver is requesting + * all requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \ + UINT32_C(0x1) + /* + * When this bit is '1', the function is requesting none of + * the requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \ + UINT32_C(0x2) + /* + * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be ignored and ver_maj, ver_min, ver_upd + * and ver_patch shall be used for the driver version information. + * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be used for the driver version information and + * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the function is indicating support of + * 64bit flow handle. The firmware that only supports 64bit flow + * handle should check this bit before allowing processing of + * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware + * with 64bit flow handle support can only be compatible with drivers + * that support 64bit flow handle. The legacy drivers that don't support + * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when + * running with new firmware that only supports 64bit flow handle. The new + * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * status to the legacy driver when encounters these commands. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ + UINT32_C(0x8) + /* + * When this bit is '1', the function is indicating support of + * Hot Reset. The driver interface will destroy the resources, + * unregister the function and register again up on receiving + * the RESET_NOTIFY Async notification from the core firmware. + * The core firmware will this use flag and trigger the Hot Reset + * process only if all the registered driver instances are capable + * of this support. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \ + UINT32_C(0x10) + /* + * When this bit is 1, the function is indicating the support of the + * error recovery capability. Error recovery support will be used by + * firmware only if all the driver instances support error recovery + * process. By setting this bit, driver is indicating support for + * corresponding async event completion message. These will be + * delivered to the driver even if they did not register for it. + * If supported, after receiving reset notify async event with fatal + * flag set in event data1, then all the drivers have to tear down + * their resources without sending any HWRM commands to FW. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \ + UINT32_C(0x20) + /* + * When this bit is 1, the function is indicating the support of the + * Master capability. The Firmware will use this capability to select the + * Master function. The master function will be used to initiate + * designated functionality like error recovery etc… If none of the + * registered PF’s or trusted VF’s indicate this support, then + * firmware will select the 1st registered PF as Master capable instance. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ + UINT32_C(0x40) + /* + * When this bit is 1, the function is indicating the support of the + * fast reset capability. Fast reset support will be used by + * firmware only if all the driver instances support fast reset + * process. By setting this bit, driver is indicating support for + * corresponding async event completion message. These will be + * delivered to the driver even if they did not register for it. + * If supported, after receiving reset notify async event with fast + * reset flag set in event data1, then all the drivers have to tear + * down their resources without sending any HWRM commands to FW. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \ + UINT32_C(0x80) + uint32_t enables; + /* + * This bit must be '1' for the os_type field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ver field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ + UINT32_C(0x2) + /* + * This bit must be '1' for the timestamp field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vf_req_fwd field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the async_event_fwd field to be + * configured. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ + UINT32_C(0x10) /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ uint16_t os_type; /* Unknown */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) /* MSDOS OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) /* Windows OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) /* Solaris OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) /* Linux OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) /* UEFI driver. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI /* This is the 8bit major version of the driver. */ uint8_t ver_maj_8b; /* This is the 8bit minor version of the driver. */ @@ -9558,6 +13335,42 @@ struct hwrm_func_drv_qver_output { /* This is the 8bit update version of the driver. */ uint8_t ver_upd_8b; uint8_t unused_0[3]; + /* + * This is a 32-bit timestamp provided by the driver for + * keep alive. + * The timestamp is in multiples of 1ms. + */ + uint32_t timestamp; + uint8_t unused_1[4]; + /* + * This is a 256-bit bit mask provided by the PF driver for + * letting the HWRM know what commands issued by the VF driver + * to the HWRM should be forwarded to the PF driver. + * Nth bit refers to the Nth req_type. + * + * Setting Nth bit to 1 indicates that requests from the + * VF driver with req_type equal to N shall be forwarded to + * the parent PF driver. + * + * This field is not valid for the VF driver. + */ + uint32_t vf_req_fwd[8]; + /* + * This is a 256-bit bit mask provided by the function driver + * (PF or VF driver) to indicate the list of asynchronous event + * completions to be forwarded. + * + * Nth bit refers to the Nth event_id. + * + * Setting Nth bit to 1 by the function driver shall result in + * the HWRM forwarding asynchronous event completion with + * event_id equal to N. + * + * If all bits are set to 0 (value of 0), then the HWRM shall + * not forward any asynchronous event completion to this + * function driver. + */ + uint32_t async_event_fwd[8]; /* This is the 16bit major version of the driver. */ uint16_t ver_maj; /* This is the 16bit minor version of the driver. */ @@ -9566,7 +13379,26 @@ struct hwrm_func_drv_qver_output { uint16_t ver_upd; /* This is the 16bit patch version of the driver. */ uint16_t ver_patch; - uint8_t unused_1[7]; +} __rte_packed; + +/* hwrm_func_drv_rgtr_output (size:128b/16B) */ +struct hwrm_func_drv_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', it indicates that the + * HWRM_FUNC_DRV_IF_CHANGE call is supported. + */ + #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \ + UINT32_C(0x1) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9577,13 +13409,13 @@ struct hwrm_func_drv_qver_output { uint8_t valid; } __rte_packed; -/**************************** - * hwrm_func_resource_qcaps * - ****************************/ +/************************ + * hwrm_func_drv_unrgtr * + ************************/ -/* hwrm_func_resource_qcaps_input (size:192b/24B) */ -struct hwrm_func_resource_qcaps_input { +/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ +struct hwrm_func_drv_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9612,17 +13444,18 @@ struct hwrm_func_resource_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * When this bit is '1', the function driver is notifying + * the HWRM to prepare for the shutdown. */ - uint16_t fid; - uint8_t unused_0[6]; + #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ + UINT32_C(0x1) + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ -struct hwrm_func_resource_qcaps_output { +/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ +struct hwrm_func_drv_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9631,72 +13464,7 @@ struct hwrm_func_resource_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ - uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ - uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ - uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ - UINT32_C(0x0) - /* The PF driver should only reserve minimal resources for each VF. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ - UINT32_C(0x1) - /* - * The PF driver should not reserve any resources for each VF until the - * the VF interface is brought up. - */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ - UINT32_C(0x2) - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ - HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ - uint16_t min_rsscos_ctx; - /* Maximum non-guaranteed number of RSS/COS contexts */ - uint16_t max_rsscos_ctx; - /* Minimum guaranteed number of completion rings */ - uint16_t min_cmpl_rings; - /* Maximum non-guaranteed number of completion rings */ - uint16_t max_cmpl_rings; - /* Minimum guaranteed number of transmit rings */ - uint16_t min_tx_rings; - /* Maximum non-guaranteed number of transmit rings */ - uint16_t max_tx_rings; - /* Minimum guaranteed number of receive rings */ - uint16_t min_rx_rings; - /* Maximum non-guaranteed number of receive rings */ - uint16_t max_rx_rings; - /* Minimum guaranteed number of L2 contexts */ - uint16_t min_l2_ctxs; - /* Maximum non-guaranteed number of L2 contexts */ - uint16_t max_l2_ctxs; - /* Minimum guaranteed number of VNICs */ - uint16_t min_vnics; - /* Maximum non-guaranteed number of VNICs */ - uint16_t max_vnics; - /* Minimum guaranteed number of statistic contexts */ - uint16_t min_stat_ctx; - /* Maximum non-guaranteed number of statistic contexts */ - uint16_t max_stat_ctx; - /* Minimum guaranteed number of ring groups */ - uint16_t min_hw_ring_grps; - /* Maximum non-guaranteed number of ring groups */ - uint16_t max_hw_ring_grps; - /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. - */ - uint16_t max_tx_scheduler_inputs; - uint16_t flags; - /* - * When this bit is '1', it indicates that VF_RESOURCE_CFG supports - * feature to reserve all minimum resources when minimum >= 1, otherwise - * returns an error. - */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ - UINT32_C(0x1) - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9707,13 +13475,13 @@ struct hwrm_func_resource_qcaps_output { uint8_t valid; } __rte_packed; -/********************************* - * hwrm_func_backing_store_qcaps * - *********************************/ +/********************** + * hwrm_func_buf_rgtr * + **********************/ -/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcaps_input { +/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ +struct hwrm_func_buf_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9742,128 +13510,96 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; - -/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ -struct hwrm_func_backing_store_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Maximum number of QP context entries supported for this function. */ - uint32_t qp_max_entries; + uint32_t enables; /* - * Minimum number of QP context entries that are needed to be reserved - * for QP1 for the PF and its VFs. PF drivers must allocate at least - * this many QP context entries, even if RoCE will not be used. + * This bit must be '1' for the vf_id field to be + * configured. */ - uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ - uint16_t qp_max_l2_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t qp_entry_size; - /* Maximum number of SRQ context entries that can be used for L2. */ - uint16_t srq_max_l2_entries; - /* Maximum number of SRQ context entries supported for this function. */ - uint32_t srq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t srq_entry_size; - /* Maximum number of CQ context entries that can be used for L2. */ - uint16_t cq_max_l2_entries; - /* Maximum number of CQ context entries supported for this function. */ - uint32_t cq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t cq_entry_size; - /* Maximum number of VNIC context entries supported for this function. */ - uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ - uint16_t vnic_max_ring_table_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ - uint32_t stat_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t stat_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tqm_entry_size; - /* Minimum number of TQM context entries required per ring. */ - uint32_t tqm_min_entries_per_ring; + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) /* - * Maximum number of TQM context entries supported per ring. This is - * actually a recommended TQM queue size based on worst case usage of - * the TQM queue. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * TQM slowpath rings should be sized as follows: - * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size - * - * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate - * the backing store. + * This bit must be '1' for the err_buf_addr field to be + * configured. */ - uint32_t tqm_max_entries_per_ring; + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) /* - * Maximum number of MR plus AV context entries supported for this - * function. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - uint32_t mrav_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t mrav_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tim_entry_size; - /* Maximum number of Timer context entries supported for this function. */ - uint32_t tim_max_entries; + uint16_t vf_id; /* - * When this field is zero, the 32b `mrav_num_entries` field in the - * `backing_store_cfg` and `backing_store_qcfg` commands represents - * the total number of MR plus AV entries allowed in the MR/AV backing - * store PBL. - * - * When this field is non-zero, the 32b `mrav_num_entries` field in - * the `backing_store_cfg` and `backing_store_qcfg` commands is - * logically divided into two 16b fields. Bits `[31:16]` represents - * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`. - * Both of these values are represented in a unit granularity - * specified by this field. For example, if this field is 16 and - * `mrav_num_entries` is `0x02000100`, then the number of MR entries - * is 8192 and the number of AV entries is 4096. + * This field represents the number of pages used for request + * buffer(s). */ - uint16_t mrav_num_entries_units; + uint16_t req_buf_num_pages; /* - * The number of entries specified for any TQM ring must be a - * multiple of this value to prevent any resource allocation - * limitations. + * This field represents the page size used for request + * buffer(s). */ - uint8_t tqm_entries_multiple; + uint16_t req_buf_page_size; + /* 16 bytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) + /* 4 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) + /* 8 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) + /* 64 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) + /* 2 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) + /* 4 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) + /* 1 Gbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ + HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G + /* The length of the request buffer per VF in bytes. */ + uint16_t req_buf_len; + /* The length of the response buffer in bytes. */ + uint16_t resp_buf_len; + uint8_t unused_0[2]; + /* This field represents the page address of page #0. */ + uint64_t req_buf_page_addr0; + /* This field represents the page address of page #1. */ + uint64_t req_buf_page_addr1; + /* This field represents the page address of page #2. */ + uint64_t req_buf_page_addr2; + /* This field represents the page address of page #3. */ + uint64_t req_buf_page_addr3; + /* This field represents the page address of page #4. */ + uint64_t req_buf_page_addr4; + /* This field represents the page address of page #5. */ + uint64_t req_buf_page_addr5; + /* This field represents the page address of page #6. */ + uint64_t req_buf_page_addr6; + /* This field represents the page address of page #7. */ + uint64_t req_buf_page_addr7; + /* This field represents the page address of page #8. */ + uint64_t req_buf_page_addr8; + /* This field represents the page address of page #9. */ + uint64_t req_buf_page_addr9; /* - * Initializer to be used by drivers - * to initialize context memory to ensure - * context subsystem flags an error for an attack - * before the first time context load. + * This field is used to receive the error reporting from + * the chipset. Only applicable for PFs. */ - uint8_t ctx_kind_initializer; - /* Reserved for future. */ - uint32_t rsvd; - /* Reserved for future. */ - uint16_t rsvd1; - /* Reserved for future. */ - uint8_t rsvd2; + uint64_t error_buf_addr; + /* + * This field is used to receive the response forwarded by the + * HWRM. + */ + uint64_t resp_buf_addr; +} __rte_packed; + +/* hwrm_func_buf_rgtr_output (size:128b/16B) */ +struct hwrm_func_buf_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9874,13 +13610,13 @@ struct hwrm_func_backing_store_qcaps_output { uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_backing_store_cfg * - *******************************/ +/************************ + * hwrm_func_buf_unrgtr * + ************************/ -/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ -struct hwrm_func_backing_store_cfg_input { +/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ +struct hwrm_func_buf_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9909,241 +13645,987 @@ struct hwrm_func_backing_store_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint32_t enables; /* - * When set, the firmware only uses on-chip resources and does not - * expect any backing store to be provided by the host driver. This - * mode provides minimal L2 functionality (e.g. limited L2 resources, - * no RoCE). + * This bit must be '1' for the vf_id field to be + * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ - UINT32_C(0x1) + #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) /* - * When set, the 32b `mrav_num_entries` field is logically divided - * into two 16b fields, `mr_num_entries` and `av_num_entries`. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \ - UINT32_C(0x2) - uint32_t enables; + uint16_t vf_id; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ +struct hwrm_func_buf_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the qp fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ - UINT32_C(0x1) + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_drv_qver * + **********************/ + + +/* hwrm_func_drv_qver_input (size:192b/24B) */ +struct hwrm_func_drv_qver_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the srq fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * This bit must be '1' for the cq fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ - UINT32_C(0x4) + uint16_t seq_id; /* - * This bit must be '1' for the vnic fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ - UINT32_C(0x8) + uint16_t target_id; /* - * This bit must be '1' for the stat fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ - UINT32_C(0x10) + uint64_t resp_addr; + /* Reserved for future use. */ + uint32_t reserved; /* - * This bit must be '1' for the tqm_sp fields to be - * configured. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ - UINT32_C(0x20) + uint16_t fid; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_drv_qver_output (size:256b/32B) */ +struct hwrm_func_drv_qver_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + uint16_t os_type; + /* Unknown */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + /* UEFI driver. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI + /* This is the 8bit major version of the driver. */ + uint8_t ver_maj_8b; + /* This is the 8bit minor version of the driver. */ + uint8_t ver_min_8b; + /* This is the 8bit update version of the driver. */ + uint8_t ver_upd_8b; + uint8_t unused_0[3]; + /* This is the 16bit major version of the driver. */ + uint16_t ver_maj; + /* This is the 16bit minor version of the driver. */ + uint16_t ver_min; + /* This is the 16bit update version of the driver. */ + uint16_t ver_upd; + /* This is the 16bit patch version of the driver. */ + uint16_t ver_patch; + uint8_t unused_1[7]; /* - * This bit must be '1' for the tqm_ring0 fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ - UINT32_C(0x40) + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_func_resource_qcaps * + ****************************/ + + +/* hwrm_func_resource_qcaps_input (size:192b/24B) */ +struct hwrm_func_resource_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the tqm_ring1 fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ - UINT32_C(0x80) + uint16_t cmpl_ring; /* - * This bit must be '1' for the tqm_ring2 fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ - UINT32_C(0x100) + uint16_t seq_id; /* - * This bit must be '1' for the tqm_ring3 fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ - UINT32_C(0x200) + uint16_t target_id; /* - * This bit must be '1' for the tqm_ring4 fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ - UINT32_C(0x400) + uint64_t resp_addr; /* - * This bit must be '1' for the tqm_ring5 fields to be - * configured. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ - UINT32_C(0x800) + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +struct hwrm_func_resource_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + uint16_t max_vfs; + /* Maximum guaranteed number of MSI-X vectors supported by function */ + uint16_t max_msix; + /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + uint16_t vf_reservation_strategy; + /* The PF driver should evenly divide its remaining resources among all VFs. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ + UINT32_C(0x0) + /* The PF driver should only reserve minimal resources for each VF. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ + UINT32_C(0x1) /* - * This bit must be '1' for the tqm_ring6 fields to be - * configured. + * The PF driver should not reserve any resources for each VF until the + * the VF interface is brought up. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ - UINT32_C(0x1000) + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ + UINT32_C(0x2) + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; /* - * This bit must be '1' for the tqm_ring7 fields to be - * configured. + * Maximum number of inputs into the transmit scheduler for this function. + * The number of TX rings assigned to the function cannot exceed this value. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ - UINT32_C(0x2000) + uint16_t max_tx_scheduler_inputs; + uint16_t flags; /* - * This bit must be '1' for the mrav fields to be - * configured. + * When this bit is '1', it indicates that VF_RESOURCE_CFG supports + * feature to reserve all minimum resources when minimum >= 1, otherwise + * returns an error. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ - UINT32_C(0x4000) + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ + UINT32_C(0x1) + uint8_t unused_0[5]; /* - * This bit must be '1' for the tim fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ - UINT32_C(0x8000) - /* QPC page size and level. */ - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 - /* QPC page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G - /* SRQ page size and level. */ - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_func_vf_resource_cfg * + *****************************/ + + +/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +struct hwrm_func_vf_resource_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF ID that is being configured by PF */ + uint16_t vf_id; + /* Maximum guaranteed number of MSI-X vectors for the function */ + uint16_t max_msix; + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; + uint16_t flags; + /* + * If this bit is set, all minimum resources requested should be + * reserved if minimum >= 1, otherwise return error. In case of + * error, keep all existing reservations before the call. + */ + #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ + UINT32_C(0x1) + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ +struct hwrm_func_vf_resource_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved number of RSS/COS contexts */ + uint16_t reserved_rsscos_ctx; + /* Reserved number of completion rings */ + uint16_t reserved_cmpl_rings; + /* Reserved number of transmit rings */ + uint16_t reserved_tx_rings; + /* Reserved number of receive rings */ + uint16_t reserved_rx_rings; + /* Reserved number of L2 contexts */ + uint16_t reserved_l2_ctxs; + /* Reserved number of VNICs */ + uint16_t reserved_vnics; + /* Reserved number of statistic contexts */ + uint16_t reserved_stat_ctx; + /* Reserved number of ring groups */ + uint16_t reserved_hw_ring_grps; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_func_backing_store_qcaps * + *********************************/ + + +/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ +struct hwrm_func_backing_store_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ +struct hwrm_func_backing_store_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum number of QP context entries supported for this function. */ + uint32_t qp_max_entries; + /* + * Minimum number of QP context entries that are needed to be reserved + * for QP1 for the PF and its VFs. PF drivers must allocate at least + * this many QP context entries, even if RoCE will not be used. + */ + uint16_t qp_min_qp1_entries; + /* Maximum number of QP context entries that can be used for L2. */ + uint16_t qp_max_l2_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t qp_entry_size; + /* Maximum number of SRQ context entries that can be used for L2. */ + uint16_t srq_max_l2_entries; + /* Maximum number of SRQ context entries supported for this function. */ + uint32_t srq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t srq_entry_size; + /* Maximum number of CQ context entries that can be used for L2. */ + uint16_t cq_max_l2_entries; + /* Maximum number of CQ context entries supported for this function. */ + uint32_t cq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t cq_entry_size; + /* Maximum number of VNIC context entries supported for this function. */ + uint16_t vnic_max_vnic_entries; + /* Maximum number of Ring table context entries supported for this function. */ + uint16_t vnic_max_ring_table_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t vnic_entry_size; + /* Maximum number of statistic context entries supported for this function. */ + uint32_t stat_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t stat_entry_size; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tqm_entry_size; + /* Minimum number of TQM context entries required per ring. */ + uint32_t tqm_min_entries_per_ring; + /* + * Maximum number of TQM context entries supported per ring. This is + * actually a recommended TQM queue size based on worst case usage of + * the TQM queue. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * TQM slowpath rings should be sized as follows: + * + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size + * + * Where: + * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_l2_tx_rings is the number of L2 rings in the QP backing store + * num_roce_qps is the number of RoCE QPs in the QP backing store + * tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_max_entries_per_ring; + /* + * Maximum number of MR plus AV context entries supported for this + * function. + */ + uint32_t mrav_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t mrav_entry_size; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tim_entry_size; + /* Maximum number of Timer context entries supported for this function. */ + uint32_t tim_max_entries; + /* + * When this field is zero, the 32b `mrav_num_entries` field in the + * `backing_store_cfg` and `backing_store_qcfg` commands represents + * the total number of MR plus AV entries allowed in the MR/AV backing + * store PBL. + * + * When this field is non-zero, the 32b `mrav_num_entries` field in + * the `backing_store_cfg` and `backing_store_qcfg` commands is + * logically divided into two 16b fields. Bits `[31:16]` represents + * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`. + * Both of these values are represented in a unit granularity + * specified by this field. For example, if this field is 16 and + * `mrav_num_entries` is `0x02000100`, then the number of MR entries + * is 8192 and the number of AV entries is 4096. + */ + uint16_t mrav_num_entries_units; + /* + * The number of entries specified for any TQM ring must be a + * multiple of this value to prevent any resource allocation + * limitations. + */ + uint8_t tqm_entries_multiple; + /* + * Initializer to be used by drivers + * to initialize context memory to ensure + * context subsystem flags an error for an attack + * before the first time context load. + */ + uint8_t ctx_kind_initializer; + /* + * Specifies which context kinds need to be initialized with the + * ctx_kind_initializer. + */ + uint16_t ctx_init_mask; + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \ + UINT32_C(0x1) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \ + UINT32_C(0x2) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \ + UINT32_C(0x4) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \ + UINT32_C(0x8) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \ + UINT32_C(0x10) + /* + * If this bit is '1' then this context type should be initialized + * with the ctx_kind_initializer at the specified offset. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \ + UINT32_C(0x20) + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t qp_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t srq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t cq_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t vnic_init_offset; + /* + * Count of TQM fastpath rings to be used for allocating backing store. + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + * Only first 8 TQM FP rings will be advertised with this field. + */ + uint8_t tqm_fp_rings_count; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t stat_init_offset; + /* + * Specifies the doubleword offset of ctx_kind_initializer for this + * context type. + */ + uint8_t mrav_init_offset; + /* + * Count of TQM extended fastpath rings to be used for allocating + * backing store beyond 8 rings(rings 9,10,11) + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count_ext; + /* Reserved for future. */ + uint8_t rsvd[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* tqm_fp_ring_cfg (size:128b/16B) */ +struct tqm_fp_ring_cfg { + /* TQM ring page size and level. */ + uint8_t tqm_ring_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G - /* CQ page size and level. */ - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ + #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \ + TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G + uint8_t unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring_page_dir; +} __rte_packed; + +/******************************* + * hwrm_func_backing_store_cfg * + *******************************/ + + +/* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ +struct hwrm_func_backing_store_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and does not + * expect any backing store to be provided by the host driver. This + * mode provides minimal L2 functionality (e.g. limited L2 resources, + * no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + /* + * When set, the 32b `mrav_num_entries` field is logically divided + * into two 16b fields, `mr_num_entries` and `av_num_entries`. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \ + UINT32_C(0x2) + uint32_t enables; + /* + * This bit must be '1' for the qp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the srq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vnic fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ + UINT32_C(0x8) + /* + * This bit must be '1' for the stat fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ + UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_sp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ + UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ + UINT32_C(0x80) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ + UINT32_C(0x100) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ + UINT32_C(0x400) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ + UINT32_C(0x800) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the mrav fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the tim fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) + /* QPC page size and level. */ + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ UINT32_C(0x1) /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 - /* CQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 + /* QPC page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ (UINT32_C(0x0) << 4) /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ (UINT32_C(0x1) << 4) /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ (UINT32_C(0x2) << 4) /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ (UINT32_C(0x3) << 4) /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ (UINT32_C(0x4) << 4) /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G + /* SRQ page size and level. */ + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G + /* CQ page size and level. */ + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 + /* CQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G /* VNIC page size and level. */ uint8_t vnic_pg_size_vnic_lvl; /* VNIC PBL indirect levels. */ @@ -10722,7 +15204,7 @@ struct hwrm_func_backing_store_cfg_input { * * TQM slowpath rings should be sized as follows: * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: * num_vnics is the number of VNICs allocated in the VNIC backing store @@ -10886,6 +15368,159 @@ struct hwrm_func_backing_store_cfg_input { uint16_t mrav_entry_size; /* Number of bytes that have been allocated for each context entry. */ uint16_t tim_entry_size; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; } __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -10946,7 +15581,7 @@ struct hwrm_func_backing_store_qcfg_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ +/* hwrm_func_backing_store_qcfg_output (size:2304b/288B) */ struct hwrm_func_backing_store_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -10971,103 +15606,121 @@ struct hwrm_func_backing_store_qcfg_output { */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \ UINT32_C(0x2) - uint8_t unused_0[4]; + uint32_t enables; /* * This bit must be '1' for the qp fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \ UINT32_C(0x1) /* * This bit must be '1' for the srq fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \ UINT32_C(0x2) /* * This bit must be '1' for the cq fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \ UINT32_C(0x4) /* * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \ UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \ UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \ UINT32_C(0x20) /* * This bit must be '1' for the tqm_ring0 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \ UINT32_C(0x40) /* * This bit must be '1' for the tqm_ring1 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \ UINT32_C(0x80) /* * This bit must be '1' for the tqm_ring2 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \ UINT32_C(0x100) /* * This bit must be '1' for the tqm_ring3 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \ UINT32_C(0x200) /* * This bit must be '1' for the tqm_ring4 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \ UINT32_C(0x400) /* * This bit must be '1' for the tqm_ring5 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \ UINT32_C(0x800) /* * This bit must be '1' for the tqm_ring6 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \ UINT32_C(0x1000) /* * This bit must be '1' for the tqm_ring7 fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \ UINT32_C(0x2000) /* * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \ UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \ UINT32_C(0x8000) + /* + * This bit must be '1' for the tqm_ring8 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the tqm_ring9 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the tqm_ring10 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \ + UINT32_C(0x40000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -11811,6 +16464,159 @@ struct hwrm_func_backing_store_qcfg_output { uint32_t mrav_num_entries; /* Number of Timer entries. */ uint32_t tim_num_entries; + /* TQM ring page size and level. */ + uint8_t tqm_ring8_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G + uint8_t ring8_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring8_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring8_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring9_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G + uint8_t ring9_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring9_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring9_page_dir; + /* TQM ring page size and level. */ + uint8_t tqm_ring10_pg_size_tqm_ring_lvl; + /* TQM ring PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \ + 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 + /* TQM ring page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \ + 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G + uint8_t ring10_unused[3]; + /* Number of TQM ring entries. */ + uint32_t tqm_ring10_num_entries; + /* TQM ring page directory. */ + uint64_t tqm_ring10_page_dir; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -12178,7 +16984,54 @@ struct hwrm_error_recovery_qcfg_output { * this much time after writing reset_reg_val in reset_reg. */ uint8_t delay_after_reset[16]; - uint8_t unused_1[7]; + /* + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12190,6 +17043,66 @@ struct hwrm_error_recovery_qcfg_output { uint8_t valid; } __rte_packed; +/*************************** + * hwrm_func_echo_response * + ****************************/ + + +/* hwrm_func_echo_response_input (size:192b/24B) */ +struct hwrm_func_echo_response_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * 0x0-0xFFF8 - The function ID + * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * 0xFFFD - Reserved for user-space HWRM interface + * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t event_data1; + uint32_t event_data2; +} __rte_packed; + +/* hwrm_func_echo_response_output (size:128b/16B) */ +struct hwrm_func_echo_response_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_func_vlan_qcfg * ***********************/ @@ -13035,6 +17948,374 @@ struct hwrm_func_host_pf_ids_query_output { uint8_t valid; } __rte_packed; +/********************* + * hwrm_func_spd_cfg * + *********************/ + + +/* hwrm_func_spd_cfg_input (size:384b/48B) */ +struct hwrm_func_spd_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Set this bit is '1' to enable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1) + /* Set this bit is '1' to disable the SPD datapath forwarding. */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2) + /* + * Set this bit is '1' to enable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4) + /* + * Set this bit is '1' to disable the SPD datapath checksum + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8) + /* + * Set this bit is '1' to enable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10) + /* + * Set this bit is '1' to disable the SPD datapath debug + * feature. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20) + uint32_t enables; + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the hash_mode_flags field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hash_type field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ring_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the hash_key_tbl_addr field to be + * configured. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \ + UINT32_C(0x10) + /* + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. + */ + uint16_t ethertype; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1; + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; +} __rte_packed; + +/* hwrm_func_spd_cfg_output (size:128b/16B) */ +struct hwrm_func_spd_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_spd_qcfg * + **********************/ + + +/* hwrm_func_spd_qcfg_input (size:128b/16B) */ +struct hwrm_func_spd_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_func_spd_qcfg_output (size:512b/64B) */ +struct hwrm_func_spd_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * The SPD datapath forwarding is currently enabled when this + * flag is set to '1'. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1) + /* + * The SPD datapath checksum feature is currently enabled when + * this flag is set to '1'. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2) + /* + * The SPD datapath debug feature is currently enabled when + * this flag is set to '1'. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4) + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1; + /* + * Ethertype value used in the encapsulated SPD packet header. + * The user must choose a value that is not conflicting with + * publicly defined ethertype values. By default, the ethertype + * value of 0xffff is used if there is no user specified value. + */ + uint16_t ethertype; + uint8_t unused_2[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /********************* * hwrm_port_phy_cfg * *********************/ @@ -13091,8 +18372,13 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ UINT32_C(0x2) /* - * When this bit is set to '1', the link shall be forced to - * the force_link_speed value. + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '0', the link shall be forced + * to the force_link_speed value. + * + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '1', the link shall be forced + * to the force_pam4_link_speed value. * * When this bit is set to '1', the HWRM client should * not enable any of the auto negotiation related @@ -13150,7 +18436,15 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x80) /* * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. + * on this port if supported. When enabled, at least one of the + * FEC modes must be advertised by enabling the fec_clause_74_enable, + * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable, + * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none + * of the FEC mode is currently enabled, the HWRM shall choose + * a default advertisement setting. + * The default advertisement setting can be queried by calling + * hwrm_port_phy_qcfg. Note that the link speed must be + * in autonegotiation mode for FEC autonegotiation to take effect. * When set to 0, then this flag shall be ignored. * If FEC autonegotiation is not supported, then the HWRM shall ignore this * flag. @@ -13159,7 +18453,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x100) /* * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port if supported. + * on this port and use forced FEC mode. In forced FEC mode, one + * or more FEC forced settings under the same clause can be set. * When set to 0, then this flag shall be ignored. * If FEC autonegotiation is not supported, then the HWRM shall ignore this * flag. @@ -13168,7 +18463,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x200) /* * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -13177,7 +18473,8 @@ struct hwrm_port_phy_cfg_input { UINT32_C(0x400) /* * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported. + * on this port if supported, by not advertising FEC CLAUSE 74 if + * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -13185,20 +18482,26 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \ UINT32_C(0x800) /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. + * When set to 1, then the HWRM shall enable FEC CLAUSE 91 + * (Reed Solomon RS(528,514) for NRZ) on this port if supported, + * by advertising FEC RS(528,514) if FEC autonegotiation is enabled + * or force enabled otherwise. In forced FEC mode, this flag + * will only take effect if the speed is NRZ. Additional + * RS544 or RS272 flags (also under clause 91) may be set for PAM4 + * in forced FEC mode. * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. + * If FEC RS(528,514) is not supported, then the HWRM shall ignore + * this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \ UINT32_C(0x1000) /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. + * When set to 1, then the HWRM shall disable FEC CLAUSE 91 + * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by + * not advertising RS(528,514) if FEC autonegotiation is enabled or + * force disabled otherwise. When set to 0, then this flag shall be + * ignored. If FEC RS(528,514) is not supported, then the HWRM + * shall ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \ UINT32_C(0x2000) @@ -13222,6 +18525,100 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ UINT32_C(0x4000) + /* + * When set to 1, then the HWRM shall enable FEC RS544_1XN + * on this port if supported, by advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs544_ieee_enable are set, the + * HWRM shall choose one of the RS544 modes. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \ + UINT32_C(0x8000) + /* + * When set to 1, then the HWRM shall disable FEC RS544_1XN + * on this port if supported, by not advertising FEC RS544_1XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \ + UINT32_C(0x10000) + /* + * When set to 1, then the HWRM shall enable FEC RS(544,514) + * on this port if supported, by advertising FEC RS(544,514) if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs544_1xn_enable are set, the + * HWRM shall choose one of the RS544 modes. + * When set to 0, then this flag shall be ignored. + * If FEC RS(544,514) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \ + UINT32_C(0x20000) + /* + * When set to 1, then the HWRM shall disable FEC RS(544,514) + * on this port if supported, by not advertising FEC RS(544,514) if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS(544,514) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \ + UINT32_C(0x40000) + /* + * When set to 1, then the HWRM shall enable FEC RS272_1XN + * on this port if supported, by advertising FEC RS272_1XN if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs272_ieee_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 + * and RS544 modes cannot be set at the same time in forced FEC mode. + * When set to 0, then this flag shall be ignored. + * If FEC RS272_1XN is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \ + UINT32_C(0x80000) + /* + * When set to 1, then the HWRM shall disable FEC RS272_1XN + * on this port if supported, by not advertising FEC RS272_1XN if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS272_1XN is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \ + UINT32_C(0x100000) + /* + * When set to 1, then the HWRM shall enable FEC RS(272,257) + * on this port if supported, by advertising FEC RS(272,257) if + * FEC autonegotiation is enabled or force enabled otherwise. + * In forced mode, this flag will only take effect if the speed is + * PAM4. If this flag and fec_rs272_1xn_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 + * and RS544 modes cannot be set at the same time in forced FEC mode. + * When set to 0, then this flag shall be ignored. + * If FEC RS(272,257) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \ + UINT32_C(0x200000) + /* + * When set to 1, then the HWRM shall disable FEC RS(272,257) + * on this port if supported, by not advertising FEC RS(272,257) if + * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 0, then this flag shall be ignored. + * If FEC RS(272,257) is not supported, then the HWRM shall ignore + * this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \ + UINT32_C(0x400000) uint32_t enables; /* * This bit must be '1' for the auto_mode field to be @@ -13289,6 +18686,18 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \ UINT32_C(0x400) + /* + * This bit must be '1' for the force_pam4_link_speed field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \ + UINT32_C(0x800) + /* + * This bit must be '1' for the auto_pam4_link_speed_mask field to + * be configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \ + UINT32_C(0x1000) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -13317,8 +18726,6 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \ @@ -13343,8 +18750,9 @@ struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* - * Select the speeds based on the corresponding link speed mask value - * that is provided. + * Select the speeds based on the corresponding link speed mask values + * that are provided. The included speeds are specified in the + * auto_link_speed and auto_pam4_link_speed fields. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \ @@ -13423,8 +18831,6 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \ @@ -13477,9 +18883,6 @@ struct hwrm_port_phy_cfg_input { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \ - UINT32_C(0x4000) /* This value controls the wirespeed feature. */ uint8_t wirespeed; /* Wirespeed feature is disabled. */ @@ -13565,7 +18968,23 @@ struct hwrm_port_phy_cfg_input { /* 10Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \ UINT32_C(0x40) - uint8_t unused_2[2]; + /* + * This is the speed that will be used if the force and force_pam4 + * bits are '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_pam4_link_speed; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \ + UINT32_C(0x7d0) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB /* * Requested setting of TX LPI timer in microseconds. * This field is valid only when EEE is enabled and TX LPI is @@ -13574,7 +18993,15 @@ struct hwrm_port_phy_cfg_input { uint32_t tx_lpi_timer; #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 - uint32_t unused_3; + /* This field specifies which PAM4 speeds are enabled for auto mode. */ + uint16_t auto_link_pam4_speed_mask; + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \ + UINT32_C(0x4) + uint8_t unused_2[2]; } __rte_packed; /* hwrm_port_phy_cfg_output (size:128b/16B) */ @@ -13687,8 +19114,54 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2) #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \ HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK - uint8_t unused_0; - /* This value indicates the current link speed of the connection. */ + uint8_t active_fec_signal_mode; + /* + * This value indicates the current link signaling mode of the + * connection. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \ + UINT32_C(0xf) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0 + /* NRZ signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \ + UINT32_C(0x0) + /* PAM4 signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 + /* This value indicates the current active FEC mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \ + UINT32_C(0xf0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4 + /* No active FEC */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \ + (UINT32_C(0x0) << 4) + /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \ + (UINT32_C(0x1) << 4) + /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \ + (UINT32_C(0x2) << 4) + /* FEC RS544_1XN active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \ + (UINT32_C(0x3) << 4) + /* FEC RS(544,528) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \ + (UINT32_C(0x4) << 4) + /* FEC RS272_1XN active, autonegotiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \ + (UINT32_C(0x5) << 4) + /* FEC RS(272,257) active, autonegoatiated or forced. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \ + (UINT32_C(0x6) << 4) + #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE + /* + * This value indicates the current link speed of the connection. + * The signal_mode field indicates if the link is using + * NRZ or PAM4 signaling. + */ uint16_t link_speed; /* 100Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1) @@ -13745,7 +19218,7 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2) /* * The supported speeds for the port. This is a bit mask. - * For each speed that is supported, the corrresponding + * For each speed that is supported, the corresponding * bit will be set to '1'. */ uint16_t support_speeds; @@ -13791,9 +19264,6 @@ struct hwrm_port_phy_qcfg_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \ - UINT32_C(0x4000) /* * Current setting of forced link speed. * When the link speed is not being forced, this @@ -13823,9 +19293,6 @@ struct hwrm_port_phy_qcfg_output { /* 100Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \ UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \ - UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \ UINT32_C(0xffff) @@ -13912,8 +19379,6 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) /* 100Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \ UINT32_C(0xffff) @@ -13969,9 +19434,6 @@ struct hwrm_port_phy_qcfg_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \ - UINT32_C(0x4000) /* Current setting for wirespeed. */ uint8_t wirespeed; /* Wirespeed feature is disabled. */ @@ -14039,6 +19501,9 @@ struct hwrm_port_phy_qcfg_output { /* Module is not inserted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ UINT32_C(0x4) + /* Module is powered down because of over current fault. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \ + UINT32_C(0x5) /* Module status is not applicable. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ UINT32_C(0xff) @@ -14429,9 +19894,6 @@ struct hwrm_port_phy_qcfg_output { * is set to 1, then all other FEC configuration flags shall be ignored. * When set to 0, then FEC is supported as indicated by other * configuration flags. - * If no cable is attached and the HWRM does not yet know the FEC - * capability, then the HWRM shall set this flag to 1 when reporting - * FEC capability. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \ UINT32_C(0x1) @@ -14455,25 +19917,91 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \ UINT32_C(0x8) /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port. + * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this + * port. This means that FEC CLAUSE 74 is either advertised if + * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled. * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \ UINT32_C(0x10) /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port. + * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for + * NRZ) is supported on this port. + * When set to 0, then FEC RS(528,418) is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \ UINT32_C(0x20) /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported. + * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for + * NRZ) is enabled on this port. This means that FEC RS(528,514) is + * either advertised if FEC autonegotiation is enabled or FEC + * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) + * is disabled if supported. * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \ UINT32_C(0x40) + /* + * When set to 1, then FEC RS544_1XN is supported on this port. + * When set to 0, then FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \ + UINT32_C(0x80) + /* + * When set to 1, then RS544_1XN is enabled on this + * port. This means that FEC RS544_1XN is either advertised if + * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled. + * When set to 0, then FEC RS544_1XN is disabled if supported. + * This flag should be ignored if FEC RS544_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \ + UINT32_C(0x100) + /* + * When set to 1, then FEC RS(544,514) is supported on this port. + * When set to 0, then FEC RS(544,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \ + UINT32_C(0x200) + /* + * When set to 1, then RS(544,514) is enabled on this + * port. This means that FEC RS(544,514) is either advertised if + * FEC autonegotiation is enabled or FEC RS(544,514) is force + * enabled. When set to 0, then FEC RS(544,514) is disabled if supported. + * This flag should be ignored if FEC RS(544,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \ + UINT32_C(0x400) + /* + * When set to 1, then FEC RS272_1XN is supported on this port. + * When set to 0, then FEC RS272_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \ + UINT32_C(0x800) + /* + * When set to 1, then RS272_1XN is enabled on this + * port. This means that FEC RS272_1XN is either advertised if + * FEC autonegotiation is enabled or FEC RS272_1XN is force + * enabled. When set to 0, then FEC RS272_1XN is disabled if supported. + * This flag should be ignored if FEC RS272_1XN is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \ + UINT32_C(0x1000) + /* + * When set to 1, then FEC RS(272,514) is supported on this port. + * When set to 0, then FEC RS(272,514) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \ + UINT32_C(0x2000) + /* + * When set to 1, then RS(272,257) is enabled on this + * port. This means that FEC RS(272,257) is either advertised if + * FEC autonegotiation is enabled or FEC RS(272,257) is force + * enabled. When set to 0, then FEC RS(272,257) is disabled if supported. + * This flag should be ignored if FEC RS(272,257) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \ + UINT32_C(0x4000) /* * This value is indicates the duplex of the current * connection state. @@ -14490,6 +20018,12 @@ struct hwrm_port_phy_qcfg_output { /* When this bit is '1', Media auto detect is enabled. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \ UINT32_C(0x1) + /* + * When this bit is '1', active_fec_signal_mode can be + * trusted. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \ + UINT32_C(0x2) /* * Up to 16 bytes of null padded ASCII string representing * PHY vendor. @@ -14504,7 +20038,63 @@ struct hwrm_port_phy_qcfg_output { * part number is not available. */ char phy_vendor_partnumber[16]; - uint8_t unused_2[7]; + /* + * The supported PAM4 speeds for the port. This is a bit mask. + * For each speed that is supported, the corresponding + * bit will be set to '1'. + */ + uint16_t support_pam4_speeds; + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \ + UINT32_C(0x4) + /* + * Current setting of forced PAM4 link speed. + * When the link speed is not being forced, this + * value shall be set to 0. + */ + uint16_t force_pam4_link_speed; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \ + UINT32_C(0x7d0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB + /* + * Current setting for auto_pam4_link_speed_mask that is used to + * advertise speeds during autonegotiation. + * This field is only valid when auto_mode is set to "mask". + * The speeds specified in this field shall be a subset of + * supported speeds on this port. + */ + uint16_t auto_pam4_link_speed_mask; + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \ + UINT32_C(0x4) + /* + * The advertised PAM4 speeds for the port by the link partner. + * Each advertised speed will be set to '1'. + */ + uint8_t link_partner_pam4_adv_speeds; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \ + UINT32_C(0x1) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \ + UINT32_C(0x2) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \ + UINT32_C(0x4) /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15010,7 +20600,7 @@ struct hwrm_port_mac_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_qcfg_output (size:192b/24B) */ +/* hwrm_port_mac_qcfg_output (size:256b/32B) */ struct hwrm_port_mac_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15250,6 +20840,20 @@ struct hwrm_port_mac_qcfg_output { UINT32_C(0xe0) #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ 5 + uint8_t unused_1; + uint16_t port_svif_info; + /* + * This field specifies the source virtual interface of the port being + * queried. Drivers can use this to program port svif field in the + * L2 context table + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \ + UINT32_C(0x7fff) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 + /* This field specifies whether port_svif is valid or not */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \ + UINT32_C(0x8000) + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15321,18 +20925,18 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ UINT32_C(0x1) - /* - * When this bit is set to '1', the PTP information is accessible - * via HWRM commands. - */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ - UINT32_C(0x2) /* * When this bit is set to '1', the device supports one-step * Tx timestamping. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \ UINT32_C(0x4) + /* + * When this bit is set to '1', the PTP information is accessible + * via HWRM commands. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ + UINT32_C(0x8) uint8_t unused_0[3]; /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ uint32_t rx_ts_reg_off_lower; @@ -15375,7 +20979,7 @@ struct hwrm_port_mac_ptp_qcfg_output { uint8_t valid; } __rte_packed; -/* Port Tx Statistics Formats */ +/* Port Tx Statistics Format */ /* tx_port_stats (size:3264b/408B) */ struct tx_port_stats { /* Total Number of 64 Bytes frames transmitted */ @@ -15516,7 +21120,7 @@ struct tx_port_stats { uint64_t tx_stat_error; } __rte_packed; -/* Port Rx Statistics Formats */ +/* Port Rx Statistics Format */ /* rx_port_stats (size:4224b/528B) */ struct rx_port_stats { /* Total Number of 64 Bytes frames received */ @@ -15768,7 +21372,18 @@ struct hwrm_port_qstats_input { uint64_t resp_addr; /* Port ID of port that is being queried. */ uint16_t port_id; - uint8_t unused_0[6]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; /* * This is the host address where * Tx port statistics will be stored @@ -15806,7 +21421,7 @@ struct hwrm_port_qstats_output { uint8_t valid; } __rte_packed; -/* Port Tx Statistics extended Formats */ +/* Port Tx Statistics extended Format */ /* tx_port_stats_ext (size:2048b/256B) */ struct tx_port_stats_ext { /* Total number of tx bytes count on cos queue 0 */ @@ -15875,7 +21490,7 @@ struct tx_port_stats_ext { uint64_t pfc_pri7_tx_transitions; } __rte_packed; -/* Port Rx Statistics extended Formats */ +/* Port Rx Statistics extended Format */ /* rx_port_stats_ext (size:3648b/456B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -15997,6 +21612,424 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos7; } __rte_packed; +/* + * Port Rx Statistics extended PFC WatchDog Format. + * StormDetect and StormRevert event determination is based + * on an integration period and a percentage threshold. + * StormDetect event - when percentage of XOFF frames received + * within an integration period exceeds the configured threshold. + * StormRevert event - when percentage of XON frames received + * within an integration period exceeds the configured threshold. + * Actual number of XOFF/XON frames for the events to be triggered + * depends on both configured integration period and sampling rate. + * The statistics in this structure represent counts of specified + * events from the moment the feature (PFC WatchDog) is enabled via + * hwrm_queue_pfc_enable_cfg call. + */ +/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */ +struct rx_port_stats_ext_pfc_wd { + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri0; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri1; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri2; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri3; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri4; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri5; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri6; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri7; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri0; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri1; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri2; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri3; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri4; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri5; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri6; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri7; + /* + * Total number of packets received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri0; + /* + * Total number of packets received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri1; + /* + * Total number of packets received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri2; + /* + * Total number of packets received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri3; + /* + * Total number of packets received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri4; + /* + * Total number of packets received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri5; + /* + * Total number of packets received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri6; + /* + * Total number of packets received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri7; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7; + /* + * Number of packets received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0; + /* + * Number of packets received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1; + /* + * Number of packets received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2; + /* + * Number of packets received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3; + /* + * Number of packets received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4; + /* + * Number of packets received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5; + /* + * Number of packets received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6; + /* + * Number of packets received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7; +} __rte_packed; + /************************ * hwrm_port_qstats_ext * ************************/ @@ -16044,7 +22077,18 @@ struct hwrm_port_qstats_ext_input { * statistics block in bytes */ uint16_t rx_stat_size; - uint8_t unused_0[2]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for the counter mask, + * representing width of each of the stats counters, rather than + * counters themselves. + */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0; /* * This is the host address where * Tx port statistics will be stored @@ -16090,6 +22134,83 @@ struct hwrm_port_qstats_ext_output { uint8_t valid; } __rte_packed; +/******************************* + * hwrm_port_qstats_ext_pfc_wd * + *******************************/ + + +/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */ +struct hwrm_port_qstats_ext_pfc_wd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + /* + * The size of rx_port_stats_ext_pfc_wd + * block in bytes + */ + uint16_t pfc_wd_stat_size; + uint8_t unused_0[4]; + /* + * This is the host address where + * rx_port_stats_ext_pfc_wd will be stored + */ + uint64_t pfc_wd_stat_host_addr; +} __rte_packed; + +/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */ +struct hwrm_port_qstats_ext_pfc_wd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The size of rx_port_stats_ext_pfc_wd + * statistics block in bytes. + */ + uint16_t pfc_wd_stat_size; + uint8_t flags; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; + uint8_t unused_0[4]; +} __rte_packed; + /************************* * hwrm_port_lpbk_qstats * *************************/ @@ -16168,6 +22289,151 @@ struct hwrm_port_lpbk_qstats_output { uint8_t valid; } __rte_packed; +/************************ + * hwrm_port_ecn_qstats * + ************************/ + + +/* hwrm_port_ecn_qstats_input (size:256b/32B) */ +struct hwrm_port_ecn_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port that is being queried. Unused if NIC is in + * multi-host mode. + */ + uint16_t port_id; + /* + * Size of the DMA buffer the caller has allocated for the firmware to + * write into. + */ + uint16_t ecn_stat_buf_size; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \ + HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[3]; + /* + * This is the host address where + * ECN port statistics will be stored + */ + uint64_t ecn_stat_host_addr; +} __rte_packed; + +/* hwrm_port_ecn_qstats_output (size:128b/16B) */ +struct hwrm_port_ecn_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes of stats the firmware wrote to the DMA buffer. */ + uint16_t ecn_stat_buf_size; + /* + * Bitmask that indicates which CoS queues have ECN marking enabled. + * Bit i corresponds to CoS queue i. + */ + uint8_t mark_en; + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* ECN mark statistics format */ +/* port_stats_ecn (size:512b/64B) */ +struct port_stats_ecn { + /* + * Number of packets marked in CoS queue 0. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos0; + /* + * Number of packets marked in CoS queue 1. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos1; + /* + * Number of packets marked in CoS queue 2. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos2; + /* + * Number of packets marked in CoS queue 3. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos3; + /* + * Number of packets marked in CoS queue 4. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos4; + /* + * Number of packets marked in CoS queue 5. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos5; + /* + * Number of packets marked in CoS queue 6. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos6; + /* + * Number of packets marked in CoS queue 7. + * Or, if the driver requested counter masks, a mask to indicate the size + * of the counter. + */ + uint64_t mark_cnt_cos7; +} __rte_packed; + /*********************** * hwrm_port_clr_stats * ***********************/ @@ -16280,7 +22546,7 @@ struct hwrm_port_phy_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_phy_qcaps_output (size:192b/24B) */ +/* hwrm_port_phy_qcaps_output (size:256b/32B) */ struct hwrm_port_phy_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -16320,12 +22586,39 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ UINT32_C(0x8) /* - * Reserved field. The HWRM shall set this field to 0. - * An HWRM client shall ignore this field. + * If set to 1, it indicates that the port counters and extended + * port counters will not reset when the firmware shuts down or + * resets the PHY. These counters will only be reset during power + * cycle or by calling HWRM_PORT_CLR_STATS. + * If set to 0, the state of the counters is unspecified when + * firmware shuts down or resets the PHY. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xf0) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \ + UINT32_C(0x10) + /* + * If set to 1, then this field indicates that the + * local loopback is not supported on this controller. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \ + UINT32_C(0x20) + /* + * If set to 1, then this field indicates that the + * PHY/Link down policy during PF shutdown is totally + * controlled by the firmware. It can shutdown the link + * even when there are active VFs associated with the PF. + * Host PF driver can send HWRM_PHY_CFG command to bring + * down the PHY even when the port is shared between VFs + * and PFs. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \ + UINT32_C(0x40) + /* + * If set to 1, this field indicates that the FCS may + * be disabled for a given packet via the transmit + * buffer descriptor. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \ + UINT32_C(0x80) /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -16389,9 +22682,6 @@ struct hwrm_port_phy_qcaps_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \ - UINT32_C(0x4000) /* * This is a bit mask to indicate what speeds are supported * for autonegotiation on this link. @@ -16441,9 +22731,6 @@ struct hwrm_port_phy_qcaps_output { /* 10Mb link speed (Full-duplex) */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \ UINT32_C(0x2000) - /* 200Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \ - UINT32_C(0x4000) /* * This is a bit mask to indicate what speeds are supported * for EEE on this link. @@ -16499,84 +22786,35 @@ struct hwrm_port_phy_qcaps_output { UINT32_C(0xffffff) #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0 /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Reserved field. The HWRM shall set this field to 0. + * An HWRM client shall ignore this field. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \ UINT32_C(0xff000000) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 -} __rte_packed; - -/**************************** - * hwrm_port_phy_mdio_write * - ****************************/ - - -/* hwrm_port_phy_mdio_write_input (size:320b/40B) */ -struct hwrm_port_phy_mdio_write_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24 /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field is used to advertise which PAM4 speeds are supported + * in auto mode. */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Reserved for future use. */ - uint32_t unused_0[2]; - /* Port ID of port. */ - uint16_t port_id; - /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */ - uint8_t phy_addr; - /* 8-bit device address. */ - uint8_t dev_addr; - /* 16-bit register address. */ - uint16_t reg_addr; - /* 16-bit register data. */ - uint16_t reg_data; + uint16_t supported_pam4_speeds_auto_mode; + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \ + UINT32_C(0x4) /* - * When this bit is set to 1 a Clause 45 mdio access is done. - * when this bit is set to 0 a Clause 22 mdio access is done. + * This field is used to advertise which PAM4 speeds are supported + * in forced mode. */ - uint8_t cl45_mdio; - /* */ - uint8_t unused_1[7]; -} __rte_packed; - -/* hwrm_port_phy_mdio_write_output (size:128b/16B) */ -struct hwrm_port_phy_mdio_write_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t supported_pam4_speeds_force_mode; + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \ + UINT32_C(0x1) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \ + UINT32_C(0x4) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16587,13 +22825,90 @@ struct hwrm_port_phy_mdio_write_output { uint8_t valid; } __rte_packed; -/*************************** - * hwrm_port_phy_mdio_read * - ***************************/ +/**************************** + * hwrm_port_phy_mdio_write * + ****************************/ -/* hwrm_port_phy_mdio_read_input (size:256b/32B) */ -struct hwrm_port_phy_mdio_read_input { +/* hwrm_port_phy_mdio_write_input (size:320b/40B) */ +struct hwrm_port_phy_mdio_write_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Reserved for future use. */ + uint32_t unused_0[2]; + /* Port ID of port. */ + uint16_t port_id; + /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */ + uint8_t phy_addr; + /* 8-bit device address. */ + uint8_t dev_addr; + /* 16-bit register address. */ + uint16_t reg_addr; + /* 16-bit register data. */ + uint16_t reg_data; + /* + * When this bit is set to 1 a Clause 45 mdio access is done. + * when this bit is set to 0 a Clause 22 mdio access is done. + */ + uint8_t cl45_mdio; + /* */ + uint8_t unused_1[7]; +} __rte_packed; + +/* hwrm_port_phy_mdio_write_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_write_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_port_phy_mdio_read * + ***************************/ + + +/* hwrm_port_phy_mdio_read_input (size:256b/32B) */ +struct hwrm_port_phy_mdio_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18424,6 +24739,161 @@ struct hwrm_port_phy_mdio_bus_release_output { uint8_t valid; } __rte_packed; +/************************ + * hwrm_port_tx_fir_cfg * + ************************/ + + +/* hwrm_port_tx_fir_cfg_input (size:320b/40B) */ +struct hwrm_port_tx_fir_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Modulation types of TX FIR: NRZ, PAM4. */ + uint8_t mod_type; + /* For NRZ */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \ + HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 + /* The lane mask of the lane TX FIR will be configured. */ + uint8_t lane_mask; + uint8_t unused_0[2]; + /* Value1 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_1; + /* Value2 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_2; + /* Value3 of TX FIR, required for PAM4. */ + uint32_t txfir_val_3; + /* Value4 of TX FIR, required for PAM4. */ + uint32_t txfir_val_4; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_tx_fir_cfg_output (size:128b/16B) */ +struct hwrm_port_tx_fir_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_port_tx_fir_qcfg * + *************************/ + + +/* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */ +struct hwrm_port_tx_fir_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Modulation types of TX FIR: NRZ, PAM4. */ + uint8_t mod_type; + /* For NRZ */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \ + HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 + /* The ID of the lane TX FIR will be queried. */ + uint8_t lane_id; + uint8_t unused[6]; +} __rte_packed; + +/* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */ +struct hwrm_port_tx_fir_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Value1 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_1; + /* Value2 of TX FIR, required for NRZ or PAM4. */ + uint32_t txfir_val_2; + /* Value3 of TX FIR, required for PAM4. */ + uint32_t txfir_val_3; + /* Value4 of TX FIR, required for PAM4. */ + uint32_t txfir_val_4; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -18491,7 +24961,7 @@ struct hwrm_queue_qportcfg_input { uint8_t unused_0; } __rte_packed; -/* hwrm_queue_qportcfg_output (size:256b/32B) */ +/* hwrm_queue_qportcfg_output (size:1344b/168B) */ struct hwrm_queue_qportcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -18587,27 +25057,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id0; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id0_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18623,27 +25095,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id1; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id1_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18659,27 +25133,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id2; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id2_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18695,27 +25171,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id3; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id3_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18731,27 +25209,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id4; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id4_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18767,27 +25247,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id5; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id5_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18803,27 +25285,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id6; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id6_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18839,27 +25323,29 @@ struct hwrm_queue_qportcfg_output { * that takes a queue id. * # IDs must always be queried by this command before any use * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. + * # The CoS queue index is obtained by applying modulo 10 to the + * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7. + * The CoS queue index is used to reference port statistics for the + * CoS queue. * # A value of 0xff indicates that the queue is not available. * # Available queues may not be in sequential order. */ uint8_t queue_id7; - /* This value is applicable to CoS queues only. */ + /* This value specifies service profile kind for CoS queue */ uint8_t queue_id7_service_profile; /* Lossy (best-effort) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ UINT32_C(0x0) - /* Lossless (legacy) */ + /* Lossless */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* Lossless RoCE */ + /* Lossless RoCE (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ UINT32_C(0x1) - /* Lossy RoCE CNP */ + /* Lossy RoCE CNP (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* Lossless NIC */ + /* Lossless NIC (deprecated) */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ UINT32_C(0x3) /* Set to 0xFF... (All Fs) if there is no service profile specified */ @@ -18868,103 +25354,153 @@ struct hwrm_queue_qportcfg_output { #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - uint8_t valid; -} __rte_packed; - -/******************* - * hwrm_queue_qcfg * - *******************/ - - -/* hwrm_queue_qcfg_input (size:192b/24B) */ -struct hwrm_queue_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint8_t queue_id0_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; + * Up to 16 bytes of null padded ASCII string describing this queue. + * The queue name includes a CoS queue index and, in some cases, text + * that distinguishes the queue from other queues in the group. + */ + char qid0_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid1_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid2_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid3_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid4_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid5_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid6_name[16]; + /* Up to 16 bytes of null padded ASCII string describing this queue. */ + char qid7_name[16]; + /* + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. + */ + uint8_t queue_id1_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - uint16_t seq_id; + uint8_t queue_id2_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - uint16_t target_id; + uint8_t queue_id3_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - uint64_t resp_addr; - uint32_t flags; + uint8_t queue_id4_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX - /* Queue ID of the queue. */ - uint32_t queue_id; -} __rte_packed; - -/* hwrm_queue_qcfg_output (size:128b/16B) */ -struct hwrm_queue_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t queue_id5_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * This value is the estimate packet length used in the - * TX arbiter. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - uint32_t queue_len; - /* This value is applicable to CoS queues only. */ - uint8_t service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) - /* Lossless */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN - /* Information about queue configuration. */ - uint8_t queue_cfg_info; + uint8_t queue_id6_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \ + UINT32_C(0x1) + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* - * If this flag is set to '1', then the queue is - * configured asymmetrically on TX and RX sides. - * If this flag is set to '0', then this queue is - * configured symmetrically on TX and RX sides. + * This value specifies traffic type for the service profile. We can + * have a TC mapped to multiple traffic types. For example shared + * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6). + * A value of zero is considered as invalid. */ - #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + uint8_t queue_id7_service_profile_type; + /* Recommended to be used for RoCE traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \ UINT32_C(0x1) - uint8_t unused_0; + /* Recommended to be used for NIC/L2 traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \ + UINT32_C(0x2) + /* Recommended to be used for CNP traffic only. */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \ + UINT32_C(0x4) /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18975,13 +25511,111 @@ struct hwrm_queue_qcfg_output { uint8_t valid; } __rte_packed; -/****************** - * hwrm_queue_cfg * - ******************/ +/******************* + * hwrm_queue_qcfg * + *******************/ -/* hwrm_queue_cfg_input (size:320b/40B) */ -struct hwrm_queue_cfg_input { +/* hwrm_queue_qcfg_input (size:192b/24B) */ +struct hwrm_queue_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX + /* Queue ID of the queue. */ + uint32_t queue_id; +} __rte_packed; + +/* hwrm_queue_qcfg_output (size:128b/16B) */ +struct hwrm_queue_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This value is the estimate packet length used in the + * TX arbiter. + */ + uint32_t queue_len; + /* This value is applicable to CoS queues only. */ + uint8_t service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN + /* Information about queue configuration. */ + uint8_t queue_cfg_info; + /* + * If this flag is set to '1', then the queue is + * configured asymmetrically on TX and RX sides. + * If this flag is set to '0', then this queue is + * configured symmetrically on TX and RX sides. + */ + #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + UINT32_C(0x1) + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_queue_cfg * + ******************/ + + +/* hwrm_queue_cfg_input (size:320b/40B) */ +struct hwrm_queue_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19158,6 +25792,30 @@ struct hwrm_queue_pfcenable_qcfg_output { /* If set to 1, then PFC is enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -19229,6 +25887,30 @@ struct hwrm_queue_pfcenable_cfg_input { /* If set to 1, then PFC is requested to be enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed @@ -21570,139 +28252,6649 @@ struct hwrm_queue_cos2bw_cfg_input { * 0..7 - Valid values. * 8..255 - Reserved. */ - uint8_t queue_id6_pri_lvl; + uint8_t queue_id6_pri_lvl; + /* + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. + */ + uint8_t queue_id6_bw_weight; + /* ID of CoS Queue 7. */ + uint8_t queue_id7; + /* + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id7_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id7_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id7_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) + /* + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. + */ + uint8_t queue_id7_pri_lvl; + /* + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. + */ + uint8_t queue_id7_bw_weight; + uint8_t unused_1[5]; +} __rte_packed; + +/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ +struct hwrm_queue_cos2bw_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ + + +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ + + +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; + /* + * This is the default PRI which un-initialized DSCP values are + * mapped to. + */ + uint8_t default_pri; + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ + + +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. + */ + uint64_t src_data_addr; + uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the default_pri field to be + * configured. + */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + UINT32_C(0x1) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + /* + * This is the default PRI which un-initialized DSCP values will be + * mapped to. + */ + uint8_t default_pri; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. + */ + uint16_t entry_cnt; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_queue_mpls_qcaps * + *************************/ + + +/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ +struct hwrm_queue_mpls_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ +struct hwrm_queue_mpls_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which queues can be configured by the + * hwrm_queue_mplstc2pri_cfg command. + * + * Each bit represents a specific pri where bit 0 represents + * pri 0 and bit 7 represents pri 7. + * # A value of 0 indicates that the pri is not configurable + * by the hwrm_queue_mplstc2pri_cfg command. + * # A value of 1 indicates that the pri is configurable. + * # A hwrm_queue_mplstc2pri_cfg command shall return error when + * trying to configure a pri that is not configurable. + */ + uint8_t queue_mplstc2pri_cfg_allowed; + /* + * This is the default PRI which un-initialized MPLS values will be + * mapped to. + */ + uint8_t hw_default_pri; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_mplstc2pri_qcfg * + ******************************/ + + +/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 0. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 1. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 2. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 3. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 4. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 5. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 6. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 7. + */ + uint8_t tc7_pri_queue_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_queue_mplstc2pri_cfg * + *****************************/ + + +/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_mplstc2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the mplstc0_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mplstc1_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the mplstc2_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the mplstc3_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the mplstc4_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the mplstc5_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the mplstc6_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the mplstc7_pri_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP)to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * pri assigned to MPLS TC(EXP) 0. This value can only + * be changed before traffic has started. + */ + uint8_t tc0_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 1. This value can only + * be changed before traffic has started. + */ + uint8_t tc1_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 2 This value can only + * be changed before traffic has started. + */ + uint8_t tc2_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 3. This value can only + * be changed before traffic has started. + */ + uint8_t tc3_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 4. This value can only + * be changed before traffic has started. + */ + uint8_t tc4_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 5. This value can only + * be changed before traffic has started. + */ + uint8_t tc5_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + */ + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + */ + uint8_t tc7_pri_queue_id; +} __rte_packed; + +/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_mplstc2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_queue_vlanpri_qcaps * + ****************************/ + + +/* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */ +struct hwrm_queue_vlanpri_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */ +struct hwrm_queue_vlanpri_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the default user priority which all VLAN priority values + * are mapped to if there is no VLAN priority to user priority mapping. + */ + uint8_t hw_default_pri; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_queue_vlanpri2pri_qcfg * + *******************************/ + + +/* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; + /* + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. + */ + uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_vnic_alloc * + *******************/ + + +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', proxy VEE PF is requesting + * allocation of a default VNIC on behalf of virtio-net + * function given in virtio_net_fid field. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \ + UINT32_C(0x2) + /* + * Virtio-net function's FID. + * This virtio-net function is requesting allocation of default + * VNIC through proxy VEE PF. + */ + uint16_t virtio_net_fid; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_vnic_update * + ********************/ + + +/* hwrm_vnic_update_input (size:256b/32B) */ +struct hwrm_vnic_update_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint32_t enables; + /* + * This bit must be '1' for the vnic_state field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the metadata_format_type field to be + * configured. + */ + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \ + UINT32_C(0x4) + /* + * This will update the context variable with the same name if + * the corresponding enable is set. + */ + uint8_t vnic_state; + /* Normal operation state for the VNIC. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* All packets are dropped in this state. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \ + HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP + /* + * The metadata format type used in all the RX packet completions + * going through this VNIC. + */ + uint8_t metadata_format_type; + /* No metadata information. */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \ + UINT32_C(0x0) + /* + * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], + * vtag[19:0]). + */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \ + UINT32_C(0x1) + /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \ + UINT32_C(0x2) + /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \ + UINT32_C(0x3) + /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \ + UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \ + HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_vnic_update_output (size:128b/16B) */ +struct hwrm_vnic_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_vnic_free * + ******************/ + + +/* hwrm_vnic_free_input (size:192b/24B) */ +struct hwrm_vnic_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_free_output (size:128b/16B) */ +struct hwrm_vnic_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_vnic_cfg * + *****************/ + + +/* hwrm_vnic_cfg_input (size:384b/48B) */ +struct hwrm_vnic_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the VNIC is requested to + * be the default VNIC for the function. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is being configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is being configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is being configured to be + * disabled on this VNIC. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to be + * operating in dual VNIC mode. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ + UINT32_C(0x8) + /* + * When this flag is set to '1', the VNIC is requested to + * be configured to receive only RoCE traffic. + * If this flag is set to '0', then this flag shall be + * ignored by the HWRM. + * If roce_dual_vnic_mode flag is set to '1' + * or roce_mirroring_capable_vnic_mode flag to 1, + * then the HWRM client shall not set this flag to '1'. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ + UINT32_C(0x10) + /* + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * This flag is used to enable a mode where + * RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured using hwrm_vnic_rss_cfg. + * + * If this mode is enabled, then the driver should not program + * RSS indirection table for the RSS context that is used for + * computing RSS hash only. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic, but forward only the + * RoCE traffic further. Also, RoCE traffic can be mirrored to + * L2 driver. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ + UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the dflt_ring_grp field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the rss_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cos_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the lb_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ + UINT32_C(0x8) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ + UINT32_C(0x10) + /* + * This bit must be '1' for the default_rx_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the default_cmpl_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the queue_id field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \ + UINT32_C(0x80) + /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \ + UINT32_C(0x100) + /* Logical vnic ID */ + uint16_t vnic_id; + /* + * Default Completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules and if + * there is no COS rule. + */ + uint16_t dflt_ring_grp; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + /* + * Default Rx ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + * The aggregation ring associated with the Rx ring is + * implied based on the Rx ring specified when the + * aggregation ring was allocated. + */ + uint16_t default_rx_ring_id; + /* + * Default completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + */ + uint16_t default_cmpl_ring_id; + /* + * When specified, only incoming packets classified to the specified CoS + * queue ID will be arriving on this VNIC. Packet priority to CoS mapping + * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, + * ntuple filters with VNIC destination specified are invalid since they + * conflict with the CoS to VNIC steering rules in this mode. + * + * If this field is not specified, packet to VNIC steering will be + * subject to the standard L2 filter rules and any additional ntuple + * filter rules with destination VNIC specified. + */ + uint16_t queue_id; + /* + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the two RX checksum modes supported by these + * completion records. + */ + uint8_t rx_csum_v2_mode; + /* + * When configured with this checksum mode, the number of header + * groups in the delivered packet with a valid IP checksum and + * the number of header groups in the delivered packet with a valid + * L4 checksum are reported. Valid checksums are counted from the + * outermost header group to the innermost header group, stopping at + * the first error. This is the default checksum mode supported if + * the driver doesn't explicitly configure the RX checksum mode. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this checksum mode, the checksum status is + * reported using 'all ok' mode. In the RX completion record, one + * bit indicates if the IP checksum is valid for all the parsed + * header groups with an IP checksum. Another bit indicates if the + * L4 checksum is valid for all the parsed header groups with an L4 + * checksum. The number of header groups that were parsed by the + * chip and passed in the delivered packet is also reported. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused0[5]; +} __rte_packed; + +/* hwrm_vnic_cfg_output (size:128b/16B) */ +struct hwrm_vnic_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_vnic_qcfg * + ******************/ + + +/* hwrm_vnic_qcfg_input (size:256b/32B) */ +struct hwrm_vnic_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id_valid field to be + * configured. + */ + #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + /* Logical vnic ID */ + uint32_t vnic_id; + /* ID of Virtual Function whose VNIC resource is being queried. */ + uint16_t vf_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_vnic_qcfg_output (size:256b/32B) */ +struct hwrm_vnic_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Default Completion ring for the VNIC. */ + uint16_t dflt_ring_grp; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* The maximum receive unit of the vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* + * When this bit is '1', the VNIC is the default VNIC for + * the function. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is disabled on + * this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to + * operate in dual VNIC mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ + UINT32_C(0x8) + /* + * When this flag is set to '1', the VNIC is configured to + * receive only RoCE traffic. + * When this flag is set to '0', the VNIC is not configured + * to receive only RoCE traffic. + * If roce_dual_vnic_mode flag and this flag both are set + * to '1', then it is an invalid configuration of the + * VNIC. The HWRM should not allow that type of + * mis-configuration by HWRM clients. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ + UINT32_C(0x10) + /* + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * When this bit is set to '1', then the VNIC is enabled in a + * mode where RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic, but forward only + * RoCE traffic further. Also RoCE traffic can be mirrored to + * L2 driver. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ + UINT32_C(0x40) + /* + * When this bit is '0', VNIC is in normal operation state. + * When this bit is '1', VNIC drops all the received packets. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \ + UINT32_C(0x80) + /* + * When returned with a valid CoS Queue id, the CoS Queue/VNIC association + * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS + * queue association. + */ + uint16_t queue_id; + /* + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the current RX checksum mode configured for all the + * RX rings of a VNIC. + */ + uint8_t rx_csum_v2_mode; + /* + * This value indicates that the VNIC is configured to use the + * default RX checksum mode for all the rings associated with this + * VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured to use the RX + * checksum ‘all_ok’ mode for all the rings associated with this + * VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused_1[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_vnic_qcaps * + *******************/ + + +/* hwrm_vnic_qcaps_input (size:192b/24B) */ +struct hwrm_vnic_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_qcaps_output (size:192b/24B) */ +struct hwrm_vnic_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The maximum receive unit that is settable on a vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* Unused. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ + UINT32_C(0x1) + /* + * When this bit is '1', the capability of stripping VLAN in + * the RX path is supported on VNIC(s). + * If set to '0', then VLAN stripping capability is + * not supported on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ + UINT32_C(0x2) + /* + * When this bit is '1', the capability to buffer receive + * packets in the hardware until the host posts new receive buffers + * is supported on VNIC(s). + * If set to '0', then bd_stall capability is not supported + * on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ + UINT32_C(0x4) + /* + * When this bit is '1', the capability to + * receive both RoCE and non-RoCE traffic on VNIC(s) is + * supported. + * If set to '0', then the capability to receive + * both RoCE and non-RoCE traffic on VNIC(s) is + * not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ + UINT32_C(0x8) + /* + * When this bit is set to '1', the capability to configure + * a VNIC to receive only RoCE traffic is supported. + * When this flag is set to '0', the VNIC capability to + * configure to receive only RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ + UINT32_C(0x10) + /* + * When this bit is set to '1', then the capability to enable + * a VNIC in a mode where RSS context without configuring + * RSS indirection table is supported (for RSS hash computation). + * When this bit is set to '0', then a VNIC can not be configured + * with a mode to enable RSS context without configuring RSS + * indirection table. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ + UINT32_C(0x20) + /* + * When this bit is '1', the capability to + * mirror the the RoCE traffic is supported. + * If set to '0', then the capability to mirror the + * RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ + UINT32_C(0x40) + /* + * When this bit is '1', the outermost RSS hashing capability + * is supported. If set to '0', then the outermost RSS hashing + * capability is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates that firmware supports the + * ability to steer incoming packets from one CoS queue to one + * VNIC. This optional feature can then be enabled + * using HWRM_VNIC_CFG on any VNIC. This feature is only + * available when NVM option “enable_cos_classfication” is set + * to 1. If set to '0', firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V2 and RX TPA start V2 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. Additionally, two new RX + * checksum features supported by these ompletion records can be + * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \ + UINT32_C(0x200) + /* + * When this bit is '1', it indicates that HW and firmware support + * vnic state change. Host drivers can change the vnic state using + * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not + * support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \ + UINT32_C(0x400) + /* + * When this bit is '1', it indicates that firmware supports + * virtio-net functions default VNIC allocation using + * HWRM_VNIC_ALLOC. + * This capability is available only on Proxy VEE PF. If set to '0', + * firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \ + UINT32_C(0x800) + /* + * When this bit is set '1', then the capability to configure the + * metadata format in the RX completion is supported for the VNIC. + * When this bit is set to '0', then the capability to configure + * the metadata format in the RX completion is not supported for + * the VNIC. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ + UINT32_C(0x1000) + /* + * This field advertises the maximum concurrent TPA aggregations + * supported by the VNIC on new devices that support TPA v2. + * '0' means that TPA v2 is not supported. + */ + uint16_t max_aggs_supported; + uint8_t unused_1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_vnic_tpa_cfg * + *********************/ + + +/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ +struct hwrm_vnic_tpa_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + UINT32_C(0x8) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + UINT32_C(0x10) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + UINT32_C(0x20) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + UINT32_C(0x40) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) + * value. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + UINT32_C(0x80) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall DMA payload data using GRO rules. + * When this bit is '0', the VNIC shall DMA payload data + * using the more efficient LRO rules of filling all + * aggregation buffers. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \ + UINT32_C(0x100) + uint32_t enables; + /* + * This bit must be '1' for the max_agg_segs field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + /* + * This bit must be '1' for the max_aggs field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + /* + * This bit must be '1' for the max_agg_timer field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + /* deprecated bit. Do not use!!! */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + /* Logical vnic ID */ + uint16_t vnic_id; + /* + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. On new + * devices supporting TPA v2, the unit is multiples of 4 and + * valid values are > 0 and <= 63. + */ + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX + /* + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7. On new devices + * supporting TPA v2, this is in unit of 1 and must be > 0 + * and <= max_aggs_supported in the hwrm_vnic_qcaps response + * to enable TPA v2. + */ + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX + uint8_t unused_0[2]; + /* + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. + */ + uint32_t max_agg_timer; + /* + * This is the minimum amount of payload length required to + * start an aggregation context. This field is deprecated and + * should be set to 0. The minimum length is set by firmware + * and can be queried using hwrm_vnic_tpa_qcfg. + */ + uint32_t min_agg_len; +} __rte_packed; + +/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ +struct hwrm_vnic_tpa_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_vnic_rss_cfg * + *********************/ + + +/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ +struct hwrm_vnic_rss_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* VNIC ID of VNIC associated with RSS table being configured. */ + uint16_t vnic_id; + /* + * Specifies which VNIC ring table pair to configure. + * Valid values range from 0 to 7. + */ + uint8_t ring_table_pair_index; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ +struct hwrm_vnic_rss_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ +struct hwrm_vnic_rss_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* + * Unable to change global RSS mode to outer due to all active + * interfaces are not ready to support outer RSS hashing. + */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \ + UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ + HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY + uint8_t unused_0[7]; +} __rte_packed; + +/********************** + * hwrm_vnic_rss_qcfg * + **********************/ + + +/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_rss_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ +struct hwrm_vnic_rss_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint8_t unused_0[4]; + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_vnic_plcmodes_cfg * + **************************/ + + +/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ +struct hwrm_vnic_plcmodes_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the VNIC shall be configured to + * use regular placement algorithm. + * By default, the regular placement algorithm shall be + * enabled on the VNIC. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC shall be configured + * use the jumbo placement algorithm. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv4 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv4, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv4, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv4 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv4 + * packet. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv6 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv6, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv6, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv6 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv6 + * packet. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) + /* + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for FCoE packets at the + * beginning of FC payload. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) + /* + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for RoCE packets at the + * beginning of RoCE payload (after BTH/GRH headers). + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC shall be configured use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the jumbo_thresh_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the hds_offset_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hds_threshold_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the max_bds_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \ + UINT32_C(0x8) + /* Logical vnic ID */ + uint32_t vnic_id; + /* + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. + */ + uint16_t jumbo_thresh; + /* + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. + */ + uint16_t hds_offset; + /* + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. + */ + uint16_t hds_threshold; + /* + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is + * supported on the function. + */ + uint16_t max_bds; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ +struct hwrm_vnic_plcmodes_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_vnic_plcmodes_qcfg * + ***************************/ + + +/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', the VNIC is configured to + * use regular placement algorithm. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to + * use the jumbo placement algorithm. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv4 packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv6 packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for FCoE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for RoCE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is configured + * to be the default VNIC of the requesting function. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ + UINT32_C(0x40) + /* + * When this bit is '1', the VNIC is configured to use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x80) + /* + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. + */ + uint16_t jumbo_thresh; + /* + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. + */ + uint16_t hds_offset; + /* + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. + */ + uint16_t hds_threshold; + /* + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is supported + * on the function + */ + uint16_t max_bds; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_vnic_rss_cos_lb_ctx_alloc * + **********************************/ + + +/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_vnic_rss_cos_lb_ctx_free * + *********************************/ + + +/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_ring_alloc * + *******************/ + + +/* hwrm_ring_alloc_input (size:704b/88B) */ +struct hwrm_ring_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the ring_arb_cfg field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ + UINT32_C(0x2) + /* + * This bit must be '1' for the stat_ctx_id_valid field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the max_bw_valid field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the rx_ring_id field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the nq_ring_id field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ + UINT32_C(0x80) + /* + * This bit must be '1' for the rx_buf_size field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ + UINT32_C(0x100) + /* + * This bit must be '1' for the schq_id field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x200) + /* + * This bit must be '1' for the mpc_chnls_type field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \ + UINT32_C(0x400) + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ + HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ + uint8_t unused_0; + /* Ring allocation flags. */ + uint16_t flags; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B or 2B offset from the start of the Rx packet buffer. When + * '1', the received packet will be padded with 2B of zeros at the + * front of the packet. Note that this flag is only used for + * Rx rings and is ignored for all other rings included Rx + * Aggregation rings. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) + /* + * This value is a pointer to the page table for the + * Ring. + */ + uint64_t page_tbl_addr; + /* First Byte Offset of the first entry in the first page. */ + uint32_t fbo; + /* + * Actual page size in 2^page_size. The supported range is increments + * in powers of 2 from 16 bytes to 1GB. + * - 4 = 16 B + * Page size is 16 B. + * - 12 = 4 KB + * Page size is 4 KB. + * - 13 = 8 KB + * Page size is 8 KB. + * - 16 = 64 KB + * Page size is 64 KB. + * - 21 = 2 MB + * Page size is 2 MB. + * - 22 = 4 MB + * Page size is 4 MB. + * - 30 = 1 GB + * Page size is 1 GB. + */ + uint8_t page_size; + /* + * This value indicates the depth of page table. + * For this version of the specification, value other than 0 or + * 1 shall be considered as an invalid value. + * When the page_tbl_depth = 0, then it is treated as a + * special case with the following. + * 1. FBO and page size fields are not valid. + * 2. page_tbl_addr is the physical address of the first + * element of the ring. + */ + uint8_t page_tbl_depth; + /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ + uint16_t schq_id; + /* + * Number of 16B units in the ring. Minimum size for + * a ring is 16 16B entries. + */ + uint32_t length; + /* + * Logical ring number for the ring to be allocated. + * This value determines the position in the doorbell + * area where the update to the ring will be made. + * + * For completion rings, this value is also the MSI-X + * vector number for the function the completion ring is + * associated with. + */ + uint16_t logical_id; + /* + * This field is used only when ring_type is a TX ring. + * This value indicates what completion ring the TX ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * This field is used only when ring_type is a TX ring. + * This value indicates what CoS queue the TX ring + * is associated with. + */ + uint16_t queue_id; + /* + * When allocating a Rx ring or Rx aggregation ring, this field + * specifies the size of the buffer descriptors posted to the ring. + */ + uint16_t rx_buf_size; + /* + * When allocating an Rx aggregation ring, this field + * specifies the associated Rx ring ID. + */ + uint16_t rx_ring_id; + /* + * When allocating a completion ring, this field + * specifies the associated NQ ring ID. + */ + uint16_t nq_ring_id; + /* + * This field is used only when ring_type is a TX ring. + * This field is used to configure arbitration related + * parameters for a TX ring. + */ + uint16_t ring_arb_cfg; + /* Arbitration policy used for the ring. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ + UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + /* + * Use strict priority for the TX ring. + * Priority value is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ + UINT32_C(0x1) + /* + * Use weighted fair queue arbitration for the TX ring. + * Weight is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ + UINT32_C(0x2) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ + HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ + /* Reserved field. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + /* + * Arbitration policy specific parameter. + * # For strict priority arbitration policy, this field + * represents a priority value. If set to 0, then the priority + * is not specified and the HWRM is allowed to select + * any priority for this TX ring. + * # For weighted fair queue arbitration policy, this field + * represents a weight value. If set to 0, then the weight + * is not specified and the HWRM is allowed to select + * any weight for this TX ring. + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ + UINT32_C(0xff00) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 + uint16_t unused_3; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved3; + /* + * This field is used only when ring_type is a TX ring. + * This input indicates what statistics context this ring + * should be associated with. + */ + uint32_t stat_ctx_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved4; + /* + * This field is used only when ring_type is a TX ring + * to specify maximum BW allocated to the TX ring. + * The HWRM will translate this value into byte counter and + * time interval used for this ring inside the device. + */ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * This field is used only when ring_type is a Completion ring. + * This value indicates what interrupt mode should be used + * on this completion ring. + * Note: In the legacy interrupt mode, no more than 16 + * completion rings are allowed. + */ + uint8_t int_mode; + /* Legacy INTA */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) + /* Reserved */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) + /* MSI-X */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) + /* No Interrupt - Polled mode */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ + HWRM_RING_ALLOC_INPUT_INT_MODE_POLL + /* Midpath channel type */ + uint8_t mpc_chnls_type; + /* + * Indicate the TX ring alloc MPC channel type is a MPC channel + * with destination to the TX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the TX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the primate processor block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \ + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE + uint8_t unused_4[2]; + /* + * The cq_handle is specified when allocating a completion ring. For + * devices that support NQs, this cq_handle will be included in the + * NQE to specify which CQ should be read to retrieve the completion + * record. + */ + uint64_t cq_handle; +} __rte_packed; + +/* hwrm_ring_alloc_output (size:128b/16B) */ +struct hwrm_ring_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Physical number of ring allocated. + * This value shall be unique for a ring type. + */ + uint16_t ring_id; + /* Logical number of ring allocated. */ + uint16_t logical_ring_id; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[2]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_ring_free * + ******************/ + + +/* hwrm_ring_free_input (size:192b/24B) */ +struct hwrm_ring_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ + HWRM_RING_FREE_INPUT_RING_TYPE_NQ + uint8_t unused_0; + /* Physical number of ring allocated. */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_free_output (size:128b/16B) */ +struct hwrm_ring_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_ring_reset * + *******************/ + + +/* hwrm_ring_reset_input (size:192b/24B) */ +struct hwrm_ring_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* + * Rx Ring Group. This is to reset rx and aggregation in an atomic + * operation. Completion ring associated with this ring group is + * not reset. + */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6) + #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ + HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP + uint8_t unused_0; + /* + * Physical number of the ring. When ring type is rx_ring_grp, ring id + * actually refers to ring group id. + */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_reset_output (size:128b/16B) */ +struct hwrm_ring_reset_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \ + UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \ + UINT32_C(0x1) + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \ + HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[3]; + /* Position of consumer index after ring reset completes. */ + uint8_t consumer_idx[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_ring_cfg * + *****************/ + + +/* hwrm_ring_cfg_input (size:320b/40B) */ +struct hwrm_ring_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_CFG_INPUT_RING_TYPE_RX + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \ + UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \ + UINT32_C(0x2) + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid + * is used as source interface of the transmitted packets. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ + UINT32_C(0x4) + /* The schq_id field is valid */ + #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \ + UINT32_C(0x8) + /* Update completion ring ID associated with Tx or Rx ring. */ + #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \ + UINT32_C(0x10) + /* + * When set to '1', metadata value provided by tx_metadata + * field in this command is inserted in the lb_header_metadata + * QP context field. When set to '0', no change done to metadata. + * Firmware rejects the tx ring metadata programming with + * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD + * metadata feature is not disabled. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \ + UINT32_C(0x20) + /* + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from + * the TX ring. + */ + uint16_t proxy_fid; + /* + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated + * with the default scheduler queue (SCHQ). + */ + uint16_t schq_id; + /* + * This field is valid for TX or Rx rings. This value identifies the + * new completion ring ID to associate with the TX or Rx ring. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_1[3]; + /* + * When tx_metadata enable bit is set, value specified in this field + * is copied to lb_header_metadata in the QP context. + */ + uint32_t tx_metadata; + uint8_t unused_2[4]; +} __rte_packed; + +/* hwrm_ring_cfg_output (size:128b/16B) */ +struct hwrm_ring_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_ring_qcfg * + ******************/ + + +/* hwrm_ring_qcfg_input (size:192b/24B) */ +struct hwrm_ring_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_QCFG_INPUT_RING_TYPE_RX + uint8_t unused_0[5]; + /* Physical number of the ring. */ + uint16_t ring_id; +} __rte_packed; + +/* hwrm_ring_qcfg_output (size:256b/32B) */ +struct hwrm_ring_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \ + UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \ + UINT32_C(0x2) + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid is + * used as source interface of the transmitted packets. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ + UINT32_C(0x4) + /* + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from the TX + * ring. + */ + uint16_t proxy_fid; + /* + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated with + * the default scheduler queue (SCHQ). + */ + uint16_t schq_id; + /* + * This field is used when ring_type is a TX or Rx ring. + * This value indicates what completion ring the TX or Rx ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_0[3]; + /* lb_header_metadata in the QP context is copied to this field. */ + uint32_t tx_metadata; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_ring_aggint_qcaps * + **************************/ + + +/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ +struct hwrm_ring_aggint_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ +struct hwrm_ring_aggint_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t cmpl_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* + * When this bit is set to '1', int_lat_tmr_max can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + UINT32_C(0x2) + /* + * When this bit is set to '1', timer_reset can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + UINT32_C(0x4) + /* + * When this bit is set to '1', ring_idle can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + UINT32_C(0x8) + /* + * When this bit is set to '1', num_cmpl_dma_aggr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x10) + /* + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x40) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ + UINT32_C(0x80) + /* + * When this bit is set to '1', num_cmpl_aggr_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ + UINT32_C(0x100) + uint32_t nq_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on notification queues. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* Minimum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_min; + /* Maximum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_max; + /* Minimum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_min; + /* Maximum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_max; + /* Minimum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_min; + /* Maximum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_max; + /* Minimum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_min; + /* Maximum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_max; + /* Minimum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_min; + /* Maximum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_max; + /* Minimum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_min; + /* Maximum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_max; + /* Minimum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_min; + /* Maximum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_max; + /* The units for timer parameters, in nanoseconds. */ + uint16_t timer_units; + uint8_t unused_0[1]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************** + * hwrm_ring_cmpl_ring_qaggint_params * + **************************************/ + + +/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \ + UINT32_C(0x3) + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0 + /* + * Set this flag to 1 when querying parameters on a notification + * queue. Set this flag to 0 when querying parameters on a + * completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t flags; + /* + * When this bit is set to '1', interrupt max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA when in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************************** + * hwrm_ring_cmpl_ring_cfg_aggint_params * + *****************************************/ + + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + /* + * When this bit is set to '1', interrupt latency max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) + /* + * Set this flag to 1 when configuring parameters on a + * notification queue. Set this flag to 0 when configuring + * parameters on a completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA while in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + /* + * Bitfield that indicates which parameters are to be applied. Only + * required when configuring devices with notification queues, and + * used in that case to set certain parameters on completion queues + * and others on notification queues. + */ + uint16_t enables; + /* + * This bit must be '1' for the num_cmpl_dma_aggr field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x1) + /* + * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cmpl_aggr_dma_tmr field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x4) + /* + * This bit must be '1' for the int_lat_tmr_min field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ + UINT32_C(0x8) + /* + * This bit must be '1' for the int_lat_tmr_max field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ + UINT32_C(0x10) + /* + * This bit must be '1' for the num_cmpl_aggr_int field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ + UINT32_C(0x20) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_ring_grp_alloc * + ***********************/ + + +/* hwrm_ring_grp_alloc_input (size:192b/24B) */ +struct hwrm_ring_grp_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value identifies the CR associated with the ring + * group. + */ + uint16_t cr; + /* + * This value identifies the main RR associated with the ring + * group. + */ + uint16_t rr; + /* + * This value identifies the aggregation RR associated with + * the ring group. If this value is 0xFF... (All Fs), then no + * Aggregation ring will be set. + */ + uint16_t ar; + /* + * This value identifies the statistics context associated + * with the ring group. + */ + uint16_t sc; +} __rte_packed; + +/* hwrm_ring_grp_alloc_output (size:128b/16B) */ +struct hwrm_ring_grp_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the ring group ID value. Use this value to program + * the default ring group for the VNIC or as table entries + * in an RSS/COS context. + */ + uint32_t ring_group_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_ring_grp_free * + **********************/ + + +/* hwrm_ring_grp_free_input (size:192b/24B) */ +struct hwrm_ring_grp_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This is the ring group ID value. */ + uint32_t ring_group_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_grp_free_output (size:128b/16B) */ +struct hwrm_ring_grp_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_ring_schq_alloc * + ************************/ + + +/* hwrm_ring_schq_alloc_input (size:1088b/136B) */ +struct hwrm_ring_schq_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) + /* Reserved for future use. */ + uint32_t reserved; + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring0_num_entries; + /* + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring1_num_entries; + /* + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring2_num_entries; + /* + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring3_num_entries; + /* + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring4_num_entries; + /* + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring5_num_entries; + /* + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring6_num_entries; + /* + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. + */ + uint32_t tqm_ring7_num_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_ring_schq_alloc_output (size:128b/16B) */ +struct hwrm_ring_schq_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is an identifier for the SCHQ to be used in other HWRM commands + * that need to reference this SCHQ. This value is greater than zero + * (i.e. a schq_id of zero references the default SCHQ). + */ + uint16_t schq_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_ring_schq_cfg * + **********************/ + + +/* hwrm_ring_schq_cfg_input (size:768b/96B) */ +struct hwrm_ring_schq_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Identifies the SCHQ being configured. A schq_id of zero refers to + * the default SCHQ. + */ + uint16_t schq_id; + /* + * This field is an 8 bit bitmap that indicates which TCs are enabled + * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents + * traffic class 7. + */ + uint8_t tc_enabled; + uint8_t unused_0; + uint32_t flags; + /* The tc_max_bw array and the max_bw parameters are valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \ + UINT32_C(0x1) + /* The tc_min_bw array is valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \ + UINT32_C(0x2) + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc0; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc1; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc2; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc3; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc4; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc5; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc6; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc7; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc0; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc1; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc2; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc3; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc4; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc5; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc6; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t min_bw_tc7; + /* + * Indicates the max bandwidth for all enabled traffic classes in + * this SCHQ, specified in Mbps. + */ + uint32_t max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_schq_cfg_output (size:128b/16B) */ +struct hwrm_ring_schq_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_ring_schq_free * + ***********************/ + + +/* hwrm_ring_schq_free_input (size:192b/24B) */ +struct hwrm_ring_schq_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Identifies the SCHQ being freed. */ + uint16_t schq_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_ring_schq_free_output (size:128b/16B) */ +struct hwrm_ring_schq_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; +/* + * special reserved flow ID to identify per function default + * flows for vSwitch offload + */ +#define DEFAULT_FLOW_ID 0xFFFFFFFFUL +/* + * special reserved flow ID to identify per function RoCEv1 + * flows + */ +#define ROCEV1_FLOW_ID 0xFFFFFFFEUL +/* + * special reserved flow ID to identify per function RoCEv2 + * flows + */ +#define ROCEV2_FLOW_ID 0xFFFFFFFDUL +/* + * special reserved flow ID to identify per function RoCEv2 + * CNP flows + */ +#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL + +/**************************** + * hwrm_cfa_l2_filter_alloc * + ****************************/ + + +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ +struct hwrm_cfa_l2_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x2) + /* + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ + UINT32_C(0x4) + /* + * If this flag is set, all t_l2_* fields are invalid + * and they should not be specified. + * If this flag is set, then l2_* fields refer to + * fields of outermost L2 header. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ + UINT32_C(0x8) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 4) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 4) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE + /* + * Setting of this flag indicates that no XDP filter is created with + * L2 filter. + * 0 - legacy behavior, XDP filter is created with L2 filter + * 1 - XDP filter won't be created with L2 filter + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \ + UINT32_C(0x40) + /* + * Setting this flag to 1 indicate the L2 fields in this command + * pertain to source fields. Setting this flag to 0 indicate the + * L2 fields in this command pertain to the destination fields + * and this is the default/legacy behavior. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \ + UINT32_C(0x80) + uint32_t enables; + /* + * This bit must be '1' for the l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ + UINT32_C(0x1) + /* + * This bit must be '1' for the l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ + UINT32_C(0x2) + /* + * This bit must be '1' for the l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ + UINT32_C(0x4) + /* + * This bit must be '1' for the l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ + UINT32_C(0x8) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x10) + /* + * This bit must be '1' for the l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the t_l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ + UINT32_C(0x80) + /* + * This bit must be '1' for the t_l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ + UINT32_C(0x100) + /* + * This bit must be '1' for the t_l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ + UINT32_C(0x200) + /* + * This bit must be '1' for the t_l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ + UINT32_C(0x400) + /* + * This bit must be '1' for the t_l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ + UINT32_C(0x800) + /* + * This bit must be '1' for the src_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the t_num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \ + UINT32_C(0x40000) + /* + * This value sets the match value for the L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* This value sets the match value for the number of VLANs. */ + uint8_t num_vlans; + /* + * This value sets the match value for the number of VLANs + * in the tunnel headers. + */ + uint8_t t_num_vlans; + /* + * This value sets the mask value for the L2 address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t l2_addr_mask[6]; + /* This value sets VLAN ID value for outer VLAN. */ + uint16_t l2_ovlan; + /* + * This value sets the mask value for the ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ovlan_mask; + /* This value sets VLAN ID value for inner VLAN. */ + uint16_t l2_ivlan; + /* + * This value sets the mask value for the ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ivlan_mask; + uint8_t unused_1[2]; + /* + * This value sets the match value for the tunnel + * L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t t_l2_addr[6]; + uint8_t unused_2[2]; + /* + * This value sets the mask value for the tunnel L2 + * address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t t_l2_addr_mask[6]; + /* This value sets VLAN ID value for tunnel outer VLAN. */ + uint16_t t_l2_ovlan; + /* + * This value sets the mask value for the tunnel ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ovlan_mask; + /* This value sets VLAN ID value for tunnel inner VLAN. */ + uint16_t t_l2_ivlan; + /* + * This value sets the mask value for the tunnel ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ivlan_mask; + /* This value identifies the type of source of the packet. */ + uint8_t src_type; + /* Network port */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) + /* Physical function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) + /* Virtual function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) + /* Virtual NIC of a function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) + /* Embedded processor for CFA management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) + /* Embedded processor for OOB management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) + /* Embedded processor for RoCE */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) + /* Embedded processor for network proxy functions */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG + uint8_t unused_3; + /* + * This value is the id of the source. + * For a network port, it represents port_id. + * For a physical function, it represents fid. + * For a virtual function, it represents vf_id. + * For a vnic, it represents vnic_id. + * For embedded processors, this id is not valid. + * + * Notes: + * 1. The function ID is implied if it src_id is + * not provided for a src_type that is either + */ + uint32_t src_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_4; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* + * This hint is provided to help in placing + * the filter in the filter table. + */ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ + UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ + UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ + UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN + uint8_t unused_5; + uint32_t unused_6; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + * + * This field is valid only for the following values. + * 1 - Above the given filter + * 2 - Below the given filter + */ + uint64_t l2_filter_id_hint; +} __rte_packed; + +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_l2_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_l2_filter_free * + ***************************/ + + +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_l2_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; +} __rte_packed; + +/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_l2_filter_cfg * + **************************/ + + +/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ +struct hwrm_cfa_l2_filter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ + UINT32_C(0x2) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 2) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 2) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE + uint32_t enables; + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ + UINT32_C(0x2) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint32_t dst_id; + /* + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t new_mirror_vnic_id; +} __rte_packed; + +/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_l2_set_rx_mask * + ***************************/ + + +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ +struct hwrm_cfa_l2_set_rx_mask_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VNIC ID */ + uint32_t vnic_id; + uint32_t mask; + /* + * When this bit is '1', the function is requested to accept + * multi-cast packets specified by the multicast addr table. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ + UINT32_C(0x2) + /* + * When this bit is '1', the function is requested to accept + * all multi-cast packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ + UINT32_C(0x4) + /* + * When this bit is '1', the function is requested to accept + * broadcast packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ + UINT32_C(0x8) + /* + * When this bit is '1', the function is requested to be + * put in the promiscuous mode. + * + * The HWRM should accept any function to set up + * promiscuous mode. + * + * The HWRM shall follow the semantics below for the + * promiscuous mode support. + * # When partitioning is not enabled on a port + * (i.e. single PF on the port), then the PF shall + * be allowed to be in the promiscuous mode. When the + * PF is in the promiscuous mode, then it shall + * receive all host bound traffic on that port. + * # When partitioning is enabled on a port + * (i.e. multiple PFs per port) and a PF on that + * port is in the promiscuous mode, then the PF + * receives all traffic within that partition as + * identified by a unique identifier for the + * PF (e.g. S-Tag). If a unique outer VLAN + * for the PF is specified, then the setting of + * promiscuous mode on that PF shall result in the + * PF receiving all host bound traffic with matching + * outer VLAN. + * # A VF shall can be set in the promiscuous mode. + * In the promiscuous mode, the VF does not receive any + * traffic unless a unique outer VLAN for the + * VF is specified. If a unique outer VLAN + * for the VF is specified, then the setting of + * promiscuous mode on that VF shall result in the + * VF receiving all host bound traffic with the + * matching outer VLAN. + * # The HWRM shall allow the setting of promiscuous + * mode on a function independently from the + * promiscuous mode settings on other functions. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ + UINT32_C(0x10) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the outermost Layer 2 destination MAC + * address field. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ + UINT32_C(0x20) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the VLAN-tagged packets that match the + * TPID and VID fields of VLAN tags in the VLAN tag + * table specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ + UINT32_C(0x40) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets that match the TPID and VID fields of VLAN + * tags in the VLAN tag table specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ + UINT32_C(0x80) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets matching any VLAN tag. + * + * If this flag is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan + * flags is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * The HWRM client shall set at most one flag out of + * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ + UINT32_C(0x100) + /* This is the address for mcast address tbl. */ + uint64_t mc_tbl_addr; + /* + * This value indicates how many entries in mc_tbl are valid. + * Each entry is 6 bytes. + */ + uint32_t num_mc_entries; + uint8_t unused_0[4]; + /* + * This is the address for VLAN tag table. + * Each VLAN entry in the table is 4 bytes of a VLAN tag + * including TPID, PCP, DEI, and VID fields in network byte + * order. + */ + uint64_t vlan_tag_tbl_addr; + /* + * This value indicates how many entries in vlan_tag_tbl are + * valid. Each entry is 4 bytes. + */ + uint32_t num_vlan_tags; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ +struct hwrm_cfa_l2_set_rx_mask_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ +struct hwrm_cfa_l2_set_rx_mask_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* Unable to complete operation due to conflict with Ntuple Filter */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ + UINT32_C(0x1) + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ + HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR + uint8_t unused_0[7]; +} __rte_packed; + +/******************************* + * hwrm_cfa_vlan_antispoof_cfg * + *******************************/ + + +/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being configured. + * Only valid for a VF FID configured by the PF. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* Number of VLAN entries in the vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table. Each table entry contains the 16-bit TPID + * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, + * all in network order to match hwrm_cfa_l2_set_rx_mask. + * For an individual VLAN entry, the mask value should be 0xfff + * for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} __rte_packed; + +/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_vlan_antispoof_qcfg * + ********************************/ + + +/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * Only valid for a VF FID queried by the PF. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* + * Maximum number of VLAN entries the firmware is allowed to DMA + * to vlan_tag_mask_tbl. + */ + uint32_t max_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table to which firmware will DMA to. Each table + * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), + * 16-bit VLAN ID, and a 16-bit mask, all in network order to + * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, + * the mask value should be 0xfff for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} __rte_packed; + +/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_tunnel_filter_alloc * + ********************************/ + + +/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ +struct hwrm_cfa_tunnel_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the l2_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ + UINT32_C(0x2) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x4) + /* + * This bit must be '1' for the l3_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the l3_addr_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the t_l3_addr_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l3_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the vni field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dst_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \ + UINT32_C(0x200) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x400) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * This value sets the match value for the inner L2 + * MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* + * This value sets VLAN ID value for inner VLAN. + * Only 12-bits of VLAN ID are used in setting the filter. + */ + uint16_t l2_ivlan; + /* + * The value of inner destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t l3_addr[4]; + /* + * The value of tunnel destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t t_l3_addr[4]; + /* + * This value indicates the type of inner IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t l3_addr_type; + /* + * This value indicates the type of tunnel IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t t_l3_addr_type; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* + * tunnel_flags allows the user to indicate the tunnel tag detection + * for the tunnel type specified in tunnel_type. + */ + uint8_t tunnel_flags; + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to match the geneve OAM packet. + * If the tunnel_type is nvgre or gre, then this bit indicates if + * we need to detect checksum present bit in geneve header. + * If the tunnel_type is mpls, then this bit indicates if we need + * to match mpls packet with explicit IPV4/IPV6 null header. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \ + UINT32_C(0x1) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to detect the critical option bit set in the oam packet. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with key present bit set in + * gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from inner/second label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \ + UINT32_C(0x2) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to match geneve packet with extended header bit set in + * geneve header. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with sequence number + * present bit set in gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from out/first label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \ + UINT32_C(0x4) + /* + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t vni; + /* Logical VNIC ID of the destination VNIC. */ + uint32_t dst_vnic_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t mirror_vnic_id; +} __rte_packed; + +/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - uint8_t queue_id6_bw_weight; - /* ID of CoS Queue 7. */ - uint8_t queue_id7; + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_cfa_tunnel_filter_free * + *******************************/ + + +/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t queue_id7_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t cmpl_ring; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t queue_id7_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id7_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t seq_id; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t queue_id7_pri_lvl; + uint16_t target_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t queue_id7_bw_weight; - uint8_t unused_1[5]; + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; } __rte_packed; -/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ -struct hwrm_queue_cos2bw_cfg_output { +/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_tunnel_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21716,19 +34908,20 @@ struct hwrm_queue_cos2bw_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************* - * hwrm_queue_dscp_qcaps * - *************************/ +/*************************************** + * hwrm_cfa_redirect_tunnel_type_alloc * + ***************************************/ -/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ -struct hwrm_queue_dscp_qcaps_input { +/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21757,17 +34950,73 @@ struct hwrm_queue_dscp_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint8_t port_id; - uint8_t unused_0[7]; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* Tunnel alloc flags. */ + uint8_t flags; + /* + * Setting of this flag indicates modify existing redirect tunnel + * to new destination function ID. + */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ + UINT32_C(0x1) + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ -struct hwrm_queue_dscp_qcaps_output { +/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21776,29 +35025,25 @@ struct hwrm_queue_dscp_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of bits provided by the hardware for the DSCP value. */ - uint8_t num_dscp_bits; - uint8_t unused_0; - /* Max number of DSCP-MASK-PRI entries supported. */ - uint16_t max_entries; - uint8_t unused_1[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/**************************** - * hwrm_queue_dscp2pri_qcfg * - ****************************/ +/************************************** + * hwrm_cfa_redirect_tunnel_type_free * + **************************************/ -/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ -struct hwrm_queue_dscp2pri_qcfg_input { +/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21827,25 +35072,65 @@ struct hwrm_queue_dscp2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * This is the host address where the 24-bits DSCP-MASK-PRI - * tuple(s) will be copied to. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint64_t dest_data_addr; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint8_t port_id; - uint8_t unused_0; - /* Size of the buffer pointed to by dest_data_addr. */ - uint16_t dest_data_buffer_size; - uint8_t unused_1[4]; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; } __rte_packed; -/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_qcfg_output { +/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21854,34 +35139,25 @@ struct hwrm_queue_dscp2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * A count of the number of DSCP-MASK-PRI tuple(s) pointed to - * by the dest_data_addr. - */ - uint16_t entry_cnt; - /* - * This is the default PRI which un-initialized DSCP values are - * mapped to. - */ - uint8_t default_pri; - uint8_t unused_0[4]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_queue_dscp2pri_cfg * - ***************************/ +/************************************** + * hwrm_cfa_redirect_tunnel_type_info * + **************************************/ -/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ -struct hwrm_queue_dscp2pri_cfg_input { +/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21910,43 +35186,65 @@ struct hwrm_queue_dscp2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI tuple - * will be copied from. - */ - uint64_t src_data_addr; - uint32_t flags; - /* use_hw_default_pri is 1 b */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ - UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the default_pri field to be - * configured. - */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + /* The source function id. */ + uint16_t src_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - /* - * This is the default PRI which un-initialized DSCP values will be - * mapped to. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint8_t default_pri; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) /* - * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed - * to by src_data_addr. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint16_t entry_cnt; - uint8_t unused_0[4]; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; } __rte_packed; -/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_cfg_output { +/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21955,24 +35253,137 @@ struct hwrm_queue_dscp2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ +struct hwrm_vxlan_ipv4_hdr { + /* IPv4 version and header length. */ + uint8_t ver_hlen; + /* IPv4 header length */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 + /* Version */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 + /* IPv4 type of service. */ + uint8_t tos; + /* IPv4 identification. */ + uint16_t ip_id; + /* IPv4 flags and offset. */ + uint16_t flags_frag_offset; + /* IPv4 TTL. */ + uint8_t ttl; + /* IPv4 protocol. */ + uint8_t protocol; + /* IPv4 source address. */ + uint32_t src_ip_addr; + /* IPv4 destination address. */ + uint32_t dest_ip_addr; +} __rte_packed; + +/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ +struct hwrm_vxlan_ipv6_hdr { + /* IPv6 version, traffic class and flow label. */ + uint32_t ver_tc_flow_label; + /* IPv6 version shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \ + UINT32_C(0x1c) + /* IPv6 version mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \ + UINT32_C(0xf0000000) + /* IPv6 TC shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \ + UINT32_C(0x14) + /* IPv6 TC mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \ + UINT32_C(0xff00000) + /* IPv6 flow label shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \ + UINT32_C(0x0) + /* IPv6 flow label mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \ + UINT32_C(0xfffff) + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \ + HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK + /* IPv6 payload length. */ + uint16_t payload_len; + /* IPv6 next header. */ + uint8_t next_hdr; + /* IPv6 TTL. */ + uint8_t ttl; + /* IPv6 source address. */ + uint32_t src_ip_addr[4]; + /* IPv6 destination address. */ + uint32_t dest_ip_addr[4]; +} __rte_packed; + +/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ +struct hwrm_cfa_encap_data_vxlan { + /* Source MAC address. */ + uint8_t src_mac_addr[6]; + /* reserved. */ + uint16_t unused_0; + /* Destination MAC address. */ + uint8_t dst_mac_addr[6]; + /* Number of VLAN tags. */ + uint8_t num_vlan_tags; + /* reserved. */ + uint8_t unused_1; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + /* L3 header fields. */ + uint32_t l3[10]; + /* IP version mask. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) + /* IP version 4. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) + /* IP version 6. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \ + HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 + /* UDP source port. */ + uint16_t src_port; + /* UDP destination port. */ + uint16_t dst_port; + /* VXLAN Network Identifier. */ + uint32_t vni; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN + * header. */ - uint8_t valid; + uint8_t hdr_rsvd0[3]; + /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ + uint8_t hdr_rsvd1; + /* VXLAN header flags field. */ + uint8_t hdr_flags; + uint8_t unused[3]; } __rte_packed; -/************************* - * hwrm_queue_mpls_qcaps * - *************************/ +/******************************* + * hwrm_cfa_encap_record_alloc * + *******************************/ -/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ -struct hwrm_queue_mpls_qcaps_input { +/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ +struct hwrm_cfa_encap_record_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22001,17 +35412,73 @@ struct hwrm_queue_mpls_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP) to pri mapping on this port. + * Setting of this flag indicates the applicability to the loopback + * path. */ - uint8_t port_id; - uint8_t unused_0[7]; + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + /* + * Setting of this flag indicates this encap record is external + * encap record. Resetting of this flag indicates this flag is + * internal encap record and this is the default setting. + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ + UINT32_C(0x2) + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ + UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 + uint8_t unused_0[3]; + /* This value is encap data used for the given encap type. */ + uint32_t encap_data[20]; } __rte_packed; -/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ -struct hwrm_queue_mpls_qcaps_output { +/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22020,42 +35487,27 @@ struct hwrm_queue_mpls_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_mplstc2pri_cfg command. - * - * Each bit represents a specific pri where bit 0 represents - * pri 0 and bit 7 represents pri 7. - * # A value of 0 indicates that the pri is not configurable - * by the hwrm_queue_mplstc2pri_cfg command. - * # A value of 1 indicates that the pri is configurable. - * # A hwrm_queue_mplstc2pri_cfg command shall return error when - * trying to configure a pri that is not configurable. - */ - uint8_t queue_mplstc2pri_cfg_allowed; - /* - * This is the default PRI which un-initialized MPLS values will be - * mapped to. - */ - uint8_t hw_default_pri; - uint8_t unused_0[5]; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; /****************************** - * hwrm_queue_mplstc2pri_qcfg * + * hwrm_cfa_encap_record_free * ******************************/ -/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_input { +/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ +struct hwrm_cfa_encap_record_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22084,17 +35536,13 @@ struct hwrm_queue_mplstc2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP) to pri mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_mplstc2pri_qcfg_output { +/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22103,80 +35551,25 @@ struct hwrm_queue_mplstc2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * pri assigned to MPLS TC(EXP) 0. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 0. - */ - uint8_t tc0_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 1. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 1. - */ - uint8_t tc1_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 2. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 2. - */ - uint8_t tc2_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 3. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 3. - */ - uint8_t tc3_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 4. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 4. - */ - uint8_t tc4_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 5. This value can only be changed - * before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 5. - */ - uint8_t tc5_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 6. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 6. - */ - uint8_t tc6_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 7. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no pri is assigned to the - * MPLS TC(EXP) 7. - */ - uint8_t tc7_pri_queue_id; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/***************************** - * hwrm_queue_mplstc2pri_cfg * - *****************************/ +/******************************** + * hwrm_cfa_ntuple_filter_alloc * + ********************************/ -/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_mplstc2pri_cfg_input { +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22205,466 +35598,359 @@ struct hwrm_queue_mplstc2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; + uint32_t flags; /* - * This bit must be '1' for the mplstc0_pri_queue_id field to be - * configured. + * Setting of this flag indicates the applicability to the loopback + * path. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x1) /* - * This bit must be '1' for the mplstc1_pri_queue_id field to be - * configured. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ UINT32_C(0x2) /* - * This bit must be '1' for the mplstc2_pri_queue_id field to be - * configured. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ UINT32_C(0x4) /* - * This bit must be '1' for the mplstc3_pri_queue_id field to be - * configured. + * Setting of this flag indicates that the dst_id field contains + * function ID. If this is not set it indicates dest_id is VNIC + * or VPORT. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ UINT32_C(0x8) /* - * This bit must be '1' for the mplstc4_pri_queue_id field to be - * configured. + * Setting of this flag indicates match on arp reply when ethertype + * is 0x0806. If this is not set it indicates no specific arp opcode + * matching. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ UINT32_C(0x10) /* - * This bit must be '1' for the mplstc5_pri_queue_id field to be - * configured. + * Setting of this flag indicates that the dst_id field contains RFS + * ring table index. If this is not set it indicates dst_id is VNIC + * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ UINT32_C(0x20) + uint32_t enables; /* - * This bit must be '1' for the mplstc6_pri_queue_id field to be + * This bit must be '1' for the l2_filter_id field to be * configured. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ - UINT32_C(0x40) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) /* - * This bit must be '1' for the mplstc7_pri_queue_id field to be + * This bit must be '1' for the ethertype field to be * configured. */ - #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure MPLS TC(EXP)to pri mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[3]; - /* - * pri assigned to MPLS TC(EXP) 0. This value can only - * be changed before traffic has started. - */ - uint8_t tc0_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 1. This value can only - * be changed before traffic has started. - */ - uint8_t tc1_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 2 This value can only - * be changed before traffic has started. - */ - uint8_t tc2_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 3. This value can only - * be changed before traffic has started. - */ - uint8_t tc3_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 4. This value can only - * be changed before traffic has started. - */ - uint8_t tc4_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 5. This value can only - * be changed before traffic has started. - */ - uint8_t tc5_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 6. This value can only - * be changed before traffic has started. - */ - uint8_t tc6_pri_queue_id; - /* - * pri assigned to MPLS TC(EXP) 7. This value can only - * be changed before traffic has started. - */ - uint8_t tc7_pri_queue_id; -} __rte_packed; - -/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_mplstc2pri_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/******************* - * hwrm_vnic_alloc * - *******************/ - - -/* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the tunnel_type field to be + * configured. */ - uint16_t seq_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit must be '1' for the src_macaddr field to be + * configured. */ - uint16_t target_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + UINT32_C(0x8) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the ipaddr_type field to be + * configured. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x10) /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - uint8_t unused_0[4]; -} __rte_packed; - -/* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[3]; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x20) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the src_ipaddr_mask field to be + * configured. */ - uint8_t valid; -} __rte_packed; - -/****************** - * hwrm_vnic_free * - ******************/ - - -/* hwrm_vnic_free_input (size:192b/24B) */ -struct hwrm_vnic_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ + UINT32_C(0x40) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x80) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the dst_ipaddr_mask field to be + * configured. */ - uint16_t seq_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ + UINT32_C(0x100) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit must be '1' for the ip_protocol field to be + * configured. */ - uint16_t target_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x200) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the src_port field to be + * configured. */ - uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; -} __rte_packed; - -/* hwrm_vnic_free_output (size:128b/16B) */ -struct hwrm_vnic_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x400) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the src_port_mask field to be + * configured. */ - uint8_t valid; -} __rte_packed; - -/***************** - * hwrm_vnic_cfg * - *****************/ - - -/* hwrm_vnic_cfg_input (size:384b/48B) */ -struct hwrm_vnic_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ + UINT32_C(0x800) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the dst_port field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x1000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the dst_port_mask field to be + * configured. */ - uint16_t seq_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ + UINT32_C(0x2000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit must be '1' for the pri_hint field to be + * configured. */ - uint16_t target_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ + UINT32_C(0x4000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the ntuple_filter_id field to be + * configured. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ + UINT32_C(0x8000) /* - * When this bit is '1', the VNIC is requested to - * be the default VNIC for the function. + * This bit must be '1' for the dst_id field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ - UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x10000) /* - * When this bit is '1', the VNIC is being configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x20000) /* - * When this bit is '1', the VNIC is being configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is being configured to be - * disabled on this VNIC. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ + UINT32_C(0x40000) + /* This flag is deprecated. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ + UINT32_C(0x80000) /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to be - * operating in dual VNIC mode. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) + uint64_t l2_filter_id; /* - * When this flag is set to '1', the VNIC is requested to - * be configured to receive only RoCE traffic. - * If this flag is set to '0', then this flag shall be - * ignored by the HWRM. - * If roce_dual_vnic_mode flag is set to '1' - * or roce_mirroring_capable_vnic_mode flag to 1, - * then the HWRM client shall not set this flag to '1'. + * This value indicates the source MAC address in + * the Ethernet header. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) + uint8_t src_macaddr[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * This flag is used to enable a mode where - * RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured using hwrm_vnic_rss_cfg. - * - * If this mode is enabled, then the driver should not program - * RSS indirection table for the RSS context that is used for - * computing RSS hash only. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic, but forward only the - * RoCE traffic further. Also, RoCE traffic can be mirrored to - * L2 driver. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) - uint32_t enables; + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP /* - * This bit must be '1' for the dflt_ring_grp field to be - * configured. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ - UINT32_C(0x1) + uint16_t dst_id; /* - * This bit must be '1' for the rss_rule field to be - * configured. + * Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ - UINT32_C(0x2) + uint16_t mirror_vnic_id; /* - * This bit must be '1' for the cos_rule field to be - * configured. + * This value indicates the tunnel type for this filter. + * If this field is not specified, then the filter shall + * apply to both non-tunneled and tunneled packets. + * If this field conflicts with the tunnel_type specified + * in the l2_filter_id, then the HWRM shall return an + * error for this command. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * This bit must be '1' for the lb_rule field to be - * configured. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ - UINT32_C(0x8) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) /* - * This bit must be '1' for the mru field to be - * configured. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ - UINT32_C(0x10) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* - * This bit must be '1' for the default_rx_ring_id field to be - * configured. + * This hint is provided to help in placing + * the filter in the filter table. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ - UINT32_C(0x20) + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ + UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ + UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ + UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST /* - * This bit must be '1' for the default_cmpl_ring_id field to be - * configured. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ - UINT32_C(0x40) - /* This bit must be '1' for the queue_id field to be configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \ - UINT32_C(0x80) - /* Logical vnic ID */ - uint16_t vnic_id; + uint32_t src_ipaddr[4]; /* - * Default Completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules and if - * there is no COS rule. + * The value of source IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. */ - uint16_t dflt_ring_grp; + uint32_t src_ipaddr_mask[4]; /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint16_t rss_rule; + uint32_t dst_ipaddr[4]; /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. + * The value of destination IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. */ - uint16_t cos_rule; + uint32_t dst_ipaddr_mask[4]; /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t lb_rule; + uint16_t src_port; /* - * The maximum receive unit of the vnic. - * Each vnic is associated with a function. - * The vnic mru value overwrites the mru setting of the - * associated function. - * The HWRM shall make sure that vnic mru does not exceed - * the mru of the port the function is associated with. + * The value of source port mask to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t mru; + uint16_t src_port_mask; /* - * Default Rx ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. - * The aggregation ring associated with the Rx ring is - * implied based on the Rx ring specified when the - * aggregation ring was allocated. + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t default_rx_ring_id; + uint16_t dst_port; /* - * Default completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. + * The value of destination port mask to be used in + * filtering. + * Applies to UDP and TCP traffic. */ - uint16_t default_cmpl_ring_id; + uint16_t dst_port_mask; /* - * When specified, only incoming packets classified to the specified CoS - * queue ID will be arriving on this VNIC. Packet priority to CoS mapping - * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, - * ntuple filters with VNIC destination specified are invalid since they - * conflict with the the CoS to VNIC steering rules in this mode. - * - * If this field is not specified, packet to VNIC steering will be - * subject to the standard L2 filter rules and any additional ntuple - * filter rules with destination VNIC specified. + * This is the ID of the filter that goes along with + * the pri_hint. */ - uint16_t queue_id; - uint8_t unused0[6]; + uint64_t ntuple_filter_id_hint; } __rte_packed; -/* hwrm_vnic_cfg_output (size:128b/16B) */ -struct hwrm_vnic_cfg_output { +/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22673,24 +35959,85 @@ struct hwrm_vnic_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/****************** - * hwrm_vnic_qcfg * - ******************/ +/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ +struct hwrm_cfa_ntuple_filter_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* Unable to complete operation due to conflict with Rx Mask VLAN */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ + UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR + uint8_t unused_0[7]; +} __rte_packed; + +/******************************* + * hwrm_cfa_ntuple_filter_free * + *******************************/ -/* hwrm_vnic_qcfg_input (size:256b/32B) */ -struct hwrm_vnic_qcfg_input { +/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22711,148 +36058,47 @@ struct hwrm_vnic_qcfg_input { * * 0xFFFD - Reserved for user-space HWRM interface * * 0xFFFF - HWRM */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vf_id_valid field to be - * configured. - */ - #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) - /* Logical vnic ID */ - uint32_t vnic_id; - /* ID of Virtual Function whose VNIC resource is being queried. */ - uint16_t vf_id; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_vnic_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Default Completion ring for the VNIC. */ - uint16_t dflt_ring_grp; - /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. - */ - uint16_t rss_rule; - /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. - */ - uint16_t cos_rule; - /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. - */ - uint16_t lb_rule; - /* The maximum receive unit of the vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* - * When this bit is '1', the VNIC is the default VNIC for - * the function. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to - * operate in dual VNIC mode. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) - /* - * When this flag is set to '1', the VNIC is configured to - * receive only RoCE traffic. - * When this flag is set to '0', the VNIC is not configured - * to receive only RoCE traffic. - * If roce_dual_vnic_mode flag and this flag both are set - * to '1', then it is an invalid configuration of the - * VNIC. The HWRM should not allow that type of - * mis-configuration by HWRM clients. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) - /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * When this bit is set to '1', then the VNIC is enabled in a - * mode where RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) - /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic, but forward only - * RoCE traffic further. Also RoCE traffic can be mirrored to - * L2 driver. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) + uint16_t target_id; /* - * When returned with a valid CoS Queue id, the CoS Queue/VNIC association - * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS - * queue association. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t queue_id; - uint8_t unused_1[5]; + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************* - * hwrm_vnic_qcaps * - *******************/ +/****************************** + * hwrm_cfa_ntuple_filter_cfg * + ******************************/ -/* hwrm_vnic_qcaps_input (size:192b/24B) */ -struct hwrm_vnic_qcaps_input { +/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ +struct hwrm_cfa_ntuple_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22882,120 +36128,100 @@ struct hwrm_vnic_qcaps_input { */ uint64_t resp_addr; uint32_t enables; - uint8_t unused_0[4]; -} __rte_packed; - -/* hwrm_vnic_qcaps_output (size:192b/24B) */ -struct hwrm_vnic_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The maximum receive unit that is settable on a vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* Unused. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ + /* + * This bit must be '1' for the new_dst_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ UINT32_C(0x1) /* - * When this bit is '1', the capability of stripping VLAN in - * the RX path is supported on VNIC(s). - * If set to '0', then VLAN stripping capability is - * not supported on VNIC(s). + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ UINT32_C(0x2) /* - * When this bit is '1', the capability to buffer receive - * packets in the hardware until the host posts new receive buffers - * is supported on VNIC(s). - * If set to '0', then bd_stall capability is not supported - * on VNIC(s). + * This bit must be '1' for the new_meter_instance_id field to be + * configured. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ UINT32_C(0x4) + uint32_t flags; /* - * When this bit is '1', the capability to - * receive both RoCE and non-RoCE traffic on VNIC(s) is - * supported. - * If set to '0', then the capability to receive - * both RoCE and non-RoCE traffic on VNIC(s) is - * not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ - UINT32_C(0x8) - /* - * When this bit is set to '1', the capability to configure - * a VNIC to receive only RoCE traffic is supported. - * When this flag is set to '0', the VNIC capability to - * configure to receive only RoCE traffic is not supported. + * Setting this bit to 1 indicates that dest_id field contains FID. + * Setting this to 0 indicates that dest_id field contains VNIC or + * VPORT. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ - UINT32_C(0x10) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ + UINT32_C(0x1) /* - * When this bit is set to '1', then the capability to enable - * a VNIC in a mode where RSS context without configuring - * RSS indirection table is supported (for RSS hash computation). - * When this bit is set to '0', then a VNIC can not be configured - * with a mode to enable RSS context without configuring RSS - * indirection table. + * Setting of this flag indicates that the new_dst_id field contains + * RFS ring table index. If this is not set it indicates new_dst_id + * is VNIC or VPORT or function ID. Note dest_fid and + * dest_rfs_ring_idx can’t be set at the same time. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ - UINT32_C(0x20) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x2) + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; /* - * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. - * If set to '0', then the capability to mirror the - * RoCE traffic is not supported. + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and new network port id of the destination port for + * the TX path. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ - UINT32_C(0x40) + uint32_t new_dst_id; /* - * When this bit is '1', the outermost RSS hashing capability - * is supported. If set to '0', then the outermost RSS hashing - * capability is not supported. + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ - UINT32_C(0x80) + uint32_t new_mirror_vnic_id; /* - * When this bit is '1', it indicates that firmware supports the - * ability to steer incoming packets from one CoS queue to one - * VNIC. This optional feature can then be enabled - * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classfication” is set - * to 1. If set to '0', firmware does not support this feature. + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ - UINT32_C(0x100) + uint16_t new_meter_instance_id; /* - * This field advertises the maximum concurrent TPA aggregations - * supported by the VNIC on new devices that support TPA v2. - * '0' means that TPA v2 is not supported. + * A value of 0xfff is considered invalid and implies the + * instance is not configured. */ - uint16_t max_aggs_supported; - uint8_t unused_1[5]; + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ + HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************* - * hwrm_vnic_tpa_cfg * - *********************/ +/************************** + * hwrm_cfa_em_flow_alloc * + **************************/ -/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ -struct hwrm_vnic_tpa_cfg_input { +/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ +struct hwrm_cfa_em_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23026,156 +36252,429 @@ struct hwrm_vnic_tpa_cfg_input { uint64_t resp_addr; uint32_t flags; /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates enabling of a byte counter for a + * given flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) + /* + * Setting of this flag indicates enabling of a packet counter for a + * given flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) + /* + * Setting of this flag indicates de-capsulation action for the + * given flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) + /* + * Setting of this flag indicates encapsulation action for the + * given flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) + /* + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) + /* + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ UINT32_C(0x1) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. + * This bit must be '1' for the tunnel_type field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ UINT32_C(0x2) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. + * This bit must be '1' for the tunnel_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ UINT32_C(0x4) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. + * This bit must be '1' for the src_macaddr field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ UINT32_C(0x8) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x10) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. + * This bit must be '1' for the ovlan_vid field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ UINT32_C(0x20) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. + * This bit must be '1' for the ivlan_vid field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ UINT32_C(0x40) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x80) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall DMA payload data using GRO rules. - * When this bit is '0', the VNIC shall DMA payload data - * using the more efficient LRO rules of filling all - * aggregation buffers. + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x200) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x400) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x800) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the encap_record_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the meter_instance_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ + UINT32_C(0x20000) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[3]; + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + /* The meter instance to attach to the flow. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID + /* + * This value indicates the destination MAC address in + * the Ethernet header. + */ + uint8_t dst_macaddr[6]; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. + */ + uint16_t ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP + uint8_t unused_1[2]; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * big_endian = True + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* Logical ID of the encapsulation record. */ + uint32_t encap_record_id; + uint8_t unused_2[4]; +} __rte_packed; + +/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ +struct hwrm_cfa_em_flow_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \ - UINT32_C(0x100) - uint32_t enables; + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) /* - * This bit must be '1' for the max_agg_segs field to be - * configured. + * If this bit set to 0, then it indicates that the flow is + * internal flow. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) /* - * This bit must be '1' for the max_aggs field to be - * configured. + * If this bit is set to 1, then it indicates that the flow is + * external flow. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; /* - * This bit must be '1' for the max_agg_timer field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) - /* deprecated bit. Do not use!!! */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) - /* Logical vnic ID */ - uint16_t vnic_id; + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_em_flow_free * + *************************/ + + +/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ +struct hwrm_cfa_em_flow_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. On new - * devices supporting TPA v2, the unit is multiples of 4 and - * valid values are > 0 and <= 63. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX + uint16_t cmpl_ring; /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7. On new devices - * supporting TPA v2, this is in unit of 1 and must be > 0 - * and <= max_aggs_supported in the hwrm_vnic_qcaps response - * to enable TPA v2. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX - uint8_t unused_0[2]; + uint16_t seq_id; /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t max_agg_timer; + uint16_t target_id; /* - * This is the minimum amount of payload length required to - * start an aggregation context. This field is deprecated and - * should be set to 0. The minimum length is set by firmware - * and can be queried using hwrm_vnic_tpa_qcfg. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t min_agg_len; + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; } __rte_packed; -/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ -struct hwrm_vnic_tpa_cfg_output { +/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ +struct hwrm_cfa_em_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23187,21 +36686,22 @@ struct hwrm_vnic_tpa_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************* - * hwrm_vnic_rss_cfg * - *********************/ +/************************ + * hwrm_cfa_meter_qcaps * + ************************/ -/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ -struct hwrm_vnic_rss_cfg_input { +/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_meter_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23230,150 +36730,92 @@ struct hwrm_vnic_rss_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) +} __rte_packed; + +/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ +struct hwrm_cfa_meter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. + * Enumeration denoting the clock at which the Meter is running + * with. This enumeration is used for resources that are similar + * for both TX and RX paths of the chip. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 + /* 375 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) + /* 625 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \ + HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ + uint8_t unused_0[4]; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. + * The minimum guaranteed number of tx meter profiles supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + uint16_t min_tx_profile; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * The maximum non-guaranteed number of tx meter profiles supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* VNIC ID of VNIC associated with RSS table being configured. */ - uint16_t vnic_id; + uint16_t max_tx_profile; /* - * Specifies which VNIC ring table pair to configure. - * Valid values range from 0 to 7. + * The minimum guaranteed number of rx meter profiles supported + * for this function. */ - uint8_t ring_table_pair_index; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; + uint16_t min_rx_profile; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * The maximum non-guaranteed number of rx meter profiles supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) + uint16_t max_rx_profile; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * The minimum guaranteed number of tx meter instances supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) + uint16_t min_tx_instance; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * The maximum non-guaranteed number of tx meter instances supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) + uint16_t max_tx_instance; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * The minimum guaranteed number of rx meter instances supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + uint16_t min_rx_instance; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * The maximum non-guaranteed number of rx meter instances supported + * for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) - /* This is the address for rss ring group table */ - uint64_t ring_grp_tbl_addr; - /* This is the address for rss hash key table */ - uint64_t hash_key_tbl_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_1[6]; -} __rte_packed; - -/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ -struct hwrm_vnic_rss_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t max_rx_instance; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ -struct hwrm_vnic_rss_cfg_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* - * Unable to change global RSS mode to outer due to all active - * interfaces are not ready to support outer RSS hashing. - */ - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \ - UINT32_C(0x1) - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ - HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY - uint8_t unused_0[7]; -} __rte_packed; - -/********************** - * hwrm_vnic_rss_qcfg * - **********************/ +/******************************** + * hwrm_cfa_meter_profile_alloc * + ********************************/ -/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_rss_qcfg_input { +/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23402,13 +36844,220 @@ struct hwrm_vnic_rss_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_0[6]; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ + UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ + UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved1; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved2; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID } __rte_packed; -/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ -struct hwrm_vnic_rss_qcfg_output { +/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23417,106 +37066,35 @@ struct hwrm_vnic_rss_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - uint8_t unused_0[4]; - /* This is the value of rss hash key */ - uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; - /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) - uint8_t unused_1[6]; + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************** - * hwrm_vnic_plcmodes_cfg * - **************************/ +/******************************* + * hwrm_cfa_meter_profile_free * + *******************************/ -/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ -struct hwrm_vnic_plcmodes_cfg_input { +/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_profile_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23545,116 +37123,37 @@ struct hwrm_vnic_plcmodes_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * When this bit is '1', the VNIC shall be configured to - * use regular placement algorithm. - * By default, the regular placement algorithm shall be - * enabled on the VNIC. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC shall be configured - * use the jumbo placement algorithm. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv4 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv4, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv4, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv4 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv4 - * packet. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv6 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv6, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv6, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv6 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv6 - * packet. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ - UINT32_C(0x8) - /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for FCoE packets at the - * beginning of FC payload. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ - UINT32_C(0x10) - /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for RoCE packets at the - * beginning of RoCE payload (after BTH/GRH headers). - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ - UINT32_C(0x20) - uint32_t enables; + uint8_t flags; /* - * This bit must be '1' for the jumbo_thresh_valid field to be - * configured. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * This bit must be '1' for the hds_offset_valid field to be - * configured. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the hds_threshold_valid field to be - * configured. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ - UINT32_C(0x4) - /* Logical vnic ID */ - uint32_t vnic_id; - /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. - */ - uint16_t jumbo_thresh; - /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. - */ - uint16_t hds_offset; - /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - uint16_t hds_threshold; - uint8_t unused_0[6]; + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ -struct hwrm_vnic_plcmodes_cfg_output { +/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23666,21 +37165,22 @@ struct hwrm_vnic_plcmodes_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_vnic_plcmodes_qcfg * - ***************************/ +/****************************** + * hwrm_cfa_meter_profile_cfg * + ******************************/ -/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_input { +/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23709,139 +37209,223 @@ struct hwrm_vnic_plcmodes_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; -} __rte_packed; - -/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + uint8_t flags; /* - * When this bit is '1', the VNIC is configured to - * use regular placement algorithm. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * use the jumbo placement algorithm. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv4 packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv6 packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ - UINT32_C(0x8) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for FCoE packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ - UINT32_C(0x10) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for RoCE packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ - UINT32_C(0x20) - /* - * When this bit is '1', the VNIC is configured - * to be the default VNIC of the requesting function. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ - UINT32_C(0x40) - /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. - */ - uint16_t jumbo_thresh; - /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. - */ - uint16_t hds_offset; - /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. - */ - uint16_t hds_threshold; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/********************************** - * hwrm_vnic_rss_cos_lb_ctx_alloc * - **********************************/ - - -/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - uint16_t target_id; + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint64_t resp_addr; + uint32_t reserved; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID } __rte_packed; -/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { +/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23850,26 +37434,25 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; /********************************* - * hwrm_vnic_rss_cos_lb_ctx_free * + * hwrm_cfa_meter_instance_alloc * *********************************/ -/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_input { +/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23898,13 +37481,38 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[6]; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xffff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_output { +/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23913,24 +37521,35 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; + /* + * A value of 0xffff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************* - * hwrm_ring_alloc * - *******************/ +/******************************* + * hwrm_cfa_meter_instance_cfg * + *******************************/ -/* hwrm_ring_alloc_input (size:704b/88B) */ -struct hwrm_ring_alloc_input { +/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23959,371 +37578,45 @@ struct hwrm_ring_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the ring_arb_cfg field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ - UINT32_C(0x2) - /* - * This bit must be '1' for the stat_ctx_id_valid field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ - UINT32_C(0x8) - /* - * This bit must be '1' for the max_bw_valid field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the rx_ring_id field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the nq_ring_id field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ - UINT32_C(0x80) - /* - * This bit must be '1' for the rx_buf_size field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ - UINT32_C(0x100) - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ - HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; - /* Ring allocation flags. */ - uint16_t flags; - /* - * For Rx rings, the incoming packet data can be placed at either - * a 0B or 2B offset from the start of the Rx packet buffer. When - * '1', the received packet will be padded with 2B of zeros at the - * front of the packet. Note that this flag is only used for - * Rx rings and is ignored for all other rings included Rx - * Aggregation rings. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) - /* - * This value is a pointer to the page table for the - * Ring. - */ - uint64_t page_tbl_addr; - /* First Byte Offset of the first entry in the first page. */ - uint32_t fbo; - /* - * Actual page size in 2^page_size. The supported range is increments - * in powers of 2 from 16 bytes to 1GB. - * - 4 = 16 B - * Page size is 16 B. - * - 12 = 4 KB - * Page size is 4 KB. - * - 13 = 8 KB - * Page size is 8 KB. - * - 16 = 64 KB - * Page size is 64 KB. - * - 21 = 2 MB - * Page size is 2 MB. - * - 22 = 4 MB - * Page size is 4 MB. - * - 30 = 1 GB - * Page size is 1 GB. - */ - uint8_t page_size; - /* - * This value indicates the depth of page table. - * For this version of the specification, value other than 0 or - * 1 shall be considered as an invalid value. - * When the page_tbl_depth = 0, then it is treated as a - * special case with the following. - * 1. FBO and page size fields are not valid. - * 2. page_tbl_addr is the physical address of the first - * element of the ring. - */ - uint8_t page_tbl_depth; - uint8_t unused_1[2]; - /* - * Number of 16B units in the ring. Minimum size for - * a ring is 16 16B entries. - */ - uint32_t length; - /* - * Logical ring number for the ring to be allocated. - * This value determines the position in the doorbell - * area where the update to the ring will be made. - * - * For completion rings, this value is also the MSI-X - * vector number for the function the completion ring is - * associated with. - */ - uint16_t logical_id; - /* - * This field is used only when ring_type is a TX ring. - * This value indicates what completion ring the TX ring - * is associated with. - */ - uint16_t cmpl_ring_id; - /* - * This field is used only when ring_type is a TX ring. - * This value indicates what CoS queue the TX ring - * is associated with. - */ - uint16_t queue_id; - /* - * When allocating a Rx ring or Rx aggregation ring, this field - * specifies the size of the buffer descriptors posted to the ring. - */ - uint16_t rx_buf_size; - /* - * When allocating an Rx aggregation ring, this field - * specifies the associated Rx ring ID. - */ - uint16_t rx_ring_id; - /* - * When allocating a completion ring, this field - * specifies the associated NQ ring ID. - */ - uint16_t nq_ring_id; - /* - * This field is used only when ring_type is a TX ring. - * This field is used to configure arbitration related - * parameters for a TX ring. - */ - uint16_t ring_arb_cfg; - /* Arbitration policy used for the ring. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ - UINT32_C(0xf) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + uint8_t flags; /* - * Use strict priority for the TX ring. - * Priority value is specified in arb_policy_param + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0; /* - * Use weighted fair queue arbitration for the TX ring. - * Weight is specified in arb_policy_param - */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ - UINT32_C(0x2) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ - HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ - /* Reserved field. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 - /* - * Arbitration policy specific parameter. - * # For strict priority arbitration policy, this field - * represents a priority value. If set to 0, then the priority - * is not specified and the HWRM is allowed to select - * any priority for this TX ring. - * # For weighted fair queue arbitration policy, this field - * represents a weight value. If set to 0, then the weight - * is not specified and the HWRM is allowed to select - * any weight for this TX ring. - */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ - UINT32_C(0xff00) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 - uint16_t unused_3; - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint32_t reserved3; - /* - * This field is used only when ring_type is a TX ring. - * This input indicates what statistics context this ring - * should be associated with. - */ - uint32_t stat_ctx_id; - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint32_t reserved4; - /* - * This field is used only when ring_type is a TX ring - * to specify maximum BW allocated to the TX ring. - * The HWRM will translate this value into byte counter and - * time interval used for this ring inside the device. - */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID - /* - * This field is used only when ring_type is a Completion ring. - * This value indicates what interrupt mode should be used - * on this completion ring. - * Note: In the legacy interrupt mode, no more than 16 - * completion rings are allowed. - */ - uint8_t int_mode; - /* Legacy INTA */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) - /* Reserved */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) - /* MSI-X */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) - /* No Interrupt - Polled mode */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ - HWRM_RING_ALLOC_INPUT_INT_MODE_POLL - uint8_t unused_4[3]; - /* - * The cq_handle is specified when allocating a completion ring. For - * devices that support NQs, this cq_handle will be included in the - * NQE to specify which CQ should be read to retrieve the completion - * record. - */ - uint64_t cq_handle; -} __rte_packed; - -/* hwrm_ring_alloc_output (size:128b/16B) */ -struct hwrm_ring_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Physical number of ring allocated. - * This value shall be unique for a ring type. - */ - uint16_t ring_id; - /* Logical number of ring allocated. */ - uint16_t logical_ring_id; - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __rte_packed; - -/****************** - * hwrm_ring_free * - ******************/ - - -/* hwrm_ring_free_input (size:192b/24B) */ -struct hwrm_ring_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value identifies a new meter profile to be associated with + * the meter instance specified in this command. */ - uint16_t seq_id; + uint16_t meter_profile_id; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * A value of 0xffff is considered invalid and implies the + * profile is not configured. */ - uint16_t target_id; + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value identifies the ID of a meter instance that needs to be + * updated with a new meter profile specified in this command. */ - uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ - HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; - /* Physical number of ring allocated. */ - uint16_t ring_id; - uint8_t unused_1[4]; + uint16_t meter_instance_id; + uint8_t unused_1[2]; } __rte_packed; -/* hwrm_ring_free_output (size:128b/16B) */ -struct hwrm_ring_free_output { +/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24335,21 +37628,22 @@ struct hwrm_ring_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************* - * hwrm_ring_reset * - *******************/ +/******************************** + * hwrm_cfa_meter_instance_free * + ********************************/ -/* hwrm_ring_reset_input (size:192b/24B) */ -struct hwrm_ring_reset_input { +/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24378,26 +37672,37 @@ struct hwrm_ring_reset_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ - HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX uint8_t unused_0; - /* Physical number of the ring. */ - uint16_t ring_id; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID uint8_t unused_1[4]; } __rte_packed; -/* hwrm_ring_reset_output (size:128b/16B) */ -struct hwrm_ring_reset_output { +/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24406,26 +37711,25 @@ struct hwrm_ring_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[4]; - /* Position of consumer index after ring reset completes. */ - uint8_t consumer_idx[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************** - * hwrm_ring_aggint_qcaps * - **************************/ +/******************************* + * hwrm_cfa_decap_filter_alloc * + *******************************/ -/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ -struct hwrm_ring_aggint_qcaps_input { +/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ +struct hwrm_cfa_decap_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24454,128 +37758,310 @@ struct hwrm_ring_aggint_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __rte_packed; - -/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ -struct hwrm_ring_aggint_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t cmpl_params; + uint32_t flags; + /* ovs_tunnel is 1 b */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \ + UINT32_C(0x1) + uint32_t enables; /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on completion rings. + * This bit must be '1' for the tunnel_type field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ UINT32_C(0x1) /* - * When this bit is set to '1', int_lat_tmr_max can be configured - * on completion rings. + * This bit must be '1' for the tunnel_id field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \ UINT32_C(0x2) /* - * When this bit is set to '1', timer_reset can be enabled - * on completion rings. + * This bit must be '1' for the src_macaddr field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ UINT32_C(0x4) /* - * When this bit is set to '1', ring_idle can be enabled - * on completion rings. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x8) /* - * When this bit is set to '1', num_cmpl_dma_aggr can be configured - * on completion rings. + * This bit must be '1' for the ovlan_vid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \ UINT32_C(0x10) /* - * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured - * on completion rings. + * This bit must be '1' for the ivlan_vid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \ UINT32_C(0x20) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured - * on completion rings. + * This bit must be '1' for the t_ovlan_vid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \ UINT32_C(0x40) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured - * on completion rings. + * This bit must be '1' for the t_ivlan_vid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \ UINT32_C(0x80) /* - * When this bit is set to '1', num_cmpl_aggr_int can be configured - * on completion rings. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x100) - uint32_t nq_params; /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on notification queues. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x200) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x400) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x800) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) - /* Minimum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_min; - /* Maximum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_max; - /* Minimum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_min; - /* Maximum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_max; - /* Minimum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_min; - /* Maximum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_max; - /* Minimum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_min; - /* Maximum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_max; - /* Minimum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_min; - /* Maximum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_max; - /* Minimum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_min; - /* Maximum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_max; - /* Minimum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_min; - /* Maximum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_max; - /* The units for timer parameters, in nanoseconds. */ - uint16_t timer_units; - uint8_t unused_0[1]; + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0; + uint16_t unused_1; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + uint8_t unused_2[2]; + /* + * This value indicates the destination MAC address in + * the Ethernet header. + */ + uint8_t dst_macaddr[6]; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. + */ + uint16_t ivlan_vid; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the tunnel Ethernet header. + */ + uint16_t t_ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the tunnel Ethernet header. + */ + uint16_t t_ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + uint16_t unused_3; + uint32_t unused_4; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path. + */ + uint16_t dst_id; + /* + * If set, this value shall represent the L2 context that matches the + * L2 information of the decap filter. + */ + uint16_t l2_ctxt_ref_id; +} __rte_packed; + +/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************************** - * hwrm_ring_cmpl_ring_qaggint_params * - **************************************/ +/****************************** + * hwrm_cfa_decap_filter_free * + ******************************/ -/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_input { +/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_decap_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24604,13 +38090,13 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint8_t unused_0[6]; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_output { +/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24619,70 +38105,25 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* - * When this bit is set to '1', interrupt max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ - UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ - UINT32_C(0x2) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; - /* - * Number of completions to aggregate before DMA - * during the interrupt mode. - */ - uint16_t num_cmpl_dma_aggr_during_int; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). - */ - uint16_t cmpl_aggr_dma_tmr; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. - */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; - /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. - */ - uint16_t int_lat_tmr_max; - /* - * Minimum number of completions aggregated before signaling - * an interrupt. - */ - uint16_t num_cmpl_aggr_int; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/***************************************** - * hwrm_ring_cmpl_ring_cfg_aggint_params * - *****************************************/ +/*********************** + * hwrm_cfa_flow_alloc * + ***********************/ -/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24711,109 +38152,268 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; uint16_t flags; + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \ + UINT32_C(0x1) + /* num_vlan is 2 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \ + UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 + /* no tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ + (UINT32_C(0x0) << 1) + /* 1 tag */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \ + (UINT32_C(0x1) << 1) + /* 2 tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \ + (UINT32_C(0x2) << 1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO + /* Enumeration denoting the Flow Type. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \ + UINT32_C(0x38) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 + /* L2 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ + (UINT32_C(0x0) << 3) + /* IPV4 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \ + (UINT32_C(0x1) << 3) + /* IPV6 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \ + (UINT32_C(0x2) << 3) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * When this bit is set to '1', interrupt latency max - * timer is reset whenever a completion is received. + * when set to 1, indicates TX flow offload for function specified + * in src_fid and the dst_fid should be set to invalid value. To + * indicate a VM to VM flow, both of the path_tx and path_rx flags + * need to be set. For virtio vSwitch offload case, the src_fid and + * dst_fid is set to the same fid value. For the SRIOV vSwitch + * offload case, the src_fid and dst_fid must be set to the same VF + * FID belong to the children VFs of the same PF to indicate VM to + * VM flow. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ - UINT32_C(0x1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x40) /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. + * when set to 1, indicates RX flow offload for function specified + * in dst_fid and the src_fid should be set to invalid value. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x80) + /* + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan + * header is required and the VXLAN VNI value is stored in the first + * 24 bits of the dmac field. This flag is only valid when the flow + * direction is RX. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ + UINT32_C(0x100) + /* + * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci + * field. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ + UINT32_C(0x200) + /* + * Tx Flow: vf fid. + * Rx Flow: pf fid. + */ + uint16_t src_fid; + /* Tunnel handle valid when tunnel flag is set. */ + uint32_t tunnel_handle; + uint16_t action_flags; + /* + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ + UINT32_C(0x1) + /* recycle is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ UINT32_C(0x2) /* - * Set this flag to 1 when configuring parameters on a - * notification queue. Set this flag to 0 when configuring - * parameters on a completion queue. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ UINT32_C(0x4) + /* meter is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \ + UINT32_C(0x8) + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \ + UINT32_C(0x10) + /* nat_src is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \ + UINT32_C(0x20) + /* nat_dest is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \ + UINT32_C(0x40) + /* nat_ipv4_address is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \ + UINT32_C(0x80) + /* l2_header_rewrite is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \ + UINT32_C(0x100) + /* ttl_decrement is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ + UINT32_C(0x200) /* - * Number of completions to aggregate before DMA - * during the normal mode. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. + * The type of tunnel is specified in the tunnel_type field. */ - uint16_t num_cmpl_dma_aggr; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ + UINT32_C(0x400) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ + UINT32_C(0x800) /* - * Number of completions to aggregate before DMA - * during the interrupt mode. + * If set to 1 an attempt will be made to try to offload this flow + * to the most optimal flow table resource. If set to 0, the flow + * will be placed to the default flow table resource. */ - uint16_t num_cmpl_dma_aggr_during_int; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ + UINT32_C(0x1000) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). + * If set to 1 there will be no attempt to allocate an on-chip try + * to offload this flow. If set to 0, which will keep compatibility + * with the older drivers, will cause the FW to attempt to allocate + * an on-chip flow counter for the newly created flow. This will + * keep the existing behavior with EM flows which always had an + * associated flow counter. */ - uint16_t cmpl_aggr_dma_tmr; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ + UINT32_C(0x2000) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. + * Tx Flow: pf or vf fid. + * Rx Flow: vf fid. */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; + uint16_t dst_fid; + /* VLAN tpid, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tci; + /* Meter id, valid when meter flag is set. */ + uint16_t act_meter_id; + /* Flow with the same l2 context tcam key. */ + uint16_t ref_flow_handle; + /* This value sets the match value for the ethertype. */ + uint16_t ethertype; + /* valid when num tags is 1 or 2. */ + uint16_t outer_vlan_tci; + /* This value sets the match value for the Destination MAC address. */ + uint16_t dmac[3]; + /* valid when num tags is 2. */ + uint16_t inner_vlan_tci; + /* This value sets the match value for the Source MAC address. */ + uint16_t smac[3]; + /* The bit length of destination IP address mask. */ + uint8_t ip_dst_mask_len; + /* The bit length of source IP address mask. */ + uint8_t ip_src_mask_len; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * cmpls before signaling the interrupt after the - * interrupt is enabled. + * The value of source port. + * Applies to UDP and TCP traffic. */ - uint16_t int_lat_tmr_max; + uint16_t l4_src_port; /* - * Minimum number of completions aggregated before signaling - * an interrupt. + * The value of source port mask. + * Applies to UDP and TCP traffic. */ - uint16_t num_cmpl_aggr_int; + uint16_t l4_src_port_mask; /* - * Bitfield that indicates which parameters are to be applied. Only - * required when configuring devices with notification queues, and - * used in that case to set certain parameters on completion queues - * and others on notification queues. + * The value of destination port. + * Applies to UDP and TCP traffic. */ - uint16_t enables; + uint16_t l4_dst_port; /* - * This bit must be '1' for the num_cmpl_dma_aggr field to be - * configured. + * The value of destination port mask. + * Applies to UDP and TCP traffic. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ - UINT32_C(0x1) + uint16_t l4_dst_port_mask; /* - * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be - * configured. + * NAT IPv4/6 address based on address type flag. + * 0 values are ignored. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ - UINT32_C(0x2) + uint32_t nat_ip_address[4]; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; /* - * This bit must be '1' for the cmpl_aggr_dma_tmr field to be - * configured. + * The NAT source/destination port based on direction flag. + * Applies to UDP and TCP traffic. + * 0 values are ignored. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ + uint16_t nat_port; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* The value of ip protocol. */ + uint8_t ip_proto; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ UINT32_C(0x4) - /* - * This bit must be '1' for the int_lat_tmr_min field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * This bit must be '1' for the int_lat_tmr_max field to be - * configured. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ - UINT32_C(0x10) + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) /* - * This bit must be '1' for the num_cmpl_aggr_int field to be - * configured. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ - UINT32_C(0x20) - uint8_t unused_0[4]; + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL } __rte_packed; -/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { +/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ +struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24822,24 +38422,99 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; + uint32_t flow_counter_id; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*********************** - * hwrm_ring_grp_alloc * - ***********************/ +/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ +struct hwrm_cfa_flow_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* No more L2 Context TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) + /* No more action records */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) + /* No more flow counters */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) + /* No more wild-card TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) + /* Hash collsion in exact match tables */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) + /* Key is already installed */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) + /* Flow Context DB is out of resource */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ + HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB + uint8_t unused_0[7]; +} __rte_packed; +/********************** + * hwrm_cfa_flow_free * + **********************/ -/* hwrm_ring_grp_alloc_input (size:192b/24B) */ -struct hwrm_ring_grp_alloc_input { + +/* hwrm_cfa_flow_free_input (size:256b/32B) */ +struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24868,31 +38543,17 @@ struct hwrm_ring_grp_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies the CR associated with the ring - * group. - */ - uint16_t cr; - /* - * This value identifies the main RR associated with the ring - * group. - */ - uint16_t rr; - /* - * This value identifies the aggregation RR associated with - * the ring group. If this value is 0xFF... (All Fs), then no - * Aggregation ring will be set. - */ - uint16_t ar; - /* - * This value identifies the statistics context associated - * with the ring group. - */ - uint16_t sc; + /* Flow record index. */ + uint16_t flow_handle; + uint16_t unused_0; + /* Flow counter id to be freed. */ + uint32_t flow_counter_id; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; } __rte_packed; -/* hwrm_ring_grp_alloc_output (size:128b/16B) */ -struct hwrm_ring_grp_alloc_output { +/* hwrm_cfa_flow_free_output (size:256b/32B) */ +struct hwrm_cfa_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24901,30 +38562,264 @@ struct hwrm_ring_grp_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet is 64 b */ + uint64_t packet; + /* byte is 64 b */ + uint64_t byte; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_cfa_flow_action_data (size:960b/120B) */ +struct hwrm_cfa_flow_action_data { + uint16_t action_flags; + /* Setting of this flag indicates accept action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \ + UINT32_C(0x1) + /* Setting of this flag indicates recycle action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \ + UINT32_C(0x2) + /* Setting of this flag indicates drop action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \ + UINT32_C(0x4) + /* Setting of this flag indicates meter action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \ + UINT32_C(0x8) + /* Setting of this flag indicates tunnel action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ + UINT32_C(0x10) + /* + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. + */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ + UINT32_C(0x20) + /* Setting of this flag indicates ttl decrement action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \ + UINT32_C(0x40) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ + UINT32_C(0x80) + /* Setting of this flag indicates encap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ + UINT32_C(0x100) + /* Setting of this flag indicates decap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ + UINT32_C(0x200) + /* Meter id. */ + uint16_t act_meter_id; + /* VNIC id. */ + uint16_t vnic_id; + /* vport number. */ + uint16_t vport_id; + /* The NAT source/destination. */ + uint16_t nat_port; + uint16_t unused_0[3]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ + HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 + uint8_t unused[7]; + /* This value is encap data for the associated encap type. */ + uint32_t encap_data[20]; +} __rte_packed; + +/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ +struct hwrm_cfa_flow_tunnel_hdr_data { + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) /* - * This is the ring group ID value. Use this value to program - * the default ring group for the VNIC or as table entries - * in an RSS/COS context. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint32_t ring_group_id; - uint8_t unused_0[3]; + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint8_t valid; + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \ + HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused[3]; + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). + */ + uint32_t tunnel_id; +} __rte_packed; + +/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ +struct hwrm_cfa_flow_l4_key_data { + /* The value of source port. */ + uint16_t l4_src_port; + /* The value of destination port. */ + uint16_t l4_dst_port; + uint32_t unused; +} __rte_packed; + +/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ +struct hwrm_cfa_flow_l3_key_data { + /* The value of ip protocol. */ + uint8_t ip_protocol; + uint8_t unused_0[7]; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + uint32_t unused[2]; +} __rte_packed; + +/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ +struct hwrm_cfa_flow_l2_key_data { + /* Destination MAC address. */ + uint16_t dmac[3]; + uint16_t unused_0; + /* Source MAC address. */ + uint16_t smac[3]; + uint16_t unused_1; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; + uint16_t unused_2; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* Ethertype. */ + uint16_t ethertype; + /* Number of VLAN tags. */ + uint16_t num_vlan_tags; + /* VLAN tpid. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci. */ + uint16_t l2_rewrite_vlan_tci; + uint8_t unused_3[2]; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + uint8_t unused[8]; +} __rte_packed; + +/* hwrm_cfa_flow_key_data (size:4160b/520B) */ +struct hwrm_cfa_flow_key_data { + /* Flow associated tunnel L2 header key info. */ + uint32_t t_l2_key_data[14]; + /* Flow associated tunnel L2 header mask info. */ + uint32_t t_l2_key_mask[14]; + /* Flow associated tunnel L3 header key info. */ + uint32_t t_l3_key_data[16]; + /* Flow associated tunnel L3 header mask info. */ + uint32_t t_l3_key_mask[16]; + /* Flow associated tunnel L4 header key info. */ + uint32_t t_l4_key_data[2]; + /* Flow associated tunnel L4 header mask info. */ + uint32_t t_l4_key_mask[2]; + /* Flow associated tunnel header info. */ + uint32_t tunnel_hdr[2]; + /* Flow associated L2 header key info. */ + uint32_t l2_key_data[14]; + /* Flow associated L2 header mask info. */ + uint32_t l2_key_mask[14]; + /* Flow associated L3 header key info. */ + uint32_t l3_key_data[16]; + /* Flow associated L3 header mask info. */ + uint32_t l3_key_mask[16]; + /* Flow associated L4 header key info. */ + uint32_t l4_key_data[2]; + /* Flow associated L4 header mask info. */ + uint32_t l4_key_mask[2]; } __rte_packed; /********************** - * hwrm_ring_grp_free * + * hwrm_cfa_flow_info * **********************/ -/* hwrm_ring_grp_free_input (size:192b/24B) */ -struct hwrm_ring_grp_free_input { +/* hwrm_cfa_flow_info_input (size:256b/32B) */ +struct hwrm_cfa_flow_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24953,13 +38848,31 @@ struct hwrm_ring_grp_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the ring group ID value. */ - uint32_t ring_group_id; - uint8_t unused_0[4]; + /* Flow record index. */ + uint16_t flow_handle; + /* Max flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ + UINT32_C(0xfff) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ + UINT32_C(0x1000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ + UINT32_C(0x2000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ + UINT32_C(0x4000) + /* Direction rx = 1 */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ + UINT32_C(0x8000) + uint8_t unused_0[6]; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; } __rte_packed; -/* hwrm_ring_grp_free_output (size:128b/16B) */ -struct hwrm_ring_grp_free_output { +/* hwrm_cfa_flow_info_output (size:5632b/704B) */ +struct hwrm_cfa_flow_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24968,451 +38881,175 @@ struct hwrm_ring_grp_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* profile is 8 b */ + uint8_t profile; + /* src_fid is 16 b */ + uint16_t src_fid; + /* dst_fid is 16 b */ + uint16_t dst_fid; + /* l2_ctxt_id is 16 b */ + uint16_t l2_ctxt_id; + /* em_info is 64 b */ + uint64_t em_info; + /* tcam_info is 64 b */ + uint64_t tcam_info; + /* vfp_tcam_info is 64 b */ + uint64_t vfp_tcam_info; + /* ar_id is 16 b */ + uint16_t ar_id; + /* flow_handle is 16 b */ + uint16_t flow_handle; + /* tunnel_handle is 32 b */ + uint32_t tunnel_handle; + /* The flow aging timer for the flow, the unit is 100 milliseconds */ + uint16_t flow_timer; + uint8_t unused_0[6]; + /* Flow associated L2, L3 and L4 headers info. */ + uint32_t flow_key_data[130]; + /* Flow associated action record info. */ + uint32_t flow_action_info[30]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* - * special reserved flow ID to identify per function default - * flows for vSwitch offload - */ -#define DEFAULT_FLOW_ID 0xFFFFFFFFUL -/* - * special reserved flow ID to identify per function RoCEv1 - * flows - */ -#define ROCEV1_FLOW_ID 0xFFFFFFFEUL -/* - * special reserved flow ID to identify per function RoCEv2 - * flows - */ -#define ROCEV2_FLOW_ID 0xFFFFFFFDUL -/* - * special reserved flow ID to identify per function RoCEv2 - * CNP flows - */ -#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL -/**************************** - * hwrm_cfa_l2_filter_alloc * - ****************************/ +/*********************** + * hwrm_cfa_flow_flush * + ***********************/ -/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ -struct hwrm_cfa_l2_filter_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x2) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x4) - /* - * If this flag is set, all t_l2_* fields are invalid - * and they should not be specified. - * If this flag is set, then l2_* fields refer to - * fields of outermost L2 header. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ - UINT32_C(0x8) - /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \ - UINT32_C(0x30) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ - (UINT32_C(0x0) << 4) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \ - (UINT32_C(0x1) << 4) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \ - (UINT32_C(0x2) << 4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE - /* - * Setting of this flag indicates that no XDP filter is created with - * L2 filter. - * 0 - legacy behavior, XDP filter is created with L2 filter - * 1 - XDP filter won't be created with L2 filter - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \ - UINT32_C(0x40) - /* - * Setting this flag to 1 indicate the L2 fields in this command - * pertain to source fields. Setting this flag to 0 indicate the - * L2 fields in this command pertain to the destination fields - * and this is the default/legacy behavior. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \ - UINT32_C(0x80) - uint32_t enables; - /* - * This bit must be '1' for the l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ - UINT32_C(0x1) - /* - * This bit must be '1' for the l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ - UINT32_C(0x2) - /* - * This bit must be '1' for the l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ - UINT32_C(0x4) - /* - * This bit must be '1' for the l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ - UINT32_C(0x8) - /* - * This bit must be '1' for the l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ - UINT32_C(0x10) - /* - * This bit must be '1' for the l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ - UINT32_C(0x20) - /* - * This bit must be '1' for the t_l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ - UINT32_C(0x40) - /* - * This bit must be '1' for the t_l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ - UINT32_C(0x80) - /* - * This bit must be '1' for the t_l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ - UINT32_C(0x100) - /* - * This bit must be '1' for the t_l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ - UINT32_C(0x200) - /* - * This bit must be '1' for the t_l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ - UINT32_C(0x400) - /* - * This bit must be '1' for the t_l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ - UINT32_C(0x800) - /* - * This bit must be '1' for the src_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the src_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the num_vlans field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the t_num_vlans field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \ - UINT32_C(0x40000) - /* - * This value sets the match value for the L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t l2_addr[6]; - /* This value sets the match value for the number of VLANs. */ - uint8_t num_vlans; - /* - * This value sets the match value for the number of VLANs - * in the tunnel headers. - */ - uint8_t t_num_vlans; - /* - * This value sets the mask value for the L2 address. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint8_t l2_addr_mask[6]; - /* This value sets VLAN ID value for outer VLAN. */ - uint16_t l2_ovlan; - /* - * This value sets the mask value for the ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ovlan_mask; - /* This value sets VLAN ID value for inner VLAN. */ - uint16_t l2_ivlan; - /* - * This value sets the mask value for the ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ivlan_mask; - uint8_t unused_1[2]; - /* - * This value sets the match value for the tunnel - * L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t t_l2_addr[6]; - uint8_t unused_2[2]; - /* - * This value sets the mask value for the tunnel L2 - * address. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint8_t t_l2_addr_mask[6]; - /* This value sets VLAN ID value for tunnel outer VLAN. */ - uint16_t t_l2_ovlan; - /* - * This value sets the mask value for the tunnel ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t t_l2_ovlan_mask; - /* This value sets VLAN ID value for tunnel inner VLAN. */ - uint16_t t_l2_ivlan; - /* - * This value sets the mask value for the tunnel ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t t_l2_ivlan_mask; - /* This value identifies the type of source of the packet. */ - uint8_t src_type; - /* Network port */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) - /* Physical function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) - /* Virtual function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) - /* Virtual NIC of a function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) - /* Embedded processor for CFA management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) - /* Embedded processor for OOB management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) - /* Embedded processor for RoCE */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) - /* Embedded processor for network proxy functions */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG - uint8_t unused_3; +/* hwrm_cfa_flow_flush_input (size:256b/32B) */ +struct hwrm_cfa_flow_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value is the id of the source. - * For a network port, it represents port_id. - * For a physical function, it represents fid. - * For a virtual function, it represents vf_id. - * For a vnic, it represents vnic_id. - * For embedded processors, this id is not valid. - * - * Notes: - * 1. The function ID is implied if it src_id is - * not provided for a src_type that is either + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t src_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_4; + uint16_t cmpl_ring; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t dst_id; + uint16_t seq_id; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t mirror_vnic_id; + uint16_t target_id; /* - * This hint is provided to help in placing - * the filter in the filter table. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ - UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ + uint64_t resp_addr; + /* flags is 32 b */ + uint32_t flags; + /* + * Set to 1 to indicate the page size, page layers, and + * flow_handle_table_dma_addr fields are valid. The flow flush + * operation should only flush the flows from the flow table + * specified. This flag is set to 0 by older driver. For older + * firmware, setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ + /* + * Set to 1 to indicate flow flush operation to cleanup all the + * flows, meters, CFA context memory tables etc. This flag is set to + * 0 by older driver. For older firmware, setting this flag has no + * effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ + /* + * Set to 1 to indicate flow flush operation to cleanup all the + * flows by the caller. This flag is set to 0 by older driver. For + * older firmware, setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ UINT32_C(0x4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN - uint8_t unused_5; - uint32_t unused_6; /* - * This is the ID of the filter that goes along with - * the pri_hint. - * - * This field is valid only for the following values. - * 1 - Above the given filter - * 2 - Below the given filter + * Set to 1 to indicate the flow counter IDs are included in the + * flow table. */ - uint64_t l2_filter_id_hint; + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ + UINT32_C(0x8000000) + /* + * This specifies the size of flow handle entries provided by the + * driver in the flow table specified below. Only two flow handle + * size enums are defined. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ + UINT32_C(0xc0000000) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \ + 30 + /* The flow handle is 16bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \ + (UINT32_C(0x0) << 30) + /* The flow handle is 64bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT + /* Specify page size of the flow table memory. */ + uint8_t page_size; + /* The page size is 4K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* The page size is 8K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* The page size is 64K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* The page size is 256K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* The page size is 1M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* The page size is 2M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* The page size is 4M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* The page size is 1G */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G + /* FLow table memory indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 + /* number of flows in the flow table */ + uint16_t num_flows; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; } __rte_packed; -/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_l2_filter_alloc_output { +/* hwrm_cfa_flow_flush_output (size:128b/16B) */ +struct hwrm_cfa_flow_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25421,69 +39058,167 @@ struct hwrm_cfa_l2_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint8_t unused_0[7]; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - uint64_t l2_filter_id; + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_cfa_flow_stats * + ***********************/ + + +/* hwrm_cfa_flow_stats_input (size:640b/80B) */ +struct hwrm_cfa_flow_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) + uint16_t cmpl_ring; /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) + uint16_t seq_id; /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Flow handle. */ + uint16_t num_flows; + /* Flow handle. */ + uint16_t flow_handle_0; + /* Flow handle. */ + uint16_t flow_handle_1; + /* Flow handle. */ + uint16_t flow_handle_2; + /* Flow handle. */ + uint16_t flow_handle_3; + /* Flow handle. */ + uint16_t flow_handle_4; + /* Flow handle. */ + uint16_t flow_handle_5; + /* Flow handle. */ + uint16_t flow_handle_6; + /* Flow handle. */ + uint16_t flow_handle_7; + /* Flow handle. */ + uint16_t flow_handle_8; + /* Flow handle. */ + uint16_t flow_handle_9; + uint8_t unused_0[2]; + /* Flow ID of a flow. */ + uint32_t flow_id_0; + /* Flow ID of a flow. */ + uint32_t flow_id_1; + /* Flow ID of a flow. */ + uint32_t flow_id_2; + /* Flow ID of a flow. */ + uint32_t flow_id_3; + /* Flow ID of a flow. */ + uint32_t flow_id_4; + /* Flow ID of a flow. */ + uint32_t flow_id_5; + /* Flow ID of a flow. */ + uint32_t flow_id_6; + /* Flow ID of a flow. */ + uint32_t flow_id_7; + /* Flow ID of a flow. */ + uint32_t flow_id_8; + /* Flow ID of a flow. */ + uint32_t flow_id_9; +} __rte_packed; + +/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ +struct hwrm_cfa_flow_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* packet_0 is 64 b */ + uint64_t packet_0; + /* packet_1 is 64 b */ + uint64_t packet_1; + /* packet_2 is 64 b */ + uint64_t packet_2; + /* packet_3 is 64 b */ + uint64_t packet_3; + /* packet_4 is 64 b */ + uint64_t packet_4; + /* packet_5 is 64 b */ + uint64_t packet_5; + /* packet_6 is 64 b */ + uint64_t packet_6; + /* packet_7 is 64 b */ + uint64_t packet_7; + /* packet_8 is 64 b */ + uint64_t packet_8; + /* packet_9 is 64 b */ + uint64_t packet_9; + /* byte_0 is 64 b */ + uint64_t byte_0; + /* byte_1 is 64 b */ + uint64_t byte_1; + /* byte_2 is 64 b */ + uint64_t byte_2; + /* byte_3 is 64 b */ + uint64_t byte_3; + /* byte_4 is 64 b */ + uint64_t byte_4; + /* byte_5 is 64 b */ + uint64_t byte_5; + /* byte_6 is 64 b */ + uint64_t byte_6; + /* byte_7 is 64 b */ + uint64_t byte_7; + /* byte_8 is 64 b */ + uint64_t byte_8; + /* byte_9 is 64 b */ + uint64_t byte_9; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_cfa_l2_filter_free * - ***************************/ +/*********************************** + * hwrm_cfa_flow_aging_timer_reset * + ***********************************/ -/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_l2_filter_free_input { +/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ +struct hwrm_cfa_flow_aging_timer_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25512,15 +39247,20 @@ struct hwrm_cfa_l2_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * New flow timer value for the flow specified in the ext_flow_handle. + * The flow timer unit is 100ms. */ - uint64_t l2_filter_id; + uint32_t flow_timer; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; } __rte_packed; -/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_free_output { +/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ +struct hwrm_cfa_flow_aging_timer_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25534,19 +39274,20 @@ struct hwrm_cfa_l2_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************** - * hwrm_cfa_l2_filter_cfg * - **************************/ +/*************************** + * hwrm_cfa_flow_aging_cfg * + ***************************/ -/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ -struct hwrm_cfa_l2_filter_cfg_input { +/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ +struct hwrm_cfa_flow_aging_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25575,80 +39316,122 @@ struct hwrm_cfa_l2_filter_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + /* The bit field to enable per flow aging configuration. */ + uint16_t enables; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This bit must be '1' for the tcp flow timer field to be + * configured */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ UINT32_C(0x1) + /* + * This bit must be '1' for the tcp finish timer field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ + UINT32_C(0x2) + /* + * This bit must be '1' for the udp flow timer field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ + UINT32_C(0x4) + /* + * This bit must be '1' for the eem dma interval field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ + UINT32_C(0x8) + /* + * This bit must be '1' for the eem notice interval field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ + UINT32_C(0x10) + /* + * This bit must be '1' for the eem context memory maximum entries + * field to be configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ + UINT32_C(0x20) + /* + * This bit must be '1' for the eem context memory ID field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the eem context memory type field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ + UINT32_C(0x80) + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) /* tx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) /* rx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * Enumeration denoting the enable, disable eem flow aging + * configuration. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ - UINT32_C(0x2) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ + (UINT32_C(0x0) << 1) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE + uint8_t unused_0; /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + * The flow aging timer for all TCP flows, the unit is 100 + * milliseconds. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \ - UINT32_C(0xc) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ - (UINT32_C(0x0) << 2) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \ - (UINT32_C(0x1) << 2) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \ - (UINT32_C(0x2) << 2) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \ - HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE - uint32_t enables; + uint32_t tcp_flow_timer; /* - * This bit must be '1' for the dst_id field to be - * configured. + * The TCP finished timer for all TCP flows, the unit is 100 + * milliseconds. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ - UINT32_C(0x1) + uint32_t tcp_fin_timer; /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * The flow aging timer for all UDP flows, the unit is 100 + * milliseconds. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) + uint32_t udp_flow_timer; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. */ - uint64_t l2_filter_id; + uint16_t eem_dma_interval; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. */ - uint32_t dst_id; + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + uint16_t eem_ctx_mem_type; /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * The content of context memory is eem ejection data, the size of + * each entry is 4 bytes. */ - uint32_t new_mirror_vnic_id; + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ + UINT32_C(0x0) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_cfg_output { +/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ +struct hwrm_cfa_flow_aging_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25662,19 +39445,20 @@ struct hwrm_cfa_l2_filter_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_cfa_l2_set_rx_mask * - ***************************/ +/**************************** + * hwrm_cfa_flow_aging_qcfg * + ****************************/ -/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ -struct hwrm_cfa_l2_set_rx_mask_input { +/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ +struct hwrm_cfa_flow_aging_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25703,134 +39487,24 @@ struct hwrm_cfa_l2_set_rx_mask_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VNIC ID */ - uint32_t vnic_id; - uint32_t mask; - /* - * When this bit is '1', the function is requested to accept - * multi-cast packets specified by the multicast addr table. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ - UINT32_C(0x2) - /* - * When this bit is '1', the function is requested to accept - * all multi-cast packets. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ - UINT32_C(0x4) - /* - * When this bit is '1', the function is requested to accept - * broadcast packets. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ - UINT32_C(0x8) - /* - * When this bit is '1', the function is requested to be - * put in the promiscuous mode. - * - * The HWRM should accept any function to set up - * promiscuous mode. - * - * The HWRM shall follow the semantics below for the - * promiscuous mode support. - * # When partitioning is not enabled on a port - * (i.e. single PF on the port), then the PF shall - * be allowed to be in the promiscuous mode. When the - * PF is in the promiscuous mode, then it shall - * receive all host bound traffic on that port. - * # When partitioning is enabled on a port - * (i.e. multiple PFs per port) and a PF on that - * port is in the promiscuous mode, then the PF - * receives all traffic within that partition as - * identified by a unique identifier for the - * PF (e.g. S-Tag). If a unique outer VLAN - * for the PF is specified, then the setting of - * promiscuous mode on that PF shall result in the - * PF receiving all host bound traffic with matching - * outer VLAN. - * # A VF shall can be set in the promiscuous mode. - * In the promiscuous mode, the VF does not receive any - * traffic unless a unique outer VLAN for the - * VF is specified. If a unique outer VLAN - * for the VF is specified, then the setting of - * promiscuous mode on that VF shall result in the - * VF receiving all host bound traffic with the - * matching outer VLAN. - * # The HWRM shall allow the setting of promiscuous - * mode on a function independently from the - * promiscuous mode settings on other functions. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ - UINT32_C(0x10) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the outermost Layer 2 destination MAC - * address field. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ - UINT32_C(0x20) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the VLAN-tagged packets that match the - * TPID and VID fields of VLAN tags in the VLAN tag - * table specified in this command. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ - UINT32_C(0x40) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets that match the TPID and VID fields of VLAN - * tags in the VLAN tag table specified in this command. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ - UINT32_C(0x80) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets matching any VLAN tag. - * - * If this flag is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan - * flags is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * The HWRM client shall set at most one flag out of - * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ - UINT32_C(0x100) - /* This is the address for mcast address tbl. */ - uint64_t mc_tbl_addr; - /* - * This value indicates how many entries in mc_tbl are valid. - * Each entry is 6 bytes. - */ - uint32_t num_mc_entries; - uint8_t unused_0[4]; - /* - * This is the address for VLAN tag table. - * Each VLAN entry in the table is 4 bytes of a VLAN tag - * including TPID, PCP, DEI, and VID fields in network byte - * order. - */ - uint64_t vlan_tag_tbl_addr; /* - * This value indicates how many entries in vlan_tag_tbl are - * valid. Each entry is 4 bytes. + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. */ - uint32_t num_vlan_tags; - uint8_t unused_1[4]; + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; } __rte_packed; -/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ -struct hwrm_cfa_l2_set_rx_mask_output { +/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ +struct hwrm_cfa_flow_aging_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25839,42 +39513,56 @@ struct hwrm_cfa_l2_set_rx_mask_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * The current flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t tcp_flow_timer; + /* + * The current TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t tcp_fin_timer; + /* + * The current flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ + uint32_t udp_flow_timer; + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ + uint16_t eem_dma_interval; + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + /* The context memory type for eem flow aging. */ + uint16_t eem_ctx_mem_type; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ -struct hwrm_cfa_l2_set_rx_mask_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* Unable to complete operation due to conflict with Ntuple Filter */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ - HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR - uint8_t unused_0[7]; -} __rte_packed; - -/******************************* - * hwrm_cfa_vlan_antispoof_cfg * - *******************************/ +/***************************** + * hwrm_cfa_flow_aging_qcaps * + *****************************/ -/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_cfg_input { +/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ +struct hwrm_cfa_flow_aging_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25904,26 +39592,23 @@ struct hwrm_cfa_vlan_antispoof_cfg_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being configured. - * Only valid for a VF FID configured by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* Number of VLAN entries in the vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table. Each table entry contains the 16-bit TPID - * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, - * all in network order to match hwrm_cfa_l2_set_rx_mask. - * For an individual VLAN entry, the mask value should be 0xfff - * for the 12-bit VLAN ID. + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. */ - uint64_t vlan_tag_mask_tbl_addr; + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; } __rte_packed; -/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_cfg_output { +/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ +struct hwrm_cfa_flow_aging_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25932,24 +39617,42 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * The maximum flow aging timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t max_tcp_flow_timer; + /* + * The maximum TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t max_tcp_fin_timer; + /* + * The maximum flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ + uint32_t max_udp_flow_timer; + /* The maximum aging flows that HW can support. */ + uint32_t max_aging_flows; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_vlan_antispoof_qcfg * - ********************************/ +/********************************** + * hwrm_cfa_tcp_flag_process_qcfg * + **********************************/ -/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_input { +/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25978,30 +39681,10 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being queried. - * Only valid for a VF FID queried by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* - * Maximum number of VLAN entries the firmware is allowed to DMA - * to vlan_tag_mask_tbl. - */ - uint32_t max_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table to which firmware will DMA to. Each table - * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), - * 16-bit VLAN ID, and a 16-bit mask, all in network order to - * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, - * the mask value should be 0xfff for the 12-bit VLAN ID. - */ - uint64_t vlan_tag_mask_tbl_addr; } __rte_packed; -/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_output { +/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26010,26 +39693,39 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - uint8_t unused_0[3]; + /* The port 0 RX mirror action record ID. */ + uint16_t rx_ar_id_port0; + /* The port 1 RX mirror action record ID. */ + uint16_t rx_ar_id_port1; + /* + * The port 0 RX action record ID for TX TCP flag packets from + * loopback path. + */ + uint16_t tx_ar_id_port0; + /* + * The port 1 RX action record ID for TX TCP flag packets from + * loopback path. + */ + uint16_t tx_ar_id_port1; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_tunnel_filter_alloc * - ********************************/ +/************************** + * hwrm_cfa_vf_pair_alloc * + **************************/ -/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ -struct hwrm_cfa_tunnel_filter_alloc_input { +/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26057,221 +39753,18 @@ struct hwrm_cfa_tunnel_filter_alloc_input { * physical address (HPA) or a guest physical address (GPA) and must * point to a physically contiguous block of memory. */ - uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the l2_addr field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ - UINT32_C(0x2) - /* - * This bit must be '1' for the l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ - UINT32_C(0x4) - /* - * This bit must be '1' for the l3_addr field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the l3_addr_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \ - UINT32_C(0x10) - /* - * This bit must be '1' for the t_l3_addr_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \ - UINT32_C(0x20) - /* - * This bit must be '1' for the t_l3_addr field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \ - UINT32_C(0x40) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the vni field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \ - UINT32_C(0x100) - /* - * This bit must be '1' for the dst_vnic_id field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \ - UINT32_C(0x200) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x400) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value sets the match value for the inner L2 - * MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t l2_addr[6]; - /* - * This value sets VLAN ID value for inner VLAN. - * Only 12-bits of VLAN ID are used in setting the filter. - */ - uint16_t l2_ivlan; - /* - * The value of inner destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t l3_addr[4]; - /* - * The value of tunnel destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t t_l3_addr[4]; - /* - * This value indicates the type of inner IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t l3_addr_type; - /* - * This value indicates the type of tunnel IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t t_l3_addr_type; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* - * tunnel_flags allows the user to indicate the tunnel tag detection - * for the tunnel type specified in tunnel_type. - */ - uint8_t tunnel_flags; - /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match the geneve OAM packet. - * If the tunnel_type is nvgre or gre, then this bit indicates if - * we need to detect checksum present bit in geneve header. - * If the tunnel_type is mpls, then this bit indicates if we need - * to match mpls packet with explicit IPV4/IPV6 null header. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \ - UINT32_C(0x1) - /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to detect the critical option bit set in the oam packet. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with key present bit set in - * gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from inner/second label. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \ - UINT32_C(0x2) - /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match geneve packet with extended header bit set in - * geneve header. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with sequence number - * present bit set in gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from out/first label. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \ - UINT32_C(0x4) - /* - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. - */ - uint32_t vni; - /* Logical VNIC ID of the destination VNIC. */ - uint32_t dst_vnic_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint32_t mirror_vnic_id; + uint64_t resp_addr; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + uint8_t unused_0[4]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; } __rte_packed; -/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_alloc_output { +/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26280,66 +39773,25 @@ struct hwrm_cfa_tunnel_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_cfa_tunnel_filter_free * - *******************************/ +/************************* + * hwrm_cfa_vf_pair_free * + *************************/ -/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_free_input { +/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ +struct hwrm_cfa_vf_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26368,12 +39820,12 @@ struct hwrm_cfa_tunnel_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; + /* VF Pair name (32 byte string). */ + char pair_name[32]; } __rte_packed; -/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_tunnel_filter_free_output { +/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26387,19 +39839,20 @@ struct hwrm_cfa_tunnel_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*************************************** - * hwrm_cfa_redirect_tunnel_type_alloc * - ***************************************/ +/************************* + * hwrm_cfa_vf_pair_info * + *************************/ -/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_input { +/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26428,64 +39881,18 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* Tunnel alloc flags. */ - uint8_t flags; - /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ - UINT32_C(0x1) - uint8_t unused_0[4]; + uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* vf pair table index. */ + uint16_t vf_pair_index; + uint8_t unused_0[2]; + /* VF Pair name (32 byte string). */ + char vf_pair_name[32]; } __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_output { +/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ +struct hwrm_cfa_vf_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26494,24 +39901,46 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* vf pair table index. */ + uint16_t next_vf_pair_index; + /* vf pair member a's vf_fid. */ + uint16_t vf_a_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* vf pair member b's vf_fid. */ + uint16_t vf_b_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* vf pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + uint8_t unused_0[5]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************************** - * hwrm_cfa_redirect_tunnel_type_free * - **************************************/ +/*********************** + * hwrm_cfa_pair_alloc * + ***********************/ -/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_free_input { +/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ +struct hwrm_cfa_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26540,59 +39969,110 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \ + /* + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). + */ + uint16_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \ UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \ + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \ UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \ + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \ UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \ + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \ UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \ + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \ UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ + /* Modify existing rep2fn pair and move pair to new PF. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \ UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \ UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \ + /* + * Truflow pair between REP on local host with PF or VF on specified + * host. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \ UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical Host (0xff-local host). */ + uint8_t host_b_id; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + /* Loopback port (0xff-internal loopback), valid for mode-3. */ + uint8_t port_id; + /* Priority used for encap of loopback packets valid for mode-3. */ + uint8_t pri; + /* New PF for rep2fn modify, valid for mode 5. */ + uint16_t new_pf_fid; + uint32_t enables; + /* + * This bit must be '1' for the q_ab field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) + /* + * This bit must be '1' for the q_ba field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) + /* + * This bit must be '1' for the fc_ab field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) + /* + * This bit must be '1' for the fc_ba field to be + * configured. + */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) + /* VF Pair name (32 byte string). */ + char pair_name[32]; + /* + * The q_ab value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the A to B direction of + * the interface pair. The default value is 0. + */ + uint8_t q_ab; + /* + * The q_ba value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the B to A direction of + * the interface pair. The default value is 1. + */ + uint8_t q_ba; + /* + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the A to B direction. The default value is 0, meaning that + * packets will be dropped when the B-side RX rings are full. + */ + uint8_t fc_ab; + /* + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the B to A direction. The default value is 1, meaning that + * the RX CoS queue will be flow controlled when the A-side RX rings + * are full. + */ + uint8_t fc_ba; + uint8_t unused_1[4]; } __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_free_output { +/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ +struct hwrm_cfa_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26601,24 +40081,33 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Only valid for modes 1 and 2. */ + uint16_t rx_cfa_code_a; + /* Only valid for modes 1 and 2. */ + uint16_t tx_cfa_action_a; + /* Only valid for mode 2. */ + uint16_t rx_cfa_code_b; + /* Only valid for mode 2. */ + uint16_t tx_cfa_action_b; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************************** - * hwrm_cfa_redirect_tunnel_type_info * - **************************************/ +/********************** + * hwrm_cfa_pair_free * + **********************/ -/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_info_input { +/* hwrm_cfa_pair_free_input (size:448b/56B) */ +struct hwrm_cfa_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26647,59 +40136,46 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + uint8_t unused_0[3]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). + */ + uint16_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + /* Modify existing rep2fn pair and move pair to new PF. */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) + /* + * Truflow pair between REP on local host with PF or VF on + * specified host. + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW } __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_info_output { +/* hwrm_cfa_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26708,133 +40184,147 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ -struct hwrm_vxlan_ipv4_hdr { - /* IPv4 version and header length. */ - uint8_t ver_hlen; - /* IPv4 header length */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 - /* Version */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 - /* IPv4 type of service. */ - uint8_t tos; - /* IPv4 identification. */ - uint16_t ip_id; - /* IPv4 flags and offset. */ - uint16_t flags_frag_offset; - /* IPv4 TTL. */ - uint8_t ttl; - /* IPv4 protocol. */ - uint8_t protocol; - /* IPv4 source address. */ - uint32_t src_ip_addr; - /* IPv4 destination address. */ - uint32_t dest_ip_addr; -} __rte_packed; +/********************** + * hwrm_cfa_pair_info * + **********************/ -/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ -struct hwrm_vxlan_ipv6_hdr { - /* IPv6 version, traffic class and flow label. */ - uint32_t ver_tc_flow_label; - /* IPv6 version shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \ - UINT32_C(0x1c) - /* IPv6 version mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \ - UINT32_C(0xf0000000) - /* IPv6 TC shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \ - UINT32_C(0x14) - /* IPv6 TC mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \ - UINT32_C(0xff00000) - /* IPv6 flow label shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \ - UINT32_C(0x0) - /* IPv6 flow label mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \ - UINT32_C(0xfffff) - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \ - HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK - /* IPv6 payload length. */ - uint16_t payload_len; - /* IPv6 next header. */ - uint8_t next_hdr; - /* IPv6 TTL. */ - uint8_t ttl; - /* IPv6 source address. */ - uint32_t src_ip_addr[4]; - /* IPv6 destination address. */ - uint32_t dest_ip_addr[4]; + +/* hwrm_cfa_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_pair_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* If this flag is set, lookup by PF id and VF id. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) + /* Pair table index. */ + uint16_t pair_index; + /* Pair pf index. */ + uint8_t pair_pfid; + /* Pair vf index. */ + uint8_t pair_vfid; + /* Pair name (32 byte string). */ + char pair_name[32]; } __rte_packed; -/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ -struct hwrm_cfa_encap_data_vxlan { - /* Source MAC address. */ - uint8_t src_mac_addr[6]; - /* reserved. */ - uint16_t unused_0; - /* Destination MAC address. */ - uint8_t dst_mac_addr[6]; - /* Number of VLAN tags. */ - uint8_t num_vlan_tags; - /* reserved. */ - uint8_t unused_1; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - /* L3 header fields. */ - uint32_t l3[10]; - /* IP version mask. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) - /* IP version 4. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) - /* IP version 6. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \ - HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 - /* UDP source port. */ - uint16_t src_port; - /* UDP destination port. */ - uint16_t dst_port; - /* VXLAN Network Identifier. */ - uint32_t vni; - /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ - uint8_t hdr_rsvd0[3]; - /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ - uint8_t hdr_rsvd1; - /* VXLAN header flags field. */ - uint8_t hdr_flags; - uint8_t unused[3]; +/* hwrm_cfa_pair_info_output (size:576b/72B) */ +struct hwrm_cfa_pair_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Pair table index. */ + uint16_t next_pair_index; + /* Pair member a's fid. */ + uint16_t a_fid; + /* Logical host number. */ + uint8_t host_a_index; + /* Logical PF number. */ + uint8_t pf_a_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_a; + /* Tx CFA action. */ + uint16_t tx_cfa_action_a; + /* Pair member b's fid. */ + uint16_t b_fid; + /* Logical host number. */ + uint8_t host_b_index; + /* Logical PF number. */ + uint8_t pf_b_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_b; + /* Tx CFA action. */ + uint16_t tx_cfa_action_b; + /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ + uint8_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR + /* Pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + /* Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; } __rte_packed; -/******************************* - * hwrm_cfa_encap_record_alloc * - *******************************/ +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ -/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ -struct hwrm_cfa_encap_record_alloc_input { +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vfr_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26863,64 +40353,20 @@ struct hwrm_cfa_encap_record_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; /* - * Setting of this flag indicates this encap record is external encap record. - * Resetting of this flag indicates this flag is internal encap record and - * this is the default setting. + * This field is reserved for the future use. + * It shall be set to 0. */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ - UINT32_C(0x2) - /* Encapsulation Type. */ - uint8_t encap_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ - UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ - HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 - uint8_t unused_0[3]; - /* This value is encap data used for the given encap type. */ - uint32_t encap_data[20]; + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; } __rte_packed; -/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_alloc_output { +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vfr_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26929,26 +40375,29 @@ struct hwrm_cfa_encap_record_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/****************************** - * hwrm_cfa_encap_record_free * - ******************************/ +/********************* + * hwrm_cfa_vfr_free * + *********************/ -/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ -struct hwrm_cfa_encap_record_free_input { +/* hwrm_cfa_vfr_free_input (size:448b/56B) */ +struct hwrm_cfa_vfr_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26977,13 +40426,20 @@ struct hwrm_cfa_encap_record_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved; uint8_t unused_0[4]; } __rte_packed; -/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_free_output { +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +struct hwrm_cfa_vfr_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26997,19 +40453,20 @@ struct hwrm_cfa_encap_record_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_ntuple_filter_alloc * - ********************************/ +/*************************************** + * hwrm_cfa_redirect_query_tunnel_type * + ***************************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_ntuple_filter_alloc_input { +/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ +struct hwrm_cfa_redirect_query_tunnel_type_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27038,348 +40495,159 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x2) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ - UINT32_C(0x4) - /* - * Setting of this flag indicates that the dst_id field contains function ID. - * If this is not set it indicates dest_id is VNIC or VPORT. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ - UINT32_C(0x8) - /* - * Setting of this flag indicates match on arp reply when ethertype is 0x0806. - * If this is not set it indicates no specific arp opcode matching. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ - UINT32_C(0x10) - /* - * Setting of this flag indicates that the dst_id field contains RFS ring - * table index. If this is not set it indicates dst_id is VNIC or VPORT - * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at - * the same time. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ - UINT32_C(0x20) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + /* The source function id. */ + uint16_t src_fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ +struct hwrm_cfa_redirect_query_tunnel_type_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Tunnel Mask. */ + uint32_t tunnel_mask; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \ UINT32_C(0x1) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \ UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \ UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \ UINT32_C(0x8) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + /* IP in IP */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \ UINT32_C(0x10) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ UINT32_C(0x20) - /* - * This bit must be '1' for the src_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ UINT32_C(0x40) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \ UINT32_C(0x80) - /* - * This bit must be '1' for the dst_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \ UINT32_C(0x100) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ UINT32_C(0x200) /* - * This bit must be '1' for the src_port field to be - * configured. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ UINT32_C(0x400) - /* - * This bit must be '1' for the src_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \ UINT32_C(0x800) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ UINT32_C(0x1000) /* - * This bit must be '1' for the dst_port_mask field to be - * configured. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ UINT32_C(0x2000) + uint8_t unused_0[3]; /* - * This bit must be '1' for the pri_hint field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the ntuple_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x40000) - /* This flag is deprecated. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ - UINT32_C(0x80000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ - UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ - UINT32_C(0x6) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ - UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ - UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ - UINT32_C(0x11) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint16_t mirror_vnic_id; - /* - * This value indicates the tunnel type for this filter. - * If this field is not specified, then the filter shall - * apply to both non-tunneled and tunneled packets. - * If this field conflicts with the tunnel_type specified - * in the l2_filter_id, then the HWRM shall return an - * error for this command. - */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* - * This hint is provided to help in placing - * the filter in the filter table. - */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ - UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ - UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ - UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ - UINT32_C(0x4) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST - /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t src_ipaddr[4]; - /* - * The value of source IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. - */ - uint32_t src_ipaddr_mask[4]; - /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t dst_ipaddr[4]; - /* - * The value of destination IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - uint32_t dst_ipaddr_mask[4]; + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_ctx_mem_rgtr * + *************************/ + + +/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ +struct hwrm_cfa_ctx_mem_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t src_port; + uint16_t cmpl_ring; /* - * The value of source port mask to be used in filtering. - * Applies to UDP and TCP traffic. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t src_port_mask; + uint16_t seq_id; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t dst_port; + uint16_t target_id; /* - * The value of destination port mask to be used in - * filtering. - * Applies to UDP and TCP traffic. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t dst_port_mask; + uint64_t resp_addr; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * This is the ID of the filter that goes along with - * the pri_hint. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint64_t ntuple_filter_id_hint; + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G + uint32_t unused_0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; } __rte_packed; -/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_alloc_output { +/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27388,84 +40656,30 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint16_t ctx_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_ntuple_filter_alloc_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* Unable to complete operation due to conflict with Rx Mask VLAN */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR - uint8_t unused_0[7]; -} __rte_packed; - -/******************************* - * hwrm_cfa_ntuple_filter_free * - *******************************/ +/*************************** + * hwrm_cfa_ctx_mem_unrgtr * + ***************************/ -/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_free_input { +/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_ctx_mem_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27494,12 +40708,16 @@ struct hwrm_cfa_ntuple_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; + /* + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. + */ + uint16_t ctx_id; + uint8_t unused_0[6]; } __rte_packed; -/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_free_output { +/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27513,19 +40731,20 @@ struct hwrm_cfa_ntuple_filter_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/****************************** - * hwrm_cfa_ntuple_filter_cfg * - ******************************/ +/************************* + * hwrm_cfa_ctx_mem_qctx * + *************************/ -/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ -struct hwrm_cfa_ntuple_filter_cfg_input { +/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ +struct hwrm_cfa_ctx_mem_qctx_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27554,73 +40773,112 @@ struct hwrm_cfa_ntuple_filter_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; /* - * This bit must be '1' for the new_dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ - UINT32_C(0x4) - uint32_t flags; + uint16_t ctx_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ +struct hwrm_cfa_ctx_mem_qctx_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * Setting this bit to 1 indicates that dest_id field contains FID. - * Setting this to 0 indicates that dest_id field contains VNIC or VPORT. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ - UINT32_C(0x1) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G + uint8_t unused_0[4]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + uint8_t unused_1[7]; /* - * Setting of this flag indicates that the new_dst_id field contains - * RFS ring table index. If this is not set it indicates new_dst_id is - * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx - * can’t be set at the same time. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ - UINT32_C(0x2) - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_ctx_mem_qcaps * + **************************/ + + +/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and new network port id of the destination port for - * the TX path. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t new_dst_id; + uint16_t cmpl_ring; /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t new_mirror_vnic_id; + uint16_t seq_id; /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t new_meter_instance_id; + uint16_t target_id; /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ - HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; + uint64_t resp_addr; } __rte_packed; -/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_cfg_output { +/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27629,24 +40887,30 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * Indicates the maximum number of context memory which can be + * registered. + */ + uint16_t max_entries; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; /************************** - * hwrm_cfa_em_flow_alloc * + * hwrm_cfa_counter_qcaps * **************************/ -/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ -struct hwrm_cfa_em_flow_alloc_input { +/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_counter_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27675,384 +40939,115 @@ struct hwrm_cfa_em_flow_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ +struct hwrm_cfa_counter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX - /* - * Setting of this flag indicates enabling of a byte counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) - /* - * Setting of this flag indicates enabling of a packet counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) - /* Setting of this flag indicates de-capsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) - /* Setting of this flag indicates encapsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + /* Enumeration denoting the supported CFA counter format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \ UINT32_C(0x1) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x10) - /* - * This bit must be '1' for the ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x100) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x200) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x400) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x800) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the encap_record_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ - UINT32_C(0x20000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + /* CFA counter types are not supported. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \ UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + /* 64-bit packet counters followed by 64-bit byte counters format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \ UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[3]; - /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. - */ - uint32_t tunnel_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* The meter instance to attach to the flow. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID - /* - * This value indicates the destination MAC address in - * the Ethernet header. - */ - uint8_t dst_macaddr[6]; + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \ + HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT + uint32_t unused_0; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. + * Minimum guaranteed number of flow counters supported for this + * function, in RX direction. */ - uint16_t ovlan_vid; + uint32_t min_rx_fc; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. + * Maximum non-guaranteed number of flow counters supported for this + * function, in RX direction. */ - uint16_t ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; + uint32_t max_rx_fc; /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * Minimum guaranteed number of flow counters supported for this + * function, in TX direction. */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + uint32_t min_tx_fc; /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP + * Maximum non-guaranteed number of flow counters supported for this + * function, in TX direction. */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP - uint8_t unused_1[2]; + uint32_t max_tx_fc; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Minimum guaranteed number of extension flow counters supported for + * this function, in RX direction. */ - uint32_t src_ipaddr[4]; + uint32_t min_rx_efc; /* - * big_endian = True - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in RX direction. */ - uint32_t dst_ipaddr[4]; + uint32_t max_rx_efc; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * Minimum guaranteed number of extension flow counters supported for + * this function, in TX direction. */ - uint16_t src_port; + uint32_t min_tx_efc; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in TX direction. */ - uint16_t dst_port; + uint32_t max_tx_efc; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Minimum guaranteed number of meter drop counters supported for + * this function, in RX direction. */ - uint16_t dst_id; + uint32_t min_rx_mdc; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in RX direction. */ - uint16_t mirror_vnic_id; - /* Logical ID of the encapsulation record. */ - uint32_t encap_record_id; - uint8_t unused_2[4]; -} __rte_packed; - -/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ -struct hwrm_cfa_em_flow_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; + uint32_t max_rx_mdc; /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. + * Minimum guaranteed number of meter drop counters supported for this + * function, in TX direction. */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) + uint32_t min_tx_mdc; /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in TX direction. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) + uint32_t max_tx_mdc; /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * Maximum guaranteed number of flow counters which can be used during + * flow alloc. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint32_t max_flow_alloc_fc; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************* - * hwrm_cfa_em_flow_free * - *************************/ +/************************ + * hwrm_cfa_counter_cfg * + ************************/ -/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ -struct hwrm_cfa_em_flow_free_input { +/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ +struct hwrm_cfa_counter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28081,12 +41076,64 @@ struct hwrm_cfa_em_flow_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; + uint16_t flags; + /* Enumeration denoting the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \ + UINT32_C(0x1) + /* Disable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \ + UINT32_C(0x0) + /* Enable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x2) + /* Tx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \ + (UINT32_C(0x0) << 1) + /* Rx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 + /* Push mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \ + (UINT32_C(0x0) << 2) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \ + (UINT32_C(0x1) << 2) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + /* Flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) + /* Extended flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) + /* Meter drop counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC + /* Ctx memory handle to be used for the counter. */ + uint16_t ctx_id; + /* Counter update cadence hint (only in Push mode). */ + uint16_t update_tmr_ms; + /* Total number of entries. */ + uint32_t num_entries; + uint32_t unused_0; } __rte_packed; -/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_free_output { +/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_counter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28100,19 +41147,20 @@ struct hwrm_cfa_em_flow_free_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/************************ - * hwrm_cfa_meter_qcaps * - ************************/ +/*************************** + * hwrm_cfa_counter_qstats * + ***************************/ -/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_meter_qcaps_input { +/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ +struct hwrm_cfa_counter_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28141,10 +41189,27 @@ struct hwrm_cfa_meter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX + uint16_t counter_type; + uint16_t input_flow_ctx_id; + uint16_t num_entries; + uint16_t delta_time_ms; + uint16_t meter_instance_id; + uint16_t mdc_ctx_id; + uint8_t unused_0[2]; + uint64_t expected_count; } __rte_packed; -/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_meter_qcaps_output { +/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ +struct hwrm_cfa_counter_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28153,79 +41218,25 @@ struct hwrm_cfa_meter_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * Enumeration denoting the clock at which the Meter is running with. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 - /* 375 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) - /* 625 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \ - HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ - uint8_t unused_0[4]; - /* - * The minimum guaranteed number of tx meter profiles supported - * for this function. - */ - uint16_t min_tx_profile; - /* - * The maximum non-guaranteed number of tx meter profiles supported - * for this function. - */ - uint16_t max_tx_profile; - /* - * The minimum guaranteed number of rx meter profiles supported - * for this function. - */ - uint16_t min_rx_profile; - /* - * The maximum non-guaranteed number of rx meter profiles supported - * for this function. - */ - uint16_t max_rx_profile; - /* - * The minimum guaranteed number of tx meter instances supported - * for this function. - */ - uint16_t min_tx_instance; - /* - * The maximum non-guaranteed number of tx meter instances supported - * for this function. - */ - uint16_t max_tx_instance; - /* - * The minimum guaranteed number of rx meter instances supported - * for this function. - */ - uint16_t min_rx_instance; - /* - * The maximum non-guaranteed number of rx meter instances supported - * for this function. - */ - uint16_t max_rx_instance; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_meter_profile_alloc * - ********************************/ +/********************** + * hwrm_cfa_eem_qcaps * + **********************/ -/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_alloc_input { +/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ +struct hwrm_cfa_eem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28254,220 +41265,219 @@ struct hwrm_cfa_meter_profile_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \ UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + uint32_t unused_0; +} __rte_packed; + +/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ +struct hwrm_cfa_eem_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \ UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 /* - * This field is reserved for the future use. - * It shall be set to 0. + * When set to 1, indicates the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. */ - uint16_t reserved1; + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x4) /* - * This field is reserved for the future use. - * It shall be set to 0. + * When set to 1, indicates the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. */ - uint32_t reserved2; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x8) + uint32_t unused_0; + uint32_t supported; + /* + * If set to 1, then EEM KEY0 table is supported using crc32 hash. + * If set to 0, EEM KEY0 table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EEM KEY1 table is supported using lookup3 hash. + * If set to 0, EEM KEY1 table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EEM External Record table is supported. + * If set to 0, EEM External Record table is not supported. + * (This table includes action record, EFC pointers, encap pointers) + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EEM External Flow Counters table is supported. + * If set to 0, EEM External Flow Counters table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush is + * supported. + * If set to 0, then FID table used for implicit flow flush is + * not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * The maximum number of entries supported by EEM. When configuring + * the host memory, the number of numbers of entries that can + * supported are: + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M + * entries. + * Any value that are not these values, the FW will round down to the + * closest support number of entries. + */ + uint32_t max_entries_supported; + /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ + uint16_t key_entry_size; + /* The entry size in bytes of each entry in the EEM RECORD tables. */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EEM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EEM FID tables. */ + uint16_t fid_entry_size; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_cfa_eem_cfg * + ********************/ + + +/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ +struct hwrm_cfa_eem_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. + */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x1) + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x8) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + uint16_t unused_0; + /* + * Configured EEM with the given number of entries. All the EEM tables + * KEY0, KEY1, RECORD, EFC all have the same number of entries and all + * tables will be configured using this value. Current minimum value + * is 32k. Current maximum value is 128M. + */ + uint32_t num_entries; + uint32_t unused_1; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint16_t unused_2; + uint32_t unused_3; } __rte_packed; -/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_alloc_output { +/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ +struct hwrm_cfa_eem_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28476,34 +41486,25 @@ struct hwrm_cfa_meter_profile_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_cfa_meter_profile_free * - *******************************/ +/********************* + * hwrm_cfa_eem_qcfg * + *********************/ -/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_profile_free_input { +/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ +struct hwrm_cfa_eem_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28532,37 +41533,16 @@ struct hwrm_cfa_meter_profile_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint32_t unused_0; } __rte_packed; -/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_free_output { +/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ +struct hwrm_cfa_eem_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28571,24 +41551,47 @@ struct hwrm_cfa_meter_profile_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ + UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + /* The number of entries the FW has configured for EEM. */ + uint32_t num_entries; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/****************************** - * hwrm_cfa_meter_profile_cfg * - ******************************/ +/******************* + * hwrm_cfa_eem_op * + *******************/ -/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_cfg_input { +/* hwrm_cfa_eem_op_input (size:192b/24B) */ +struct hwrm_cfa_eem_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28617,223 +41620,49 @@ struct hwrm_cfa_meter_profile_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When set to 1, indicates the host memory which is passed will be + * used for the TX flow offload function specified in fid. + * Note if this bit is set then the path_rx bit can't be set. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ - UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ - UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. + * When set to 1, indicates the host memory which is passed will be + * used for the RX flow offload function specified in fid. + * Note if this bit is set then the path_tx bit can't be set. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint16_t unused_0; + /* The number of EEM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) /* - * This field is reserved for the future use. - * It shall be set to 0. + * To properly stop EEM and ensure there are no DMA's, the caller + * must disable EEM for the given PF, using this call. This will + * safely disable EEM and ensure that all DMA'ed to the + * keys/records/efc have been completed. */ - uint32_t reserved; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) + /* + * Once the EEM host memory has been configured, EEM options have + * been configured. Then the caller should enable EEM for the given + * PF. Note once this call has been made, then the EEM mechanism + * will be active and DMA's will occur as packets are processed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) + /* + * Clear EEM settings for the given PF so that the register values + * are reset back to there initial state. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) + #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ + HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP } __rte_packed; -/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_cfg_output { +/* hwrm_cfa_eem_op_output (size:128b/16B) */ +struct hwrm_cfa_eem_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28847,19 +41676,203 @@ struct hwrm_cfa_meter_profile_cfg_output { * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_adv_flow_mgnt_qcaps * + ********************************/ + + +/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + UINT32_C(0x1) + /* + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + UINT32_C(0x2) + /* + * Value of 1 to indicate firmware support flow batch delete + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow + * batch delete operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + UINT32_C(0x4) + /* + * Value of 1 to indicate that the firmware support flow reset all + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all + * operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + UINT32_C(0x8) + /* + * Value of 1 to indicate that firmware supports use of FID as + * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as + * dest_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + UINT32_C(0x10) + /* + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x20) + /* + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x40) + /* + * Value of 1 to indicate that firmware supports the dynamic + * allocation of an on-chip flow counter which can be used for EEM + * flows. Value of 0 indicates firmware does not support the dynamic + * allocation of an on-chip flow counter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + UINT32_C(0x80) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + UINT32_C(0x100) + /* + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + UINT32_C(0x200) + /* + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ + UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that core firmware is + * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX + * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \ + UINT32_C(0x8000) + /* + * If set to 1, firmware is capable of supporting L2/ROCE as + * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. + * By default, this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \ + UINT32_C(0x10000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************************* - * hwrm_cfa_meter_instance_alloc * - *********************************/ +/****************** + * hwrm_cfa_tflib * + ******************/ -/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_alloc_input { +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28888,38 +41901,18 @@ struct hwrm_cfa_meter_instance_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; } __rte_packed; -/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_alloc_output { +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28928,34 +41921,34 @@ struct hwrm_cfa_meter_instance_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xffff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_0[5]; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_cfa_meter_instance_cfg * - *******************************/ +/*********** + * hwrm_tf * + ***********/ -/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_cfg_input { +/* hwrm_tf_input (size:1024b/128B) */ +struct hwrm_tf_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28984,45 +41977,18 @@ struct hwrm_cfa_meter_instance_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* - * This value identifies a new meter profile to be associated with - * the meter instance specified in this command. - */ - uint16_t meter_profile_id; - /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID - /* - * This value identifies the ID of a meter instance that needs to be updated with - * a new meter profile specified in this command. - */ - uint16_t meter_instance_id; - uint8_t unused_1[2]; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* unused. */ + uint8_t unused0[4]; + /* TF request data. */ + uint32_t req[26]; } __rte_packed; -/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_cfg_output { +/* hwrm_tf_output (size:5632b/704B) */ +struct hwrm_tf_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29031,24 +41997,34 @@ struct hwrm_cfa_meter_instance_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* TF response code */ + uint32_t resp_code; + /* TF response data. */ + uint32_t resp[170]; + /* unused. */ + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_meter_instance_free * - ********************************/ +/*********************** + * hwrm_tf_version_get * + ***********************/ -/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_free_input { +/* hwrm_tf_version_get_input (size:128b/16B) */ +struct hwrm_tf_version_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29077,37 +42053,10 @@ struct hwrm_cfa_meter_instance_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_1[4]; } __rte_packed; -/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_free_output { +/* hwrm_tf_version_get_output (size:128b/16B) */ +struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29116,24 +42065,32 @@ struct hwrm_cfa_meter_instance_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Version Major number. */ + uint8_t major; + /* Version Minor number. */ + uint8_t minor; + /* Version Update number. */ + uint8_t update; + /* unused. */ + uint8_t unused0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/******************************* - * hwrm_cfa_decap_filter_alloc * - *******************************/ +/************************ + * hwrm_tf_session_open * + ************************/ -/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ -struct hwrm_cfa_decap_filter_alloc_input { +/* hwrm_tf_session_open_input (size:640b/80B) */ +struct hwrm_tf_session_open_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29162,275 +42119,180 @@ struct hwrm_cfa_decap_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* ovs_tunnel is 1 b */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \ - UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x1) - /* - * This bit must be '1' for the tunnel_id field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x4) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \ - UINT32_C(0x10) - /* - * This bit must be '1' for the ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the t_ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the t_ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \ - UINT32_C(0x80) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x100) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x200) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x400) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x800) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x10000) + /* Name of the session. */ + uint8_t session_name[64]; +} __rte_packed; + +/* hwrm_tf_session_open_output (size:192b/24B) */ +struct hwrm_tf_session_open_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * Unique session identifier for the session created by the + * firmware. */ - uint32_t tunnel_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0; - uint16_t unused_1; + uint32_t fw_session_id; /* - * This value indicates the source MAC address in - * the Ethernet header. + * Unique session client identifier for the first client on + * the newly created session. */ - uint8_t src_macaddr[6]; - uint8_t unused_2[2]; + uint32_t fw_session_client_id; + /* unused. */ + uint32_t unused0; + /* unused. */ + uint8_t unused1[3]; /* - * This value indicates the destination MAC address in - * the Ethernet header. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - uint8_t dst_macaddr[6]; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tf_session_attach * + **************************/ + + +/* hwrm_tf_session_attach_input (size:704b/88B) */ +struct hwrm_tf_session_attach_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t ovlan_vid; + uint16_t cmpl_ring; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t ivlan_vid; + uint16_t seq_id; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the tunnel Ethernet header. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t t_ovlan_vid; + uint16_t target_id; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the tunnel Ethernet header. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t t_ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; + uint64_t resp_addr; /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * Unique session identifier for the session that the attach + * request want to attach to. This value originates from the + * shared session memory that the attach request opened by + * way of the 'attach name' that was passed in to the core + * attach API. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ - UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ - UINT32_C(0x6) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + uint32_t attach_fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session it self. */ + uint8_t session_name[64]; +} __rte_packed; + +/* hwrm_tf_session_attach_output (size:128b/16B) */ +struct hwrm_tf_session_attach_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. This fw_session_id is unique to the attach + * request. */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ - UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ - UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ - UINT32_C(0x11) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - uint16_t unused_3; - uint32_t unused_4; + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - uint32_t src_ipaddr[4]; + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tf_session_register * + ****************************/ + + +/* hwrm_tf_session_register_input (size:704b/88B) */ +struct hwrm_tf_session_register_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t dst_ipaddr[4]; + uint16_t cmpl_ring; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t src_port; + uint16_t seq_id; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t dst_port; + uint16_t target_id; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t dst_id; + uint64_t resp_addr; /* - * If set, this value shall represent the L2 context that matches the L2 - * information of the decap filter. + * Unique session identifier for the session that the + * register request want to create a new client on. This + * value originates from the first open request. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. */ - uint16_t l2_ctxt_ref_id; + uint32_t fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session client. */ + uint8_t session_client_name[64]; } __rte_packed; -/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_alloc_output { +/* hwrm_tf_session_register_output (size:128b/16B) */ +struct hwrm_tf_session_register_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29439,26 +42301,32 @@ struct hwrm_cfa_decap_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; - uint8_t unused_0[3]; + /* + * Unique session client identifier for the session created + * by the firmware. It includes the session the client it + * attached to and session client info. + */ + uint32_t fw_session_client_id; + /* unused. */ + uint8_t unused0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; /****************************** - * hwrm_cfa_decap_filter_free * + * hwrm_tf_session_unregister * ******************************/ -/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_decap_filter_free_input { +/* hwrm_tf_session_unregister_input (size:192b/24B) */ +struct hwrm_tf_session_unregister_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29487,13 +42355,20 @@ struct hwrm_cfa_decap_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; - uint8_t unused_0[4]; + /* + * Unique session identifier for the session that the + * unregister request want to close a session client on. + */ + uint32_t fw_session_id; + /* + * Unique session client identifier for the session that the + * unregister request want to close. + */ + uint32_t fw_session_client_id; } __rte_packed; -/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_free_output { +/* hwrm_tf_session_unregister_output (size:128b/16B) */ +struct hwrm_tf_session_unregister_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29502,24 +42377,26 @@ struct hwrm_cfa_decap_filter_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*********************** - * hwrm_cfa_flow_alloc * - ***********************/ +/************************* + * hwrm_tf_session_close * + *************************/ -/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_flow_alloc_input { +/* hwrm_tf_session_close_input (size:192b/24B) */ +struct hwrm_tf_session_close_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29548,255 +42425,212 @@ struct hwrm_cfa_flow_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \ - UINT32_C(0x1) - /* num_vlan is 2 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \ - UINT32_C(0x6) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 - /* no tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ - (UINT32_C(0x0) << 1) - /* 1 tag */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \ - (UINT32_C(0x1) << 1) - /* 2 tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \ - (UINT32_C(0x2) << 1) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO - /* Enumeration denoting the Flow Type. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \ - UINT32_C(0x38) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 - /* L2 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ - (UINT32_C(0x0) << 3) - /* IPV4 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \ - (UINT32_C(0x1) << 3) - /* IPV6 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \ - (UINT32_C(0x2) << 3) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; + +/* hwrm_tf_session_close_output (size:128b/16B) */ +struct hwrm_tf_session_close_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tf_session_qcfg * + ************************/ + + +/* hwrm_tf_session_qcfg_input (size:192b/24B) */ +struct hwrm_tf_session_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * when set to 1, indicates TX flow offload for function specified in src_fid and - * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both - * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload - * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV - * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID - * belong to the children VFs of the same PF to indicate VM to VM flow. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x40) + uint16_t cmpl_ring; /* - * when set to 1, indicates RX flow offload for function specified in dst_fid and - * the src_fid should be set to invalid value. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x80) + uint16_t seq_id; /* - * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is - * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. - * This flag is only valid when the flow direction is RX. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ - UINT32_C(0x100) - /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ - UINT32_C(0x200) + uint16_t target_id; /* - * Tx Flow: vf fid. - * Rx Flow: pf fid. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t src_fid; - /* Tunnel handle valid when tunnel flag is set. */ - uint32_t tunnel_handle; - uint16_t action_flags; + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; + +/* hwrm_tf_session_qcfg_output (size:128b/16B) */ +struct hwrm_tf_session_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* RX action control settings flags. */ + uint8_t rx_act_flags; /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * A value of 1 in this field indicates that Global Flow ID + * reporting into cfa_code and cfa_metadata is enabled. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \ UINT32_C(0x1) - /* recycle is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ + /* + * A value of 1 in this field indicates that both inner and outer + * are stripped and inner tag is passed. + * Enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \ UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * A value of 1 in this field indicates that the re-use of + * existing tunnel L2 header SMAC is enabled for + * Non-tunnel L2, L2-L3 and IP-IP tunnel. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \ UINT32_C(0x4) - /* meter is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \ - UINT32_C(0x8) - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \ - UINT32_C(0x10) - /* nat_src is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \ - UINT32_C(0x20) - /* nat_dest is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \ - UINT32_C(0x40) - /* nat_ipv4_address is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \ - UINT32_C(0x80) - /* l2_header_rewrite is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \ - UINT32_C(0x100) - /* ttl_decrement is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ - UINT32_C(0x200) + /* TX Action control settings flags. */ + uint8_t tx_act_flags; + /* Disabled. */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \ + UINT32_C(0x1) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. The type of tunnel - * is specified in the tunnel_type field. + * When set to 1 any GRE tunnels will include the + * optional Key field. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ - UINT32_C(0x400) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ - UINT32_C(0x800) + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \ + UINT32_C(0x2) /* - * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be - * placed to the default flow table resource. + * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap + * record. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ - UINT32_C(0x1000) + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \ + UINT32_C(0x4) /* - * If set to 1 there will be no attempt to allocate an on-chip try to - * offload this flow. If set to 0, which will keep compatibility with the - * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior - * with EM flows which always had an associated flow counter. + * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap record. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ - UINT32_C(0x2000) + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \ + UINT32_C(0x8) + /* unused. */ + uint8_t unused0[5]; /* - * Tx Flow: pf or vf fid. - * Rx Flow: vf fid. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ - uint16_t dst_fid; - /* VLAN tpid, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tci; - /* Meter id, valid when meter flag is set. */ - uint16_t act_meter_id; - /* Flow with the same l2 context tcam key. */ - uint16_t ref_flow_handle; - /* This value sets the match value for the ethertype. */ - uint16_t ethertype; - /* valid when num tags is 1 or 2. */ - uint16_t outer_vlan_tci; - /* This value sets the match value for the Destination MAC address. */ - uint16_t dmac[3]; - /* valid when num tags is 2. */ - uint16_t inner_vlan_tci; - /* This value sets the match value for the Source MAC address. */ - uint16_t smac[3]; - /* The bit length of destination IP address mask. */ - uint8_t ip_dst_mask_len; - /* The bit length of source IP address mask. */ - uint8_t ip_src_mask_len; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_resc_qcaps * + ******************************/ + + +/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ +struct hwrm_tf_session_resc_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The value of source port. - * Applies to UDP and TCP traffic. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t l4_src_port; + uint16_t cmpl_ring; /* - * The value of source port mask. - * Applies to UDP and TCP traffic. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t l4_src_port_mask; + uint16_t seq_id; /* - * The value of destination port. - * Applies to UDP and TCP traffic. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t l4_dst_port; + uint16_t target_id; /* - * The value of destination port mask. - * Applies to UDP and TCP traffic. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t l4_dst_port_mask; + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX /* - * NAT IPv4/6 address based on address type flag. - * 0 values are ignored. + * Defines the size of the provided qcaps_addr array + * buffer. The size should be set to the Resource Manager + * provided max number of qcaps entries which is device + * specific. Resource Manager gets the max size from HCAPI + * RM. */ - uint32_t nat_ip_address[4]; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; + uint16_t qcaps_size; /* - * The NAT source/destination port based on direction flag. - * Applies to UDP and TCP traffic. - * 0 values are ignored. + * This is the DMA address for the qcaps output data array + * buffer. Array is of tf_rm_resc_req_entry type and is + * device specific. */ - uint16_t nat_port; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* The value of ip protocol. */ - uint8_t ip_proto; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint64_t qcaps_addr; } __rte_packed; -/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ -struct hwrm_cfa_flow_alloc_output { +/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ +struct hwrm_tf_session_resc_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29805,98 +42639,154 @@ struct hwrm_cfa_flow_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; + /* Control flags. */ + uint32_t flags; + /* Session reservation strategy. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \ + 0 + /* Static partitioning. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \ + UINT32_C(0x0) + /* Strategy 1. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \ + UINT32_C(0x1) + /* Strategy 2. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \ + UINT32_C(0x2) + /* Strategy 3. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. + * Size of the returned qcaps_addr data array buffer. The + * value cannot exceed the size defined by the input msg, + * qcaps_size. */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) + uint16_t size; + /* unused. */ + uint16_t unused0; + /* unused. */ + uint8_t unused1[7]; /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tf_session_resc_alloc * + ******************************/ + + +/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ +struct hwrm_tf_session_resc_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; - uint32_t flow_counter_id; - uint8_t unused_1[3]; + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. */ - uint8_t valid; + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; } __rte_packed; -/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_flow_alloc_cmd_err { +/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ +struct hwrm_tf_session_resc_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* No more L2 Context TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) - /* No more action records */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) - /* No more flow counters */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) - /* No more wild-card TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collsion in exact match tables */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) - /* Key is already installed */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) - /* Flow Context DB is out of resource */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ - HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB - uint8_t unused_0[7]; + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; } __rte_packed; -/********************** - * hwrm_cfa_flow_free * - **********************/ +/***************************** + * hwrm_tf_session_resc_free * + *****************************/ -/* hwrm_cfa_flow_free_input (size:256b/32B) */ -struct hwrm_cfa_flow_free_input { +/* hwrm_tf_session_resc_free_input (size:256b/32B) */ +struct hwrm_tf_session_resc_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29925,17 +42815,34 @@ struct hwrm_cfa_flow_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint16_t unused_0; - /* Flow counter id to be freed. */ - uint32_t flow_counter_id; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided free_addr + * buffer. + */ + uint16_t free_size; + /* + * This is the DMA address for the free input data array + * buffer. Array is of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'free_size' field of this + * message. + */ + uint64_t free_addr; } __rte_packed; -/* hwrm_cfa_flow_free_output (size:256b/32B) */ -struct hwrm_cfa_flow_free_output { +/* hwrm_tf_session_resc_free_output (size:128b/16B) */ +struct hwrm_tf_session_resc_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29944,251 +42851,26 @@ struct hwrm_cfa_flow_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* packet is 64 b */ - uint64_t packet; - /* byte is 64 b */ - uint64_t byte; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/* hwrm_cfa_flow_action_data (size:960b/120B) */ -struct hwrm_cfa_flow_action_data { - uint16_t action_flags; - /* Setting of this flag indicates accept action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \ - UINT32_C(0x1) - /* Setting of this flag indicates recycle action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \ - UINT32_C(0x2) - /* Setting of this flag indicates drop action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \ - UINT32_C(0x4) - /* Setting of this flag indicates meter action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \ - UINT32_C(0x8) - /* Setting of this flag indicates tunnel action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ - UINT32_C(0x10) - /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. - */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ - UINT32_C(0x20) - /* Setting of this flag indicates ttl decrement action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \ - UINT32_C(0x40) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ - UINT32_C(0x80) - /* Setting of this flag indicates encap action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ - UINT32_C(0x100) - /* Setting of this flag indicates decap action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ - UINT32_C(0x200) - /* Meter id. */ - uint16_t act_meter_id; - /* VNIC id. */ - uint16_t vnic_id; - /* vport number. */ - uint16_t vport_id; - /* The NAT source/destination. */ - uint16_t nat_port; - uint16_t unused_0[3]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - /* Encapsulation Type. */ - uint8_t encap_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ - HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 - uint8_t unused[7]; - /* This value is encap data for the associated encap type. */ - uint32_t encap_data[20]; -} __rte_packed; - -/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ -struct hwrm_cfa_flow_tunnel_hdr_data { - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \ - HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused[3]; - /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). - */ - uint32_t tunnel_id; -} __rte_packed; - -/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ -struct hwrm_cfa_flow_l4_key_data { - /* The value of source port. */ - uint16_t l4_src_port; - /* The value of destination port. */ - uint16_t l4_dst_port; - uint32_t unused; -} __rte_packed; - -/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ -struct hwrm_cfa_flow_l3_key_data { - /* The value of ip protocol. */ - uint8_t ip_protocol; - uint8_t unused_0[7]; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - uint32_t unused[2]; -} __rte_packed; - -/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ -struct hwrm_cfa_flow_l2_key_data { - /* Destination MAC address. */ - uint16_t dmac[3]; - uint16_t unused_0; - /* Source MAC address. */ - uint16_t smac[3]; - uint16_t unused_1; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; - uint16_t unused_2; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* Ethertype. */ - uint16_t ethertype; - /* Number of VLAN tags. */ - uint16_t num_vlan_tags; - /* VLAN tpid. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci. */ - uint16_t l2_rewrite_vlan_tci; - uint8_t unused_3[2]; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - uint8_t unused[8]; -} __rte_packed; - -/* hwrm_cfa_flow_key_data (size:4160b/520B) */ -struct hwrm_cfa_flow_key_data { - /* Flow associated tunnel L2 header key info. */ - uint32_t t_l2_key_data[14]; - /* Flow associated tunnel L2 header mask info. */ - uint32_t t_l2_key_mask[14]; - /* Flow associated tunnel L3 header key info. */ - uint32_t t_l3_key_data[16]; - /* Flow associated tunnel L3 header mask info. */ - uint32_t t_l3_key_mask[16]; - /* Flow associated tunnel L4 header key info. */ - uint32_t t_l4_key_data[2]; - /* Flow associated tunnel L4 header mask info. */ - uint32_t t_l4_key_mask[2]; - /* Flow associated tunnel header info. */ - uint32_t tunnel_hdr[2]; - /* Flow associated L2 header key info. */ - uint32_t l2_key_data[14]; - /* Flow associated L2 header mask info. */ - uint32_t l2_key_mask[14]; - /* Flow associated L3 header key info. */ - uint32_t l3_key_data[16]; - /* Flow associated L3 header mask info. */ - uint32_t l3_key_mask[16]; - /* Flow associated L4 header key info. */ - uint32_t l4_key_data[2]; - /* Flow associated L4 header mask info. */ - uint32_t l4_key_mask[2]; -} __rte_packed; - -/********************** - * hwrm_cfa_flow_info * - **********************/ +/****************************** + * hwrm_tf_session_resc_flush * + ******************************/ -/* hwrm_cfa_flow_info_input (size:256b/32B) */ -struct hwrm_cfa_flow_info_input { +/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ +struct hwrm_tf_session_resc_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30217,31 +42899,34 @@ struct hwrm_cfa_flow_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - /* Max flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ - UINT32_C(0xfff) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 - /* CNP flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ - UINT32_C(0x1000) - /* RoCEv1 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ - UINT32_C(0x2000) - /* RoCEv2 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ - UINT32_C(0x4000) - /* Direction rx = 1 */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ - UINT32_C(0x8000) - uint8_t unused_0[6]; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided flush_addr + * buffer. + */ + uint16_t flush_size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'flush_size' field in this + * message. + */ + uint64_t flush_addr; } __rte_packed; -/* hwrm_cfa_flow_info_output (size:5632b/704B) */ -struct hwrm_cfa_flow_info_output { +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +struct hwrm_tf_session_resc_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30250,56 +42935,48 @@ struct hwrm_cfa_flow_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* profile is 8 b */ - uint8_t profile; - /* src_fid is 16 b */ - uint16_t src_fid; - /* dst_fid is 16 b */ - uint16_t dst_fid; - /* l2_ctxt_id is 16 b */ - uint16_t l2_ctxt_id; - /* em_info is 64 b */ - uint64_t em_info; - /* tcam_info is 64 b */ - uint64_t tcam_info; - /* vfp_tcam_info is 64 b */ - uint64_t vfp_tcam_info; - /* ar_id is 16 b */ - uint16_t ar_id; - /* flow_handle is 16 b */ - uint16_t flow_handle; - /* tunnel_handle is 32 b */ - uint32_t tunnel_handle; - /* The flow aging timer for the flow, the unit is 100 milliseconds */ - uint16_t flow_timer; - uint8_t unused_0[6]; - /* Flow associated L2, L3 and L4 headers info. */ - uint32_t flow_key_data[130]; - /* Flow associated action record info. */ - uint32_t flow_action_info[30]; - uint8_t unused_1[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/*********************** - * hwrm_cfa_flow_flush * - ***********************/ +/* TruFlow RM capability of a resource. */ +/* tf_rm_resc_req_entry (size:64b/8B) */ +struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __rte_packed; + +/* TruFlow RM reservation information. */ +/* tf_rm_resc_entry (size:64b/8B) */ +struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __rte_packed; +/************************ + * hwrm_tf_tbl_type_get * + ************************/ -/* hwrm_cfa_flow_flush_input (size:256b/32B) */ -struct hwrm_cfa_flow_flush_input { + +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30328,86 +43005,31 @@ struct hwrm_cfa_flow_flush_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* flags is 32 b */ - uint32_t flags; - /* - * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr - * fields are valid. The flow flush operation should only flush the flows from the - * flow table specified. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ - UINT32_C(0x1) - /* - * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables etc. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ - UINT32_C(0x2) - /* - * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller. - * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ - UINT32_C(0x4) - /* Set to 1 to indicate the flow counter IDs are included in the flow table. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ - UINT32_C(0x8000000) + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; /* - * This specifies the size of flow handle entries provided by the driver - * in the flow table specified below. Only two flow handle size enums are defined. + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ - UINT32_C(0xc0000000) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \ - 30 - /* The flow handle is 16bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \ - (UINT32_C(0x0) << 30) - /* The flow handle is 64bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT - /* Specify page size of the flow table memory. */ - uint8_t page_size; - /* The page size is 4K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* The page size is 8K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* The page size is 64K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* The page size is 256K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* The page size is 1M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* The page size is 2M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* The page size is 4M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* The page size is 1G */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G - /* FLow table memory indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 - /* number of flows in the flow table */ - uint16_t num_flows; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; } __rte_packed; -/* hwrm_cfa_flow_flush_output (size:128b/16B) */ -struct hwrm_cfa_flow_flush_output { +/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30416,24 +43038,34 @@ struct hwrm_cfa_flow_flush_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; -/*********************** - * hwrm_cfa_flow_stats * - ***********************/ +/************************ + * hwrm_tf_tbl_type_set * + ************************/ -/* hwrm_cfa_flow_stats_input (size:640b/80B) */ -struct hwrm_cfa_flow_stats_input { +/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ +struct hwrm_tf_tbl_type_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30462,119 +43094,65 @@ struct hwrm_cfa_flow_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow handle. */ - uint16_t num_flows; - /* Flow handle. */ - uint16_t flow_handle_0; - /* Flow handle. */ - uint16_t flow_handle_1; - /* Flow handle. */ - uint16_t flow_handle_2; - /* Flow handle. */ - uint16_t flow_handle_3; - /* Flow handle. */ - uint16_t flow_handle_4; - /* Flow handle. */ - uint16_t flow_handle_5; - /* Flow handle. */ - uint16_t flow_handle_6; - /* Flow handle. */ - uint16_t flow_handle_7; - /* Flow handle. */ - uint16_t flow_handle_8; - /* Flow handle. */ - uint16_t flow_handle_9; - uint8_t unused_0[2]; - /* Flow ID of a flow. */ - uint32_t flow_id_0; - /* Flow ID of a flow. */ - uint32_t flow_id_1; - /* Flow ID of a flow. */ - uint32_t flow_id_2; - /* Flow ID of a flow. */ - uint32_t flow_id_3; - /* Flow ID of a flow. */ - uint32_t flow_id_4; - /* Flow ID of a flow. */ - uint32_t flow_id_5; - /* Flow ID of a flow. */ - uint32_t flow_id_6; - /* Flow ID of a flow. */ - uint32_t flow_id_7; - /* Flow ID of a flow. */ - uint32_t flow_id_8; - /* Flow ID of a flow. */ - uint32_t flow_id_9; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; } __rte_packed; -/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ -struct hwrm_cfa_flow_stats_output { +/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ uint16_t req_type; /* The sequence ID from the original command. */ uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* packet_0 is 64 b */ - uint64_t packet_0; - /* packet_1 is 64 b */ - uint64_t packet_1; - /* packet_2 is 64 b */ - uint64_t packet_2; - /* packet_3 is 64 b */ - uint64_t packet_3; - /* packet_4 is 64 b */ - uint64_t packet_4; - /* packet_5 is 64 b */ - uint64_t packet_5; - /* packet_6 is 64 b */ - uint64_t packet_6; - /* packet_7 is 64 b */ - uint64_t packet_7; - /* packet_8 is 64 b */ - uint64_t packet_8; - /* packet_9 is 64 b */ - uint64_t packet_9; - /* byte_0 is 64 b */ - uint64_t byte_0; - /* byte_1 is 64 b */ - uint64_t byte_1; - /* byte_2 is 64 b */ - uint64_t byte_2; - /* byte_3 is 64 b */ - uint64_t byte_3; - /* byte_4 is 64 b */ - uint64_t byte_4; - /* byte_5 is 64 b */ - uint64_t byte_5; - /* byte_6 is 64 b */ - uint64_t byte_6; - /* byte_7 is 64 b */ - uint64_t byte_7; - /* byte_8 is 64 b */ - uint64_t byte_8; - /* byte_9 is 64 b */ - uint64_t byte_9; - uint8_t unused_0[7]; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; -/*********************************** - * hwrm_cfa_flow_aging_timer_reset * - ***********************************/ +/************************** + * hwrm_tf_ctxt_mem_alloc * + **************************/ -/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ -struct hwrm_cfa_flow_aging_timer_reset_input { +/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30603,20 +43181,14 @@ struct hwrm_cfa_flow_aging_timer_reset_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; - /* - * New flow timer value for the flow specified in the ext_flow_handle. - * The flow timer unit is 100ms. - */ - uint32_t flow_timer; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; + /* Size in KB of memory to be allocated. */ + uint32_t mem_size; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_timer_reset_output { +/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30625,24 +43197,69 @@ struct hwrm_cfa_flow_aging_timer_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G + /* unused. */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_cfa_flow_aging_cfg * - ***************************/ +/************************* + * hwrm_tf_ctxt_mem_free * + *************************/ -/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ -struct hwrm_cfa_flow_aging_cfg_input { +/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */ +struct hwrm_tf_ctxt_mem_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30671,77 +43288,59 @@ struct hwrm_cfa_flow_aging_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The bit field to enable per flow aging configuration. */ - uint16_t enables; - /* This bit must be '1' for the tcp flow timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ - UINT32_C(0x1) - /* This bit must be '1' for the tcp finish timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ - UINT32_C(0x2) - /* This bit must be '1' for the udp flow timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ - UINT32_C(0x4) - /* This bit must be '1' for the eem dma interval field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ - UINT32_C(0x8) - /* This bit must be '1' for the eem notice interval field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ - UINT32_C(0x10) - /* This bit must be '1' for the eem context memory maximum entries field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ - UINT32_C(0x20) - /* This bit must be '1' for the eem context memory ID field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ - UINT32_C(0x40) - /* This bit must be '1' for the eem context memory type field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ - UINT32_C(0x80) - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the enable, disable eem flow aging configuration. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ - (UINT32_C(0x0) << 1) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \ - (UINT32_C(0x1) << 1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE - uint8_t unused_0; - /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */ - uint32_t tcp_flow_timer; - /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */ - uint32_t tcp_fin_timer; - /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */ - uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ - uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - uint16_t eem_ctx_mem_type; - /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ - UINT32_C(0x0) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA - uint8_t unused_1[4]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G + /* unused. */ + uint8_t unused0[2]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + /* Size of memory allocated. */ + uint32_t mem_size; + /* unused. */ + uint8_t unused1[4]; } __rte_packed; -/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_cfg_output { +/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30750,24 +43349,26 @@ struct hwrm_cfa_flow_aging_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/**************************** - * hwrm_cfa_flow_aging_qcfg * - ****************************/ +/************************* + * hwrm_tf_ctxt_mem_rgtr * + *************************/ -/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcfg_input { +/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ +struct hwrm_tf_ctxt_mem_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30796,21 +43397,55 @@ struct hwrm_cfa_flow_aging_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; + /* Control flags. */ + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 128KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 512KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 8MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; } __rte_packed; -/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ -struct hwrm_cfa_flow_aging_qcfg_output { +/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30819,40 +43454,31 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t tcp_flow_timer; - /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t tcp_fin_timer; - /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */ - uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ - uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - /* The context memory type for eem flow aging. */ - uint16_t eem_ctx_mem_type; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/***************************** - * hwrm_cfa_flow_aging_qcaps * - *****************************/ +/*************************** + * hwrm_tf_ctxt_mem_unrgtr * + ***************************/ -/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcaps_input { +/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30881,21 +43507,19 @@ struct hwrm_cfa_flow_aging_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[2]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ -struct hwrm_cfa_flow_aging_qcaps_output { +/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30904,32 +43528,26 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_flow_timer; - /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_fin_timer; - /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */ - uint32_t max_udp_flow_timer; - /* The maximum aging flows that HW can support. */ - uint32_t max_aging_flows; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************************** - * hwrm_cfa_tcp_flag_process_qcfg * - **********************************/ +/************************ + * hwrm_tf_ext_em_qcaps * + ************************/ -/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_input { +/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30958,10 +43576,28 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_output { +/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */ +struct hwrm_tf_ext_em_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30970,32 +43606,128 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The port 0 RX mirror action record ID. */ - uint16_t rx_ar_id_port0; - /* The port 1 RX mirror action record ID. */ - uint16_t rx_ar_id_port1; - /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port0; - /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port1; - uint8_t unused_0[7]; + uint32_t flags; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When set to 1, indicates the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x1) + /* + * When set to 1, indicates the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x2) + /* When set to 1, indicates FW support for host based EEM memory. */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \ + UINT32_C(0x4) + /* When set to 1, indicates FW support for on-chip based EEM memory. */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \ + UINT32_C(0x8) + /* unused. */ + uint32_t unused0; + /* Support flags. */ + uint32_t supported; + /* + * If set to 1, then EXT EM KEY0 table is supported using + * crc32 hash. + * If set to 0, EXT EM KEY0 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EXT EM KEY1 table is supported using + * lookup3 hash. + * If set to 0, EXT EM KEY1 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EXT EM External Record table is supported. + * If set to 0, EXT EM External Record table is not + * supported. (This table includes action record, EFC + * pointers, encap pointers) + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EXT EM External Flow Counters table is + * supported. + * If set to 0, EXT EM External Flow Counters table is not + * supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush + * is supported. + * If set to 0, then FID table used for implicit flow flush + * is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * If set to 1, then table scopes are supported. + * If set to 0, then table scopes are not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \ + UINT32_C(0x20) + /* + * The maximum number of entries supported by EXT EM. When + * configuring the host memory the number of numbers of + * entries that can supported are - + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, + * 128M entries. + * Any value that are not these values, the FW will round + * down to the closest support number of entries. + */ + uint32_t max_entries_supported; + /* + * The entry size in bytes of each entry in the EXT EM + * KEY0/KEY1 tables. + */ + uint16_t key_entry_size; + /* + * The entry size in bytes of each entry in the EXT EM RECORD + * tables. + */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EXT EM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EXT EM FID tables. */ + uint16_t fid_entry_size; + /* Maximum number of ctxt mem allocations allowed. */ + uint32_t max_ctxt_mem_allocs; + /* + * Maximum number of static buckets that can be assigned to lookup + * table scopes. + */ + uint32_t max_static_buckets; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/********************** - * hwrm_cfa_pair_info * - **********************/ +/********************* + * hwrm_tf_ext_em_op * + *********************/ -/* hwrm_cfa_pair_info_input (size:448b/56B) */ -struct hwrm_cfa_pair_info_input { +/* hwrm_tf_ext_em_op_input (size:256b/32B) */ +struct hwrm_tf_ext_em_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31024,23 +43756,55 @@ struct hwrm_cfa_pair_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* If this flag is set, lookup by name else lookup by index. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) - /* If this flag is set, lookup by PF id and VF id. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) - /* Pair table index. */ - uint16_t pair_index; - /* Pair pf index. */ - uint8_t pair_pfid; - /* Pair vf index. */ - uint8_t pair_vfid; - /* Pair name (32 byte string). */ - char pair_name[32]; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX + /* unused. */ + uint16_t unused0; + /* The number of EXT EM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EXT EM and ensure there are no DMA's, + * the caller must disable EXT EM for the given PF, using + * this call. This will safely disable EXT EM and ensure + * that all DMA'ed to the keys/records/efc have been + * completed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) + /* + * Once the EXT EM host memory has been configured, EXT EM + * options have been configured. Then the caller should + * enable EXT EM for the given PF. Note once this call has + * been made, then the EXT EM mechanism will be active and + * DMA's will occur as packets are processed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) + /* + * Clear EXT EM settings for the given PF so that the + * register values are reset back to their initial state. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) + #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP + /* unused. */ + uint16_t unused1; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused2; } __rte_packed; -/* hwrm_cfa_pair_info_output (size:576b/72B) */ -struct hwrm_cfa_pair_info_output { +/* hwrm_tf_ext_em_op_output (size:128b/16B) */ +struct hwrm_tf_ext_em_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31049,74 +43813,26 @@ struct hwrm_cfa_pair_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Pair table index. */ - uint16_t next_pair_index; - /* Pair member a's fid. */ - uint16_t a_fid; - /* Logical host number. */ - uint8_t host_a_index; - /* Logical PF number. */ - uint8_t pf_a_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_a_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_a; - /* Tx CFA action. */ - uint16_t tx_cfa_action_a; - /* Pair member b's fid. */ - uint16_t b_fid; - /* Logical host number. */ - uint8_t host_b_index; - /* Logical PF number. */ - uint8_t pf_b_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_b_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_b; - /* Tx CFA action. */ - uint16_t tx_cfa_action_b; - /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ - uint8_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ - HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR - /* Pair state. */ - uint8_t pair_state; - /* Pair has been allocated */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) - /* Both pair members are active */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ - HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE - /* Pair name (32 byte string). */ - char pair_name[32]; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/*************************************** - * hwrm_cfa_redirect_query_tunnel_type * - ***************************************/ +/********************** + * hwrm_tf_ext_em_cfg * + **********************/ -/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ -struct hwrm_cfa_redirect_query_tunnel_type_input { +/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */ +struct hwrm_tf_ext_em_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31145,83 +43861,185 @@ struct hwrm_cfa_redirect_query_tunnel_type_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ -struct hwrm_cfa_redirect_query_tunnel_type_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Tunnel Mask. */ - uint32_t tunnel_mask; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \ + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ UINT32_C(0x1) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \ + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x2) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \ + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ UINT32_C(0x4) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \ + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* + * Dynamically reconfigure EEM pending cache every 1/10th of second. + * If set to 0 it will disable the EEM HW flush of the pending cache. + */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused0; + /* + * Configured EXT EM with the given number of entries. All + * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the + * same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current + * maximum value is 128M. + */ + uint32_t num_entries; + uint32_t enables; + /* + * This bit must be '1' for the group_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the flush_interval field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \ + UINT32_C(0x2) + /* + * This bit must be '1' for the num_entries field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \ + UINT32_C(0x4) + /* + * This bit must be '1' for the key0_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \ UINT32_C(0x8) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \ + /* + * This bit must be '1' for the key1_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \ UINT32_C(0x10) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ + /* + * This bit must be '1' for the record_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \ UINT32_C(0x20) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ + /* + * This bit must be '1' for the efc_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \ UINT32_C(0x40) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \ + /* + * This bit must be '1' for the fid_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \ UINT32_C(0x80) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \ + /* + * This bit must be '1' for the action_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \ UINT32_C(0x100) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ + /* + * This bit must be '1' for the action_tbl_scope field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \ UINT32_C(0x200) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ + /* + * This bit must be '1' for the lkup_ctx_id field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \ UINT32_C(0x400) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \ + /* + * This bit must be '1' for the lkup_tbl_scope field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \ UINT32_C(0x800) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ + /* + * This bit must be '1' for the lkup_static_buckets field to be + * configured. + */ + #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \ UINT32_C(0x1000) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ - UINT32_C(0x2000) - uint8_t unused_0[3]; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* Context id of action table scope. */ + uint16_t action_ctx_id; + /* Table scope id used for action record entries. */ + uint16_t action_tbl_scope; + /* Context id of lookup table scope. */ + uint16_t lkup_ctx_id; + /* Table scope id used for EM lookup entries. */ + uint16_t lkup_tbl_scope; + /* unused. */ + uint16_t unused1; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Number of 32B static buckets to be allocated at the beginning + * of table scope. + */ + uint32_t lkup_static_buckets; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused2; +} __rte_packed; + +/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +struct hwrm_tf_ext_em_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/************************* - * hwrm_cfa_ctx_mem_rgtr * - *************************/ +/*********************** + * hwrm_tf_ext_em_qcfg * + ***********************/ -/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_rgtr_input { +/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31250,44 +44068,22 @@ struct hwrm_cfa_ctx_mem_rgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ - HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G - uint32_t unused_0; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; } __rte_packed; -/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_rgtr_output { +/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ +struct hwrm_tf_ext_em_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31296,29 +44092,118 @@ struct hwrm_cfa_ctx_mem_rgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint16_t unused0; + uint32_t supported; + /* This bit must be '1' for the group_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \ + UINT32_C(0x1) + /* This bit must be '1' for the flush_interval field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \ + UINT32_C(0x2) + /* This bit must be '1' for the num_entries field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \ + UINT32_C(0x4) + /* This bit must be '1' for the key0_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \ + UINT32_C(0x8) + /* This bit must be '1' for the key1_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \ + UINT32_C(0x10) + /* This bit must be '1' for the record_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \ + UINT32_C(0x20) + /* This bit must be '1' for the efc_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the fid_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \ + UINT32_C(0x80) + /* This bit must be '1' for the action_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \ + UINT32_C(0x100) + /* This bit must be '1' for the action_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \ + UINT32_C(0x200) + /* This bit must be '1' for the lkup_ctx_id field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \ + UINT32_C(0x400) + /* This bit must be '1' for the lkup_tbl_scope field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \ + UINT32_C(0x800) + /* This bit must be '1' for the lkup_static_buckets field is set. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \ + UINT32_C(0x1000) /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. + * Group id is used by firmware to identify memory pools belonging + * to certain group. */ - uint16_t ctx_id; - uint8_t unused_0[5]; + uint16_t group_id; + /* EEM pending cache flush interval in 1/10th of second. */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused1; + /* Context id of action table scope. */ + uint16_t action_ctx_id; + /* Table scope id used for action record entries. */ + uint16_t action_tbl_scope; + /* Context id of lookup table scope. */ + uint16_t lkup_ctx_id; + /* Table scope id used for EM lookup entries. */ + uint16_t lkup_tbl_scope; + /* + * Number of 32B static buckets to be allocated at the beginning + * of table scope. + */ + uint32_t lkup_static_buckets; + /* unused. */ + uint8_t unused2[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/*************************** - * hwrm_cfa_ctx_mem_unrgtr * - ***************************/ +/********************* + * hwrm_tf_em_insert * + *********************/ -/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_unrgtr_input { +/* hwrm_tf_em_insert_input (size:832b/104B) */ +struct hwrm_tf_em_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31347,16 +44232,34 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[6]; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX + /* Reported match strength. */ + uint16_t strength; + /* Index to action. */ + uint32_t action_ptr; + /* Index of EM record. */ + uint32_t em_record_idx; + /* EM Key value. */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused0[3]; } __rte_packed; -/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_unrgtr_output { +/* hwrm_tf_em_insert_output (size:128b/16B) */ +struct hwrm_tf_em_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31365,24 +44268,23 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; } __rte_packed; -/************************* - * hwrm_cfa_ctx_mem_qctx * - *************************/ +/************************** + * hwrm_tf_em_hash_insert * + **************************/ -/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_qctx_input { +/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ +struct hwrm_tf_em_hash_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31411,16 +44313,34 @@ struct hwrm_cfa_ctx_mem_qctx_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[6]; + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX + /* Number of bits in the EM record. */ + uint16_t em_record_size_bits; + /* CRC32 hash of key. */ + uint32_t key0_hash; + /* Lookup3 hash of key. */ + uint32_t key1_hash; + /* Index of EM record. */ + uint32_t em_record_idx; + /* Unused. */ + uint32_t unused0; + /* EM record. */ + uint64_t em_record[11]; } __rte_packed; -/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_qctx_output { +/* hwrm_tf_em_hash_insert_output (size:128b/16B) */ +struct hwrm_tf_em_hash_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31429,58 +44349,23 @@ struct hwrm_cfa_ctx_mem_qctx_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G - uint8_t unused_0[4]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - uint8_t unused_1[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; } __rte_packed; -/************************** - * hwrm_cfa_ctx_mem_qcaps * - **************************/ +/********************* + * hwrm_tf_em_delete * + *********************/ -/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_input { +/* hwrm_tf_em_delete_input (size:832b/104B) */ +struct hwrm_tf_em_delete_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31509,10 +44394,32 @@ struct hwrm_cfa_ctx_mem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX + /* Unused0 */ + uint16_t unused0; + /* EM internal flow hanndle. */ + uint64_t flow_handle; + /* EM Key value */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused1[3]; } __rte_packed; -/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_output { +/* hwrm_tf_em_delete_output (size:128b/16B) */ +struct hwrm_tf_em_delete_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31521,26 +44428,19 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Indicates the maximum number of context memory which can be registered. */ - uint16_t max_entries; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; + /* Original stack allocation index. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; } __rte_packed; -/********************** - * hwrm_cfa_eem_qcaps * - **********************/ +/******************** + * hwrm_tf_tcam_set * + ********************/ -/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcaps_input { +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +struct hwrm_tf_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31569,29 +44469,52 @@ struct hwrm_cfa_eem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. + * Indicate device data is being sent via DMA, the device + * data is packing does not change. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - uint32_t unused_0; + uint32_t type; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[88]; } __rte_packed; -/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_eem_qcaps_output { +/* hwrm_tf_tcam_set_output (size:128b/16B) */ +struct hwrm_tf_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31600,104 +44523,26 @@ struct hwrm_cfa_eem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* - * When set to 1, indicates the the FW supports the Centralized - * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ - UINT32_C(0x4) - /* - * When set to 1, indicates the the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct - * or semi-direct access to the allocated memory while none of - * which can interfere with the management of the memory. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ - UINT32_C(0x8) - uint32_t unused_0; - uint32_t supported; - /* - * If set to 1, then EEM KEY0 table is supported using crc32 hash. - * If set to 0, EEM KEY0 table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ - UINT32_C(0x1) - /* - * If set to 1, then EEM KEY1 table is supported using lookup3 hash. - * If set to 0, EEM KEY1 table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ - UINT32_C(0x2) - /* - * If set to 1, then EEM External Record table is supported. - * If set to 0, EEM External Record table is not supported. - * (This table includes action record, EFC pointers, encap pointers) - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ - UINT32_C(0x4) - /* - * If set to 1, then EEM External Flow Counters table is supported. - * If set to 0, EEM External Flow Counters table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ - UINT32_C(0x8) - /* - * If set to 1, then FID table used for implicit flow flush is supported. - * If set to 0, then FID table used for implicit flow flush is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ - UINT32_C(0x10) - /* - * The maximum number of entries supported by EEM. When configuring the host memory - * the number of numbers of entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. - * Any value that are not these values, the FW will round down to the closest support - * number of entries. - */ - uint32_t max_entries_supported; - /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ - uint16_t key_entry_size; - /* The entry size in bytes of each entry in the EEM RECORD tables. */ - uint16_t record_entry_size; - /* The entry size in bytes of each entry in the EEM EFC tables. */ - uint16_t efc_entry_size; - /* The FID size in bytes of each entry in the EEM FID tables. */ - uint16_t fid_entry_size; - uint8_t unused_1[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; /******************** - * hwrm_cfa_eem_cfg * + * hwrm_tf_tcam_get * ********************/ -/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ -struct hwrm_cfa_eem_cfg_input { +/* hwrm_tf_tcam_get_input (size:256b/32B) */ +struct hwrm_tf_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31726,56 +44571,31 @@ struct hwrm_cfa_eem_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \ - UINT32_C(0x8) - /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - uint16_t unused_0; - /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, - * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - uint32_t num_entries; - uint32_t unused_1; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint16_t unused_2; - uint32_t unused_3; + uint32_t type; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; } __rte_packed; -/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ -struct hwrm_cfa_eem_cfg_output { +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +struct hwrm_tf_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31784,24 +44604,41 @@ struct hwrm_cfa_eem_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; /********************* - * hwrm_cfa_eem_qcfg * + * hwrm_tf_tcam_move * *********************/ -/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcfg_input { +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +struct hwrm_tf_tcam_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31830,16 +44667,33 @@ struct hwrm_cfa_eem_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint32_t unused_0; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; } __rte_packed; -/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ -struct hwrm_cfa_eem_qcfg_output { +/* hwrm_tf_tcam_move_output (size:128b/16B) */ +struct hwrm_tf_tcam_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31848,46 +44702,26 @@ struct hwrm_cfa_eem_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - /* The number of entries the FW has configured for EEM. */ - uint32_t num_entries; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint8_t unused_2[5]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/******************* - * hwrm_cfa_eem_op * - *******************/ +/********************* + * hwrm_tf_tcam_free * + *********************/ -/* hwrm_cfa_eem_op_input (size:192b/24B) */ -struct hwrm_cfa_eem_op_input { +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +struct hwrm_tf_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31916,49 +44750,33 @@ struct hwrm_cfa_eem_op_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the host memory which is passed will be - * used for the TX flow offload function specified in fid. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* - * When set to 1, indicates the host memory which is passed will be - * used for the RX flow offload function specified in fid. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint16_t unused_0; - /* The number of EEM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) - /* - * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will - * safely disable EEM and ensure that all DMA'ed to the - * keys/records/efc have been completed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) - /* - * Once the EEM host memory has been configured, EEM options have - * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism - * will be active and DMA's will occur as packets are processed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) - /* - * Clear EEM settings for the given PF so that the register values - * are reset back to there initial state. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) - #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ - HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; } __rte_packed; -/* hwrm_cfa_eem_op_output (size:128b/16B) */ -struct hwrm_cfa_eem_op_output { +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31967,24 +44785,26 @@ struct hwrm_cfa_eem_op_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __rte_packed; -/******************************** - * hwrm_cfa_adv_flow_mgnt_qcaps * - ********************************/ +/************************** + * hwrm_tf_global_cfg_set * + **************************/ -/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_input { +/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ +struct hwrm_tf_global_cfg_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32013,11 +44833,34 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[8]; + /* Mask of data to set, 0 indicates no mask */ + uint8_t mask[8]; } __rte_packed; -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { +/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ +struct hwrm_tf_global_cfg_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32026,131 +44869,277 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; + /* unused. */ + uint8_t unused0[7]; /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ - UINT32_C(0x1) + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tf_global_cfg_get * + **************************/ + + +/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ +struct hwrm_tf_global_cfg_get_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ - UINT32_C(0x4) + uint16_t seq_id; /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ - UINT32_C(0x8) + uint16_t target_id; /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ - UINT32_C(0x10) + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +struct hwrm_tf_global_cfg_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Size of the data read in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[16]; +} __rte_packed; + +/********************** + * hwrm_tf_if_tbl_get * + **********************/ + + +/* hwrm_tf_if_tbl_get_input (size:256b/32B) */ +struct hwrm_tf_if_tbl_get_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x20) + uint16_t cmpl_ring; /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x40) + uint16_t seq_id; /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ - UINT32_C(0x80) + uint16_t target_id; /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ - UINT32_C(0x100) + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Size of the data to set. */ + uint16_t size; /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ - UINT32_C(0x200) + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} __rte_packed; + +/* hwrm_tf_if_tbl_get_output (size:256b/32B) */ +struct hwrm_tf_if_tbl_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[8]; + /* unused */ + uint8_t unused1[7]; /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ - UINT32_C(0x400) + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_tf_if_tbl_type_set * + ***************************/ + + +/* hwrm_tf_if_tbl_set_input (size:384b/48B) */ +struct hwrm_tf_if_tbl_set_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) + uint16_t cmpl_ring; /* - * If set to 1, firmware is capable of supporting ARP ethertype as - * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the - * RX direction. By default, this flag should be 0 for older version - * of firmware. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ - UINT32_C(0x1000) + uint16_t seq_id; /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC - * command. Value of 0 indicates firmware does not support - * rfs_ring_tbl_idx in dst_id field. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ - UINT32_C(0x2000) + uint16_t target_id; /* - * If set to 1, firmware is capable of supporting IPv4/IPv6 as - * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX - * direction. By default, this flag should be 0 for older version - * of firmware. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ - UINT32_C(0x4000) - uint8_t unused_0[3]; + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[8]; +} __rte_packed; + +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +struct hwrm_tf_if_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; -/****************** - * hwrm_cfa_tflib * - ******************/ +/***************************** + * hwrm_tf_tbl_type_bulk_get * + *****************************/ -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { +/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ +struct hwrm_tf_tbl_type_bulk_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32179,18 +45168,37 @@ struct hwrm_cfa_tflib_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Starting index of the type to retrieve. */ + uint32_t start_index; + /* Number of entries to retrieve. */ + uint32_t num_entries; + /* Number of entries to retrieve. */ + uint32_t unused1; + /* Host memory where data will be stored. */ + uint64_t host_addr; } __rte_packed; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_bulk_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32199,22 +45207,19 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; - /* unused. */ - uint8_t unused1[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint8_t unused0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __rte_packed; @@ -32512,10 +45517,10 @@ struct ctx_hw_stats { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -32528,10 +45533,10 @@ struct ctx_hw_stats { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -32548,8 +45553,12 @@ struct ctx_hw_stats { uint64_t tpa_aborts; } __rte_packed; -/* Periodic statistics context DMA to host. */ -/* ctx_hw_stats_ext (size:1344b/168B) */ +/* + * Extended periodic statistics context DMA to host. On cards that + * support TPA v2, additional TPA related stats exist and can be retrieved + * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. + */ +/* ctx_hw_stats_ext (size:1408b/176B) */ struct ctx_hw_stats_ext { /* Number of received unicast packets */ uint64_t rx_ucast_pkts; @@ -32557,10 +45566,10 @@ struct ctx_hw_stats_ext { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -32573,10 +45582,10 @@ struct ctx_hw_stats_ext { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -32593,6 +45602,8 @@ struct ctx_hw_stats_ext { uint64_t rx_tpa_bytes; /* Number of TPA errors */ uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; } __rte_packed; /* Periodic Engine statistics context DMA to host. */ @@ -32842,7 +45853,14 @@ struct hwrm_stat_ctx_query_input { uint64_t resp_addr; /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; - uint8_t unused_0[4]; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[3]; } __rte_packed; /* hwrm_stat_ctx_query_output (size:1408b/176B) */ @@ -32861,10 +45879,10 @@ struct hwrm_stat_ctx_query_output { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; - /* Number of transmitted packets with error */ - uint64_t tx_err_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; + /* Number of packets discarded in transmit path */ + uint64_t tx_discard_pkts; + /* Number of packets in transmit path with error */ + uint64_t tx_error_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -32877,10 +45895,10 @@ struct hwrm_stat_ctx_query_output { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of received packets with error */ - uint64_t rx_err_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets discarded in receive path */ + uint64_t rx_discard_pkts; + /* Number of packets in receive path with errors */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -32906,6 +45924,119 @@ struct hwrm_stat_ctx_query_output { uint8_t valid; } __rte_packed; +/*************************** + * hwrm_stat_ext_ctx_query * + ***************************/ + + +/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ +struct hwrm_stat_ext_ctx_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* ID of the extended statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \ + UINT32_C(0x1) + uint8_t unused_0[3]; +} __rte_packed; + +/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ +struct hwrm_stat_ext_ctx_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*************************** * hwrm_stat_ctx_eng_query * ***************************/ @@ -33155,9 +46286,9 @@ struct pcie_ctx_hw_stats { uint64_t pcie_tl_signal_integrity; /* Number of times LTSSM entered Recovery state */ uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been transmitted */ + /* Report number of TLP bits that have been transmitted in Mbps */ uint64_t pcie_tx_traffic_rate; - /* Number of TLP bytes that have been received */ + /* Report number of TLP bits that have been received in Mbps */ uint64_t pcie_rx_traffic_rate; /* Number of DLLP bytes that have been transmitted */ uint64_t pcie_tx_dllp_statistics; @@ -33857,7 +46988,10 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ + /* + * The Directory Entry Type (valid values are defined in the bnxnvm + * directory_type enum defined in the file bnxnvm_defs.h). + */ uint16_t dir_type; /* * Directory ordinal. @@ -33869,8 +47003,10 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated + * size for the directory entry. + * The data length stored in the directory entry will be updated to reflect + * this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -33883,11 +47019,15 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). + * The requested length of the allocated NVM for the item, in bytes. This + * value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be + * greater than the requested item length. + * The purpose for allocating more than the required number of bytes for + * an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a + * size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; uint32_t unused_0; @@ -33904,8 +47044,11 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be + * greater than or equal to the specified data length or the requested + * item length. + * The actual item length used when creating a new directory entry will be + * a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -33981,7 +47124,23 @@ struct hwrm_nvm_modify_input { uint64_t host_src_addr; /* 16-bit directory entry index. */ uint16_t dir_idx; - uint8_t unused_0[2]; + uint16_t flags; + /* + * This flag indicates the sender wants to modify a continuous NVRAM + * area using a batch of this HWRM requests. The offset of a request + * must be continuous to the end of previous request's. Firmware does + * not update the directory entry until receiving the last request, + * which is indicated by the batch_last flag. + * This flag is set usually when a sender does not have a block of + * memory that is big enough to hold the entire NVRAM data for send + * at one time. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) + /* + * This flag can be used only when the batch_mode flag is set. + * It indicates this request is the last of batch requests. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) /* 32-bit NVRAM byte-offset to modify content from. */ uint32_t offset; /* @@ -34048,42 +47207,174 @@ struct hwrm_nvm_find_dir_entry_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the dir_idx_valid field to be - * configured. - */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \ - UINT32_C(0x1) - /* Directory Entry Index */ - uint16_t dir_idx; - /* Directory Entry (Image) Type */ - uint16_t dir_type; - /* - * Directory ordinal. - * The instance of this Directory Type - */ - uint16_t dir_ordinal; - /* The Directory Entry Extension flags. */ - uint16_t dir_ext; - /* This value indicates the search option using dir_ordinal. */ - uint8_t opt_ordinal; - /* This value indicates the search option using dir_ordinal. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 - /* Equal to specified ordinal value. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) - /* Greater than or equal to specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) - /* Greater than specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ - HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT - uint8_t unused_0[3]; + uint32_t enables; + /* + * This bit must be '1' for the dir_idx_valid field to be + * configured. + */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \ + UINT32_C(0x1) + /* Directory Entry Index */ + uint16_t dir_idx; + /* Directory Entry (Image) Type */ + uint16_t dir_type; + /* + * Directory ordinal. + * The instance of this Directory Type + */ + uint16_t dir_ordinal; + /* The Directory Entry Extension flags. */ + uint16_t dir_ext; + /* This value indicates the search option using dir_ordinal. */ + uint8_t opt_ordinal; + /* This value indicates the search option using dir_ordinal. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 + /* Equal to specified ordinal value. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) + /* Greater than or equal to specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) + /* Greater than specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ + HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT + uint8_t unused_0[3]; +} __rte_packed; + +/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ +struct hwrm_nvm_find_dir_entry_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Allocated NVRAM for this directory entry, in bytes. */ + uint32_t dir_item_length; + /* Size of the stored data for this directory entry, in bytes. */ + uint32_t dir_data_length; + /* + * Firmware version. + * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + */ + uint32_t fw_ver; + /* Directory ordinal. */ + uint16_t dir_ordinal; + /* Directory Entry Index */ + uint16_t dir_idx; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_nvm_erase_dir_entry * + ****************************/ + + +/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ +struct hwrm_nvm_erase_dir_entry_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Directory Entry Index */ + uint16_t dir_idx; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ +struct hwrm_nvm_erase_dir_entry_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_nvm_get_dev_info * + *************************/ + + +/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ +struct hwrm_nvm_get_dev_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; } __rte_packed; -/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ -struct hwrm_nvm_find_dir_entry_output { +/* hwrm_nvm_get_dev_info_output (size:640b/80B) */ +struct hwrm_nvm_get_dev_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34092,155 +47383,102 @@ struct hwrm_nvm_find_dir_entry_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Allocated NVRAM for this directory entry, in bytes. */ - uint32_t dir_item_length; - /* Size of the stored data for this directory entry, in bytes. */ - uint32_t dir_data_length; + /* Manufacturer ID. */ + uint16_t manufacturer_id; + /* Device ID. */ + uint16_t device_id; + /* Sector size of the NVRAM device. */ + uint32_t sector_size; + /* Total size, in bytes of the NVRAM device. */ + uint32_t nvram_size; + uint32_t reserved_size; /* - * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + * Available size that can be used, in bytes. Available size is the + * NVRAM size take away the used size and reserved size. */ - uint32_t fw_ver; - /* Directory ordinal. */ - uint16_t dir_ordinal; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[7]; + uint32_t available_size; + /* This field represents the major version of NVM cfg */ + uint8_t nvm_cfg_ver_maj; + /* This field represents the minor version of NVM cfg */ + uint8_t nvm_cfg_ver_min; + /* This field represents the update version of NVM cfg */ + uint8_t nvm_cfg_ver_upd; + uint8_t flags; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If set to 1, firmware will provide various firmware version + * information stored in the flash. */ - uint8_t valid; -} __rte_packed; - -/**************************** - * hwrm_nvm_erase_dir_entry * - ****************************/ - - -/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ -struct hwrm_nvm_erase_dir_entry_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \ + UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field represents the board package name stored in the flash. + * (ASCII chars with NULL at the end). */ - uint16_t cmpl_ring; + char pkg_name[16]; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field represents the major version of HWRM firmware, stored in + * the flash. */ - uint16_t seq_id; + uint16_t hwrm_fw_major; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field represents the minor version of HWRM firmware, stored in + * the flash. */ - uint16_t target_id; + uint16_t hwrm_fw_minor; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field represents the build version of HWRM firmware, stored in + * the flash. */ - uint64_t resp_addr; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[6]; -} __rte_packed; - -/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ -struct hwrm_nvm_erase_dir_entry_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t hwrm_fw_build; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the HWRM firmware. */ - uint8_t valid; -} __rte_packed; - -/************************* - * hwrm_nvm_get_dev_info * - *************************/ - - -/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ -struct hwrm_nvm_get_dev_info_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t hwrm_fw_patch; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field represents the major version of mgmt firmware, stored in + * the flash. */ - uint16_t cmpl_ring; + uint16_t mgmt_fw_major; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field represents the minor version of mgmt firmware, stored in + * the flash. */ - uint16_t seq_id; + uint16_t mgmt_fw_minor; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This field represents the build version of mgmt firmware, stored in + * the flash. */ - uint16_t target_id; + uint16_t mgmt_fw_build; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the mgmt firmware. */ - uint64_t resp_addr; -} __rte_packed; - -/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ -struct hwrm_nvm_get_dev_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Manufacturer ID. */ - uint16_t manufacturer_id; - /* Device ID. */ - uint16_t device_id; - /* Sector size of the NVRAM device. */ - uint32_t sector_size; - /* Total size, in bytes of the NVRAM device. */ - uint32_t nvram_size; - uint32_t reserved_size; - /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ - uint32_t available_size; - /* This field represents the major version of NVM cfg */ - uint8_t nvm_cfg_ver_maj; - /* This field represents the minor version of NVM cfg */ - uint8_t nvm_cfg_ver_min; - /* This field represents the update version of NVM cfg */ - uint8_t nvm_cfg_ver_upd; + uint16_t mgmt_fw_patch; + /* + * This field represents the major version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_major; + /* + * This field represents the minor version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_minor; + /* + * This field represents the build version of roce firmware, stored in + * the flash. + */ + uint16_t roce_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the roce firmware. + */ + uint16_t roce_fw_patch; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -34299,9 +47537,15 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension + * flag definitions). + */ uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag + * definitions). + */ uint16_t dir_attr; /* * If valid, then this field updates the checksum @@ -34468,8 +47712,10 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, will be safely deleted. - * When combined with erase_unused_space then unspecified images will be securely erased. + * If set to 1, then unspecified images, images not in the package file, + * will be safely deleted. + * When combined with erase_unused_space then unspecified images will be + * securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -34479,6 +47725,13 @@ struct hwrm_nvm_install_update_input { */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) + /* + * If set to 1, FW will verify the package in the "UPDATE" NVM item + * without installing it. This flag is for FW internal use only. + * Users should not set this flag. The request will otherwise fail. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \ + UINT32_C(0x8) uint8_t unused_0[2]; } __rte_packed; @@ -34847,7 +48100,10 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ + /* + * When this bit is 1, flush internal cache after this write operation + * (see hwrm_nvm_flush command.) + */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -35029,6 +48285,72 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/**************** + * hwrm_oem_cmd * + ****************/ + + +/* hwrm_oem_cmd_input (size:1024b/128B) */ +struct hwrm_oem_cmd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific command data. */ + uint32_t oem_data[26]; +} __rte_packed; + +/* hwrm_oem_cmd_output (size:768b/96B) */ +struct hwrm_oem_cmd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific response data. */ + uint32_t oem_data[18]; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /***************** * hwrm_fw_reset * ******************/ @@ -35083,7 +48405,10 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \ UINT32_C(0x4) - /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */ + /* + * AP processor complex (in multi-host environment). Use host_idx to + * control which core is reset + */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \ UINT32_C(0x5) /* Reset all blocks of the chip (including all processors) */ @@ -35252,4 +48577,52 @@ struct hwrm_port_ts_query_output { uint8_t valid; } __rte_packed; +/* + * This structure is fixed at the beginning of the ChiMP SRAM (GRC + * offset: 0x31001F0). Host software is expected to read from this + * location for a defined signature. If it exists, the software can + * assume the presence of this structure and the validity of the + * FW_STATUS location in the next field. + */ +/* hcomm_status (size:64b/8B) */ +struct hcomm_status { + uint32_t sig_ver; + /* + * This field defines the version of the structure. The latest + * version value is 1. + */ + #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) + #define HCOMM_STATUS_VER_SFT 0 + #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) + #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST + /* + * This field is to store the signature value to indicate the + * presence of the structure. + */ + #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) + #define HCOMM_STATUS_SIGNATURE_SFT 8 + #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) + #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL + uint32_t fw_status_loc; + #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) + #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 + /* PCIE configuration space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) + /* GRC space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) + /* BAR0 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) + /* BAR1 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \ + HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + /* + * This offset where the fw_status register is located. The value + * is generally 4-byte aligned. + */ + #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) + #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 +} __rte_packed; +/* This is the GRC offset where the hcomm_status struct resides. */ +#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL #endif /* _HSI_STRUCT_DEF_DPDK_H_ */