X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=fd6d8807e5d2b8be90d1d0f7a212300c4a6284af;hb=5dadd757188e68260880924dea38c22858ac2ca9;hp=5788632a454cc7051b45c2227cfea1f0d4a0df30;hpb=9a891c1764eaa0e9b8982f8509d2ccadfb4ca624;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 5788632a45..fd6d8807e5 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -3282,574 +3282,1225 @@ struct hwrm_async_event_cmpl_link_status_change { 4 } __attribute__((packed)); -/******************* - * hwrm_func_reset * - *******************/ - - -/* hwrm_func_reset_input (size:192b/24B) */ -struct hwrm_func_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; +/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_mtu_change { + uint16_t type; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \ + UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* The new MTU of the link in bytes. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_change { + uint16_t type; /* - * This bit must be '1' for the vf_id_valid field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The ID of the VF that this PF is trying to reset. - * Only the parent PF shall be allowed to reset a child VF. - * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t vf_id; - /* This value indicates the level of a function reset. */ - uint8_t func_reset_level; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * Reset the caller function and its children VFs (if any). If no - * children functions exist, then reset the caller function only. + * When this bit is '1', the link was forced to the + * force_link_speed value. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ - UINT32_C(0x0) - /* Reset the caller function only */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \ UINT32_C(0x1) + /* The new link speed in 100 Mbps units. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \ + UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \ + 1 + /* 100Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \ + (UINT32_C(0x1) << 1) + /* 1Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \ + (UINT32_C(0xa) << 1) + /* 2Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \ + (UINT32_C(0x14) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \ + (UINT32_C(0x19) << 1) + /* 10Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \ + (UINT32_C(0x64) << 1) + /* 20Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \ + (UINT32_C(0xc8) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \ + (UINT32_C(0xfa) << 1) + /* 40Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \ + (UINT32_C(0x190) << 1) + /* 50Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \ + (UINT32_C(0x1f4) << 1) + /* 100Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \ + (UINT32_C(0x3e8) << 1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 16 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_dcb_config_change { + uint16_t type; /* - * Reset all children VFs of the caller function driver if the - * caller is a PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver with - * no children VFs. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE + /* Event specific data */ + uint32_t event_data2; + /* ETS configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \ + UINT32_C(0x1) + /* PFC configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \ UINT32_C(0x2) + /* APP configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \ + UINT32_C(0x4) + uint8_t opaque_v; /* - * Reset a specific VF of the caller function driver if the caller - * is the parent PF driver. - * It is an error to specify this level by a VF driver. - * It is an error to specify this level by a PF driver that is not - * the parent of the VF that is being requested to reset. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ - UINT32_C(0x3) - #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ - HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF - uint8_t unused_0; + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 + /* Priority recommended for RoCE traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \ + 16 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \ + (UINT32_C(0xff) << 16) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE + /* Priority recommended for L2 traffic */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \ + UINT32_C(0xff000000) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \ + 24 + /* none is 255 */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \ + (UINT32_C(0xff) << 24) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE } __attribute__((packed)); -/* hwrm_func_reset_output (size:128b/16B) */ -struct hwrm_func_reset_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_conn_not_allowed { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __attribute__((packed)); - -/******************** - * hwrm_func_getfid * - ********************/ - - -/* hwrm_func_getfid_input (size:192b/24B) */ -struct hwrm_func_getfid_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; + * This value indicates the current port level enforcement policy + * for the optics module when there is an optical module mismatch + * and port is not connected. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \ + 16 + /* No enforcement */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \ + (UINT32_C(0x0) << 16) + /* Disable Transmit side Laser. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \ + (UINT32_C(0x1) << 16) + /* Raise a warning message. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \ + (UINT32_C(0x2) << 16) + /* Power down the module. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \ + (UINT32_C(0x3) << 16) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { + uint16_t type; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \ + UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ + 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_link_speed_cfg_change { + uint16_t type; /* - * This bit must be '1' for the pci_id field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \ + UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This value is the PCI ID of the queried function. - * If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (5b):Function Number(3b). + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t pci_id; - uint8_t unused_0[2]; -} __attribute__((packed)); - -/* hwrm_func_getfid_output (size:128b/16B) */ -struct hwrm_func_getfid_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * If set to 1, it indicates that the supported link speeds + * configuration on the port has changed. + * If set to 0, then there is no change in supported link speeds + * configuration. */ - uint16_t fid; - uint8_t unused_0[5]; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \ + UINT32_C(0x10000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * If set to 1, it indicates that the link speed configuration + * on the port has become illegal or invalid. + * If set to 0, then the link speed configuration on the port is + * legal or valid. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ + UINT32_C(0x20000) } __attribute__((packed)); -/********************** - * hwrm_func_vf_alloc * - **********************/ - - -/* hwrm_func_vf_alloc_input (size:192b/24B) */ -struct hwrm_func_vf_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; +/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_port_phy_cfg_change { + uint16_t type; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \ + UINT32_C(0x7) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 0 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1, it indicates that the FEC + * configuration on the port has changed. + * If set to 0, then there is no change in FEC configuration. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \ + UINT32_C(0x10000) /* - * This bit must be '1' for the first_vf_id field to be - * configured. + * If set to 1, it indicates that the EEE configuration + * on the port has changed. + * If set to 0, then there is no change in EEE configuration + * on the port. */ - #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \ + UINT32_C(0x20000) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * If set to 1, it indicates that the pause configuration + * on the PHY has changed. + * If set to 0, then there is no change in the pause + * configuration on the PHY. */ - uint16_t first_vf_id; - /* The number of virtual functions requested. */ - uint16_t num_vfs; + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ + UINT32_C(0x40000) } __attribute__((packed)); -/* hwrm_func_vf_alloc_output (size:128b/16B) */ -struct hwrm_func_vf_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The ID of the first VF allocated. */ - uint16_t first_vf_id; - uint8_t unused_0[5]; +/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_unload { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \ + UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ + 0 } __attribute__((packed)); -/********************* - * hwrm_func_vf_free * - *********************/ - - -/* hwrm_func_vf_free_input (size:192b/24B) */ -struct hwrm_func_vf_free_input { - /* The HWRM command request type. */ - uint16_t req_type; +/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_drvr_load { + uint16_t type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \ + UINT32_C(0x11) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ +struct hwrm_async_event_cmpl_func_flr_proc_cmplt { + uint16_t type; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \ + UINT32_C(0x12) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the first_vf_id field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ + 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_unload { + uint16_t type; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t first_vf_id; + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \ + UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The number of virtual functions requested. - * 0xFFFF - Cleanup all children of this PF. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t num_vfs; + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 } __attribute__((packed)); -/* hwrm_func_vf_free_output (size:128b/16B) */ -struct hwrm_func_vf_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; +/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_drvr_load { + uint16_t type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t valid; -} __attribute__((packed)); - -/******************** - * hwrm_func_vf_cfg * - ********************/ - - -/* hwrm_func_vf_cfg_input (size:448b/56B) */ -struct hwrm_func_vf_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \ + UINT32_C(0x21) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t cmpl_ring; + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_flr { + uint16_t type; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint16_t seq_id; + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t target_id; + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_mac_addr_change { + uint16_t type; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \ + UINT32_C(0x31) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the mtu field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ + 0 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pf_vf_comm_status_change { + uint16_t type; /* - * This bit must be '1' for the guest_vlan field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ - UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \ + UINT32_C(0x32) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the async_event_cr field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ - UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. + * If this bit is set to 1, then it indicates that the PF-VF + * communication was lost and it is established. + * If this bit set to 0, then it indicates that the PF-VF + * communication was established and it is lost. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ - UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ + UINT32_C(0x1) +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_vf_cfg_change { + uint16_t type; /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ - UINT32_C(0x10) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \ + UINT32_C(0x33) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * This bit must be '1' for the num_cmpl_rings field to be - * configured. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ - UINT32_C(0x20) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; /* - * This bit must be '1' for the num_tx_rings field to be - * configured. + * Each flag provided in this field indicates a specific VF + * configuration change. At least one of these flags shall be set to 1 + * when an asynchronous event completion of this type is provided + * by the HWRM. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ - UINT32_C(0x40) + uint32_t event_data1; /* - * This bit must be '1' for the num_rx_rings field to be - * configured. + * If this bit is set to 1, then the value of MTU + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ - UINT32_C(0x80) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \ + UINT32_C(0x1) /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. + * If this bit is set to 1, then the value of MRU + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ - UINT32_C(0x100) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \ + UINT32_C(0x2) /* - * This bit must be '1' for the num_vnics field to be - * configured. + * If this bit is set to 1, then the value of default MAC + * address was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ - UINT32_C(0x200) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \ + UINT32_C(0x4) /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. + * If this bit is set to 1, then the value of default VLAN + * was changed on this VF. + * If set to 0, then this bit should be ignored. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ - UINT32_C(0x400) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ + UINT32_C(0x8) +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_llfc_pfc_change { + uint16_t type; /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x800) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* unused1 is 10 b */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \ + UINT32_C(0xffc0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6 + /* Identifiers of events. */ + uint16_t event_id; + /* LLFC/PFC Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \ + UINT32_C(0x34) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; /* - * The maximum transmission unit requested on the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to requesting mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint16_t mtu; + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates llfc pfc status change */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \ + 0 /* - * The guest VLAN for the function being configured. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). + * If this field set to 1, then it indicates that llfc is + * enabled. */ - uint16_t guest_vlan; + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \ + UINT32_C(0x1) /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. + * If this field is set to 2, then it indicates that pfc + * is enabled. */ - uint16_t async_event_cr; + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \ + HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC + /* Indicates the physical port this llfc pfc change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \ + UINT32_C(0x1c) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \ + 2 + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0x1fffe0) + #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 5 +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_hwrm_error { + uint16_t type; /* - * This value is the current MAC address requested by the VF - * driver to be configured on this VF. A value of - * 00-00-00-00-00-00 indicates no MAC address configuration - * is requested by the VF driver. - * The parent PF driver may reject or overwrite this - * MAC address. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - uint8_t dflt_mac_addr[6]; - uint32_t flags; + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Severity of HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 + /* Warning */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \ + UINT32_C(0x0) + /* Non-fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \ + UINT32_C(0x1) + /* Fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \ + HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL + uint8_t opaque_v; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ UINT32_C(0x1) +} __attribute__((packed)); + +/******************* + * hwrm_func_reset * + *******************/ + + +/* hwrm_func_reset_input (size:192b/24B) */ +struct hwrm_func_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ - UINT32_C(0x4) + uint16_t seq_id; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ - UINT32_C(0x8) + uint16_t target_id; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ - UINT32_C(0x10) + uint64_t resp_addr; + uint32_t enables; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This bit must be '1' for the vf_id_valid field to be + * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ - UINT32_C(0x20) + #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The ID of the VF that this PF is trying to reset. + * Only the parent PF shall be allowed to reset a child VF. + * + * A parent PF driver shall use this field only when a specific child VF + * is requested to be reset. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ - UINT32_C(0x40) + uint16_t vf_id; + /* This value indicates the level of a function reset. */ + uint8_t func_reset_level; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * Reset the caller function and its children VFs (if any). If no + * children functions exist, then reset the caller function only. */ - #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ - UINT32_C(0x80) - /* The number of RSS/COS contexts requested for the VF. */ - uint16_t num_rsscos_ctxs; - /* The number of completion rings requested for the VF. */ - uint16_t num_cmpl_rings; - /* The number of transmit rings requested for the VF. */ - uint16_t num_tx_rings; - /* The number of receive rings requested for the VF. */ - uint16_t num_rx_rings; - /* The number of L2 contexts requested for the VF. */ - uint16_t num_l2_ctxs; - /* The number of vnics requested for the VF. */ - uint16_t num_vnics; - /* The number of statistic contexts requested for the VF. */ - uint16_t num_stat_ctxs; - /* The number of HW ring groups requested for the VF. */ - uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \ + UINT32_C(0x0) + /* Reset the caller function only */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \ + UINT32_C(0x1) + /* + * Reset all children VFs of the caller function driver if the + * caller is a PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver with + * no children VFs. + */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \ + UINT32_C(0x2) + /* + * Reset a specific VF of the caller function driver if the caller + * is the parent PF driver. + * It is an error to specify this level by a VF driver. + * It is an error to specify this level by a PF driver that is not + * the parent of the VF that is being requested to reset. + */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \ + UINT32_C(0x3) + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ + HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF + uint8_t unused_0; } __attribute__((packed)); -/* hwrm_func_vf_cfg_output (size:128b/16B) */ -struct hwrm_func_vf_cfg_output { +/* hwrm_func_reset_output (size:128b/16B) */ +struct hwrm_func_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -3869,13 +4520,13 @@ struct hwrm_func_vf_cfg_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_func_qcaps * - *******************/ +/******************** + * hwrm_func_getfid * + ********************/ -/* hwrm_func_qcaps_input (size:192b/24B) */ -struct hwrm_func_qcaps_input { +/* hwrm_func_getfid_input (size:192b/24B) */ +struct hwrm_func_getfid_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -3903,17 +4554,24 @@ struct hwrm_func_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit must be '1' for the pci_id field to be + * configured. */ - uint16_t fid; - uint8_t unused_0[6]; + #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) + /* + * This value is the PCI ID of the queried function. + * If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (5b):Function Number(3b). + */ + uint16_t pci_id; + uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_func_qcaps_output (size:640b/80B) */ -struct hwrm_func_qcaps_output { +/* hwrm_func_getfid_output (size:128b/16B) */ +struct hwrm_func_getfid_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -3927,251 +4585,152 @@ struct hwrm_func_qcaps_output { * bus as belonging to a particular PCI function. */ uint16_t fid; + uint8_t unused_0[5]; /* - * Port ID of port that this function is associated with. - * Valid only for the PF. - * 0xFF... (All Fs) if this function is not associated with - * any port. - * 0xFF... (All Fs) if this function is called from a VF. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t port_id; - uint32_t flags; - /* If 1, then Push mode is supported on this function. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ - UINT32_C(0x1) + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_vf_alloc * + **********************/ + + +/* hwrm_func_vf_alloc_input (size:192b/24B) */ +struct hwrm_func_vf_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If 1, then the global MSI-X auto-masking is enabled for the - * device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * If 1, then the Precision Time Protocol (PTP) processing - * is supported on this function. - * The HWRM should enable PTP on only a single Physical - * Function (PF) per port. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ - UINT32_C(0x4) + uint16_t seq_id; /* - * If 1, then RDMA over Converged Ethernet (RoCE) v1 - * is supported on this function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ - UINT32_C(0x8) + uint16_t target_id; /* - * If 1, then RDMA over Converged Ethernet (RoCE) v2 - * is supported on this function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ - UINT32_C(0x10) + uint64_t resp_addr; + uint32_t enables; /* - * If 1, then control and configuration of WoL magic packet - * are supported on this function. + * This bit must be '1' for the first_vf_id field to be + * configured. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ - UINT32_C(0x20) + #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) /* - * If 1, then control and configuration of bitmap pattern - * packet are supported on this function. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ - UINT32_C(0x40) + uint16_t first_vf_id; + /* The number of virtual functions requested. */ + uint16_t num_vfs; +} __attribute__((packed)); + +/* hwrm_func_vf_alloc_output (size:128b/16B) */ +struct hwrm_func_vf_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The ID of the first VF allocated. */ + uint16_t first_vf_id; + uint8_t unused_0[5]; /* - * If set to 1, then the control and configuration of rate limit - * of an allocated TX ring on the queried function is supported. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ - UINT32_C(0x80) + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_func_vf_free * + *********************/ + + +/* hwrm_func_vf_free_input (size:192b/24B) */ +struct hwrm_func_vf_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If 1, then control and configuration of minimum and - * maximum bandwidths are supported on the queried function. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ - UINT32_C(0x100) + uint16_t cmpl_ring; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the rate limits - * on the TX rings of its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the rate limits - * on the TX rings of its children VFs. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ - UINT32_C(0x200) + uint16_t seq_id; /* - * If the query is for a VF, then this flag shall be ignored. - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to set the minimum and/or - * maximum bandwidths for its children VFs. - * If this query is for a PF and this flag is set to 0, then - * the PF does not have the capability to set the minimum or - * maximum bandwidths for its children VFs. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ - UINT32_C(0x400) + uint16_t target_id; /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is supported - * on the queried function. - * If set to 0, then standard TX ring mode is not available - * on the queried function. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ - UINT32_C(0x800) - /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GENEVE tunnel - * flags. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x1000) - /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect NVGRE tunnel - * flags. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x2000) - /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect GRE tunnel - * flags. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x4000) - /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to detect MPLS tunnel - * flags. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ - UINT32_C(0x8000) - /* - * If the query is for a VF, then this flag shall be ignored, - * If this query is for a PF and this flag is set to 1, - * then the PF has the capability to support pcie stats. - */ - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ - UINT32_C(0x10000) - /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. - */ - uint8_t mac_address[6]; - /* - * The maximum number of RSS/COS contexts that can be - * allocated to the function. - */ - uint16_t max_rsscos_ctx; - /* - * The maximum number of completion rings that can be - * allocated to the function. - */ - uint16_t max_cmpl_rings; - /* - * The maximum number of transmit rings that can be - * allocated to the function. - */ - uint16_t max_tx_rings; - /* - * The maximum number of receive rings that can be - * allocated to the function. - */ - uint16_t max_rx_rings; - /* - * The maximum number of L2 contexts that can be - * allocated to the function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t max_l2_ctxs; + uint64_t resp_addr; + uint32_t enables; /* - * The maximum number of VNICs that can be - * allocated to the function. + * This bit must be '1' for the first_vf_id field to be + * configured. */ - uint16_t max_vnics; + #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) /* - * The identifier for the first VF enabled on a PF. This - * is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ uint16_t first_vf_id; /* - * The maximum number of VFs that can be - * allocated to the function. This is valid only on the - * PF with SR-IOV enabled. 0xFF... (All Fs) if this - * command is called on a PF with SR-IOV disabled or - * on a VF. - */ - uint16_t max_vfs; - /* - * The maximum number of statistic contexts that can be - * allocated to the function. - */ - uint16_t max_stat_ctx; - /* - * The maximum number of Encapsulation records that can be - * offloaded by this function. - */ - uint32_t max_encap_records; - /* - * The maximum number of decapsulation records that can - * be offloaded by this function. - */ - uint32_t max_decap_records; - /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the TX side. - */ - uint32_t max_tx_em_flows; - /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the TX side. - */ - uint32_t max_tx_wm_flows; - /* - * The maximum number of Exact Match (EM) flows that can be - * offloaded by this function on the RX side. - */ - uint32_t max_rx_em_flows; - /* - * The maximum number of Wildcard Match (WM) flows that can - * be offloaded by this function on the RX side. - */ - uint32_t max_rx_wm_flows; - /* - * The maximum number of multicast filters that can - * be supported by this function on the RX side. - */ - uint32_t max_mcast_filters; - /* - * The maximum value of flow_id that can be supported - * in completion records. - */ - uint32_t max_flow_id; - /* - * The maximum number of HW ring groups that can be - * supported on this function. - */ - uint32_t max_hw_ring_grps; - /* - * The maximum number of strict priority transmit rings - * that can be allocated to the function. - * This number indicates the maximum number of TX rings - * that can be assigned strict priorities out of the - * maximum number of TX rings that can be allocated - * (max_tx_rings) to the function. + * The number of virtual functions requested. + * 0xFFFF - Cleanup all children of this PF. */ - uint16_t max_sp_tx_rings; - uint8_t unused_0; + uint16_t num_vfs; +} __attribute__((packed)); + +/* hwrm_func_vf_free_output (size:128b/16B) */ +struct hwrm_func_vf_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -4182,13 +4741,13 @@ struct hwrm_func_qcaps_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_func_qcfg * - ******************/ +/******************** + * hwrm_func_vf_cfg * + ********************/ -/* hwrm_func_qcfg_input (size:192b/24B) */ -struct hwrm_func_qcfg_input { +/* hwrm_func_vf_cfg_input (size:448b/56B) */ +struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -4216,350 +4775,225 @@ struct hwrm_func_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit must be '1' for the mtu field to be + * configured. */ - uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_func_qcfg_output (size:640b/80B) */ -struct hwrm_func_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \ + UINT32_C(0x1) /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * This bit must be '1' for the guest_vlan field to be + * configured. */ - uint16_t fid; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \ + UINT32_C(0x2) /* - * Port ID of port that this function is associated with. - * 0xFF... (All Fs) if this function is not associated with - * any port. + * This bit must be '1' for the async_event_cr field to be + * configured. */ - uint16_t port_id; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4) /* - * This value is the current VLAN setting for this - * function. The value of 0 for this field indicates - * no priority tagging or VLAN is used. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). + * This bit must be '1' for the dflt_mac_addr field to be + * configured. */ - uint16_t vlan; - uint16_t flags; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x8) /* - * If 1, then magic packet based Out-Of-Box WoL is enabled on - * the port associated with this function. + * This bit must be '1' for the num_rsscos_ctxs field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ - UINT32_C(0x1) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ + UINT32_C(0x10) /* - * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled - * on the port associated with this function. + * This bit must be '1' for the num_cmpl_rings field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ - UINT32_C(0x2) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ + UINT32_C(0x20) /* - * If set to 1, then FW based DCBX agent is enabled and running on - * the port associated with this function. - * If set to 0, then DCBX agent is not running in the firmware. + * This bit must be '1' for the num_tx_rings field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ - UINT32_C(0x4) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \ + UINT32_C(0x40) /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is enabled - * on the queried function. - * If set to 0, then the standard TX ring mode is disabled - * on the queried function. In this extended TX ring resource - * mode, the minimum and maximum bandwidth settings are not - * supported to allow the allocation of TX rings to span multiple - * scheduler nodes. + * This bit must be '1' for the num_rx_rings field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ - UINT32_C(0x8) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + UINT32_C(0x80) /* - * If set to 1 then FW based LLDP agent is enabled and running on - * the port associated with this function. - * If set to 0 then the LLDP agent is not running in the firmware. + * This bit must be '1' for the num_l2_ctxs field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ - UINT32_C(0x10) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + UINT32_C(0x100) /* - * If set to 1, then multi-host mode is active for this function. - * If set to 0, then multi-host mode is inactive for this function - * or not applicable for this device. + * This bit must be '1' for the num_vnics field to be + * configured. */ - #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ - UINT32_C(0x20) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x200) /* - * This value is current MAC address configured for this - * function. A value of 00-00-00-00-00-00 indicates no - * MAC address is currently configured. + * This bit must be '1' for the num_stat_ctxs field to be + * configured. */ - uint8_t mac_address[6]; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x400) /* - * This value is current PCI ID of this - * function. If ARI is enabled, then it is - * Bus Number (8b):Function Number(8b). Otherwise, it is - * Bus Number (8b):Device Number (4b):Function Number(4b). - * If multi-host mode is active, the 4 lsb will indicate - * the PF index for this function. + * This bit must be '1' for the num_hw_ring_grps field to be + * configured. */ - uint16_t pci_id; + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x800) /* - * The number of RSS/COS contexts currently - * allocated to the function. + * The maximum transmission unit requested on the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to requesting mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. */ - uint16_t alloc_rsscos_ctx; + uint16_t mtu; /* - * The number of completion rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * The guest VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). */ - uint16_t alloc_cmpl_rings; + uint16_t guest_vlan; /* - * The number of transmit rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. */ - uint16_t alloc_tx_rings; + uint16_t async_event_cr; /* - * The number of receive rings currently allocated to - * the function. This does not include the rings allocated - * to any children functions if any. + * This value is the current MAC address requested by the VF + * driver to be configured on this VF. A value of + * 00-00-00-00-00-00 indicates no MAC address configuration + * is requested by the VF driver. + * The parent PF driver may reject or overwrite this + * MAC address. */ - uint16_t alloc_rx_rings; - /* The allocated number of L2 contexts to the function. */ - uint16_t alloc_l2_ctx; - /* The allocated number of vnics to the function. */ - uint16_t alloc_vnics; + uint8_t dflt_mac_addr[6]; + uint32_t flags; /* - * The maximum transmission unit of the function. - * For rings allocated on this function, this default - * value is used if ring MTU is not specified. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t mtu; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x1) /* - * The maximum receive unit of the function. - * For vnics allocated on this function, this default - * value is used if vnic MRU is not specified. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t mru; - /* The statistics context assigned to a function. */ - uint16_t stat_ctx_id; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x2) /* - * The HWRM shall return Unknown value for this field - * when this command is used to query VF's configuration. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint8_t port_partition_type; - /* Single physical function */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) - /* Multiple physical functions */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) - /* Network Partitioning 1.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) - /* Network Partitioning 1.5 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) - /* Network Partitioning 2.0 */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) - /* Unknown */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x4) /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint8_t port_pf_cnt; - /* number of PFs is not available */ - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) - #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x8) /* - * The default VNIC ID assigned to a function that is - * being queried. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t dflt_vnic_id; - uint16_t max_mtu_configured; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x10) /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates the minimum bandwidth is not - * configured. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint32_t min_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x20) /* - * Maximum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - * A value of 0 indicates that the maximum bandwidth is not - * configured. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID - /* - * This value indicates the Edge virtual bridge mode for the - * domain that this function belongs to. - */ - uint8_t evb_mode; - /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) - /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) - /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA - uint8_t options; - /* - * This value indicates the PCIE device cache line size. - * The cache line size allows the DMA writes to terminate and - * start at the cache boundary. - */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ - UINT32_C(0x3) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 - /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ - UINT32_C(0x0) - /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ - UINT32_C(0x1) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 - /* Reserved for future. */ - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xfc) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2 - /* - * The number of VFs that are allocated to the function. - * This is valid only on the PF with SR-IOV enabled. - * 0xFF... (All Fs) if this command is called on a PF with - * SR-IOV disabled or on a VF. - */ - uint16_t alloc_vfs; - /* - * The number of allocated multicast filters for this - * function on the RX side. - */ - uint32_t alloc_mcast_filters; - /* - * The number of allocated HW ring groups for this - * function. - */ - uint32_t alloc_hw_ring_grps; - /* - * The number of strict priority transmit rings out of - * currently allocated TX rings to the function - * (alloc_tx_rings). - */ - uint16_t alloc_sp_tx_rings; - /* - * The number of statistics contexts - * currently reserved for the function. - */ - uint16_t alloc_stat_ctx; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x40) /* - * This field specifies how many NQs are reserved for the PF. - * Remaining NQs that belong to the PF are available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - uint16_t alloc_msix; - uint8_t unused_2[5]; + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x80) + /* The number of RSS/COS contexts requested for the VF. */ + uint16_t num_rsscos_ctxs; + /* The number of completion rings requested for the VF. */ + uint16_t num_cmpl_rings; + /* The number of transmit rings requested for the VF. */ + uint16_t num_tx_rings; + /* The number of receive rings requested for the VF. */ + uint16_t num_rx_rings; + /* The number of L2 contexts requested for the VF. */ + uint16_t num_l2_ctxs; + /* The number of vnics requested for the VF. */ + uint16_t num_vnics; + /* The number of statistic contexts requested for the VF. */ + uint16_t num_stat_ctxs; + /* The number of HW ring groups requested for the VF. */ + uint16_t num_hw_ring_grps; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_func_vf_cfg_output (size:128b/16B) */ +struct hwrm_func_vf_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -4570,13 +5004,13 @@ struct hwrm_func_qcfg_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/******************* + * hwrm_func_qcaps * + *******************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_qcaps_input (size:192b/24B) */ +struct hwrm_func_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -4605,17 +5039,16 @@ struct hwrm_func_vlan_qcfg_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ uint16_t fid; uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_qcaps_output (size:640b/80B) */ +struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -4624,153 +5057,256 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint8_t valid; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + uint16_t fid; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * Port ID of port that this function is associated with. + * Valid only for the PF. + * 0xFF... (All Fs) if this function is not associated with + * any port. + * 0xFF... (All Fs) if this function is called from a VF. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint16_t port_id; + uint32_t flags; + /* If 1, then Push mode is supported on this function. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \ + UINT32_C(0x1) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * If 1, then the global MSI-X auto-masking is enabled for the + * device. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint32_t unused_3; -} __attribute__((packed)); - -/********************** - * hwrm_func_vlan_cfg * - **********************/ - - -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \ + UINT32_C(0x2) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * If 1, then the Precision Time Protocol (PTP) processing + * is supported on this function. + * The HWRM should enable PTP on only a single Physical + * Function (PF) per port. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \ + UINT32_C(0x4) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If 1, then RDMA over Converged Ethernet (RoCE) v1 + * is supported on this function. */ - uint16_t seq_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \ + UINT32_C(0x8) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * If 1, then RDMA over Converged Ethernet (RoCE) v2 + * is supported on this function. */ - uint16_t target_id; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \ + UINT32_C(0x10) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If 1, then control and configuration of WoL magic packet + * are supported on this function. */ - uint64_t resp_addr; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \ + UINT32_C(0x20) /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. + * If 1, then control and configuration of bitmap pattern + * packet are supported on this function. */ - uint16_t fid; - uint8_t unused_0[2]; - uint32_t enables; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \ + UINT32_C(0x40) /* - * This bit must be '1' for the stag_vid field to be - * configured. + * If set to 1, then the control and configuration of rate limit + * of an allocated TX ring on the queried function is supported. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \ + UINT32_C(0x80) /* - * This bit must be '1' for the ctag_vid field to be - * configured. + * If 1, then control and configuration of minimum and + * maximum bandwidths are supported on the queried function. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \ + UINT32_C(0x100) /* - * This bit must be '1' for the stag_pcp field to be - * configured. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the rate limits + * on the TX rings of its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the rate limits + * on the TX rings of its children VFs. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \ + UINT32_C(0x200) /* - * This bit must be '1' for the ctag_pcp field to be - * configured. + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to set the minimum and/or + * maximum bandwidths for its children VFs. + * If this query is for a PF and this flag is set to 0, then + * the PF does not have the capability to set the minimum or + * maximum bandwidths for its children VFs. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \ + UINT32_C(0x400) /* - * This bit must be '1' for the stag_tpid field to be - * configured. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is supported + * on the queried function. + * If set to 0, then standard TX ring mode is not available + * on the queried function. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \ + UINT32_C(0x800) /* - * This bit must be '1' for the ctag_tpid field to be - * configured. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GENEVE tunnel + * flags. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x1000) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect NVGRE tunnel + * flags. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x2000) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect GRE tunnel + * flags. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; -} __attribute__((packed)); - -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x4000) + /* + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to detect MPLS tunnel + * flags. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \ + UINT32_C(0x8000) + /* + * If the query is for a VF, then this flag shall be ignored, + * If this query is for a PF and this flag is set to 1, + * then the PF has the capability to support pcie stats. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \ + UINT32_C(0x10000) + /* + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. + */ + uint8_t mac_address[6]; + /* + * The maximum number of RSS/COS contexts that can be + * allocated to the function. + */ + uint16_t max_rsscos_ctx; + /* + * The maximum number of completion rings that can be + * allocated to the function. + */ + uint16_t max_cmpl_rings; + /* + * The maximum number of transmit rings that can be + * allocated to the function. + */ + uint16_t max_tx_rings; + /* + * The maximum number of receive rings that can be + * allocated to the function. + */ + uint16_t max_rx_rings; + /* + * The maximum number of L2 contexts that can be + * allocated to the function. + */ + uint16_t max_l2_ctxs; + /* + * The maximum number of VNICs that can be + * allocated to the function. + */ + uint16_t max_vnics; + /* + * The identifier for the first VF enabled on a PF. This + * is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t first_vf_id; + /* + * The maximum number of VFs that can be + * allocated to the function. This is valid only on the + * PF with SR-IOV enabled. 0xFF... (All Fs) if this + * command is called on a PF with SR-IOV disabled or + * on a VF. + */ + uint16_t max_vfs; + /* + * The maximum number of statistic contexts that can be + * allocated to the function. + */ + uint16_t max_stat_ctx; + /* + * The maximum number of Encapsulation records that can be + * offloaded by this function. + */ + uint32_t max_encap_records; + /* + * The maximum number of decapsulation records that can + * be offloaded by this function. + */ + uint32_t max_decap_records; + /* + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the TX side. + */ + uint32_t max_tx_em_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the TX side. + */ + uint32_t max_tx_wm_flows; + /* + * The maximum number of Exact Match (EM) flows that can be + * offloaded by this function on the RX side. + */ + uint32_t max_rx_em_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can + * be offloaded by this function on the RX side. + */ + uint32_t max_rx_wm_flows; + /* + * The maximum number of multicast filters that can + * be supported by this function on the RX side. + */ + uint32_t max_mcast_filters; + /* + * The maximum value of flow_id that can be supported + * in completion records. + */ + uint32_t max_flow_id; + /* + * The maximum number of HW ring groups that can be + * supported on this function. + */ + uint32_t max_hw_ring_grps; + /* + * The maximum number of strict priority transmit rings + * that can be allocated to the function. + * This number indicates the maximum number of TX rings + * that can be assigned strict priorities out of the + * maximum number of TX rings that can be allocated + * (max_tx_rings) to the function. + */ + uint16_t max_sp_tx_rings; + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -4781,13 +5317,13 @@ struct hwrm_func_vlan_cfg_output { uint8_t valid; } __attribute__((packed)); -/***************** - * hwrm_func_cfg * - *****************/ +/****************** + * hwrm_func_qcfg * + ******************/ -/* hwrm_func_cfg_input (size:704b/88B) */ -struct hwrm_func_cfg_input { +/* hwrm_func_qcfg_input (size:192b/24B) */ +struct hwrm_func_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -4816,546 +5352,349 @@ struct hwrm_func_cfg_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the the configuration is - * for the requesting function. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ uint16_t fid; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_func_qcfg_output (size:640b/80B) */ +struct hwrm_func_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This field specifies how many NQs will be reserved for the PF. - * Remaining NQs that belong to the PF become available for VFs. - * Once a PF has created VFs, it cannot change how many NQs are - * reserved for itself (since the NQs must be contiguous in HW). + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. */ - uint16_t num_msix; - uint32_t flags; + uint16_t fid; /* - * When this bit is '1', the function is disabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to disallow - * transmission of frames with the source MAC address that - * is configured for this function. + * Port ID of port that this function is associated with. + * 0xFF... (All Fs) if this function is not associated with + * any port. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ + uint16_t port_id; + /* + * This value is the current VLAN setting for this + * function. The value of 0 for this field indicates + * no priority tagging or VLAN is used. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). + */ + uint16_t vlan; + uint16_t flags; + /* + * If 1, then magic packet based Out-Of-Box WoL is enabled on + * the port associated with this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \ UINT32_C(0x1) /* - * When this bit is '1', the function is enabled with - * source MAC address check. - * This is an anti-spoofing check. If this flag is set, - * then the function shall be configured to allow - * transmission of frames with the source MAC address that - * is configured for this function. + * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled + * on the port associated with this function. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ - UINT32_C(0x1fc) - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 /* - * Standard TX Ring mode is used for the allocation of TX ring - * and underlying scheduling resources that allow bandwidth - * reservation and limit settings on the queried function. - * If set to 1, then standard TX ring mode is requested to be - * enabled on the function being configured. + * If set to 1, then FW based DCBX agent is enabled and running on + * the port associated with this function. + * If set to 0, then DCBX agent is not running in the firmware. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ - UINT32_C(0x200) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \ + UINT32_C(0x4) /* * Standard TX Ring mode is used for the allocation of TX ring * and underlying scheduling resources that allow bandwidth * reservation and limit settings on the queried function. - * If set to 1, then the standard TX ring mode is requested to - * be disabled on the function being configured. In this extended - * TX ring resource mode, the minimum and maximum bandwidth settings - * are not supported to allow the allocation of TX rings to - * span multiple scheduler nodes. + * If set to 1, then standard TX ring mode is enabled + * on the queried function. + * If set to 0, then the standard TX ring mode is disabled + * on the queried function. In this extended TX ring resource + * mode, the minimum and maximum bandwidth settings are not + * supported to allow the allocation of TX rings to span multiple + * scheduler nodes. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ - UINT32_C(0x400) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \ + UINT32_C(0x8) /* - * If this bit is set, virtual mac address configured - * in this command will be persistent over warm boot. + * If set to 1 then FW based LLDP agent is enabled and running on + * the port associated with this function. + * If set to 0 then the LLDP agent is not running in the firmware. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ - UINT32_C(0x800) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \ + UINT32_C(0x10) /* - * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * If set to 1, then multi-host mode is active for this function. + * If set to 0, then multi-host mode is inactive for this function + * or not applicable for this device. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ - UINT32_C(0x1000) + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ + UINT32_C(0x20) /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of TX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is current MAC address configured for this + * function. A value of 00-00-00-00-00-00 indicates no + * MAC address is currently configured. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ - UINT32_C(0x2000) + uint8_t mac_address[6]; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RX rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * This value is current PCI ID of this + * function. If ARI is enabled, then it is + * Bus Number (8b):Function Number(8b). Otherwise, it is + * Bus Number (8b):Device Number (4b):Function Number(4b). + * If multi-host mode is active, the 4 lsb will indicate + * the PF index for this function. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ - UINT32_C(0x4000) + uint16_t pci_id; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The number of RSS/COS contexts currently + * allocated to the function. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ - UINT32_C(0x8000) + uint16_t alloc_rsscos_ctx; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of RSS ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The number of completion rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ - UINT32_C(0x10000) + uint16_t alloc_cmpl_rings; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The number of transmit rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ - UINT32_C(0x20000) + uint16_t alloc_tx_rings; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of stat ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The number of receive rings currently allocated to + * the function. This does not include the rings allocated + * to any children functions if any. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ - UINT32_C(0x40000) + uint16_t alloc_rx_rings; + /* The allocated number of L2 contexts to the function. */ + uint16_t alloc_l2_ctx; + /* The allocated number of vnics to the function. */ + uint16_t alloc_vnics; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of VNICs) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The maximum transmission unit of the function. + * For rings allocated on this function, this default + * value is used if ring MTU is not specified. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ - UINT32_C(0x80000) + uint16_t mtu; /* - * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of L2 ctx) are available. - * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they - * are available. + * The maximum receive unit of the function. + * For vnics allocated on this function, this default + * value is used if vnic MRU is not specified. */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ - UINT32_C(0x100000) - uint32_t enables; + uint16_t mru; + /* The statistics context assigned to a function. */ + uint16_t stat_ctx_id; /* - * This bit must be '1' for the mtu field to be - * configured. + * The HWRM shall return Unknown value for this field + * when this command is used to query VF's configuration. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ - UINT32_C(0x1) + uint8_t port_partition_type; + /* Single physical function */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) + /* Multiple physical functions */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) + /* Network Partitioning 1.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) + /* Network Partitioning 1.5 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) + /* Network Partitioning 2.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Unknown */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN /* - * This bit must be '1' for the mru field to be - * configured. + * This field will indicate number of physical functions on this port_partition. + * HWRM shall return unavail (i.e. value of 0) for this field + * when this command is used to query VF's configuration or + * from older firmware that doesn't support this field. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ - UINT32_C(0x2) + uint8_t port_pf_cnt; + /* number of PFs is not available */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL /* - * This bit must be '1' for the num_rsscos_ctxs field to be - * configured. + * The default VNIC ID assigned to a function that is + * being queried. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ - UINT32_C(0x4) + uint16_t dflt_vnic_id; + uint16_t max_mtu_configured; /* - * This bit must be '1' for the num_cmpl_rings field to be + * Minimum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. + * A value of 0 indicates the minimum bandwidth is not * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ - UINT32_C(0x8) - /* - * This bit must be '1' for the num_tx_rings field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ - UINT32_C(0x10) - /* - * This bit must be '1' for the num_rx_rings field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ - UINT32_C(0x20) - /* - * This bit must be '1' for the num_l2_ctxs field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ - UINT32_C(0x40) - /* - * This bit must be '1' for the num_vnics field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ - UINT32_C(0x80) - /* - * This bit must be '1' for the num_stat_ctxs field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ - UINT32_C(0x100) - /* - * This bit must be '1' for the dflt_mac_addr field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ - UINT32_C(0x200) - /* - * This bit must be '1' for the dflt_vlan field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ - UINT32_C(0x400) - /* - * This bit must be '1' for the dflt_ip_addr field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ - UINT32_C(0x800) - /* - * This bit must be '1' for the min_bw field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the max_bw field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the async_event_cr field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the vlan_antispoof_mode field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the allowed_vlan_pris field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the evb_mode field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the num_mcast_filters field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ - UINT32_C(0x40000) - /* - * This bit must be '1' for the num_hw_ring_grps field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ - UINT32_C(0x80000) - /* - * This bit must be '1' for the cache_linesize field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ - UINT32_C(0x100000) - /* - * This bit must be '1' for the num_msix field to be - * configured. - */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ - UINT32_C(0x200000) - /* - * The maximum transmission unit of the function. - * The HWRM should make sure that the mtu of - * the function does not exceed the mtu of the physical - * port that this function is associated with. - * - * In addition to configuring mtu per function, it is - * possible to configure mtu per transmit ring. - * By default, the mtu of each transmit ring associated - * with a function is equal to the mtu of the function. - * The HWRM should make sure that the mtu of each transmit - * ring that is assigned to a function has a valid mtu. - */ - uint16_t mtu; - /* - * The maximum receive unit of the function. - * The HWRM should make sure that the mru of - * the function does not exceed the mru of the physical - * port that this function is associated with. - * - * In addition to configuring mru per function, it is - * possible to configure mru per vnic. - * By default, the mru of each vnic associated - * with a function is equal to the mru of the function. - * The HWRM should make sure that the mru of each vnic - * that is assigned to a function has a valid mru. - */ - uint16_t mru; - /* - * The number of RSS/COS contexts requested for the - * function. - */ - uint16_t num_rsscos_ctxs; - /* - * The number of completion rings requested for the - * function. This does not include the rings allocated - * to any children functions if any. - */ - uint16_t num_cmpl_rings; - /* - * The number of transmit rings requested for the function. - * This does not include the rings allocated to any - * children functions if any. - */ - uint16_t num_tx_rings; - /* - * The number of receive rings requested for the function. - * This does not include the rings allocated - * to any children functions if any. - */ - uint16_t num_rx_rings; - /* The requested number of L2 contexts for the function. */ - uint16_t num_l2_ctxs; - /* The requested number of vnics for the function. */ - uint16_t num_vnics; - /* The requested number of statistic contexts for the function. */ - uint16_t num_stat_ctxs; - /* - * The number of HW ring groups that should - * be reserved for this function. - */ - uint16_t num_hw_ring_grps; - /* The default MAC address for the function being configured. */ - uint8_t dflt_mac_addr[6]; - /* - * The default VLAN for the function being configured. - * This field's format is same as 802.1Q Tag's - * Tag Control Information (TCI) format that includes both - * Priority Code Point (PCP) and VLAN Identifier (VID). - */ - uint16_t dflt_vlan; - /* - * The default IP address for the function being configured. - * This address is only used in enabling source property check. - */ - uint32_t dflt_ip_addr[4]; - /* - * Minimum BW allocated for this function. - * The HWRM will translate this value into byte counter and - * time interval used for the scheduler inside the device. - */ uint32_t min_bw; /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* * Maximum BW allocated for this function. * The HWRM will translate this value into byte counter and * time interval used for the scheduler inside the device. + * A value of 0 indicates that the maximum bandwidth is not + * configured. */ uint32_t max_bw; /* The bandwidth value. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \ UINT32_C(0xfffffff) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0 /* The granularity of the value (bits or bytes). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \ UINT32_C(0x10000000) /* Value is in bits. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \ (UINT32_C(0x0) << 28) /* Value is in bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \ (UINT32_C(0x1) << 28) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES /* bw_value_unit is 3 b */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \ UINT32_C(0xe0000000) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 /* Value is in Mb or MB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ (UINT32_C(0x0) << 29) /* Value is in Kb or KB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \ (UINT32_C(0x2) << 29) /* Value is in bits or bytes. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \ (UINT32_C(0x4) << 29) /* Value is in Gb or GB (base 10). */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ (UINT32_C(0x6) << 29) /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ (UINT32_C(0x1) << 29) /* Invalid unit */ - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ (UINT32_C(0x7) << 29) - #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID - /* - * ID of the target completion ring for receiving asynchronous - * event completions. If this field is not valid, then the - * HWRM shall use the default completion ring of the function - * that is being configured as the target completion ring for - * providing any asynchronous event completions for that - * function. - * If this field is valid, then the HWRM shall use the - * completion ring identified by this ID as the target - * completion ring for providing any asynchronous event - * completions for the function that is being configured. - */ - uint16_t async_event_cr; - /* VLAN Anti-spoofing mode. */ - uint8_t vlan_antispoof_mode; - /* No VLAN anti-spoofing checks are enabled */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ - UINT32_C(0x0) - /* Validate VLAN against the configured VLAN(s) */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ - UINT32_C(0x1) - /* Insert VLAN if it does not exist, otherwise discard */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ - UINT32_C(0x2) - /* Insert VLAN if it does not exist, override VLAN if it exists */ - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ - UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN - /* - * This bit field defines VLAN PRIs that are allowed on - * this function. - * If nth bit is set, then VLAN PRI n is allowed on this - * function. - */ - uint8_t allowed_vlan_pris; + #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID /* - * The HWRM shall allow a PF driver to change EVB mode for the - * partition it belongs to. - * The HWRM shall not allow a VF driver to change the EVB mode. - * The HWRM shall take into account the switching of EVB mode - * from one to another and reconfigure hardware resources as - * appropriately. - * The switching from VEB to VEPA mode requires - * the disabling of the loopback traffic. Additionally, - * source knock outs are handled differently in VEB and VEPA - * modes. + * This value indicates the Edge virtual bridge mode for the + * domain that this function belongs to. */ uint8_t evb_mode; /* No Edge Virtual Bridging (EVB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) /* Virtual Ethernet Bridge (VEB) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) /* Virtual Ethernet Port Aggregator (VEPA) */ - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) - #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ - HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA uint8_t options; /* * This value indicates the PCIE device cache line size. * The cache line size allows the DMA writes to terminate and * start at the cache boundary. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 /* Cache Line Size 64 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ UINT32_C(0x0) /* Cache Line Size 128 bytes */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ UINT32_C(0x1) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ - HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 /* Reserved for future. */ - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ UINT32_C(0xfc) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2 /* - * The number of multicast filters that should - * be reserved for this function on the RX side. + * The number of VFs that are allocated to the function. + * This is valid only on the PF with SR-IOV enabled. + * 0xFF... (All Fs) if this command is called on a PF with + * SR-IOV disabled or on a VF. */ - uint16_t num_mcast_filters; -} __attribute__((packed)); - -/* hwrm_func_cfg_output (size:128b/16B) */ -struct hwrm_func_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t alloc_vfs; + /* + * The number of allocated multicast filters for this + * function on the RX side. + */ + uint32_t alloc_mcast_filters; + /* + * The number of allocated HW ring groups for this + * function. + */ + uint32_t alloc_hw_ring_grps; + /* + * The number of strict priority transmit rings out of + * currently allocated TX rings to the function + * (alloc_tx_rings). + */ + uint16_t alloc_sp_tx_rings; + /* + * The number of statistics contexts + * currently reserved for the function. + */ + uint16_t alloc_stat_ctx; + /* + * This field specifies how many NQs are reserved for the PF. + * Remaining NQs that belong to the PF are available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). + */ + uint16_t alloc_msix; + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -5366,13 +5705,13 @@ struct hwrm_func_cfg_output { uint8_t valid; } __attribute__((packed)); -/******************** - * hwrm_func_qstats * - ********************/ +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ -/* hwrm_func_qstats_input (size:192b/24B) */ -struct hwrm_func_qstats_input { +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -5401,16 +5740,17 @@ struct hwrm_func_qstats_input { */ uint64_t resp_addr; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. */ uint16_t fid; uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_qstats_output (size:1408b/176B) */ -struct hwrm_func_qstats_output { +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -5419,67 +5759,6 @@ struct hwrm_func_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast packets on the function. */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets on the function. */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets on the function. */ - uint64_t tx_bcast_pkts; - /* - * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this - * can only happen if TMP is configured to allow dropping - * in HOL blocking conditions, which is not a normal - * configuration. - */ - uint64_t tx_discard_pkts; - /* - * Number of dropped packets on transmit path on the function. - * These are packets that have been marked for drop by - * the TE CFA block or are packets that exceeded the - * transmit MTU limit for the function. - */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic on the function. */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic on the function. */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic on the function. */ - uint64_t tx_bcast_bytes; - /* Number of received unicast packets on the function. */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets on the function. */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets on the function. */ - uint64_t rx_bcast_pkts; - /* - * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. - * # The BD used for the packet has a bad format. - * # There were no BDs available in the ring for the packet. - * # There were no BDs available on-chip for the packet. - */ - uint64_t rx_discard_pkts; - /* - * Number of dropped packets on received path on the function. - * These are packets that have been marked for drop by the - * RE CFA. - */ - uint64_t rx_drop_pkts; - /* Number of received bytes for unicast traffic on the function. */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic on the function. */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic on the function. */ - uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets on the function. */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes on the function. */ - uint64_t rx_agg_bytes; - /* Number of aggregation events on the function. */ - uint64_t rx_agg_events; - /* Number of aborted aggregations on the function. */ - uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -5489,15 +5768,40 @@ struct hwrm_func_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint32_t unused_3; } __attribute__((packed)); -/*********************** - * hwrm_func_clr_stats * - ***********************/ +/********************** + * hwrm_func_vlan_cfg * + **********************/ -/* hwrm_func_clr_stats_input (size:192b/24B) */ -struct hwrm_func_clr_stats_input { +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -5526,79 +5830,73 @@ struct hwrm_func_clr_stats_input { */ uint64_t resp_addr; /* - * Function ID of the function. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. */ uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_func_clr_stats_output (size:128b/16B) */ -struct hwrm_func_clr_stats_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t unused_0[2]; + uint32_t enables; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the stag_vid field to be + * configured. */ - uint8_t valid; -} __attribute__((packed)); - -/************************** - * hwrm_func_vf_resc_free * - **************************/ - - -/* hwrm_func_vf_resc_free_input (size:192b/24B) */ -struct hwrm_func_vf_resc_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the ctag_vid field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the stag_pcp field to be + * configured. */ - uint16_t seq_id; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This bit must be '1' for the ctag_pcp field to be + * configured. */ - uint16_t target_id; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the stag_tpid field to be + * configured. */ - uint64_t resp_addr; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This bit must be '1' for the ctag_tpid field to be + * configured. */ - uint16_t vf_id; - uint8_t unused_0[6]; + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; } __attribute__((packed)); -/* hwrm_func_vf_resc_free_output (size:128b/16B) */ -struct hwrm_func_vf_resc_free_output { +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -5618,13 +5916,13 @@ struct hwrm_func_vf_resc_free_output { uint8_t valid; } __attribute__((packed)); -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/***************** + * hwrm_func_cfg * + *****************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_cfg_input (size:704b/88B) */ +struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -5653,552 +5951,537 @@ struct hwrm_func_vf_vnic_ids_query_input { */ uint64_t resp_addr; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. - */ - uint16_t vf_id; - uint8_t unused_0[2]; - /* Max number of vnic ids in vnic id table */ - uint32_t max_vnic_id_cnt; - /* This is the address for VF VNIC ID table */ - uint64_t vnic_id_tbl_addr; -} __attribute__((packed)); - -/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ -struct hwrm_func_vf_vnic_ids_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Actual number of vnic ids - * - * Each VNIC ID is written as a 32-bit number. + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the the configuration is + * for the requesting function. */ - uint32_t vnic_id_cnt; - uint8_t unused_0[3]; + uint16_t fid; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field specifies how many NQs will be reserved for the PF. + * Remaining NQs that belong to the PF become available for VFs. + * Once a PF has created VFs, it cannot change how many NQs are + * reserved for itself (since the NQs must be contiguous in HW). */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_func_drv_rgtr * - **********************/ - - -/* hwrm_func_drv_rgtr_input (size:896b/112B) */ -struct hwrm_func_drv_rgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t num_msix; + uint32_t flags; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * When this bit is '1', the function is disabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to disallow + * transmission of frames with the source MAC address that + * is configured for this function. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \ + UINT32_C(0x1) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * When this bit is '1', the function is enabled with + * source MAC address check. + * This is an anti-spoofing check. If this flag is set, + * then the function shall be configured to allow + * transmission of frames with the source MAC address that + * is configured for this function. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \ + UINT32_C(0x1fc) + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2 /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then standard TX ring mode is requested to be + * enabled on the function being configured. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \ + UINT32_C(0x200) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Standard TX Ring mode is used for the allocation of TX ring + * and underlying scheduling resources that allow bandwidth + * reservation and limit settings on the queried function. + * If set to 1, then the standard TX ring mode is requested to + * be disabled on the function being configured. In this extended + * TX ring resource mode, the minimum and maximum bandwidth settings + * are not supported to allow the allocation of TX rings to + * span multiple scheduler nodes. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \ + UINT32_C(0x400) /* - * When this bit is '1', the function driver is requesting - * all requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * If this bit is set, virtual mac address configured + * in this command will be persistent over warm boot. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \ + UINT32_C(0x800) /* - * When this bit is '1', the function is requesting none of - * the requests from its children VF drivers to be - * forwarded to itself. - * This flag can only be set by the PF driver. - * If a VF driver sets this flag, it should be ignored - * by the HWRM. + * This bit only applies to the VF. If this bit is set, the statistic + * context counters will not be cleared when the statistic context is freed + * or a function reset is called on VF. This bit will be cleared when the PF + * is unloaded or a function reset is called on the PF. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \ + UINT32_C(0x1000) /* - * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be ignored and ver_maj, ver_min, ver_upd - * and ver_patch shall be used for the driver version information. - * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b - * fields shall be used for the driver version information and - * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of TX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4) - uint32_t enables; + #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ + UINT32_C(0x2000) /* - * This bit must be '1' for the os_type field to be + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RX rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ + UINT32_C(0x4000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of CMPL rings) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ + UINT32_C(0x8000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of RSS ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ + UINT32_C(0x10000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of ring groups) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ + UINT32_C(0x20000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of stat ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ + UINT32_C(0x40000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of VNICs) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ + UINT32_C(0x80000) + /* + * This bit requests that the firmware test to see if all the assets + * requested in this command (i.e. number of L2 ctx) are available. + * The firmware will return an error if the requested assets are + * not available. The firwmare will NOT reserve the assets if they + * are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ + UINT32_C(0x100000) + uint32_t enables; + /* + * This bit must be '1' for the mtu field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \ UINT32_C(0x1) /* - * This bit must be '1' for the ver field to be + * This bit must be '1' for the mru field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \ UINT32_C(0x2) /* - * This bit must be '1' for the timestamp field to be + * This bit must be '1' for the num_rsscos_ctxs field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \ UINT32_C(0x4) /* - * This bit must be '1' for the vf_req_fwd field to be + * This bit must be '1' for the num_cmpl_rings field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \ UINT32_C(0x8) /* - * This bit must be '1' for the async_event_fwd field to be + * This bit must be '1' for the num_tx_rings field to be * configured. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \ UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ - uint16_t os_type; - /* Unknown */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) - /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) - /* MSDOS OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) - /* Windows OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) - /* Solaris OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) - /* Linux OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) - /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) - /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) - /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) - /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) - /* UEFI driver. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI - /* This is the 8bit major version of the driver. */ - uint8_t ver_maj_8b; - /* This is the 8bit minor version of the driver. */ - uint8_t ver_min_8b; - /* This is the 8bit update version of the driver. */ - uint8_t ver_upd_8b; - uint8_t unused_0[3]; /* - * This is a 32-bit timestamp provided by the driver for - * keep alive. - * The timestamp is in multiples of 1ms. + * This bit must be '1' for the num_rx_rings field to be + * configured. */ - uint32_t timestamp; - uint8_t unused_1[4]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \ + UINT32_C(0x20) /* - * This is a 256-bit bit mask provided by the PF driver for - * letting the HWRM know what commands issued by the VF driver - * to the HWRM should be forwarded to the PF driver. - * Nth bit refers to the Nth req_type. - * - * Setting Nth bit to 1 indicates that requests from the - * VF driver with req_type equal to N shall be forwarded to - * the parent PF driver. - * - * This field is not valid for the VF driver. + * This bit must be '1' for the num_l2_ctxs field to be + * configured. */ - uint32_t vf_req_fwd[8]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \ + UINT32_C(0x40) /* - * This is a 256-bit bit mask provided by the function driver - * (PF or VF driver) to indicate the list of asynchronous event - * completions to be forwarded. - * - * Nth bit refers to the Nth event_id. - * - * Setting Nth bit to 1 by the function driver shall result in - * the HWRM forwarding asynchronous event completion with - * event_id equal to N. - * - * If all bits are set to 0 (value of 0), then the HWRM shall - * not forward any asynchronous event completion to this - * function driver. + * This bit must be '1' for the num_vnics field to be + * configured. */ - uint32_t async_event_fwd[8]; - /* This is the 16bit major version of the driver. */ - uint16_t ver_maj; - /* This is the 16bit minor version of the driver. */ - uint16_t ver_min; - /* This is the 16bit update version of the driver. */ - uint16_t ver_upd; - /* This is the 16bit patch version of the driver. */ - uint16_t ver_patch; -} __attribute__((packed)); - -/* hwrm_func_drv_rgtr_output (size:128b/16B) */ -struct hwrm_func_drv_rgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \ + UINT32_C(0x80) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the num_stat_ctxs field to be + * configured. */ - uint8_t valid; -} __attribute__((packed)); - -/************************ - * hwrm_func_drv_unrgtr * - ************************/ - - -/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ -struct hwrm_func_drv_unrgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \ + UINT32_C(0x100) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the dflt_mac_addr field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \ + UINT32_C(0x200) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the dflt_vlan field to be + * configured. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \ + UINT32_C(0x400) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This bit must be '1' for the dflt_ip_addr field to be + * configured. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \ + UINT32_C(0x800) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the min_bw field to be + * configured. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \ + UINT32_C(0x1000) /* - * When this bit is '1', the function driver is notifying - * the HWRM to prepare for the shutdown. + * This bit must be '1' for the max_bw field to be + * configured. */ - #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ - UINT32_C(0x1) - uint8_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ -struct hwrm_func_drv_unrgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_func_buf_rgtr * - **********************/ - - -/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ -struct hwrm_func_buf_rgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \ + UINT32_C(0x2000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the async_event_cr field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \ + UINT32_C(0x4000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the vlan_antispoof_mode field to be + * configured. */ - uint16_t seq_id; + #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \ + UINT32_C(0x8000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This bit must be '1' for the allowed_vlan_pris field to be + * configured. */ - uint16_t target_id; + #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \ + UINT32_C(0x10000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the evb_mode field to be + * configured. */ - uint64_t resp_addr; - uint32_t enables; + #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \ + UINT32_C(0x20000) /* - * This bit must be '1' for the vf_id field to be + * This bit must be '1' for the num_mcast_filters field to be * configured. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \ + UINT32_C(0x40000) /* - * This bit must be '1' for the err_buf_addr field to be + * This bit must be '1' for the num_hw_ring_grps field to be * configured. */ - #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ + UINT32_C(0x80000) /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * This bit must be '1' for the cache_linesize field to be + * configured. */ - uint16_t vf_id; + #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \ + UINT32_C(0x100000) /* - * This field represents the number of pages used for request - * buffer(s). + * This bit must be '1' for the num_msix field to be + * configured. */ - uint16_t req_buf_num_pages; + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ + UINT32_C(0x200000) /* - * This field represents the page size used for request - * buffer(s). + * The maximum transmission unit of the function. + * The HWRM should make sure that the mtu of + * the function does not exceed the mtu of the physical + * port that this function is associated with. + * + * In addition to configuring mtu per function, it is + * possible to configure mtu per transmit ring. + * By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. + * The HWRM should make sure that the mtu of each transmit + * ring that is assigned to a function has a valid mtu. */ - uint16_t req_buf_page_size; - /* 16 bytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) - /* 4 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) - /* 8 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) - /* 64 Kbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) - /* 2 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) - /* 4 Mbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) - /* 1 Gbytes */ - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) - #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ - HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G - /* The length of the request buffer per VF in bytes. */ - uint16_t req_buf_len; - /* The length of the response buffer in bytes. */ - uint16_t resp_buf_len; - uint8_t unused_0[2]; - /* This field represents the page address of page #0. */ - uint64_t req_buf_page_addr0; - /* This field represents the page address of page #1. */ - uint64_t req_buf_page_addr1; - /* This field represents the page address of page #2. */ - uint64_t req_buf_page_addr2; - /* This field represents the page address of page #3. */ - uint64_t req_buf_page_addr3; - /* This field represents the page address of page #4. */ - uint64_t req_buf_page_addr4; - /* This field represents the page address of page #5. */ - uint64_t req_buf_page_addr5; - /* This field represents the page address of page #6. */ - uint64_t req_buf_page_addr6; - /* This field represents the page address of page #7. */ - uint64_t req_buf_page_addr7; - /* This field represents the page address of page #8. */ - uint64_t req_buf_page_addr8; - /* This field represents the page address of page #9. */ - uint64_t req_buf_page_addr9; + uint16_t mtu; /* - * This field is used to receive the error reporting from - * the chipset. Only applicable for PFs. + * The maximum receive unit of the function. + * The HWRM should make sure that the mru of + * the function does not exceed the mru of the physical + * port that this function is associated with. + * + * In addition to configuring mru per function, it is + * possible to configure mru per vnic. + * By default, the mru of each vnic associated + * with a function is equal to the mru of the function. + * The HWRM should make sure that the mru of each vnic + * that is assigned to a function has a valid mru. */ - uint64_t error_buf_addr; + uint16_t mru; /* - * This field is used to receive the response forwarded by the - * HWRM. + * The number of RSS/COS contexts requested for the + * function. */ - uint64_t resp_buf_addr; -} __attribute__((packed)); - -/* hwrm_func_buf_rgtr_output (size:128b/16B) */ -struct hwrm_func_buf_rgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t num_rsscos_ctxs; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * The number of completion rings requested for the + * function. This does not include the rings allocated + * to any children functions if any. */ - uint8_t valid; -} __attribute__((packed)); - -/************************ - * hwrm_func_buf_unrgtr * - ************************/ - - -/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ -struct hwrm_func_buf_unrgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t num_cmpl_rings; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The number of transmit rings requested for the function. + * This does not include the rings allocated to any + * children functions if any. */ - uint16_t cmpl_ring; + uint16_t num_tx_rings; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The number of receive rings requested for the function. + * This does not include the rings allocated + * to any children functions if any. */ - uint16_t seq_id; + uint16_t num_rx_rings; + /* The requested number of L2 contexts for the function. */ + uint16_t num_l2_ctxs; + /* The requested number of vnics for the function. */ + uint16_t num_vnics; + /* The requested number of statistic contexts for the function. */ + uint16_t num_stat_ctxs; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * The number of HW ring groups that should + * be reserved for this function. */ - uint16_t target_id; + uint16_t num_hw_ring_grps; + /* The default MAC address for the function being configured. */ + uint8_t dflt_mac_addr[6]; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The default VLAN for the function being configured. + * This field's format is same as 802.1Q Tag's + * Tag Control Information (TCI) format that includes both + * Priority Code Point (PCP) and VLAN Identifier (VID). */ - uint64_t resp_addr; - uint32_t enables; + uint16_t dflt_vlan; /* - * This bit must be '1' for the vf_id field to be - * configured. + * The default IP address for the function being configured. + * This address is only used in enabling source property check. */ - #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + uint32_t dflt_ip_addr[4]; /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. + * Minimum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. */ - uint16_t vf_id; - uint8_t unused_0[2]; -} __attribute__((packed)); - -/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ -struct hwrm_func_buf_unrgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t min_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Maximum BW allocated for this function. + * The HWRM will translate this value into byte counter and + * time interval used for the scheduler inside the device. */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_func_drv_qver * - **********************/ - - -/* hwrm_func_drv_qver_input (size:192b/24B) */ -struct hwrm_func_drv_qver_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * ID of the target completion ring for receiving asynchronous + * event completions. If this field is not valid, then the + * HWRM shall use the default completion ring of the function + * that is being configured as the target completion ring for + * providing any asynchronous event completions for that + * function. + * If this field is valid, then the HWRM shall use the + * completion ring identified by this ID as the target + * completion ring for providing any asynchronous event + * completions for the function that is being configured. */ - uint16_t cmpl_ring; + uint16_t async_event_cr; + /* VLAN Anti-spoofing mode. */ + uint8_t vlan_antispoof_mode; + /* No VLAN anti-spoofing checks are enabled */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \ + UINT32_C(0x0) + /* Validate VLAN against the configured VLAN(s) */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \ + UINT32_C(0x1) + /* Insert VLAN if it does not exist, otherwise discard */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \ + UINT32_C(0x2) + /* Insert VLAN if it does not exist, override VLAN if it exists */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit field defines VLAN PRIs that are allowed on + * this function. + * If nth bit is set, then VLAN PRI n is allowed on this + * function. */ - uint16_t seq_id; + uint8_t allowed_vlan_pris; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * The HWRM shall allow a PF driver to change EVB mode for the + * partition it belongs to. + * The HWRM shall not allow a VF driver to change the EVB mode. + * The HWRM shall take into account the switching of EVB mode + * from one to another and reconfigure hardware resources as + * appropriately. + * The switching from VEB to VEPA mode requires + * the disabling of the loopback traffic. Additionally, + * source knock outs are handled differently in VEB and VEPA + * modes. */ - uint16_t target_id; + uint8_t evb_mode; + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA + uint8_t options; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value indicates the PCIE device cache line size. + * The cache line size allows the DMA writes to terminate and + * start at the cache boundary. */ - uint64_t resp_addr; - /* Reserved for future use. */ - uint32_t reserved; + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ + UINT32_C(0x3) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + /* Cache Line Size 64 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ + UINT32_C(0x0) + /* Cache Line Size 128 bytes */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \ + UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* Reserved for future. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ + UINT32_C(0xfc) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2 /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * The number of multicast filters that should + * be reserved for this function on the RX side. */ - uint16_t fid; - uint8_t unused_0[2]; + uint16_t num_mcast_filters; } __attribute__((packed)); -/* hwrm_func_drv_qver_output (size:192b/24B) */ -struct hwrm_func_drv_qver_output { +/* hwrm_func_cfg_output (size:128b/16B) */ +struct hwrm_func_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -6207,39 +6490,7 @@ struct hwrm_func_drv_qver_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ - uint16_t os_type; - /* Unknown */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) - /* Other OS not listed below. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) - /* MSDOS OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) - /* Windows OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) - /* Solaris OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) - /* Linux OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) - /* FreeBSD OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) - /* VMware ESXi OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) - /* Microsoft Windows 8 64-bit OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) - /* Microsoft Windows Server 2012 R2 OS. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) - /* UEFI driver. */ - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) - #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ - HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI - /* This is the 8bit major version of the driver. */ - uint8_t ver_maj_8b; - /* This is the 8bit minor version of the driver. */ - uint8_t ver_min_8b; - /* This is the 8bit update version of the driver. */ - uint8_t ver_upd_8b; - uint8_t unused_0[2]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -6248,23 +6499,15 @@ struct hwrm_func_drv_qver_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; - /* This is the 16bit major version of the driver. */ - uint16_t ver_maj; - /* This is the 16bit minor version of the driver. */ - uint16_t ver_min; - /* This is the 16bit update version of the driver. */ - uint16_t ver_upd; - /* This is the 16bit patch version of the driver. */ - uint16_t ver_patch; } __attribute__((packed)); -/**************************** - * hwrm_func_resource_qcaps * - ****************************/ +/******************** + * hwrm_func_qstats * + ********************/ -/* hwrm_func_resource_qcaps_input (size:192b/24B) */ -struct hwrm_func_resource_qcaps_input { +/* hwrm_func_qstats_input (size:192b/24B) */ +struct hwrm_func_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -6301,8 +6544,8 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ -struct hwrm_func_resource_qcaps_output { +/* hwrm_func_qstats_output (size:1408b/176B) */ +struct hwrm_func_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -6311,63 +6554,67 @@ struct hwrm_func_resource_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ - uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ - uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ - uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ - UINT32_C(0x0) - /* The PF driver should only reserve minimal resources for each VF. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ - UINT32_C(0x1) + /* Number of transmitted unicast packets on the function. */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets on the function. */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets on the function. */ + uint64_t tx_bcast_pkts; /* - * The PF driver should not reserve any resources for each VF until the - * the VF interface is brought up. + * Number of transmitted packets that were discarded due to + * internal NIC resource problems. For transmit, this + * can only happen if TMP is configured to allow dropping + * in HOL blocking conditions, which is not a normal + * configuration. */ - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ - UINT32_C(0x2) - #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ - HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ - uint16_t min_rsscos_ctx; - /* Maximum non-guaranteed number of RSS/COS contexts */ - uint16_t max_rsscos_ctx; - /* Minimum guaranteed number of completion rings */ - uint16_t min_cmpl_rings; - /* Maximum non-guaranteed number of completion rings */ - uint16_t max_cmpl_rings; - /* Minimum guaranteed number of transmit rings */ - uint16_t min_tx_rings; - /* Maximum non-guaranteed number of transmit rings */ - uint16_t max_tx_rings; - /* Minimum guaranteed number of receive rings */ - uint16_t min_rx_rings; - /* Maximum non-guaranteed number of receive rings */ - uint16_t max_rx_rings; - /* Minimum guaranteed number of L2 contexts */ - uint16_t min_l2_ctxs; - /* Maximum non-guaranteed number of L2 contexts */ - uint16_t max_l2_ctxs; - /* Minimum guaranteed number of VNICs */ - uint16_t min_vnics; - /* Maximum non-guaranteed number of VNICs */ - uint16_t max_vnics; - /* Minimum guaranteed number of statistic contexts */ - uint16_t min_stat_ctx; - /* Maximum non-guaranteed number of statistic contexts */ - uint16_t max_stat_ctx; - /* Minimum guaranteed number of ring groups */ - uint16_t min_hw_ring_grps; - /* Maximum non-guaranteed number of ring groups */ - uint16_t max_hw_ring_grps; + uint64_t tx_discard_pkts; /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. + * Number of dropped packets on transmit path on the function. + * These are packets that have been marked for drop by + * the TE CFA block or are packets that exceeded the + * transmit MTU limit for the function. */ - uint16_t max_tx_scheduler_inputs; + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic on the function. */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic on the function. */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic on the function. */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets on the function. */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets on the function. */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets on the function. */ + uint64_t rx_bcast_pkts; + /* + * Number of received packets that were discarded on the function + * due to resource limitations. This can happen for 3 reasons. + * # The BD used for the packet has a bad format. + * # There were no BDs available in the ring for the packet. + * # There were no BDs available on-chip for the packet. + */ + uint64_t rx_discard_pkts; + /* + * Number of dropped packets on received path on the function. + * These are packets that have been marked for drop by the + * RE CFA. + */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic on the function. */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic on the function. */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic on the function. */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets on the function. */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes on the function. */ + uint64_t rx_agg_bytes; + /* Number of aggregation events on the function. */ + uint64_t rx_agg_events; + /* Number of aborted aggregations on the function. */ + uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -6379,13 +6626,13 @@ struct hwrm_func_resource_qcaps_output { uint8_t valid; } __attribute__((packed)); -/***************************** - * hwrm_func_vf_resource_cfg * - *****************************/ +/*********************** + * hwrm_func_clr_stats * + ***********************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ -struct hwrm_func_vf_resource_cfg_input { +/* hwrm_func_clr_stats_input (size:192b/24B) */ +struct hwrm_func_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -6413,47 +6660,17 @@ struct hwrm_func_vf_resource_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VF ID that is being configured by PF */ - uint16_t vf_id; - /* Maximum guaranteed number of MSI-X vectors for the function */ - uint16_t max_msix; - /* Minimum guaranteed number of RSS/COS contexts */ - uint16_t min_rsscos_ctx; - /* Maximum non-guaranteed number of RSS/COS contexts */ - uint16_t max_rsscos_ctx; - /* Minimum guaranteed number of completion rings */ - uint16_t min_cmpl_rings; - /* Maximum non-guaranteed number of completion rings */ - uint16_t max_cmpl_rings; - /* Minimum guaranteed number of transmit rings */ - uint16_t min_tx_rings; - /* Maximum non-guaranteed number of transmit rings */ - uint16_t max_tx_rings; - /* Minimum guaranteed number of receive rings */ - uint16_t min_rx_rings; - /* Maximum non-guaranteed number of receive rings */ - uint16_t max_rx_rings; - /* Minimum guaranteed number of L2 contexts */ - uint16_t min_l2_ctxs; - /* Maximum non-guaranteed number of L2 contexts */ - uint16_t max_l2_ctxs; - /* Minimum guaranteed number of VNICs */ - uint16_t min_vnics; - /* Maximum non-guaranteed number of VNICs */ - uint16_t max_vnics; - /* Minimum guaranteed number of statistic contexts */ - uint16_t min_stat_ctx; - /* Maximum non-guaranteed number of statistic contexts */ - uint16_t max_stat_ctx; - /* Minimum guaranteed number of ring groups */ - uint16_t min_hw_ring_grps; - /* Maximum non-guaranteed number of ring groups */ - uint16_t max_hw_ring_grps; - uint8_t unused_0[4]; + /* + * Function ID of the function. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ -struct hwrm_func_vf_resource_cfg_output { +/* hwrm_func_clr_stats_output (size:128b/16B) */ +struct hwrm_func_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -6462,22 +6679,6 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Reserved number of RSS/COS contexts */ - uint16_t reserved_rsscos_ctx; - /* Reserved number of completion rings */ - uint16_t reserved_cmpl_rings; - /* Reserved number of transmit rings */ - uint16_t reserved_tx_rings; - /* Reserved number of receive rings */ - uint16_t reserved_rx_rings; - /* Reserved number of L2 contexts */ - uint16_t reserved_l2_ctxs; - /* Reserved number of VNICs */ - uint16_t reserved_vnics; - /* Reserved number of statistic contexts */ - uint16_t reserved_stat_ctx; - /* Reserved number of ring groups */ - uint16_t reserved_hw_ring_grps; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -6489,13 +6690,13 @@ struct hwrm_func_vf_resource_cfg_output { uint8_t valid; } __attribute__((packed)); -/********************************* - * hwrm_func_backing_store_qcaps * - *********************************/ +/************************** + * hwrm_func_vf_resc_free * + **************************/ -/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcaps_input { +/* hwrm_func_vf_resc_free_input (size:192b/24B) */ +struct hwrm_func_vf_resc_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -6523,10 +6724,16 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_backing_store_qcaps_output (size:512b/64B) */ -struct hwrm_func_backing_store_qcaps_output { +/* hwrm_func_vf_resc_free_output (size:128b/16B) */ +struct hwrm_func_vf_resc_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -6535,53 +6742,7 @@ struct hwrm_func_backing_store_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum number of QP context entries supported for this function. */ - uint32_t qp_max_entries; - /* - * Minimum number of QP context entries that are needed to be reserved - * for QP1 for the PF and its VFs. PF drivers must allocate at least - * this many QP context entries, even if RoCE will not be used. - */ - uint16_t qp_min_qp1_entries; - /* Maximum number of QP context entries that can be used for L2. */ - uint16_t qp_max_l2_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t qp_entry_size; - /* Maximum number of SRQ context entries that can be used for L2. */ - uint16_t srq_max_l2_entries; - /* Maximum number of SRQ context entries supported for this function. */ - uint32_t srq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t srq_entry_size; - /* Maximum number of CQ context entries that can be used for L2. */ - uint16_t cq_max_l2_entries; - /* Maximum number of CQ context entries supported for this function. */ - uint32_t cq_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t cq_entry_size; - /* Maximum number of VNIC context entries supported for this function. */ - uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ - uint16_t vnic_max_ring_table_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ - uint32_t stat_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t stat_entry_size; - /* Maximum number of TQM context entries supported per ring. */ - uint16_t tqm_max_entries_per_ring; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tqm_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t mrav_entry_size; - /* Maximum number of MR/AV context entries supported for this function. */ - uint32_t mrav_max_entries; - /* Maximum number of Timer context entries supported for this function. */ - uint32_t tim_max_entries; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t tim_entry_size; - uint8_t unused_0; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -6593,12 +6754,12 @@ struct hwrm_func_backing_store_qcaps_output { } __attribute__((packed)); /******************************* - * hwrm_func_backing_store_cfg * + * hwrm_func_vf_vnic_ids_query * *******************************/ -/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ -struct hwrm_func_backing_store_cfg_input { +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -6626,862 +6787,5077 @@ struct hwrm_func_backing_store_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When set, the firmware only uses on-chip resources and does not - * expect any backing store to be provided by the host driver. This - * mode provides minimal L2 functionality (e.g. limited L2 resources, - * no RoCE). + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ - UINT32_C(0x1) - uint32_t enables; + uint16_t vf_id; + uint8_t unused_0[2]; + /* Max number of vnic ids in vnic id table */ + uint32_t max_vnic_id_cnt; + /* This is the address for VF VNIC ID table */ + uint64_t vnic_id_tbl_addr; +} __attribute__((packed)); + +/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ +struct hwrm_func_vf_vnic_ids_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This bit must be '1' for the qp fields to be - * configured. + * Actual number of vnic ids + * + * Each VNIC ID is written as a 32-bit number. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ - UINT32_C(0x1) + uint32_t vnic_id_cnt; + uint8_t unused_0[3]; /* - * This bit must be '1' for the srq fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ - UINT32_C(0x2) + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_drv_rgtr * + **********************/ + + +/* hwrm_func_drv_rgtr_input (size:896b/112B) */ +struct hwrm_func_drv_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the cq fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ - UINT32_C(0x4) + uint16_t cmpl_ring; /* - * This bit must be '1' for the vnic fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ - UINT32_C(0x8) + uint16_t seq_id; /* - * This bit must be '1' for the stat fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ - UINT32_C(0x10) + uint16_t target_id; /* - * This bit must be '1' for the tqm_sp fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ - UINT32_C(0x20) + uint64_t resp_addr; + uint32_t flags; /* - * This bit must be '1' for the tqm_ring0 fields to be - * configured. + * When this bit is '1', the function driver is requesting + * all requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ - UINT32_C(0x40) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1) /* - * This bit must be '1' for the tqm_ring1 fields to be - * configured. + * When this bit is '1', the function is requesting none of + * the requests from its children VF drivers to be + * forwarded to itself. + * This flag can only be set by the PF driver. + * If a VF driver sets this flag, it should be ignored + * by the HWRM. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ - UINT32_C(0x80) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2) /* - * This bit must be '1' for the tqm_ring2 fields to be - * configured. + * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be ignored and ver_maj, ver_min, ver_upd + * and ver_patch shall be used for the driver version information. + * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b + * fields shall be used for the driver version information and + * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ - UINT32_C(0x100) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4) + uint32_t enables; /* - * This bit must be '1' for the tqm_ring3 fields to be + * This bit must be '1' for the os_type field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ - UINT32_C(0x200) + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \ + UINT32_C(0x1) /* - * This bit must be '1' for the tqm_ring4 fields to be + * This bit must be '1' for the ver field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ - UINT32_C(0x400) + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \ + UINT32_C(0x2) /* - * This bit must be '1' for the tqm_ring5 fields to be + * This bit must be '1' for the timestamp field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ - UINT32_C(0x800) + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \ + UINT32_C(0x4) /* - * This bit must be '1' for the tqm_ring6 fields to be + * This bit must be '1' for the vf_req_fwd field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ - UINT32_C(0x1000) + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \ + UINT32_C(0x8) /* - * This bit must be '1' for the tqm_ring7 fields to be + * This bit must be '1' for the async_event_fwd field to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ - UINT32_C(0x2000) + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \ + UINT32_C(0x10) + /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + uint16_t os_type; + /* Unknown */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + /* UEFI driver. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI + /* This is the 8bit major version of the driver. */ + uint8_t ver_maj_8b; + /* This is the 8bit minor version of the driver. */ + uint8_t ver_min_8b; + /* This is the 8bit update version of the driver. */ + uint8_t ver_upd_8b; + uint8_t unused_0[3]; /* - * This bit must be '1' for the mrav fields to be - * configured. + * This is a 32-bit timestamp provided by the driver for + * keep alive. + * The timestamp is in multiples of 1ms. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ - UINT32_C(0x4000) + uint32_t timestamp; + uint8_t unused_1[4]; /* - * This bit must be '1' for the tim fields to be - * configured. + * This is a 256-bit bit mask provided by the PF driver for + * letting the HWRM know what commands issued by the VF driver + * to the HWRM should be forwarded to the PF driver. + * Nth bit refers to the Nth req_type. + * + * Setting Nth bit to 1 indicates that requests from the + * VF driver with req_type equal to N shall be forwarded to + * the parent PF driver. + * + * This field is not valid for the VF driver. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ - UINT32_C(0x8000) - /* QPC page size and level. */ - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 - /* QPC page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G - /* SRQ page size and level. */ - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G - /* CQ page size and level. */ - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 - /* CQ page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G - /* VNIC page size and level. */ - uint8_t vnic_pg_size_vnic_lvl; - /* VNIC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 - /* VNIC page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G - /* Stat page size and level. */ - uint8_t stat_pg_size_stat_lvl; - /* Stat PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \ + uint32_t vf_req_fwd[8]; + /* + * This is a 256-bit bit mask provided by the function driver + * (PF or VF driver) to indicate the list of asynchronous event + * completions to be forwarded. + * + * Nth bit refers to the Nth event_id. + * + * Setting Nth bit to 1 by the function driver shall result in + * the HWRM forwarding asynchronous event completion with + * event_id equal to N. + * + * If all bits are set to 0 (value of 0), then the HWRM shall + * not forward any asynchronous event completion to this + * function driver. + */ + uint32_t async_event_fwd[8]; + /* This is the 16bit major version of the driver. */ + uint16_t ver_maj; + /* This is the 16bit minor version of the driver. */ + uint16_t ver_min; + /* This is the 16bit update version of the driver. */ + uint16_t ver_upd; + /* This is the 16bit patch version of the driver. */ + uint16_t ver_patch; +} __attribute__((packed)); + +/* hwrm_func_drv_rgtr_output (size:128b/16B) */ +struct hwrm_func_drv_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_func_drv_unrgtr * + ************************/ + + +/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ +struct hwrm_func_drv_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the function driver is notifying + * the HWRM to prepare for the shutdown. + */ + #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 - /* Stat page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G - /* TQM slow path page size and level. */ - uint8_t tqm_sp_pg_size_tqm_sp_lvl; - /* TQM slow path PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \ + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ +struct hwrm_func_drv_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_buf_rgtr * + **********************/ + + +/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ +struct hwrm_func_buf_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id field to be + * configured. + */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + /* + * This bit must be '1' for the err_buf_addr field to be + * configured. + */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + /* + * This field represents the number of pages used for request + * buffer(s). + */ + uint16_t req_buf_num_pages; + /* + * This field represents the page size used for request + * buffer(s). + */ + uint16_t req_buf_page_size; + /* 16 bytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) + /* 4 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) + /* 8 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) + /* 64 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) + /* 2 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) + /* 4 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) + /* 1 Gbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \ + HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G + /* The length of the request buffer per VF in bytes. */ + uint16_t req_buf_len; + /* The length of the response buffer in bytes. */ + uint16_t resp_buf_len; + uint8_t unused_0[2]; + /* This field represents the page address of page #0. */ + uint64_t req_buf_page_addr0; + /* This field represents the page address of page #1. */ + uint64_t req_buf_page_addr1; + /* This field represents the page address of page #2. */ + uint64_t req_buf_page_addr2; + /* This field represents the page address of page #3. */ + uint64_t req_buf_page_addr3; + /* This field represents the page address of page #4. */ + uint64_t req_buf_page_addr4; + /* This field represents the page address of page #5. */ + uint64_t req_buf_page_addr5; + /* This field represents the page address of page #6. */ + uint64_t req_buf_page_addr6; + /* This field represents the page address of page #7. */ + uint64_t req_buf_page_addr7; + /* This field represents the page address of page #8. */ + uint64_t req_buf_page_addr8; + /* This field represents the page address of page #9. */ + uint64_t req_buf_page_addr9; + /* + * This field is used to receive the error reporting from + * the chipset. Only applicable for PFs. + */ + uint64_t error_buf_addr; + /* + * This field is used to receive the response forwarded by the + * HWRM. + */ + uint64_t resp_buf_addr; +} __attribute__((packed)); + +/* hwrm_func_buf_rgtr_output (size:128b/16B) */ +struct hwrm_func_buf_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_func_buf_unrgtr * + ************************/ + + +/* hwrm_func_buf_unrgtr_input (size:192b/24B) */ +struct hwrm_func_buf_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id field to be + * configured. + */ + #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[2]; +} __attribute__((packed)); + +/* hwrm_func_buf_unrgtr_output (size:128b/16B) */ +struct hwrm_func_buf_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_drv_qver * + **********************/ + + +/* hwrm_func_drv_qver_input (size:192b/24B) */ +struct hwrm_func_drv_qver_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Reserved for future use. */ + uint32_t reserved; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[2]; +} __attribute__((packed)); + +/* hwrm_func_drv_qver_output (size:192b/24B) */ +struct hwrm_func_drv_qver_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + uint16_t os_type; + /* Unknown */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + /* UEFI driver. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000) + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \ + HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI + /* This is the 8bit major version of the driver. */ + uint8_t ver_maj_8b; + /* This is the 8bit minor version of the driver. */ + uint8_t ver_min_8b; + /* This is the 8bit update version of the driver. */ + uint8_t ver_upd_8b; + uint8_t unused_0[2]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; + /* This is the 16bit major version of the driver. */ + uint16_t ver_maj; + /* This is the 16bit minor version of the driver. */ + uint16_t ver_min; + /* This is the 16bit update version of the driver. */ + uint16_t ver_upd; + /* This is the 16bit patch version of the driver. */ + uint16_t ver_patch; +} __attribute__((packed)); + +/**************************** + * hwrm_func_resource_qcaps * + ****************************/ + + +/* hwrm_func_resource_qcaps_input (size:192b/24B) */ +struct hwrm_func_resource_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +struct hwrm_func_resource_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + uint16_t max_vfs; + /* Maximum guaranteed number of MSI-X vectors supported by function */ + uint16_t max_msix; + /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + uint16_t vf_reservation_strategy; + /* The PF driver should evenly divide its remaining resources among all VFs. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \ + UINT32_C(0x0) + /* The PF driver should only reserve minimal resources for each VF. */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \ + UINT32_C(0x1) + /* + * The PF driver should not reserve any resources for each VF until the + * the VF interface is brought up. + */ + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \ + UINT32_C(0x2) + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \ + HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; + /* + * Maximum number of inputs into the transmit scheduler for this function. + * The number of TX rings assigned to the function cannot exceed this value. + */ + uint16_t max_tx_scheduler_inputs; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/***************************** + * hwrm_func_vf_resource_cfg * + *****************************/ + + +/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +struct hwrm_func_vf_resource_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VF ID that is being configured by PF */ + uint16_t vf_id; + /* Maximum guaranteed number of MSI-X vectors for the function */ + uint16_t max_msix; + /* Minimum guaranteed number of RSS/COS contexts */ + uint16_t min_rsscos_ctx; + /* Maximum non-guaranteed number of RSS/COS contexts */ + uint16_t max_rsscos_ctx; + /* Minimum guaranteed number of completion rings */ + uint16_t min_cmpl_rings; + /* Maximum non-guaranteed number of completion rings */ + uint16_t max_cmpl_rings; + /* Minimum guaranteed number of transmit rings */ + uint16_t min_tx_rings; + /* Maximum non-guaranteed number of transmit rings */ + uint16_t max_tx_rings; + /* Minimum guaranteed number of receive rings */ + uint16_t min_rx_rings; + /* Maximum non-guaranteed number of receive rings */ + uint16_t max_rx_rings; + /* Minimum guaranteed number of L2 contexts */ + uint16_t min_l2_ctxs; + /* Maximum non-guaranteed number of L2 contexts */ + uint16_t max_l2_ctxs; + /* Minimum guaranteed number of VNICs */ + uint16_t min_vnics; + /* Maximum non-guaranteed number of VNICs */ + uint16_t max_vnics; + /* Minimum guaranteed number of statistic contexts */ + uint16_t min_stat_ctx; + /* Maximum non-guaranteed number of statistic contexts */ + uint16_t max_stat_ctx; + /* Minimum guaranteed number of ring groups */ + uint16_t min_hw_ring_grps; + /* Maximum non-guaranteed number of ring groups */ + uint16_t max_hw_ring_grps; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ +struct hwrm_func_vf_resource_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved number of RSS/COS contexts */ + uint16_t reserved_rsscos_ctx; + /* Reserved number of completion rings */ + uint16_t reserved_cmpl_rings; + /* Reserved number of transmit rings */ + uint16_t reserved_tx_rings; + /* Reserved number of receive rings */ + uint16_t reserved_rx_rings; + /* Reserved number of L2 contexts */ + uint16_t reserved_l2_ctxs; + /* Reserved number of VNICs */ + uint16_t reserved_vnics; + /* Reserved number of statistic contexts */ + uint16_t reserved_stat_ctx; + /* Reserved number of ring groups */ + uint16_t reserved_hw_ring_grps; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************************* + * hwrm_func_backing_store_qcaps * + *********************************/ + + +/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ +struct hwrm_func_backing_store_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_func_backing_store_qcaps_output (size:512b/64B) */ +struct hwrm_func_backing_store_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Maximum number of QP context entries supported for this function. */ + uint32_t qp_max_entries; + /* + * Minimum number of QP context entries that are needed to be reserved + * for QP1 for the PF and its VFs. PF drivers must allocate at least + * this many QP context entries, even if RoCE will not be used. + */ + uint16_t qp_min_qp1_entries; + /* Maximum number of QP context entries that can be used for L2. */ + uint16_t qp_max_l2_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t qp_entry_size; + /* Maximum number of SRQ context entries that can be used for L2. */ + uint16_t srq_max_l2_entries; + /* Maximum number of SRQ context entries supported for this function. */ + uint32_t srq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t srq_entry_size; + /* Maximum number of CQ context entries that can be used for L2. */ + uint16_t cq_max_l2_entries; + /* Maximum number of CQ context entries supported for this function. */ + uint32_t cq_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t cq_entry_size; + /* Maximum number of VNIC context entries supported for this function. */ + uint16_t vnic_max_vnic_entries; + /* Maximum number of Ring table context entries supported for this function. */ + uint16_t vnic_max_ring_table_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t vnic_entry_size; + /* Maximum number of statistic context entries supported for this function. */ + uint32_t stat_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t stat_entry_size; + /* Maximum number of TQM context entries supported per ring. */ + uint16_t tqm_max_entries_per_ring; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tqm_entry_size; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t mrav_entry_size; + /* Maximum number of MR/AV context entries supported for this function. */ + uint32_t mrav_max_entries; + /* Maximum number of Timer context entries supported for this function. */ + uint32_t tim_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t tim_entry_size; + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************* + * hwrm_func_backing_store_cfg * + *******************************/ + + +/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ +struct hwrm_func_backing_store_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and does not + * expect any backing store to be provided by the host driver. This + * mode provides minimal L2 functionality (e.g. limited L2 resources, + * no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the qp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the srq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vnic fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \ + UINT32_C(0x8) + /* + * This bit must be '1' for the stat fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \ + UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_sp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \ + UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \ + UINT32_C(0x80) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \ + UINT32_C(0x100) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \ + UINT32_C(0x400) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \ + UINT32_C(0x800) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the mrav fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the tim fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \ + UINT32_C(0x8000) + /* QPC page size and level. */ + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 + /* QPC page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G + /* SRQ page size and level. */ + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G + /* CQ page size and level. */ + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 + /* CQ page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G + /* VNIC page size and level. */ + uint8_t vnic_pg_size_vnic_lvl; + /* VNIC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 + /* VNIC page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G + /* Stat page size and level. */ + uint8_t stat_pg_size_stat_lvl; + /* Stat PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 + /* Stat page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G + /* TQM slow path page size and level. */ + uint8_t tqm_sp_pg_size_tqm_sp_lvl; + /* TQM slow path PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 + /* TQM slow path page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* MR/AV page size and level. */ + uint8_t mrav_pg_size_mrav_lvl; + /* MR/AV PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 + /* MR/AV page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G + /* Timer page size and level. */ + uint8_t tim_pg_size_tim_lvl; + /* Timer PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 + /* Timer page size. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G + /* QP page directory. */ + uint64_t qpc_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* VNIC page directory. */ + uint64_t vnic_page_dir; + /* Stat page directory. */ + uint64_t stat_page_dir; + /* TQM slowpath page directory. */ + uint64_t tqm_sp_page_dir; + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* MR/AV page directory. */ + uint64_t mrav_page_dir; + /* Timer page directory. */ + uint64_t tim_page_dir; + /* Number of QPs. */ + uint32_t qp_num_entries; + /* Number of SRQs. */ + uint32_t srq_num_entries; + /* Number of CQs. */ + uint32_t cq_num_entries; + /* Number of Stats. */ + uint32_t stat_num_entries; + /* Number of TQM slowpath entries. */ + uint32_t tqm_sp_num_entries; + /* Number of TQM ring 0 entries. */ + uint32_t tqm_ring0_num_entries; + /* Number of TQM ring 1 entries. */ + uint32_t tqm_ring1_num_entries; + /* Number of TQM ring 2 entries. */ + uint32_t tqm_ring2_num_entries; + /* Number of TQM ring 3 entries. */ + uint32_t tqm_ring3_num_entries; + /* Number of TQM ring 4 entries. */ + uint32_t tqm_ring4_num_entries; + /* Number of TQM ring 5 entries. */ + uint32_t tqm_ring5_num_entries; + /* Number of TQM ring 6 entries. */ + uint32_t tqm_ring6_num_entries; + /* Number of TQM ring 7 entries. */ + uint32_t tqm_ring7_num_entries; + /* Number of MR/AV entries. */ + uint32_t mrav_num_entries; + /* Number of Timer entries. */ + uint32_t tim_num_entries; + /* Number of entries to reserve for QP1 */ + uint16_t qp_num_qp1_entries; + /* Number of entries to reserve for L2 */ + uint16_t qp_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t qp_entry_size; + /* Number of entries to reserve for L2 */ + uint16_t srq_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t srq_entry_size; + /* Number of entries to reserve for L2 */ + uint16_t cq_num_l2_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t cq_entry_size; + /* Number of entries to reserve for VNIC entries */ + uint16_t vnic_num_vnic_entries; + /* Number of entries to reserve for Ring table entries */ + uint16_t vnic_num_ring_table_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t vnic_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t stat_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t mrav_entry_size; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tim_entry_size; +} __attribute__((packed)); + +/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ +struct hwrm_func_backing_store_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************** + * hwrm_func_backing_store_qcfg * + ********************************/ + + +/* hwrm_func_backing_store_qcfg_input (size:128b/16B) */ +struct hwrm_func_backing_store_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ +struct hwrm_func_backing_store_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When set, the firmware only uses on-chip resources and does not + * expect any backing store to be provided by the host driver. This + * mode provides minimal L2 functionality (e.g. limited L2 resources, + * no RoCE). + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \ + UINT32_C(0x1) + uint8_t unused_0[4]; + /* + * This bit must be '1' for the qp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \ + UINT32_C(0x1) + /* + * This bit must be '1' for the srq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cq fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vnic fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \ + UINT32_C(0x8) + /* + * This bit must be '1' for the stat fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \ + UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_sp fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \ + UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \ + UINT32_C(0x80) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \ + UINT32_C(0x100) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \ + UINT32_C(0x400) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \ + UINT32_C(0x800) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the mrav fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the tim fields to be + * configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \ + UINT32_C(0x8000) + /* QPC page size and level. */ + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 + /* QPC page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G + /* SRQ page size and level. */ + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G + /* CQ page size and level. */ + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 + /* CQ page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G + /* VNIC page size and level. */ + uint8_t vnic_pg_size_vnic_lvl; + /* VNIC PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 + /* VNIC page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G + /* Stat page size and level. */ + uint8_t stat_pg_size_stat_lvl; + /* Stat PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 + /* Stat page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G + /* TQM slow path page size and level. */ + uint8_t tqm_sp_pg_size_tqm_sp_lvl; + /* TQM slow path PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 + /* TQM slow path page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0 + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G + /* MR/AV page size and level. */ + uint8_t mrav_pg_size_mrav_lvl; + /* MR/AV PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 + /* MR/AV page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G + /* Timer page size and level. */ + uint8_t tim_pg_size_tim_lvl; + /* Timer PBL indirect levels. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ + UINT32_C(0xf) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ + UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 + /* Timer page size. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ + UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ + HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G + /* QP page directory. */ + uint64_t qpc_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* VNIC page directory. */ + uint64_t vnic_page_dir; + /* Stat page directory. */ + uint64_t stat_page_dir; + /* TQM slowpath page directory. */ + uint64_t tqm_sp_page_dir; + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* MR/AV page directory. */ + uint64_t mrav_page_dir; + /* Timer page directory. */ + uint64_t tim_page_dir; + /* Number of entries to reserve for QP1 */ + uint16_t qp_num_qp1_entries; + /* Number of entries to reserve for L2 */ + uint16_t qp_num_l2_entries; + /* Number of QPs. */ + uint32_t qp_num_entries; + /* Number of SRQs. */ + uint32_t srq_num_entries; + /* Number of entries to reserve for L2 */ + uint16_t srq_num_l2_entries; + /* Number of entries to reserve for L2 */ + uint16_t cq_num_l2_entries; + /* Number of CQs. */ + uint32_t cq_num_entries; + /* Number of entries to reserve for VNIC entries */ + uint16_t vnic_num_vnic_entries; + /* Number of entries to reserve for Ring table entries */ + uint16_t vnic_num_ring_table_entries; + /* Number of Stats. */ + uint32_t stat_num_entries; + /* Number of TQM slowpath entries. */ + uint32_t tqm_sp_num_entries; + /* Number of TQM ring 0 entries. */ + uint32_t tqm_ring0_num_entries; + /* Number of TQM ring 1 entries. */ + uint32_t tqm_ring1_num_entries; + /* Number of TQM ring 2 entries. */ + uint32_t tqm_ring2_num_entries; + /* Number of TQM ring 3 entries. */ + uint32_t tqm_ring3_num_entries; + /* Number of TQM ring 4 entries. */ + uint32_t tqm_ring4_num_entries; + /* Number of TQM ring 5 entries. */ + uint32_t tqm_ring5_num_entries; + /* Number of TQM ring 6 entries. */ + uint32_t tqm_ring6_num_entries; + /* Number of TQM ring 7 entries. */ + uint32_t tqm_ring7_num_entries; + /* Number of MR/AV entries. */ + uint32_t mrav_num_entries; + /* Number of Timer entries. */ + uint32_t tim_num_entries; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_port_phy_cfg * + *********************/ + + +/* hwrm_port_phy_cfg_input (size:448b/56B) */ +struct hwrm_port_phy_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is set to '1', the PHY for the port shall + * be reset. + * + * # If this bit is set to 1, then the HWRM shall reset the + * PHY after applying PHY configuration changes specified + * in this command. + * # In order to guarantee that PHY configuration changes + * specified in this command take effect, the HWRM + * client should set this flag to 1. + * # If this bit is not set to 1, then the HWRM may reset + * the PHY depending on the current PHY configuration and + * settings specified in this command. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \ + UINT32_C(0x1) + /* deprecated bit. Do not use!!! */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ + UINT32_C(0x2) + /* + * When this bit is set to '1', the link shall be forced to + * the force_link_speed value. + * + * When this bit is set to '1', the HWRM client should + * not enable any of the auto negotiation related + * fields represented by auto_XXX fields in this command. + * When this bit is set to '1' and the HWRM client has + * enabled a auto_XXX field in this command, then the + * HWRM shall ignore the enabled auto_XXX field. + * + * When this bit is set to zero, the link + * shall be allowed to autoneg. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \ + UINT32_C(0x4) + /* + * When this bit is set to '1', the auto-negotiation process + * shall be restarted on the link. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \ + UINT32_C(0x8) + /* + * When this bit is set to '1', Energy Efficient Ethernet + * (EEE) is requested to be enabled on this link. + * If EEE is not supported on this port, then this flag + * shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \ + UINT32_C(0x10) + /* + * When this bit is set to '1', Energy Efficient Ethernet + * (EEE) is requested to be disabled on this link. + * If EEE is not supported on this port, then this flag + * shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \ + UINT32_C(0x20) + /* + * When this bit is set to '1' and EEE is enabled on this + * link, then TX LPI is requested to be enabled on the link. + * If EEE is not supported on this port, then this flag + * shall be ignored by the HWRM. + * If EEE is disabled on this port, then this flag shall be + * ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \ + UINT32_C(0x40) + /* + * When this bit is set to '1' and EEE is enabled on this + * link, then TX LPI is requested to be disabled on the link. + * If EEE is not supported on this port, then this flag + * shall be ignored by the HWRM. + * If EEE is disabled on this port, then this flag shall be + * ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \ + UINT32_C(0x80) + /* + * When set to 1, then the HWRM shall enable FEC autonegotitation + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC autonegotiation is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \ + UINT32_C(0x100) + /* + * When set to 1, then the HWRM shall disable FEC autonegotiation + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC autonegotiation is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \ + UINT32_C(0x200) + /* + * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \ + UINT32_C(0x400) + /* + * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \ + UINT32_C(0x800) + /* + * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon) + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \ + UINT32_C(0x1000) + /* + * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon) + * on this port if supported. + * When set to 0, then this flag shall be ignored. + * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this + * flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \ + UINT32_C(0x2000) + /* + * When this bit is set to '1', the link shall be forced to + * be taken down. + * + * # When this bit is set to '1", all other + * command input settings related to the link speed shall + * be ignored. + * Once the link state is forced down, it can be + * explicitly cleared from that state by setting this flag + * to '0'. + * # If this flag is set to '0', then the link shall be + * cleared from forced down state if the link is in forced + * down state. + * There may be conditions (e.g. out-of-band or sideband + * configuration changes for the link) outside the scope + * of the HWRM implementation that may clear forced down + * link state. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ + UINT32_C(0x4000) + uint32_t enables; + /* + * This bit must be '1' for the auto_mode field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the auto_duplex field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \ + UINT32_C(0x2) + /* + * This bit must be '1' for the auto_pause field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the auto_link_speed field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \ + UINT32_C(0x8) + /* + * This bit must be '1' for the auto_link_speed_mask field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \ + UINT32_C(0x10) + /* + * This bit must be '1' for the wirespeed field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \ + UINT32_C(0x20) + /* + * This bit must be '1' for the lpbk field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \ + UINT32_C(0x40) + /* + * This bit must be '1' for the preemphasis field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \ + UINT32_C(0x80) + /* + * This bit must be '1' for the force_pause field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \ + UINT32_C(0x100) + /* + * This bit must be '1' for the eee_link_speed_mask field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \ + UINT32_C(0x200) + /* + * This bit must be '1' for the tx_lpi_timer field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \ + UINT32_C(0x400) + /* Port ID of port that is to be configured. */ + uint16_t port_id; + /* + * This is the speed that will be used if the force + * bit is '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_link_speed; + /* 100Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB + /* + * This value is used to identify what autoneg mode is + * used when the link speed is not being forced. + */ + uint8_t auto_mode; + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0) + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + /* + * Select only the auto_link_speed speed for autoneg mode. This mode has + * been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + /* + * Select the auto_link_speed or any speed below that speed for autoneg. + * This mode has been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask value + * that is provided. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \ + HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK + /* + * This is the duplex setting that will be used if the autoneg_mode + * is "one_speed" or "one_or_below". + */ + uint8_t auto_duplex; + /* Half Duplex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) + /* Full duplex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) + /* Both Half and Full dupex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \ + HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH + /* + * This value is used to configure the pause that will be + * used for autonegotiation. + * Add text on the usage of auto_pause and force_pause. + */ + uint8_t auto_pause; + /* + * When this bit is '1', Generation of tx pause messages + * has been requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \ + UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages + * has been requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \ + UINT32_C(0x2) + /* + * When set to 1, the advertisement of pause is enabled. + * + * # When the auto_mode is not set to none and this flag is + * set to 1, then the auto_pause bits on this port are being + * advertised and autoneg pause results are being interpreted. + * # When the auto_mode is not set to none and this + * flag is set to 0, the pause is forced as indicated in + * force_pause, and also advertised as auto_pause bits, but + * the autoneg results are not interpreted since the pause + * configuration is being forced. + * # When the auto_mode is set to none and this flag is set to + * 1, auto_pause bits should be ignored and should be set to 0. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \ + UINT32_C(0x4) + uint8_t unused_0; + /* + * This is the speed that will be used if the autoneg_mode + * is "one_speed" or "one_or_below". If an unsupported speed + * is selected, an error will be generated. + */ + uint16_t auto_link_speed; + /* 100Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB + /* + * This is a mask of link speeds that will be used if + * autoneg_mode is "mask". If unsupported speed is enabled + * an error will be generated. + */ + uint16_t auto_link_speed_mask; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \ + UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \ + UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \ + UINT32_C(0x2000) + /* This value controls the wirespeed feature. */ + uint8_t wirespeed; + /* Wirespeed feature is disabled. */ + #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0) + /* Wirespeed feature is enabled. */ + #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1) + #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON + /* This value controls the loopback setting for the PHY. */ + uint8_t lpbk; + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that + * host data is sent back to the host without modification. + */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that + * port logic will send packets back out the transmitter that + * are received. + */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) + /* + * The HW will be configured with external loopback such that + * host data is sent on the trasmitter and based on the external + * loopback connection the data will be received without modification. + */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \ + HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL + /* + * This value is used to configure the pause that will be + * used for force mode. + */ + uint8_t force_pause; + /* + * When this bit is '1', Generation of tx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2) + uint8_t unused_1; + /* + * This value controls the pre-emphasis to be used for the + * link. Driver should not set this value (use + * enable.preemphasis = 0) unless driver is sure of setting. + * Normally HWRM FW will determine proper pre-emphasis. + */ + uint32_t preemphasis; + /* + * Setting for link speed mask that is used to + * advertise speeds during autonegotiation when EEE is enabled. + * This field is valid only when EEE is enabled. + * The speeds specified in this field shall be a subset of + * speeds specified in auto_link_speed_mask. + * If EEE is enabled,then at least one speed shall be provided + * in this mask. + */ + uint16_t eee_link_speed_mask; + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \ + UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \ + UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \ + UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \ + UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \ + UINT32_C(0x40) + uint8_t unused_2[2]; + /* + * Reuested setting of TX LPI timer in microseconds. + * This field is valid only when EEE is enabled and TX LPI is + * enabled. + */ + uint32_t tx_lpi_timer; + #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) + #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 + uint32_t unused_3; +} __attribute__((packed)); + +/* hwrm_port_phy_cfg_output (size:128b/16B) */ +struct hwrm_port_phy_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_phy_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to invalid speed */ + #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1) + /* + * retry the command since the phy is not ready. + * retry count is returned in opaque_0. + * This is only valid for the first command and + * this value will not change for successive calls. + * but if a 0 is returned at any time then this should + * be treated as an un recoverable failure, + * + * retry interval in milli seconds is returned in opaque_1. + * This specifies the time that user should wait before + * issuing the next port_phy_cfg command. + */ + #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2) + #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY + uint8_t unused_0[7]; +} __attribute__((packed)); + +/********************** + * hwrm_port_phy_qcfg * + **********************/ + + +/* hwrm_port_phy_qcfg_input (size:192b/24B) */ +struct hwrm_port_phy_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_phy_qcfg_output (size:768b/96B) */ +struct hwrm_port_phy_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value indicates the current link status. */ + uint8_t link; + /* There is no link or cable detected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0) + /* There is no link, but a cable has been detected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1) + /* There is a link. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK + uint8_t unused_0; + /* This value indicates the current link speed of the connection. */ + uint16_t link_speed; + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB + /* + * This value is indicates the duplex of the current + * configuration. + */ + uint8_t duplex_cfg; + /* Half Duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0) + /* Full duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL + /* + * This value is used to indicate the current + * pause configuration. When autoneg is enabled, this value + * represents the autoneg results of pause configuration. + */ + uint8_t pause; + /* + * When this bit is '1', Generation of tx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2) + /* + * The supported speeds for the port. This is a bit mask. + * For each speed that is supported, the corrresponding + * bit will be set to '1'. + */ + uint16_t support_speeds; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \ + UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \ + UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \ + UINT32_C(0x2000) + /* + * Current setting of forced link speed. + * When the link speed is not being forced, this + * value shall be set to 0. + */ + uint16_t force_link_speed; + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \ + UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \ + UINT32_C(0xffff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB + /* Current setting of auto negotiation mode. */ + uint8_t auto_mode; + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0) + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + /* + * Select only the auto_link_speed speed for autoneg mode. This mode has + * been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + /* + * Select the auto_link_speed or any speed below that speed for autoneg. + * This mode has been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask value + * that is provided. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK + /* + * Current setting of pause autonegotiation. + * Move autoneg_pause flag here. + */ + uint8_t auto_pause; + /* + * When this bit is '1', Generation of tx pause messages + * has been requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \ + UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages + * has been requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \ + UINT32_C(0x2) + /* + * When set to 1, the advertisement of pause is enabled. + * + * # When the auto_mode is not set to none and this flag is + * set to 1, then the auto_pause bits on this port are being + * advertised and autoneg pause results are being interpreted. + * # When the auto_mode is not set to none and this + * flag is set to 0, the pause is forced as indicated in + * force_pause, and also advertised as auto_pause bits, but + * the autoneg results are not interpreted since the pause + * configuration is being forced. + * # When the auto_mode is set to none and this flag is set to + * 1, auto_pause bits should be ignored and should be set to 0. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \ + UINT32_C(0x4) + /* + * Current setting for auto_link_speed. This field is only + * valid when auto_mode is set to "one_speed" or "one_or_below". + */ + uint16_t auto_link_speed; + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \ + UINT32_C(0xffff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB + /* + * Current setting for auto_link_speed_mask that is used to + * advertise speeds during autonegotiation. + * This field is only valid when auto_mode is set to "mask". + * The speeds specified in this field shall be a subset of + * supported speeds on this port. + */ + uint16_t auto_link_speed_mask; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \ + UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \ + UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \ + UINT32_C(0x2000) + /* Current setting for wirespeed. */ + uint8_t wirespeed; + /* Wirespeed feature is disabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0) + /* Wirespeed feature is enabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON + /* Current setting for loopback. */ + uint8_t lpbk; + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that + * host data is sent back to the host without modification. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that + * port logic will send packets back out the transmitter that + * are received. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + /* + * The HW will be configured with external loopback such that + * host data is sent on the trasmitter and based on the external + * loopback connection the data will be received without modification. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL + /* + * Current setting of forced pause. + * When the pause configuration is not being forced, then + * this value shall be set to 0. + */ + uint8_t force_pause; + /* + * When this bit is '1', Generation of tx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2) + /* + * This value indicates the current status of the optics module on + * this port. + */ + uint8_t module_status; + /* Module is inserted and accepted */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \ + /* Module is rejected and transmit side Laser is disabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \ + /* Module mismatch warning. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 - /* TQM slow path page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G - /* TQM ring 0 page size and level. */ - uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; - /* TQM ring 0 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \ + /* Module is rejected and powered down. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \ + UINT32_C(0x3) + /* Module is not inserted. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ + UINT32_C(0x4) + /* Module status is not applicable. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ + UINT32_C(0xff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE + /* Current setting for preemphasis. */ + uint32_t preemphasis; + /* This field represents the major version of the PHY. */ + uint8_t phy_maj; + /* This field represents the minor version of the PHY. */ + uint8_t phy_min; + /* This field represents the build version of the PHY. */ + uint8_t phy_bld; + /* This value represents a PHY type. */ + uint8_t phy_type; + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \ + /* BASE-CR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \ + /* BASE-KR4 (Deprecated) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 - /* TQM ring 0 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G - /* TQM ring 1 page size and level. */ - uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; - /* TQM ring 1 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \ + /* BASE-LR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \ + UINT32_C(0x3) + /* BASE-SR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \ + UINT32_C(0x4) + /* BASE-KR2 (Deprecated) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \ + UINT32_C(0x5) + /* BASE-KX */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \ + UINT32_C(0x6) + /* BASE-KR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \ + UINT32_C(0x7) + /* BASE-T */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \ + UINT32_C(0x8) + /* EEE capable BASE-T */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \ + UINT32_C(0x9) + /* SGMII connected external PHY */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \ + UINT32_C(0xa) + /* 25G_BASECR_CA_L */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \ + UINT32_C(0xb) + /* 25G_BASECR_CA_S */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \ + UINT32_C(0xc) + /* 25G_BASECR_CA_N */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \ + UINT32_C(0xd) + /* 25G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \ + UINT32_C(0xe) + /* 100G_BASECR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \ UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \ + /* 100G_BASESR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \ + UINT32_C(0x10) + /* 100G_BASELR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \ + UINT32_C(0x11) + /* 100G_BASEER4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \ + UINT32_C(0x12) + /* 100G_BASESR10 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \ + UINT32_C(0x13) + /* 40G_BASECR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \ + UINT32_C(0x14) + /* 40G_BASESR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \ + UINT32_C(0x15) + /* 40G_BASELR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \ + UINT32_C(0x16) + /* 40G_BASEER4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \ + UINT32_C(0x17) + /* 40G_ACTIVE_CABLE */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \ + UINT32_C(0x18) + /* 1G_baseT */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \ + UINT32_C(0x19) + /* 1G_baseSX */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \ + UINT32_C(0x1a) + /* 1G_baseCX */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ + UINT32_C(0x1b) + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX + /* This value represents a media type. */ + uint8_t media_type; + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0) + /* Twisted Pair */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1) + /* Direct Attached Copper */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2) + /* Fiber */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3) + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE + /* This value represents a transceiver type. */ + uint8_t xcvr_pkg_type; + /* PHY and MAC are in the same package */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \ + UINT32_C(0x1) + /* PHY and MAC are in different packages */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \ + UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL + uint8_t eee_config_phy_addr; + /* This field represents PHY address. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \ + UINT32_C(0x1f) + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0 + /* + * This field represents flags related to EEE configuration. + * These EEE configuration flags are valid only when the + * auto_mode is not set to none (in other words autonegotiation + * is enabled). + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \ + UINT32_C(0xe0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5 + /* + * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled. + * Speeds for autoneg with EEE mode enabled + * are based on eee_link_speed_mask. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \ + UINT32_C(0x20) + /* + * This flag is valid only when eee_enabled is set to 1. + * + * # If eee_enabled is set to 0, then EEE mode is disabled + * and this flag shall be ignored. + * # If eee_enabled is set to 1 and this flag is set to 1, + * then Energy Efficient Ethernet (EEE) mode is enabled + * and in use. + * # If eee_enabled is set to 1 and this flag is set to 0, + * then Energy Efficient Ethernet (EEE) mode is enabled + * but is currently not in use. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \ + UINT32_C(0x40) + /* + * This flag is valid only when eee_enabled is set to 1. + * + * # If eee_enabled is set to 0, then EEE mode is disabled + * and this flag shall be ignored. + * # If eee_enabled is set to 1 and this flag is set to 1, + * then Energy Efficient Ethernet (EEE) mode is enabled + * and TX LPI is enabled. + * # If eee_enabled is set to 1 and this flag is set to 0, + * then Energy Efficient Ethernet (EEE) mode is enabled + * but TX LPI is disabled. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \ + UINT32_C(0x80) + /* + * When set to 1, the parallel detection is used to determine + * the speed of the link partner. + * + * Parallel detection is used when a autonegotiation capable + * device is connected to a link parter that is not capable + * of autonegotiation. + */ + uint8_t parallel_detect; + /* + * When set to 1, the parallel detection is used to determine + * the speed of the link partner. + * + * Parallel detection is used when a autonegotiation capable + * device is connected to a link parter that is not capable + * of autonegotiation. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) + /* + * The advertised speeds for the port by the link partner. + * Each advertised speed will be set to '1'. + */ + uint16_t link_partner_adv_speeds; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \ + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 - /* TQM ring 1 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G - /* TQM ring 2 page size and level. */ - uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; - /* TQM ring 2 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \ + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \ + UINT32_C(0x2000) + /* + * The advertised autoneg for the port by the link partner. + * This field is deprecated and should be set to 0. + */ + uint8_t link_partner_adv_auto_mode; + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \ UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \ + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \ + /* + * Select only the auto_link_speed speed for autoneg mode. This mode has + * been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 - /* TQM ring 2 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G - /* TQM ring 3 page size and level. */ - uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; - /* TQM ring 3 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \ + /* + * Select the auto_link_speed or any speed below that speed for autoneg. + * This mode has been DEPRECATED. An HWRM client should not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \ + UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask value + * that is provided. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \ + UINT32_C(0x4) + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK + /* The advertised pause settings on the port by the link partner. */ + uint8_t link_partner_adv_pause; + /* + * When this bit is '1', Generation of tx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \ + /* + * When this bit is '1', Reception of rx pause messages + * is supported. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 - /* TQM ring 3 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G - /* TQM ring 4 page size and level. */ - uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; - /* TQM ring 4 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \ + /* + * Current setting for link speed mask that is used to + * advertise speeds during autonegotiation when EEE is enabled. + * This field is valid only when eee_enabled flags is set to 1. + * The speeds specified in this field shall be a subset of + * speeds specified in auto_link_speed_mask. + */ + uint16_t adv_eee_link_speed_mask; + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \ + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \ + UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \ + UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \ + UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \ + UINT32_C(0x40) + /* + * Current setting for link speed mask that is advertised by + * the link partner when EEE is enabled. + * This field is valid only when eee_enabled flags is set to 1. + */ + uint16_t link_partner_adv_eee_link_speed_mask; + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \ + UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 - /* TQM ring 4 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G - /* TQM ring 5 page size and level. */ - uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; - /* TQM ring 5 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \ + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \ + UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \ + UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \ + UINT32_C(0x40) + uint32_t xcvr_identifier_type_tx_lpi_timer; + /* + * Current setting of TX LPI timer in microseconds. + * This field is valid only when_eee_enabled flag is set to 1 + * and tx_lpi_enabled is set to 1. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \ + UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0 + /* This value represents transceiver identifier type. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \ + UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24 + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \ + (UINT32_C(0x0) << 24) + /* SFP/SFP+/SFP28 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \ + (UINT32_C(0x3) << 24) + /* QSFP+ */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \ + (UINT32_C(0xc) << 24) + /* QSFP+ */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \ + (UINT32_C(0xd) << 24) + /* QSFP28 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \ + (UINT32_C(0x11) << 24) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 + /* + * This value represents the current configuration of + * Forward Error Correction (FEC) on the port. + */ + uint16_t fec_cfg; + /* + * When set to 1, then FEC is not supported on this port. If this flag + * is set to 1, then all other FEC configuration flags shall be ignored. + * When set to 0, then FEC is supported as indicated by other + * configuration flags. + * If no cable is attached and the HWRM does not yet know the FEC + * capability, then the HWRM shall set this flag to 1 when reporting + * FEC capability. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \ + /* + * When set to 1, then FEC autonegotiation is supported on this port. + * When set to 0, then FEC autonegotiation is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 - /* TQM ring 5 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G - /* TQM ring 6 page size and level. */ - uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; - /* TQM ring 6 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \ + /* + * When set to 1, then FEC autonegotiation is enabled on this port. + * When set to 0, then FEC autonegotiation is disabled if supported. + * This flag should be ignored if FEC autonegotiation is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \ + UINT32_C(0x4) + /* + * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port. + * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \ + UINT32_C(0x8) + /* + * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port. + * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. + * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \ + UINT32_C(0x10) + /* + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port. + * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \ + UINT32_C(0x20) + /* + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port. + * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported. + * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \ + UINT32_C(0x40) + /* + * This value is indicates the duplex of the current + * connection state. + */ + uint8_t duplex_state; + /* Half Duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0) + /* Full duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1) + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \ + HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL + /* Option flags fields. */ + uint8_t option_flags; + /* When this bit is '1', Media auto detect is enabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \ + UINT32_C(0x1) + /* + * Up to 16 bytes of null padded ASCII string representing + * PHY vendor. + * If the string is set to null, then the vendor name is not + * available. + */ + char phy_vendor_name[16]; + /* + * Up to 16 bytes of null padded ASCII string that + * identifies vendor specific part number of the PHY. + * If the string is set to null, then the vendor specific + * part number is not available. + */ + char phy_vendor_partnumber[16]; + uint8_t unused_2[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_port_mac_cfg * + *********************/ + + +/* hwrm_port_mac_cfg_input (size:320b/40B) */ +struct hwrm_port_mac_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * In this field, there are a number of CoS mappings related flags + * that are used to configure CoS mappings and their corresponding + * priorities in the hardware. + * For the priorities of CoS mappings, the HWRM uses the following + * priority order (high to low) by default: + * # vlan pri + * # ip_dscp + * # tunnel_vlan_pri + * # default cos + * + * A subset of CoS mappings can be enabled. + * If a priority is not specified for an enabled CoS mapping, the + * priority will be assigned in the above order for the enabled CoS + * mappings. For example, if vlan_pri and ip_dscp CoS mappings are + * enabled and their priorities are not specified, the following + * priority order (high to low) will be used by the HWRM: + * # vlan_pri + * # ip_dscp + * # default cos + * + * vlan_pri CoS mapping together with default CoS with lower priority + * are enabled by default by the HWRM. + */ + uint32_t flags; + /* + * When this bit is '1', this command will configure + * the MAC to match the current link state of the PHY. + * If the link is not established on the PHY, then this + * bit has no effect. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \ + /* + * When this bit is set to '1', the inner VLAN PRI to CoS mapping + * is requested to be enabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 - /* TQM ring 6 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G - /* TQM ring 7 page size and level. */ - uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; - /* TQM ring 7 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \ + /* + * When this bit is set to '1', tunnel VLAN PRI field to + * CoS mapping is requested to be enabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \ + UINT32_C(0x4) + /* + * When this bit is set to '1', the IP DSCP to CoS mapping is + * requested to be enabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \ + UINT32_C(0x8) + /* + * When this bit is '1', the HWRM is requested to + * enable timestamp capture capability on the receive side + * of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \ + UINT32_C(0x10) + /* + * When this bit is '1', the HWRM is requested to + * disable timestamp capture capability on the receive side + * of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \ + UINT32_C(0x20) + /* + * When this bit is '1', the HWRM is requested to + * enable timestamp capture capability on the transmit side + * of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \ + UINT32_C(0x40) + /* + * When this bit is '1', the HWRM is requested to + * disable timestamp capture capability on the transmit side + * of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \ + UINT32_C(0x80) + /* + * When this bit is '1', the Out-Of-Box WoL is requested to + * be enabled on this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \ + UINT32_C(0x100) + /* + * When this bit is '1', the the Out-Of-Box WoL is requested to + * be disabled on this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \ + UINT32_C(0x200) + /* + * When this bit is set to '1', the inner VLAN PRI to CoS mapping + * is requested to be disabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \ + UINT32_C(0x400) + /* + * When this bit is set to '1', tunnel VLAN PRI field to + * CoS mapping is requested to be disabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \ + UINT32_C(0x800) + /* + * When this bit is set to '1', the IP DSCP to CoS mapping is + * requested to be disabled. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \ + UINT32_C(0x1000) + uint32_t enables; + /* + * This bit must be '1' for the ipg field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \ + UINT32_C(0x1) + /* + * This bit must be '1' for the lpbk field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlan_pri2cos_map_pri field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \ + UINT32_C(0x4) + /* + * This bit must be '1' for the tunnel_pri2cos_map_pri field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \ + UINT32_C(0x10) + /* + * This bit must be '1' for the dscp2cos_map_pri field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \ + UINT32_C(0x20) + /* + * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the cos_field_cfg field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \ + UINT32_C(0x100) + /* Port ID of port that is to be configured. */ + uint16_t port_id; + /* + * This value is used to configure the minimum IPG that will + * be sent between packets by this port. + */ + uint8_t ipg; + /* This value controls the loopback setting for the MAC. */ + uint8_t lpbk; + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that + * host data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that + * port logic will send packets back out the transmitter that + * are received. + */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \ + HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE + /* + * This value controls the priority setting of VLAN PRI to CoS + * mapping based on VLAN Tags of inner packet headers of + * tunneled packets or packet headers of non-tunneled packets. + * + * # Each XXX_pri variable shall have a unique priority value + * when it is being specified. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + */ + uint8_t vlan_pri2cos_map_pri; + /* Reserved field. */ + uint8_t reserved1; + /* + * This value controls the priority setting of VLAN PRI to CoS + * mapping based on VLAN Tags of tunneled header. + * This mapping only applies when tunneled headers + * are present. + * + * # Each XXX_pri variable shall have a unique priority value + * when it is being specified. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + */ + uint8_t tunnel_pri2cos_map_pri; + /* + * This value controls the priority setting of IP DSCP to CoS + * mapping based on inner IP header of tunneled packets or + * IP header of non-tunneled packets. + * + * # Each XXX_pri variable shall have a unique priority value + * when it is being specified. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + */ + uint8_t dscp2pri_map_pri; + /* + * This is a 16-bit bit mask that is used to request a + * specific configuration of time stamp capture of PTP messages + * on the receive side of this port. + * This field shall be ignored if the ptp_rx_ts_capture_enable + * flag is not set in this command. + * Otherwise, if bit 'i' is set, then the HWRM is being + * requested to configure the receive side of the port to + * capture the time stamp of every received PTP message + * with messageType field value set to i. + */ + uint16_t rx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that is used to request a + * specific configuration of time stamp capture of PTP messages + * on the transmit side of this port. + * This field shall be ignored if the ptp_tx_ts_capture_enable + * flag is not set in this command. + * Otherwise, if bit 'i' is set, then the HWRM is being + * requested to configure the transmit sied of the port to + * capture the time stamp of every transmitted PTP message + * with messageType field value set to i. + */ + uint16_t tx_ts_capture_ptp_msg_type; + /* Configuration of CoS fields. */ + uint8_t cos_field_cfg; + /* Reserved */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \ + UINT32_C(0x1) + /* + * This field is used to specify selection of VLAN PRI value + * based on whether one or two VLAN Tags are present in + * the inner packet headers of tunneled packets or + * non-tunneled packets. + * This field is valid only if inner VLAN PRI to CoS mapping + * is enabled. + * If VLAN PRI to CoS mapping is not enabled, then this + * field shall be ignored. + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \ + UINT32_C(0x6) + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \ + 1 + /* + * Select inner VLAN PRI when 1 or 2 VLAN Tags are + * present in the inner packet headers + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \ + (UINT32_C(0x0) << 1) + /* + * Select outer VLAN Tag PRI when 2 VLAN Tags are + * present in the inner packet headers. + * No VLAN PRI shall be selected for this configuration + * if only one VLAN Tag is present in the inner + * packet headers. + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \ + (UINT32_C(0x1) << 1) + /* + * Select outermost VLAN PRI when 1 or 2 VLAN Tags + * are present in the inner packet headers + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \ + (UINT32_C(0x2) << 1) + /* Unspecified */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \ + (UINT32_C(0x3) << 1) + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \ + HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED + /* + * This field is used to specify selection of tunnel VLAN + * PRI value based on whether one or two VLAN Tags are + * present in tunnel headers. + * This field is valid only if tunnel VLAN PRI to CoS mapping + * is enabled. + * If tunnel VLAN PRI to CoS mapping is not enabled, then this + * field shall be ignored. + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \ + UINT32_C(0x18) + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \ + 3 + /* + * Select inner VLAN PRI when 1 or 2 VLAN Tags are + * present in the tunnel packet headers + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \ + (UINT32_C(0x0) << 3) + /* + * Select outer VLAN Tag PRI when 2 VLAN Tags are + * present in the tunnel packet headers. + * No tunnel VLAN PRI shall be selected for this + * configuration if only one VLAN Tag is present in + * the tunnel packet headers. + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \ + (UINT32_C(0x1) << 3) + /* + * Select outermost VLAN PRI when 1 or 2 VLAN Tags + * are present in the tunnel packet headers + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \ + (UINT32_C(0x2) << 3) + /* Unspecified */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \ + (UINT32_C(0x3) << 3) + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \ + HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED + /* + * This field shall be used to provide default CoS value + * that has been configured on this port. + * This field is valid only if default CoS mapping + * is enabled. + * If default CoS mapping is not enabled, then this + * field shall be ignored. + */ + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \ + UINT32_C(0xe0) + #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ + 5 + uint8_t unused_0[3]; +} __attribute__((packed)); + +/* hwrm_port_mac_cfg_output (size:128b/16B) */ +struct hwrm_port_mac_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the configured maximum length of Ethernet packet + * payload that is allowed to be received on the port. + * This value does not include the number of bytes used by + * Ethernet header and trailer (CRC). + */ + uint16_t mru; + /* + * This is the configured maximum length of Ethernet packet + * payload that is allowed to be transmitted on the port. + * This value does not include the number of bytes used by + * Ethernet header and trailer (CRC). + */ + uint16_t mtu; + /* Current configuration of the IPG value. */ + uint8_t ipg; + /* Current value of the loopback value. */ + uint8_t lpbk; + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that + * host data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that + * port logic will send packets back out the transmitter that + * are received. + */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \ + HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE + uint8_t unused_0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_port_mac_qcfg * + **********************/ + + +/* hwrm_port_mac_qcfg_input (size:192b/24B) */ +struct hwrm_port_mac_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be configured. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_mac_qcfg_output (size:192b/24B) */ +struct hwrm_port_mac_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the configured maximum length of Ethernet packet + * payload that is allowed to be received on the port. + * This value does not include the number of bytes used by the + * Ethernet header and trailer (CRC). + */ + uint16_t mru; + /* + * This is the configured maximum length of Ethernet packet + * payload that is allowed to be transmitted on the port. + * This value does not include the number of bytes used by the + * Ethernet header and trailer (CRC). + */ + uint16_t mtu; + /* + * The minimum IPG that will + * be sent between packets by this port. + */ + uint8_t ipg; + /* The loopback setting for the MAC. */ + uint8_t lpbk; + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that + * host data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that + * port logic will send packets back out the transmitter that + * are received. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \ + HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE + /* + * Priority setting for VLAN PRI to CoS mapping. + * # Each XXX_pri variable shall have a unique priority value + * when it is being used. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + * # If the correspoding CoS mapping is not enabled, then this + * field should be ignored. + * # This value indicates the normalized priority value retained + * in the HWRM. + */ + uint8_t vlan_pri2cos_map_pri; + /* + * In this field, a number of CoS mappings related flags + * are used to indicate configured CoS mappings. + */ + uint8_t flags; + /* + * When this bit is set to '1', the inner VLAN PRI to CoS mapping + * is enabled. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \ + /* + * When this bit is set to '1', tunnel VLAN PRI field to + * CoS mapping is enabled. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 - /* TQM ring 7 page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G - /* MR/AV page size and level. */ - uint8_t mrav_pg_size_mrav_lvl; - /* MR/AV PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \ + /* + * When this bit is set to '1', the IP DSCP to CoS mapping is + * enabled. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \ + UINT32_C(0x4) + /* + * When this bit is '1', the Out-Of-Box WoL is enabled on this + * port. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \ + UINT32_C(0x8) + /* When this bit is '1', PTP is enabled for RX on this port. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \ + UINT32_C(0x10) + /* When this bit is '1', PTP is enabled for TX on this port. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \ + UINT32_C(0x20) + /* + * Priority setting for tunnel VLAN PRI to CoS mapping. + * # Each XXX_pri variable shall have a unique priority value + * when it is being used. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + * # If the correspoding CoS mapping is not enabled, then this + * field should be ignored. + * # This value indicates the normalized priority value retained + * in the HWRM. + */ + uint8_t tunnel_pri2cos_map_pri; + /* + * Priority setting for DSCP to PRI mapping. + * # Each XXX_pri variable shall have a unique priority value + * when it is being used. + * # When comparing priorities of mappings, higher value + * indicates higher priority. + * For example, a value of 0-3 is returned where 0 is being + * the lowest priority and 3 is being the highest priority. + * # If the correspoding CoS mapping is not enabled, then this + * field should be ignored. + * # This value indicates the normalized priority value retained + * in the HWRM. + */ + uint8_t dscp2pri_map_pri; + /* + * This is a 16-bit bit mask that represents the + * current configuration of time stamp capture of PTP messages + * on the receive side of this port. + * If bit 'i' is set, then the receive side of the port + * is configured to capture the time stamp of every + * received PTP message with messageType field value set + * to i. + * If all bits are set to 0 (i.e. field value set 0), + * then the receive side of the port is not configured + * to capture timestamp for PTP messages. + * If all bits are set to 1, then the receive side of the + * port is configured to capture timestamp for all PTP + * messages. + */ + uint16_t rx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that represents the + * current configuration of time stamp capture of PTP messages + * on the transmit side of this port. + * If bit 'i' is set, then the transmit side of the port + * is configured to capture the time stamp of every + * received PTP message with messageType field value set + * to i. + * If all bits are set to 0 (i.e. field value set 0), + * then the transmit side of the port is not configured + * to capture timestamp for PTP messages. + * If all bits are set to 1, then the transmit side of the + * port is configured to capture timestamp for all PTP + * messages. + */ + uint16_t tx_ts_capture_ptp_msg_type; + /* Configuration of CoS fields. */ + uint8_t cos_field_cfg; + /* Reserved */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 - /* MR/AV page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G - /* Timer page size and level. */ - uint8_t tim_pg_size_tim_lvl; - /* Timer PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \ + /* + * This field is used for selecting VLAN PRI value + * based on whether one or two VLAN Tags are present in + * the inner packet headers of tunneled packets or + * non-tunneled packets. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \ + UINT32_C(0x6) + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \ + 1 + /* + * Select inner VLAN PRI when 1 or 2 VLAN Tags are + * present in the inner packet headers + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \ + (UINT32_C(0x0) << 1) + /* + * Select outer VLAN Tag PRI when 2 VLAN Tags are + * present in the inner packet headers. + * No VLAN PRI is selected for this configuration + * if only one VLAN Tag is present in the inner + * packet headers. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \ + (UINT32_C(0x1) << 1) + /* + * Select outermost VLAN PRI when 1 or 2 VLAN Tags + * are present in the inner packet headers + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \ + (UINT32_C(0x2) << 1) + /* Unspecified */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \ + (UINT32_C(0x3) << 1) + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \ + HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED + /* + * This field is used for selecting tunnel VLAN PRI value + * based on whether one or two VLAN Tags are present in + * the tunnel headers of tunneled packets. This selection + * does not apply to non-tunneled packets. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \ + UINT32_C(0x18) + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \ + 3 + /* + * Select inner VLAN PRI when 1 or 2 VLAN Tags are + * present in the tunnel packet headers + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \ + (UINT32_C(0x0) << 3) + /* + * Select outer VLAN Tag PRI when 2 VLAN Tags are + * present in the tunnel packet headers. + * No VLAN PRI is selected for this configuration + * if only one VLAN Tag is present in the tunnel + * packet headers. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \ + (UINT32_C(0x1) << 3) + /* + * Select outermost VLAN PRI when 1 or 2 VLAN Tags + * are present in the tunnel packet headers + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \ + (UINT32_C(0x2) << 3) + /* Unspecified */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \ + (UINT32_C(0x3) << 3) + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \ + HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED + /* + * This field is used to provide default CoS value that + * has been configured on this port. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \ + UINT32_C(0xe0) + #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ + 5 + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_port_mac_ptp_qcfg * + **************************/ + + +/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ +struct hwrm_port_mac_ptp_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +struct hwrm_port_mac_ptp_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * In this field, a number of PTP related flags + * are used to indicate configured PTP capabilities. + */ + uint8_t flags; + /* + * When this bit is set to '1', the PTP related registers are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \ + /* + * When this bit is set to '1', the PTP information is accessible + * via HWRM commands. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 - /* Timer page size. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G - /* QP page directory. */ - uint64_t qpc_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* VNIC page directory. */ - uint64_t vnic_page_dir; - /* Stat page directory. */ - uint64_t stat_page_dir; - /* TQM slowpath page directory. */ - uint64_t tqm_sp_page_dir; - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; - /* MR/AV page directory. */ - uint64_t mrav_page_dir; - /* Timer page directory. */ - uint64_t tim_page_dir; - /* Number of QPs. */ - uint32_t qp_num_entries; - /* Number of SRQs. */ - uint32_t srq_num_entries; - /* Number of CQs. */ - uint32_t cq_num_entries; - /* Number of Stats. */ - uint32_t stat_num_entries; - /* Number of TQM slowpath entries. */ - uint32_t tqm_sp_num_entries; - /* Number of TQM ring 0 entries. */ - uint32_t tqm_ring0_num_entries; - /* Number of TQM ring 1 entries. */ - uint32_t tqm_ring1_num_entries; - /* Number of TQM ring 2 entries. */ - uint32_t tqm_ring2_num_entries; - /* Number of TQM ring 3 entries. */ - uint32_t tqm_ring3_num_entries; - /* Number of TQM ring 4 entries. */ - uint32_t tqm_ring4_num_entries; - /* Number of TQM ring 5 entries. */ - uint32_t tqm_ring5_num_entries; - /* Number of TQM ring 6 entries. */ - uint32_t tqm_ring6_num_entries; - /* Number of TQM ring 7 entries. */ - uint32_t tqm_ring7_num_entries; - /* Number of MR/AV entries. */ - uint32_t mrav_num_entries; - /* Number of Timer entries. */ - uint32_t tim_num_entries; - /* Number of entries to reserve for QP1 */ - uint16_t qp_num_qp1_entries; - /* Number of entries to reserve for L2 */ - uint16_t qp_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t qp_entry_size; - /* Number of entries to reserve for L2 */ - uint16_t srq_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t srq_entry_size; - /* Number of entries to reserve for L2 */ - uint16_t cq_num_l2_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t cq_entry_size; - /* Number of entries to reserve for VNIC entries */ - uint16_t vnic_num_vnic_entries; - /* Number of entries to reserve for Ring table entries */ - uint16_t vnic_num_ring_table_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t vnic_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t stat_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t tqm_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t mrav_entry_size; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t tim_entry_size; + uint8_t unused_0[3]; + /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + uint32_t rx_ts_reg_off_lower; + /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + uint32_t rx_ts_reg_off_upper; + /* Offset of the PTP register for the sequence ID for RX. */ + uint32_t rx_ts_reg_off_seq_id; + /* Offset of the first PTP source ID for RX. */ + uint32_t rx_ts_reg_off_src_id_0; + /* Offset of the second PTP source ID for RX. */ + uint32_t rx_ts_reg_off_src_id_1; + /* Offset of the third PTP source ID for RX. */ + uint32_t rx_ts_reg_off_src_id_2; + /* Offset of the domain ID for RX. */ + uint32_t rx_ts_reg_off_domain_id; + /* Offset of the PTP FIFO register for RX. */ + uint32_t rx_ts_reg_off_fifo; + /* Offset of the PTP advance FIFO register for RX. */ + uint32_t rx_ts_reg_off_fifo_adv; + /* PTP timestamp granularity for RX. */ + uint32_t rx_ts_reg_off_granularity; + /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + uint32_t tx_ts_reg_off_lower; + /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + uint32_t tx_ts_reg_off_upper; + /* Offset of the PTP register for the sequence ID for TX. */ + uint32_t tx_ts_reg_off_seq_id; + /* Offset of the PTP FIFO register for TX. */ + uint32_t tx_ts_reg_off_fifo; + /* PTP timestamp granularity for TX. */ + uint32_t tx_ts_reg_off_granularity; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************** + * hwrm_port_qstats * + ********************/ + + +/* hwrm_port_qstats_input (size:320b/40B) */ +struct hwrm_port_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; + /* + * This is the host address where + * Tx port statistics will be stored + */ + uint64_t tx_stat_host_addr; + /* + * This is the host address where + * Rx port statistics will be stored + */ + uint64_t rx_stat_host_addr; } __attribute__((packed)); -/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ -struct hwrm_func_backing_store_cfg_output { +/* hwrm_port_qstats_output (size:128b/16B) */ +struct hwrm_port_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -7490,7 +11866,11 @@ struct hwrm_func_backing_store_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* The size of TX port statistics block in bytes. */ + uint16_t tx_stat_size; + /* The size of RX port statistics block in bytes. */ + uint16_t rx_stat_size; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7501,13 +11881,13 @@ struct hwrm_func_backing_store_cfg_output { uint8_t valid; } __attribute__((packed)); -/******************************** - * hwrm_func_backing_store_qcfg * - ********************************/ +/************************ + * hwrm_port_qstats_ext * + ************************/ -/* hwrm_func_backing_store_qcfg_input (size:128b/16B) */ -struct hwrm_func_backing_store_qcfg_input { +/* hwrm_port_qstats_ext_input (size:320b/40B) */ +struct hwrm_port_qstats_ext_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -7535,10 +11915,33 @@ struct hwrm_func_backing_store_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + /* + * The size of TX port extended + * statistics block in bytes. + */ + uint16_t tx_stat_size; + /* + * The size of RX port extended + * statistics block in bytes + */ + uint16_t rx_stat_size; + uint8_t unused_0[2]; + /* + * This is the host address where + * Tx port statistics will be stored + */ + uint64_t tx_stat_host_addr; + /* + * This is the host address where + * Rx port statistics will be stored + */ + uint64_t rx_stat_host_addr; } __attribute__((packed)); -/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ -struct hwrm_func_backing_store_qcfg_output { +/* hwrm_port_qstats_ext_output (size:128b/16B) */ +struct hwrm_port_qstats_ext_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -7547,843 +11950,1775 @@ struct hwrm_func_backing_store_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When set, the firmware only uses on-chip resources and does not - * expect any backing store to be provided by the host driver. This - * mode provides minimal L2 functionality (e.g. limited L2 resources, - * no RoCE). - */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \ - UINT32_C(0x1) - uint8_t unused_0[4]; + /* The size of TX port statistics block in bytes. */ + uint16_t tx_stat_size; + /* The size of RX port statistics block in bytes. */ + uint16_t rx_stat_size; + uint8_t unused_0[3]; /* - * This bit must be '1' for the qp fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \ - UINT32_C(0x1) + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_port_lpbk_qstats * + *************************/ + + +/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ +struct hwrm_port_lpbk_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the srq fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \ - UINT32_C(0x2) + uint16_t cmpl_ring; /* - * This bit must be '1' for the cq fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \ - UINT32_C(0x4) + uint16_t seq_id; /* - * This bit must be '1' for the vnic fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \ - UINT32_C(0x8) + uint16_t target_id; /* - * This bit must be '1' for the stat fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \ - UINT32_C(0x10) + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ +struct hwrm_port_lpbk_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of transmitted unicast frames */ + uint64_t lpbk_ucast_frames; + /* Number of transmitted multicast frames */ + uint64_t lpbk_mcast_frames; + /* Number of transmitted broadcast frames */ + uint64_t lpbk_bcast_frames; + /* Number of transmitted bytes for unicast traffic */ + uint64_t lpbk_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t lpbk_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t lpbk_bcast_bytes; + /* Total Tx Drops for loopback traffic reported by STATS block */ + uint64_t tx_stat_discard; + /* Total Tx Error Drops for loopback traffic reported by STATS block */ + uint64_t tx_stat_error; + /* Total Rx Drops for loopback traffic reported by STATS block */ + uint64_t rx_stat_discard; + /* Total Rx Error Drops for loopback traffic reported by STATS block */ + uint64_t rx_stat_error; + uint8_t unused_0[7]; /* - * This bit must be '1' for the tqm_sp fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \ - UINT32_C(0x20) + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_port_clr_stats * + ***********************/ + + +/* hwrm_port_clr_stats_input (size:192b/24B) */ +struct hwrm_port_clr_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the tqm_ring0 fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \ - UINT32_C(0x40) + uint16_t cmpl_ring; /* - * This bit must be '1' for the tqm_ring1 fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \ - UINT32_C(0x80) + uint16_t seq_id; /* - * This bit must be '1' for the tqm_ring2 fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \ - UINT32_C(0x100) + uint16_t target_id; /* - * This bit must be '1' for the tqm_ring3 fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \ - UINT32_C(0x200) + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_clr_stats_output (size:128b/16B) */ +struct hwrm_port_clr_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the tqm_ring4 fields to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \ - UINT32_C(0x400) + uint8_t valid; +} __attribute__((packed)); + +/**************************** + * hwrm_port_lpbk_clr_stats * + ****************************/ + + +/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ +struct hwrm_port_lpbk_clr_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the tqm_ring5 fields to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \ - UINT32_C(0x800) + uint16_t cmpl_ring; /* - * This bit must be '1' for the tqm_ring6 fields to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \ - UINT32_C(0x1000) + uint16_t seq_id; /* - * This bit must be '1' for the tqm_ring7 fields to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \ - UINT32_C(0x2000) + uint16_t target_id; /* - * This bit must be '1' for the mrav fields to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \ - UINT32_C(0x4000) + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ +struct hwrm_port_lpbk_clr_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the tim fields to be - * configured. - */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \ - UINT32_C(0x8000) - /* QPC page size and level. */ - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 - /* QPC page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G - /* SRQ page size and level. */ - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G - /* CQ page size and level. */ - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 - /* CQ page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G - /* VNIC page size and level. */ - uint8_t vnic_pg_size_vnic_lvl; - /* VNIC PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \ - UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 - /* VNIC page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G - /* Stat page size and level. */ - uint8_t stat_pg_size_stat_lvl; - /* Stat PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \ + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_port_ts_query * + **********************/ + + +/* hwrm_port_ts_query_input (size:192b/24B) */ +struct hwrm_port_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \ + HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[2]; +} __attribute__((packed)); + +/* hwrm_port_ts_query_output (size:192b/24B) */ +struct hwrm_port_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of PTP message captured. */ + uint64_t ptp_msg_ts; + /* Sequence ID of the PTP message captured. */ + uint16_t ptp_msg_seqid; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_port_phy_qcaps * + ***********************/ + + +/* hwrm_port_phy_qcaps_input (size:192b/24B) */ +struct hwrm_port_phy_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_phy_qcaps_output (size:192b/24B) */ +struct hwrm_port_phy_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* PHY capability flags */ + uint8_t flags; + /* + * If set to 1, then this field indicates that the + * link is capable of supporting EEE. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \ + /* + * If set to 1, then this field indicates that the + * PHY is capable of supporting external loopback. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 - /* Stat page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G - /* TQM slow path page size and level. */ - uint8_t tqm_sp_pg_size_tqm_sp_lvl; - /* TQM slow path PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \ + /* + * Reserved field. The HWRM shall set this field to 0. + * An HWRM client shall ignore this field. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ + UINT32_C(0xfc) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2 + /* Number of front panel ports for this device. */ + uint8_t port_cnt; + /* Not supported or unknown */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0) + /* single port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1) + /* 2-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2) + /* 3-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) + /* 4-port device */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ + HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + /* + * This is a bit mask to indicate what speeds are supported + * as forced speeds on this link. + * For each speed that can be forced on this link, the + * corresponding mask bit shall be set to '1'. + */ + uint16_t supported_speeds_force_mode; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \ + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 - /* TQM slow path page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G - /* TQM ring 0 page size and level. */ - uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; - /* TQM ring 0 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \ + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \ + UINT32_C(0x2000) + /* + * This is a bit mask to indicate what speeds are supported + * for autonegotiation on this link. + * For each speed that can be autonegotiated on this link, the + * corresponding mask bit shall be set to '1'. + */ + uint16_t supported_speeds_auto_mode; + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \ + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 - /* TQM ring 0 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G - /* TQM ring 1 page size and level. */ - uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; - /* TQM ring 1 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \ + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \ + UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \ + UINT32_C(0x10) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \ + UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \ + UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \ + UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \ + UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \ + UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \ + UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \ + UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \ + UINT32_C(0x2000) + /* + * This is a bit mask to indicate what speeds are supported + * for EEE on this link. + * For each speed that can be autonegotiated when EEE is enabled + * on this link, the corresponding mask bit shall be set to '1'. + * This field is only valid when the eee_suppotred is set to '1'. + */ + uint16_t supported_speeds_eee_mode; + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \ + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 - /* TQM ring 1 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G - /* TQM ring 2 page size and level. */ - uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; - /* TQM ring 2 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \ + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \ + UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \ + UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \ + UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \ + UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \ + UINT32_C(0x40) + uint32_t tx_lpi_timer_low; + /* + * The lowest value of TX LPI timer that can be set on this link + * when EEE is enabled. This value is in microseconds. + * This field is valid only when_eee_supported is set to '1'. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \ + UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0 + /* + * Reserved field. The HWRM shall set this field to 0. + * An HWRM client shall ignore this field. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \ + UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24 + uint32_t valid_tx_lpi_timer_high; + /* + * The highest value of TX LPI timer that can be set on this link + * when EEE is enabled. This value is in microseconds. + * This field is valid only when_eee_supported is set to '1'. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \ + UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0 + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ + UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 +} __attribute__((packed)); + +/*************************** + * hwrm_port_phy_i2c_write * + ***************************/ + + +/* hwrm_port_phy_i2c_write_input (size:832b/104B) */ +struct hwrm_port_phy_i2c_write_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the page_offset field to be + * configured. + */ + #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 - /* TQM ring 2 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G - /* TQM ring 3 page size and level. */ - uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; - /* TQM ring 3 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \ + /* Port ID of port. */ + uint16_t port_id; + /* 8-bit I2C slave address. */ + uint8_t i2c_slave_addr; + uint8_t unused_0; + /* The page number that is being accessed over I2C. */ + uint16_t page_number; + /* Offset within the page that is being accessed over I2C. */ + uint16_t page_offset; + /* + * Length of data to write, in bytes starting at the offset + * specified above. If the offset is not specified, then + * the data shall be written from the beginning of the page. + */ + uint8_t data_length; + uint8_t unused_1[7]; + /* Up to 64B of data. */ + uint32_t data[16]; +} __attribute__((packed)); + +/* hwrm_port_phy_i2c_write_output (size:128b/16B) */ +struct hwrm_port_phy_i2c_write_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_port_phy_i2c_read * + **************************/ + + +/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ +struct hwrm_port_phy_i2c_read_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the page_offset field to be + * configured. + */ + #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \ - UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 - /* TQM ring 3 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G - /* TQM ring 4 page size and level. */ - uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; - /* TQM ring 4 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \ + /* Port ID of port. */ + uint16_t port_id; + /* 8-bit I2C slave address. */ + uint8_t i2c_slave_addr; + uint8_t unused_0; + /* The page number that is being accessed over I2C. */ + uint16_t page_number; + /* Offset within the page that is being accessed over I2C. */ + uint16_t page_offset; + /* + * Length of data to read, in bytes starting at the offset + * specified above. If the offset is not specified, then + * the data shall be read from the beginning of the page. + */ + uint8_t data_length; + uint8_t unused_1[7]; +} __attribute__((packed)); + +/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ +struct hwrm_port_phy_i2c_read_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Up to 64B of data. */ + uint32_t data[16]; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_port_led_cfg * + *********************/ + + +/* hwrm_port_led_cfg_input (size:512b/64B) */ +struct hwrm_port_led_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the led0_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the led0_state field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the led0_color field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \ + UINT32_C(0x4) + /* + * This bit must be '1' for the led0_blink_on field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \ + UINT32_C(0x8) + /* + * This bit must be '1' for the led0_blink_off field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \ + UINT32_C(0x10) + /* + * This bit must be '1' for the led0_group_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the led1_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the led1_state field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the led1_color field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \ + UINT32_C(0x100) + /* + * This bit must be '1' for the led1_blink_on field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \ + UINT32_C(0x200) + /* + * This bit must be '1' for the led1_blink_off field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \ + UINT32_C(0x400) + /* + * This bit must be '1' for the led1_group_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \ + UINT32_C(0x800) + /* + * This bit must be '1' for the led2_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the led2_state field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the led2_color field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the led2_blink_on field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the led2_blink_off field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the led2_group_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the led3_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \ + UINT32_C(0x40000) + /* + * This bit must be '1' for the led3_state field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \ + UINT32_C(0x80000) + /* + * This bit must be '1' for the led3_color field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \ + UINT32_C(0x100000) + /* + * This bit must be '1' for the led3_blink_on field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \ + UINT32_C(0x200000) + /* + * This bit must be '1' for the led3_blink_off field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \ + UINT32_C(0x400000) + /* + * This bit must be '1' for the led3_group_id field to be + * configured. + */ + #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \ + UINT32_C(0x800000) + /* Port ID of port whose LEDs are configured. */ + uint16_t port_id; + /* + * The number of LEDs that are being configured. + * Up to 4 LEDs can be configured with this command. + */ + uint8_t num_leds; + /* Reserved field. */ + uint8_t rsvd; + /* An identifier for the LED #0. */ + uint8_t led0_id; + /* The requested state of the LED #0. */ + uint8_t led0_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT + /* The requested color of LED #0. */ + uint8_t led0_color; + /* Default */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER + uint8_t unused_0; + /* + * If the LED #0 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led0_blink_on; + /* + * If the LED #0 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led0_blink_off; + /* + * An identifier for the group of LEDs that LED #0 belongs + * to. + * If set to 0, then the LED #0 shall not be grouped and + * shall be treated as an individual resource. + * For all other non-zero values of this field, LED #0 shall + * be grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led0_group_id; + /* Reserved field. */ + uint8_t rsvd0; + /* An identifier for the LED #1. */ + uint8_t led1_id; + /* The requested state of the LED #1. */ + uint8_t led1_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT + /* The requested color of LED #1. */ + uint8_t led1_color; + /* Default */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER + uint8_t unused_1; + /* + * If the LED #1 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led1_blink_on; + /* + * If the LED #1 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led1_blink_off; + /* + * An identifier for the group of LEDs that LED #1 belongs + * to. + * If set to 0, then the LED #1 shall not be grouped and + * shall be treated as an individual resource. + * For all other non-zero values of this field, LED #1 shall + * be grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led1_group_id; + /* Reserved field. */ + uint8_t rsvd1; + /* An identifier for the LED #2. */ + uint8_t led2_id; + /* The requested state of the LED #2. */ + uint8_t led2_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT + /* The requested color of LED #2. */ + uint8_t led2_color; + /* Default */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER + uint8_t unused_2; + /* + * If the LED #2 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led2_blink_on; + /* + * If the LED #2 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led2_blink_off; + /* + * An identifier for the group of LEDs that LED #2 belongs + * to. + * If set to 0, then the LED #2 shall not be grouped and + * shall be treated as an individual resource. + * For all other non-zero values of this field, LED #2 shall + * be grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led2_group_id; + /* Reserved field. */ + uint8_t rsvd2; + /* An identifier for the LED #3. */ + uint8_t led3_id; + /* The requested state of the LED #3. */ + uint8_t led3_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT + /* The requested color of LED #3. */ + uint8_t led3_color; + /* Default */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \ + HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER + uint8_t unused_3; + /* + * If the LED #3 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led3_blink_on; + /* + * If the LED #3 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led3_blink_off; + /* + * An identifier for the group of LEDs that LED #3 belongs + * to. + * If set to 0, then the LED #3 shall not be grouped and + * shall be treated as an individual resource. + * For all other non-zero values of this field, LED #3 shall + * be grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led3_group_id; + /* Reserved field. */ + uint8_t rsvd3; +} __attribute__((packed)); + +/* hwrm_port_led_cfg_output (size:128b/16B) */ +struct hwrm_port_led_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_port_led_qcfg * + **********************/ + + +/* hwrm_port_led_qcfg_input (size:192b/24B) */ +struct hwrm_port_led_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port whose LED configuration is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_led_qcfg_output (size:448b/56B) */ +struct hwrm_port_led_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of LEDs that are configured on this port. + * Up to 4 LEDs can be returned in the response. + */ + uint8_t num_leds; + /* An identifier for the LED #0. */ + uint8_t led0_id; + /* The type of LED #0. */ + uint8_t led0_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID + /* The current state of the LED #0. */ + uint8_t led0_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT + /* The color of LED #0. */ + uint8_t led0_color; + /* Default */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER + uint8_t unused_0; + /* + * If the LED #0 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led0_blink_on; + /* + * If the LED #0 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led0_blink_off; + /* + * An identifier for the group of LEDs that LED #0 belongs + * to. + * If set to 0, then the LED #0 is not grouped. + * For all other non-zero values of this field, LED #0 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led0_group_id; + /* An identifier for the LED #1. */ + uint8_t led1_id; + /* The type of LED #1. */ + uint8_t led1_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID + /* The current state of the LED #1. */ + uint8_t led1_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT + /* The color of LED #1. */ + uint8_t led1_color; + /* Default */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER + uint8_t unused_1; + /* + * If the LED #1 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led1_blink_on; + /* + * If the LED #1 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led1_blink_off; + /* + * An identifier for the group of LEDs that LED #1 belongs + * to. + * If set to 0, then the LED #1 is not grouped. + * For all other non-zero values of this field, LED #1 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led1_group_id; + /* An identifier for the LED #2. */ + uint8_t led2_id; + /* The type of LED #2. */ + uint8_t led2_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID + /* The current state of the LED #2. */ + uint8_t led2_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT + /* The color of LED #2. */ + uint8_t led2_color; + /* Default */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER + uint8_t unused_2; + /* + * If the LED #2 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led2_blink_on; + /* + * If the LED #2 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led2_blink_off; + /* + * An identifier for the group of LEDs that LED #2 belongs + * to. + * If set to 0, then the LED #2 is not grouped. + * For all other non-zero values of this field, LED #2 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led2_group_id; + /* An identifier for the LED #3. */ + uint8_t led3_id; + /* The type of LED #3. */ + uint8_t led3_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID + /* The current state of the LED #3. */ + uint8_t led3_state; + /* Default state of the LED */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0) + /* Off */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1) + /* On */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2) + /* Blink */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3) + /* Blink Alternately */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT + /* The color of LED #3. */ + uint8_t led3_color; + /* Default */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0) + /* Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1) + /* Green */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2) + /* Green or Amber */ + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3) + #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \ + HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER + uint8_t unused_3; + /* + * If the LED #3 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED on between cycles. + */ + uint16_t led3_blink_on; + /* + * If the LED #3 state is "blink" or "blinkalt", then + * this field represents the requested time in milliseconds + * to keep LED off between cycles. + */ + uint16_t led3_blink_off; + /* + * An identifier for the group of LEDs that LED #3 belongs + * to. + * If set to 0, then the LED #3 is not grouped. + * For all other non-zero values of this field, LED #3 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led3_group_id; + uint8_t unused_4[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_port_led_qcaps * + ***********************/ + + +/* hwrm_port_led_qcaps_input (size:192b/24B) */ +struct hwrm_port_led_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port whose LED configuration is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_led_qcaps_output (size:384b/48B) */ +struct hwrm_port_led_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of LEDs that are configured on this port. + * Up to 4 LEDs can be returned in the response. + */ + uint8_t num_leds; + /* Reserved for future use. */ + uint8_t unused[3]; + /* An identifier for the LED #0. */ + uint8_t led0_id; + /* The type of LED #0. */ + uint8_t led0_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \ + HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID + /* + * An identifier for the group of LEDs that LED #0 belongs + * to. + * If set to 0, then the LED #0 cannot be grouped. + * For all other non-zero values of this field, LED #0 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led0_group_id; + uint8_t unused_0; + /* The states supported by LED #0. */ + uint16_t led0_state_caps; + /* + * If set to 1, this LED is enabled. + * If set to 0, this LED is disabled. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \ + /* + * If set to 1, off state is supported on this LED. + * If set to 0, off state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 - /* TQM ring 4 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G - /* TQM ring 5 page size and level. */ - uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; - /* TQM ring 5 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \ + /* + * If set to 1, on state is supported on this LED. + * If set to 0, on state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, blink state is supported on this LED. + * If set to 0, blink state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \ + UINT32_C(0x8) + /* + * If set to 1, blink_alt state is supported on this LED. + * If set to 0, blink_alt state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \ + UINT32_C(0x10) + /* The colors supported by LED #0. */ + uint16_t led0_color_caps; + /* reserved. */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \ + /* + * If set to 1, Amber color is supported on this LED. + * If set to 0, Amber color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 - /* TQM ring 5 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G - /* TQM ring 6 page size and level. */ - uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; - /* TQM ring 6 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \ + /* + * If set to 1, Green color is supported on this LED. + * If set to 0, Green color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \ + UINT32_C(0x4) + /* An identifier for the LED #1. */ + uint8_t led1_id; + /* The type of LED #1. */ + uint8_t led1_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \ + HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID + /* + * An identifier for the group of LEDs that LED #1 belongs + * to. + * If set to 0, then the LED #0 cannot be grouped. + * For all other non-zero values of this field, LED #0 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led1_group_id; + uint8_t unused_1; + /* The states supported by LED #1. */ + uint16_t led1_state_caps; + /* + * If set to 1, this LED is enabled. + * If set to 0, this LED is disabled. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \ + /* + * If set to 1, off state is supported on this LED. + * If set to 0, off state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 - /* TQM ring 6 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G - /* TQM ring 7 page size and level. */ - uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; - /* TQM ring 7 PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \ + /* + * If set to 1, on state is supported on this LED. + * If set to 0, on state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, blink state is supported on this LED. + * If set to 0, blink state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \ + UINT32_C(0x8) + /* + * If set to 1, blink_alt state is supported on this LED. + * If set to 0, blink_alt state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \ + UINT32_C(0x10) + /* The colors supported by LED #1. */ + uint16_t led1_color_caps; + /* reserved. */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \ + /* + * If set to 1, Amber color is supported on this LED. + * If set to 0, Amber color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \ + UINT32_C(0x2) + /* + * If set to 1, Green color is supported on this LED. + * If set to 0, Green color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \ + UINT32_C(0x4) + /* An identifier for the LED #2. */ + uint8_t led2_id; + /* The type of LED #2. */ + uint8_t led2_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \ + HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID + /* + * An identifier for the group of LEDs that LED #0 belongs + * to. + * If set to 0, then the LED #0 cannot be grouped. + * For all other non-zero values of this field, LED #0 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led2_group_id; + uint8_t unused_2; + /* The states supported by LED #2. */ + uint16_t led2_state_caps; + /* + * If set to 1, this LED is enabled. + * If set to 0, this LED is disabled. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \ + UINT32_C(0x1) + /* + * If set to 1, off state is supported on this LED. + * If set to 0, off state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 - /* TQM ring 7 page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G - /* MR/AV page size and level. */ - uint8_t mrav_pg_size_mrav_lvl; - /* MR/AV PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \ + /* + * If set to 1, on state is supported on this LED. + * If set to 0, on state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, blink state is supported on this LED. + * If set to 0, blink state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \ + UINT32_C(0x8) + /* + * If set to 1, blink_alt state is supported on this LED. + * If set to 0, blink_alt state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \ + UINT32_C(0x10) + /* The colors supported by LED #2. */ + uint16_t led2_color_caps; + /* reserved. */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \ + /* + * If set to 1, Amber color is supported on this LED. + * If set to 0, Amber color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 - /* MR/AV page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G - /* Timer page size and level. */ - uint8_t tim_pg_size_tim_lvl; - /* Timer PBL indirect levels. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \ - UINT32_C(0xf) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \ - UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \ + /* + * If set to 1, Green color is supported on this LED. + * If set to 0, Green color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \ + UINT32_C(0x4) + /* An identifier for the LED #3. */ + uint8_t led3_id; + /* The type of LED #3. */ + uint8_t led3_type; + /* Speed LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0) + /* Activity LED */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1) + /* Invalid */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff) + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \ + HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID + /* + * An identifier for the group of LEDs that LED #3 belongs + * to. + * If set to 0, then the LED #0 cannot be grouped. + * For all other non-zero values of this field, LED #0 is + * grouped together with the LEDs with the same group ID + * value. + */ + uint8_t led3_group_id; + uint8_t unused_3; + /* The states supported by LED #3. */ + uint16_t led3_state_caps; + /* + * If set to 1, this LED is enabled. + * If set to 0, this LED is disabled. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \ UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \ + /* + * If set to 1, off state is supported on this LED. + * If set to 0, off state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \ UINT32_C(0x2) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 - /* Timer page size. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \ - UINT32_C(0xf0) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \ - (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \ - (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \ - (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \ - (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \ - (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \ - (UINT32_C(0x5) << 4) - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \ - HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G - /* QP page directory. */ - uint64_t qpc_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* VNIC page directory. */ - uint64_t vnic_page_dir; - /* Stat page directory. */ - uint64_t stat_page_dir; - /* TQM slowpath page directory. */ - uint64_t tqm_sp_page_dir; - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; - /* MR/AV page directory. */ - uint64_t mrav_page_dir; - /* Timer page directory. */ - uint64_t tim_page_dir; - /* Number of entries to reserve for QP1 */ - uint16_t qp_num_qp1_entries; - /* Number of entries to reserve for L2 */ - uint16_t qp_num_l2_entries; - /* Number of QPs. */ - uint32_t qp_num_entries; - /* Number of SRQs. */ - uint32_t srq_num_entries; - /* Number of entries to reserve for L2 */ - uint16_t srq_num_l2_entries; - /* Number of entries to reserve for L2 */ - uint16_t cq_num_l2_entries; - /* Number of CQs. */ - uint32_t cq_num_entries; - /* Number of entries to reserve for VNIC entries */ - uint16_t vnic_num_vnic_entries; - /* Number of entries to reserve for Ring table entries */ - uint16_t vnic_num_ring_table_entries; - /* Number of Stats. */ - uint32_t stat_num_entries; - /* Number of TQM slowpath entries. */ - uint32_t tqm_sp_num_entries; - /* Number of TQM ring 0 entries. */ - uint32_t tqm_ring0_num_entries; - /* Number of TQM ring 1 entries. */ - uint32_t tqm_ring1_num_entries; - /* Number of TQM ring 2 entries. */ - uint32_t tqm_ring2_num_entries; - /* Number of TQM ring 3 entries. */ - uint32_t tqm_ring3_num_entries; - /* Number of TQM ring 4 entries. */ - uint32_t tqm_ring4_num_entries; - /* Number of TQM ring 5 entries. */ - uint32_t tqm_ring5_num_entries; - /* Number of TQM ring 6 entries. */ - uint32_t tqm_ring6_num_entries; - /* Number of TQM ring 7 entries. */ - uint32_t tqm_ring7_num_entries; - /* Number of MR/AV entries. */ - uint32_t mrav_num_entries; - /* Number of Timer entries. */ - uint32_t tim_num_entries; - uint8_t unused_1[7]; + /* + * If set to 1, on state is supported on this LED. + * If set to 0, on state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, blink state is supported on this LED. + * If set to 0, blink state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \ + UINT32_C(0x8) + /* + * If set to 1, blink_alt state is supported on this LED. + * If set to 0, blink_alt state is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \ + UINT32_C(0x10) + /* The colors supported by LED #3. */ + uint16_t led3_color_caps; + /* reserved. */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \ + UINT32_C(0x1) + /* + * If set to 1, Amber color is supported on this LED. + * If set to 0, Amber color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \ + UINT32_C(0x2) + /* + * If set to 1, Green color is supported on this LED. + * If set to 0, Green color is not supported on this LED. + */ + #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \ + UINT32_C(0x4) + uint8_t unused_4[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8394,13 +13729,13 @@ struct hwrm_func_backing_store_qcfg_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_port_phy_cfg * - *********************/ +/*********************** + * hwrm_queue_qportcfg * + ***********************/ -/* hwrm_port_phy_cfg_input (size:448b/56B) */ -struct hwrm_port_phy_cfg_input { +/* hwrm_queue_qportcfg_input (size:192b/24B) */ +struct hwrm_queue_qportcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -8430,506 +13765,475 @@ struct hwrm_port_phy_cfg_input { uint64_t resp_addr; uint32_t flags; /* - * When this bit is set to '1', the PHY for the port shall - * be reset. - * - * # If this bit is set to 1, then the HWRM shall reset the - * PHY after applying PHY configuration changes specified - * in this command. - * # In order to guarantee that PHY configuration changes - * specified in this command take effect, the HWRM - * client should set this flag to 1. - * # If this bit is not set to 1, then the HWRM may reset - * the PHY depending on the current PHY configuration and - * settings specified in this command. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \ - UINT32_C(0x1) - /* deprecated bit. Do not use!!! */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ - UINT32_C(0x2) - /* - * When this bit is set to '1', the link shall be forced to - * the force_link_speed value. - * - * When this bit is set to '1', the HWRM client should - * not enable any of the auto negotiation related - * fields represented by auto_XXX fields in this command. - * When this bit is set to '1' and the HWRM client has - * enabled a auto_XXX field in this command, then the - * HWRM shall ignore the enabled auto_XXX field. - * - * When this bit is set to zero, the link - * shall be allowed to autoneg. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \ - UINT32_C(0x4) - /* - * When this bit is set to '1', the auto-negotiation process - * shall be restarted on the link. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \ - UINT32_C(0x8) - /* - * When this bit is set to '1', Energy Efficient Ethernet - * (EEE) is requested to be enabled on this link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \ - UINT32_C(0x10) - /* - * When this bit is set to '1', Energy Efficient Ethernet - * (EEE) is requested to be disabled on this link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \ - UINT32_C(0x20) - /* - * When this bit is set to '1' and EEE is enabled on this - * link, then TX LPI is requested to be enabled on the link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - * If EEE is disabled on this port, then this flag shall be - * ignored by the HWRM. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \ - UINT32_C(0x40) - /* - * When this bit is set to '1' and EEE is enabled on this - * link, then TX LPI is requested to be disabled on the link. - * If EEE is not supported on this port, then this flag - * shall be ignored by the HWRM. - * If EEE is disabled on this port, then this flag shall be - * ignored by the HWRM. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \ - UINT32_C(0x80) - /* - * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \ - UINT32_C(0x100) - /* - * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \ - UINT32_C(0x200) - /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \ - UINT32_C(0x400) - /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \ - UINT32_C(0x800) - /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \ - UINT32_C(0x1000) - /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon) - * on this port if supported. - * When set to 0, then this flag shall be ignored. - * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this - * flag. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \ - UINT32_C(0x2000) - /* - * When this bit is set to '1', the link shall be forced to - * be taken down. - * - * # When this bit is set to '1", all other - * command input settings related to the link speed shall - * be ignored. - * Once the link state is forced down, it can be - * explicitly cleared from that state by setting this flag - * to '0'. - * # If this flag is set to '0', then the link shall be - * cleared from forced down state if the link is in forced - * down state. - * There may be conditions (e.g. out-of-band or sideband - * configuration changes for the link) outside the scope - * of the HWRM implementation that may clear forced down - * link state. - */ - #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \ - UINT32_C(0x4000) - uint32_t enables; - /* - * This bit must be '1' for the auto_mode field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \ - UINT32_C(0x1) - /* - * This bit must be '1' for the auto_duplex field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \ - UINT32_C(0x2) - /* - * This bit must be '1' for the auto_pause field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \ - UINT32_C(0x4) - /* - * This bit must be '1' for the auto_link_speed field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \ - UINT32_C(0x8) - /* - * This bit must be '1' for the auto_link_speed_mask field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \ - UINT32_C(0x10) - /* - * This bit must be '1' for the wirespeed field to be - * configured. - */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \ - UINT32_C(0x20) - /* - * This bit must be '1' for the lpbk field to be - * configured. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \ - UINT32_C(0x40) + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX /* - * This bit must be '1' for the preemphasis field to be - * configured. + * Port ID of port for which the queue configuration is being + * queried. This field is only required when sent by IPC. */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \ - UINT32_C(0x80) + uint16_t port_id; /* - * This bit must be '1' for the force_pause field to be - * configured. + * Drivers will set this capability when it can use + * queue_idx_service_profile to map the queues to application. */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \ - UINT32_C(0x100) + uint8_t drv_qmap_cap; + /* disabled */ + #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0) + /* enabled */ + #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \ + HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED + uint8_t unused_0; +} __attribute__((packed)); + +/* hwrm_queue_qportcfg_output (size:256b/32B) */ +struct hwrm_queue_qportcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This bit must be '1' for the eee_link_speed_mask field to be - * configured. + * The maximum number of queues that can be configured on this + * port. + * Valid values range from 1 through 8. */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \ - UINT32_C(0x200) + uint8_t max_configurable_queues; /* - * This bit must be '1' for the tx_lpi_timer field to be - * configured. + * The maximum number of lossless queues that can be configured + * on this port. + * Valid values range from 0 through 8. */ - #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \ - UINT32_C(0x400) - /* Port ID of port that is to be configured. */ - uint16_t port_id; + uint8_t max_configurable_lossless_queues; /* - * This is the speed that will be used if the force - * bit is '1'. If unsupported speed is selected, an error - * will be generated. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_cfg command. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * # A value of 0 indicates that the queue is not configurable + * by the hwrm_queue_cfg command. + * # A value of 1 indicates that the queue is configurable. + * # A hwrm_queue_cfg command shall return error when trying to + * configure a queue not configurable. */ - uint16_t force_link_speed; - /* 100Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) - /* 1Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) - /* 20Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 10Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \ - HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB + uint8_t queue_cfg_allowed; + /* Information about queue configuration. */ + uint8_t queue_cfg_info; /* - * This value is used to identify what autoneg mode is - * used when the link speed is not being forced. + * If this flag is set to '1', then the queues are + * configured asymmetrically on TX and RX sides. + * If this flag is set to '0', then the queues are + * configured symmetrically on TX and RX sides. For + * symmetric configuration, the queue configuration + * including queue ids and service profiles on the + * TX side is the same as the corresponding queue + * configuration on the RX side. */ - uint8_t auto_mode; - /* Disable autoneg or autoneg disabled. No speeds are selected. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0) - /* Select all possible speeds for autoneg mode. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_pfcenable_cfg command. + * + * Each bit represents a specific priority where bit 0 represents + * priority 0 and bit 7 represents priority 7. + * # A value of 0 indicates that the priority is not configurable by + * the hwrm_queue_pfcenable_cfg command. + * # A value of 1 indicates that the priority is configurable. + * # A hwrm_queue_pfcenable_cfg command shall return error when + * trying to configure a priority that is not configurable. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + uint8_t queue_pfcenable_cfg_allowed; /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_pri2cos_cfg command. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * # A value of 0 indicates that the queue is not configurable + * by the hwrm_queue_pri2cos_cfg command. + * # A value of 1 indicates that the queue is configurable. + * # A hwrm_queue_pri2cos_cfg command shall return error when + * trying to configure a queue that is not configurable. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + uint8_t queue_pri2cos_cfg_allowed; /* - * Select the speeds based on the corresponding link speed mask value - * that is provided. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_pri2cos_cfg command. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * # A value of 0 indicates that the queue is not configurable + * by the hwrm_queue_pri2cos_cfg command. + * # A value of 1 indicates that the queue is configurable. + * # A hwrm_queue_pri2cos_cfg command shall return error when + * trying to configure a queue not configurable. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \ - HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK + uint8_t queue_cos2bw_cfg_allowed; /* - * This is the duplex setting that will be used if the autoneg_mode - * is "one_speed" or "one_or_below". + * ID of CoS Queue 0. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - uint8_t auto_duplex; - /* Half Duplex will be requested. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) - /* Full duplex will be requested. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) - /* Both Half and Full dupex will be requested. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \ - HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH + uint8_t queue_id0; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id0_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN /* - * This value is used to configure the pause that will be - * used for autonegotiation. - * Add text on the usage of auto_pause and force_pause. + * ID of CoS Queue 1. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - uint8_t auto_pause; + uint8_t queue_id1; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id1_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN /* - * When this bit is '1', Generation of tx pause messages - * has been requested. Disabled otherwise. + * ID of CoS Queue 2. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \ + uint8_t queue_id2; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id2_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN /* - * When this bit is '1', Reception of rx pause messages - * has been requested. Disabled otherwise. + * ID of CoS Queue 3. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \ + uint8_t queue_id3; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id3_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN /* - * When set to 1, the advertisement of pause is enabled. + * ID of CoS Queue 4. + * FF - Invalid id * - * # When the auto_mode is not set to none and this flag is - * set to 1, then the auto_pause bits on this port are being - * advertised and autoneg pause results are being interpreted. - * # When the auto_mode is not set to none and this - * flag is set to 0, the pause is forced as indicated in - * force_pause, and also advertised as auto_pause bits, but - * the autoneg results are not interpreted since the pause - * configuration is being forced. - * # When the auto_mode is set to none and this flag is set to - * 1, auto_pause bits should be ignored and should be set to 0. - */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \ - UINT32_C(0x4) - uint8_t unused_0; - /* - * This is the speed that will be used if the autoneg_mode - * is "one_speed" or "one_or_below". If an unsupported speed - * is selected, an error will be generated. - */ - uint16_t auto_link_speed; - /* 100Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) - /* 1Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) - /* 20Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 10Mb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \ - HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB - /* - * This is a mask of link speeds that will be used if - * autoneg_mode is "mask". If unsupported speed is enabled - * an error will be generated. + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - uint16_t auto_link_speed_mask; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \ + uint8_t queue_id4; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id4_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \ UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \ + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \ UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \ - UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \ - UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \ - UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \ - UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \ - UINT32_C(0x2000) - /* This value controls the wirespeed feature. */ - uint8_t wirespeed; - /* Wirespeed feature is disabled. */ - #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0) - /* Wirespeed feature is enabled. */ - #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1) - #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \ - HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON - /* This value controls the loopback setting for the PHY. */ - uint8_t lpbk; - /* No loopback is selected. Normal operation. */ - #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN /* - * The HW will be configured with local loopback such that - * host data is sent back to the host without modification. + * ID of CoS Queue 5. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + uint8_t queue_id5; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id5_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN /* - * The HW will be configured with remote loopback such that - * port logic will send packets back out the transmitter that - * are received. + * ID of CoS Queue 6. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t queue_id6; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id6_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN /* - * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external - * loopback connection the data will be received without modification. + * ID of CoS Queue 7. + * FF - Invalid id + * + * # This ID can be used on any subsequent call to an hwrm command + * that takes a queue id. + * # IDs must always be queried by this command before any use + * by the driver or software. + * # Any driver or software should not make any assumptions about + * queue IDs. + * # A value of 0xff indicates that the queue is not available. + * # Available queues may not be in sequential order. */ - #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) - #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \ - HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL + uint8_t queue_id7; + /* This value is applicable to CoS queues only. */ + uint8_t queue_id7_service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ + UINT32_C(0x0) + /* Lossless (legacy) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ + UINT32_C(0x1) + /* Lossless RoCE */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ + UINT32_C(0x1) + /* Lossy RoCE CNP */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + UINT32_C(0x2) + /* Lossless NIC */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ + UINT32_C(0x3) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \ + UINT32_C(0xff) + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN /* - * This value is used to configure the pause that will be - * used for force mode. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t force_pause; + uint8_t valid; +} __attribute__((packed)); + +/******************* + * hwrm_queue_qcfg * + *******************/ + + +/* hwrm_queue_qcfg_input (size:192b/24B) */ +struct hwrm_queue_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', Generation of tx pause messages - * is supported. Disabled otherwise. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1) + uint16_t cmpl_ring; /* - * When this bit is '1', Reception of rx pause messages - * is supported. Disabled otherwise. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2) - uint8_t unused_1; + uint16_t seq_id; /* - * This value controls the pre-emphasis to be used for the - * link. Driver should not set this value (use - * enable.preemphasis = 0) unless driver is sure of setting. - * Normally HWRM FW will determine proper pre-emphasis. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint32_t preemphasis; + uint16_t target_id; /* - * Setting for link speed mask that is used to - * advertise speeds during autonegotiation when EEE is enabled. - * This field is valid only when EEE is enabled. - * The speeds specified in this field shall be a subset of - * speeds specified in auto_link_speed_mask. - * If EEE is enabled,then at least one speed shall be provided - * in this mask. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t eee_link_speed_mask; - /* Reserved */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \ - UINT32_C(0x2) - /* Reserved */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \ - UINT32_C(0x8) - /* Reserved */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \ - UINT32_C(0x10) - /* Reserved */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \ - UINT32_C(0x40) - uint8_t unused_2[2]; + uint64_t resp_addr; + uint32_t flags; /* - * Reuested setting of TX LPI timer in microseconds. - * This field is valid only when EEE is enabled and TX LPI is - * enabled. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint32_t tx_lpi_timer; - #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) - #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 - uint32_t unused_3; + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX + /* Queue ID of the queue. */ + uint32_t queue_id; } __attribute__((packed)); -/* hwrm_port_phy_cfg_output (size:128b/16B) */ -struct hwrm_port_phy_cfg_output { +/* hwrm_queue_qcfg_output (size:128b/16B) */ +struct hwrm_queue_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -8938,7 +14242,32 @@ struct hwrm_port_phy_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This value is a the estimate packet length used in the + * TX arbiter. + */ + uint32_t queue_len; + /* This value is applicable to CoS queues only. */ + uint8_t service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN + /* Information about queue configuration. */ + uint8_t queue_cfg_info; + /* + * If this flag is set to '1', then the queue is + * configured asymmetrically on TX and RX sides. + * If this flag is set to '0', then this queue is + * configured symmetrically on TX and RX sides. + */ + #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + UINT32_C(0x1) + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8949,42 +14278,116 @@ struct hwrm_port_phy_cfg_output { uint8_t valid; } __attribute__((packed)); -/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ -struct hwrm_port_phy_cfg_cmd_err { +/****************** + * hwrm_queue_cfg * + ******************/ + + +/* hwrm_queue_cfg_input (size:320b/40B) */ +struct hwrm_queue_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t code; - /* Unknown error */ - #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to invalid speed */ - #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1) + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX, or both directions applicable to the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 + /* tx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + /* Bi-directional (Symmetrically applicable to TX and RX paths) */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR + uint32_t enables; + /* + * This bit must be '1' for the dflt_len field to be + * configured. + */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1) + /* + * This bit must be '1' for the service_profile field to be + * configured. + */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2) + /* Queue ID of queue that is to be configured by this function. */ + uint32_t queue_id; + /* + * This value is a the estimate packet length used in the + * TX arbiter. + * Set to 0xFF... (All Fs) to not adjust this value. + */ + uint32_t dflt_len; + /* This value is applicable to CoS queues only. */ + uint8_t service_profile; + /* Lossy (best-effort) */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ + HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* hwrm_queue_cfg_output (size:128b/16B) */ +struct hwrm_queue_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * retry the command since the phy is not ready. - * retry count is returned in opaque_0. - * This is only valid for the first command and - * this value will not change for successive calls. - * but if a 0 is returned at any time then this should - * be treated as an un recoverable failure, - * - * retry interval in milli seconds is returned in opaque_1. - * This specifies the time that user should wait before - * issuing the next port_phy_cfg command. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2) - #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \ - HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY - uint8_t unused_0[7]; + uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_port_phy_qcfg * - **********************/ +/***************************** + * hwrm_queue_pfcenable_qcfg * + *****************************/ -/* hwrm_port_phy_qcfg_input (size:192b/24B) */ -struct hwrm_port_phy_qcfg_input { +/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ +struct hwrm_queue_pfcenable_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9012,13 +14415,17 @@ struct hwrm_port_phy_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port that is to be queried. */ + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ uint16_t port_id; uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_port_phy_qcfg_output (size:768b/96B) */ -struct hwrm_port_phy_qcfg_output { +/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ +struct hwrm_queue_pfcenable_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -9027,809 +14434,447 @@ struct hwrm_port_phy_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value indicates the current link status. */ - uint8_t link; - /* There is no link or cable detected. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0) - /* There is no link, but a cable has been detected. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1) - /* There is a link. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2) - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK - uint8_t unused_0; - /* This value indicates the current link speed of the connection. */ - uint16_t link_speed; - /* 100Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1) - /* 1Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64) - /* 20Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 10Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff) - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB - /* - * This value is indicates the duplex of the current - * configuration. - */ - uint8_t duplex_cfg; - /* Half Duplex connection. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0) - /* Full duplex connection. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1) - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL - /* - * This value is used to indicate the current - * pause configuration. When autoneg is enabled, this value - * represents the autoneg results of pause configuration. - */ - uint8_t pause; - /* - * When this bit is '1', Generation of tx pause messages - * is supported. Disabled otherwise. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1) - /* - * When this bit is '1', Reception of rx pause messages - * is supported. Disabled otherwise. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2) - /* - * The supported speeds for the port. This is a bit mask. - * For each speed that is supported, the corrresponding - * bit will be set to '1'. - */ - uint16_t support_speeds; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \ + uint32_t flags; + /* If set to 1, then PFC is enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \ UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \ + /* If set to 1, then PFC is enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \ UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \ + /* If set to 1, then PFC is enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \ UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \ + /* If set to 1, then PFC is enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \ UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \ + /* If set to 1, then PFC is enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \ UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \ + /* If set to 1, then PFC is enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \ UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \ + /* If set to 1, then PFC is enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \ UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \ + /* If set to 1, then PFC is enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \ - UINT32_C(0x2000) - /* - * Current setting of forced link speed. - * When the link speed is not being forced, this - * value shall be set to 0. - */ - uint16_t force_link_speed; - /* 100Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) - /* 1Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) - /* 20Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \ - UINT32_C(0x190) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \ - UINT32_C(0x1f4) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \ - UINT32_C(0x3e8) - /* 10Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \ - UINT32_C(0xffff) - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB - /* Current setting of auto negotiation mode. */ - uint8_t auto_mode; - /* Disable autoneg or autoneg disabled. No speeds are selected. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0) - /* Select all possible speeds for autoneg mode. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) - /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) - /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) - /* - * Select the speeds based on the corresponding link speed mask value - * that is provided. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK - /* - * Current setting of pause autonegotiation. - * Move autoneg_pause flag here. - */ - uint8_t auto_pause; + uint8_t unused_0[3]; /* - * When this bit is '1', Generation of tx pause messages - * has been requested. Disabled otherwise. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \ - UINT32_C(0x1) + uint8_t valid; +} __attribute__((packed)); + +/**************************** + * hwrm_queue_pfcenable_cfg * + ****************************/ + + +/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ +struct hwrm_queue_pfcenable_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', Reception of rx pause messages - * has been requested. Disabled otherwise. - */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \ - UINT32_C(0x2) + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; /* - * When set to 1, the advertisement of pause is enabled. - * - * # When the auto_mode is not set to none and this flag is - * set to 1, then the auto_pause bits on this port are being - * advertised and autoneg pause results are being interpreted. - * # When the auto_mode is not set to none and this - * flag is set to 0, the pause is forced as indicated in - * force_pause, and also advertised as auto_pause bits, but - * the autoneg results are not interpreted since the pause - * configuration is being forced. - * # When the auto_mode is set to none and this flag is set to - * 1, auto_pause bits should be ignored and should be set to 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \ - UINT32_C(0x4) + uint16_t seq_id; /* - * Current setting for auto_link_speed. This field is only - * valid when auto_mode is set to "one_speed" or "one_or_below". + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint16_t auto_link_speed; - /* 100Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) - /* 1Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) - /* 20Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) - /* 10Mb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \ - UINT32_C(0xffff) - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB + uint16_t target_id; /* - * Current setting for auto_link_speed_mask that is used to - * advertise speeds during autonegotiation. - * This field is only valid when auto_mode is set to "mask". - * The speeds specified in this field shall be a subset of - * supported speeds on this port. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t auto_link_speed_mask; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \ + uint64_t resp_addr; + uint32_t flags; + /* If set to 1, then PFC is requested to be enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \ UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \ + /* If set to 1, then PFC is requested to be enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \ + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \ + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \ + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \ + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \ + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \ + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \ - UINT32_C(0x2000) - /* Current setting for wirespeed. */ - uint8_t wirespeed; - /* Wirespeed feature is disabled. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0) - /* Wirespeed feature is enabled. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1) - #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON - /* Current setting for loopback. */ - uint8_t lpbk; - /* No loopback is selected. Normal operation. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* - * The HW will be configured with local loopback such that - * host data is sent back to the host without modification. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + uint16_t port_id; + uint8_t unused_0[2]; +} __attribute__((packed)); + +/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ +struct hwrm_queue_pfcenable_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * The HW will be configured with remote loopback such that - * port logic will send packets back out the transmitter that - * are received. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_queue_pri2cos_qcfg * + ***************************/ + + +/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ +struct hwrm_queue_pri2cos_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external - * loopback connection the data will be received without modification. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) - #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL + uint16_t cmpl_ring; /* - * Current setting of forced pause. - * When the pause configuration is not being forced, then - * this value shall be set to 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t force_pause; + uint16_t seq_id; /* - * When this bit is '1', Generation of tx pause messages - * is supported. Disabled otherwise. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX + /* + * When this bit is set to '0', the query is + * for VLAN PRI field in tunnel headers. + * When this bit is set to '1', the query is + * for VLAN PRI field in inner packet headers. + */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; +} __attribute__((packed)); + +/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ +struct hwrm_queue_pri2cos_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * CoS Queue assigned to priority 0. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri0_cos_queue_id; + /* + * CoS Queue assigned to priority 1. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. + */ + uint8_t pri1_cos_queue_id; + /* + * CoS Queue assigned to priority 2 This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1) + uint8_t pri2_cos_queue_id; /* - * When this bit is '1', Reception of rx pause messages - * is supported. Disabled otherwise. + * CoS Queue assigned to priority 3. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2) + uint8_t pri3_cos_queue_id; /* - * This value indicates the current status of the optics module on - * this port. + * CoS Queue assigned to priority 4. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - uint8_t module_status; - /* Module is inserted and accepted */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \ - UINT32_C(0x0) - /* Module is rejected and transmit side Laser is disabled. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \ - UINT32_C(0x1) - /* Module mismatch warning. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \ - UINT32_C(0x2) - /* Module is rejected and powered down. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \ - UINT32_C(0x3) - /* Module is not inserted. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ - UINT32_C(0x4) - /* Module status is not applicable. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ - UINT32_C(0xff) - #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE - /* Current setting for preemphasis. */ - uint32_t preemphasis; - /* This field represents the major version of the PHY. */ - uint8_t phy_maj; - /* This field represents the minor version of the PHY. */ - uint8_t phy_min; - /* This field represents the build version of the PHY. */ - uint8_t phy_bld; - /* This value represents a PHY type. */ - uint8_t phy_type; - /* Unknown */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* BASE-CR */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \ - UINT32_C(0x1) - /* BASE-KR4 (Deprecated) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \ - UINT32_C(0x2) - /* BASE-LR */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \ - UINT32_C(0x3) - /* BASE-SR */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \ - UINT32_C(0x4) - /* BASE-KR2 (Deprecated) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \ - UINT32_C(0x5) - /* BASE-KX */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \ - UINT32_C(0x6) - /* BASE-KR */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \ - UINT32_C(0x7) - /* BASE-T */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \ - UINT32_C(0x8) - /* EEE capable BASE-T */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \ - UINT32_C(0x9) - /* SGMII connected external PHY */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \ - UINT32_C(0xa) - /* 25G_BASECR_CA_L */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \ - UINT32_C(0xb) - /* 25G_BASECR_CA_S */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \ - UINT32_C(0xc) - /* 25G_BASECR_CA_N */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \ - UINT32_C(0xd) - /* 25G_BASESR */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \ - UINT32_C(0xe) - /* 100G_BASECR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \ - UINT32_C(0xf) - /* 100G_BASESR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \ - UINT32_C(0x10) - /* 100G_BASELR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \ - UINT32_C(0x11) - /* 100G_BASEER4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \ - UINT32_C(0x12) - /* 100G_BASESR10 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \ - UINT32_C(0x13) - /* 40G_BASECR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \ - UINT32_C(0x14) - /* 40G_BASESR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \ - UINT32_C(0x15) - /* 40G_BASELR4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \ - UINT32_C(0x16) - /* 40G_BASEER4 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \ - UINT32_C(0x17) - /* 40G_ACTIVE_CABLE */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \ - UINT32_C(0x18) - /* 1G_baseT */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \ - UINT32_C(0x19) - /* 1G_baseSX */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \ - UINT32_C(0x1a) - /* 1G_baseCX */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \ - UINT32_C(0x1b) - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX - /* This value represents a media type. */ - uint8_t media_type; - /* Unknown */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0) - /* Twisted Pair */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1) - /* Direct Attached Copper */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2) - /* Fiber */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3) - #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE - /* This value represents a transceiver type. */ - uint8_t xcvr_pkg_type; - /* PHY and MAC are in the same package */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \ - UINT32_C(0x1) - /* PHY and MAC are in different packages */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \ - UINT32_C(0x2) - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL - uint8_t eee_config_phy_addr; - /* This field represents PHY address. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \ - UINT32_C(0x1f) - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0 + uint8_t pri4_cos_queue_id; /* - * This field represents flags related to EEE configuration. - * These EEE configuration flags are valid only when the - * auto_mode is not set to none (in other words autonegotiation - * is enabled). + * CoS Queue assigned to priority 5. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \ - UINT32_C(0xe0) - #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5 + uint8_t pri5_cos_queue_id; /* - * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled. - * Speeds for autoneg with EEE mode enabled - * are based on eee_link_speed_mask. + * CoS Queue assigned to priority 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \ - UINT32_C(0x20) + uint8_t pri6_cos_queue_id; /* - * This flag is valid only when eee_enabled is set to 1. - * - * # If eee_enabled is set to 0, then EEE mode is disabled - * and this flag shall be ignored. - * # If eee_enabled is set to 1 and this flag is set to 1, - * then Energy Efficient Ethernet (EEE) mode is enabled - * and in use. - * # If eee_enabled is set to 1 and this flag is set to 0, - * then Energy Efficient Ethernet (EEE) mode is enabled - * but is currently not in use. + * CoS Queue assigned to priority 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no CoS queue is assigned to the + * specified priority. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \ - UINT32_C(0x40) + uint8_t pri7_cos_queue_id; + /* Information about queue configuration. */ + uint8_t queue_cfg_info; /* - * This flag is valid only when eee_enabled is set to 1. - * - * # If eee_enabled is set to 0, then EEE mode is disabled - * and this flag shall be ignored. - * # If eee_enabled is set to 1 and this flag is set to 1, - * then Energy Efficient Ethernet (EEE) mode is enabled - * and TX LPI is enabled. - * # If eee_enabled is set to 1 and this flag is set to 0, - * then Energy Efficient Ethernet (EEE) mode is enabled - * but TX LPI is disabled. + * If this flag is set to '1', then the PRI to CoS + * configuration is asymmetric on TX and RX sides. + * If this flag is set to '0', then PRI to CoS configuration + * is symmetric on TX and RX sides. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \ - UINT32_C(0x80) + #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + UINT32_C(0x1) + uint8_t unused_0[6]; /* - * When set to 1, the parallel detection is used to determine - * the speed of the link partner. - * - * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable - * of autonegotiation. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t parallel_detect; + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_queue_pri2cos_cfg * + **************************/ + + +/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ +struct hwrm_queue_pri2cos_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When set to 1, the parallel detection is used to determine - * the speed of the link partner. - * - * Parallel detection is used when a autonegotiation capable - * device is connected to a link parter that is not capable - * of autonegotiation. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) + uint16_t cmpl_ring; /* - * The advertised speeds for the port by the link partner. - * Each advertised speed will be set to '1'. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t link_partner_adv_speeds; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \ - UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \ - UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \ - UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \ - UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \ - UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \ - UINT32_C(0x2000) + uint16_t seq_id; /* - * The advertised autoneg for the port by the link partner. - * This field is deprecated and should be set to 0. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t link_partner_adv_auto_mode; - /* Disable autoneg or autoneg disabled. No speeds are selected. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \ - UINT32_C(0x0) - /* Select all possible speeds for autoneg mode. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \ - UINT32_C(0x1) + uint16_t target_id; /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \ - UINT32_C(0x2) + uint64_t resp_addr; + uint32_t flags; /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Enumeration denoting the RX, TX, or both directions applicable to the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \ - UINT32_C(0x3) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 + /* tx path */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + /* Bi-directional (Symmetrically applicable to TX and RX paths) */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR /* - * Select the speeds based on the corresponding link speed mask value - * that is provided. + * When this bit is set to '0', the mapping is requested + * for VLAN PRI field in tunnel headers. + * When this bit is set to '1', the mapping is requested + * for VLAN PRI field in inner packet headers. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \ - UINT32_C(0x4) - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK - /* The advertised pause settings on the port by the link partner. */ - uint8_t link_partner_adv_pause; + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) + uint32_t enables; /* - * When this bit is '1', Generation of tx pause messages - * is supported. Disabled otherwise. + * This bit must be '1' for the pri0_cos_queue_id field to be + * configured. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \ UINT32_C(0x1) /* - * When this bit is '1', Reception of rx pause messages - * is supported. Disabled otherwise. + * This bit must be '1' for the pri1_cos_queue_id field to be + * configured. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \ UINT32_C(0x2) /* - * Current setting for link speed mask that is used to - * advertise speeds during autonegotiation when EEE is enabled. - * This field is valid only when eee_enabled flags is set to 1. - * The speeds specified in this field shall be a subset of - * speeds specified in auto_link_speed_mask. + * This bit must be '1' for the pri2_cos_queue_id field to be + * configured. */ - uint16_t adv_eee_link_speed_mask; - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \ - UINT32_C(0x2) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \ UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \ - UINT32_C(0x8) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \ - UINT32_C(0x10) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \ - UINT32_C(0x40) /* - * Current setting for link speed mask that is advertised by - * the link partner when EEE is enabled. - * This field is valid only when eee_enabled flags is set to 1. + * This bit must be '1' for the pri3_cos_queue_id field to be + * configured. */ - uint16_t link_partner_adv_eee_link_speed_mask; - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \ - UINT32_C(0x2) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \ UINT32_C(0x8) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \ + /* + * This bit must be '1' for the pri4_cos_queue_id field to be + * configured. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \ UINT32_C(0x10) - /* Reserved */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \ - UINT32_C(0x40) - uint32_t xcvr_identifier_type_tx_lpi_timer; /* - * Current setting of TX LPI timer in microseconds. - * This field is valid only when_eee_enabled flag is set to 1 - * and tx_lpi_enabled is set to 1. + * This bit must be '1' for the pri5_cos_queue_id field to be + * configured. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \ - UINT32_C(0xffffff) - #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0 - /* This value represents transceiver identifier type. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \ - UINT32_C(0xff000000) - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24 - /* Unknown */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \ - (UINT32_C(0x0) << 24) - /* SFP/SFP+/SFP28 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \ - (UINT32_C(0x3) << 24) - /* QSFP+ */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \ - (UINT32_C(0xc) << 24) - /* QSFP+ */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \ - (UINT32_C(0xd) << 24) - /* QSFP28 */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \ - (UINT32_C(0x11) << 24) - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \ + UINT32_C(0x20) /* - * This value represents the current configuration of - * Forward Error Correction (FEC) on the port. + * This bit must be '1' for the pri6_cos_queue_id field to be + * configured. */ - uint16_t fec_cfg; + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \ + UINT32_C(0x40) /* - * When set to 1, then FEC is not supported on this port. If this flag - * is set to 1, then all other FEC configuration flags shall be ignored. - * When set to 0, then FEC is supported as indicated by other - * configuration flags. - * If no cable is attached and the HWRM does not yet know the FEC - * capability, then the HWRM shall set this flag to 1 when reporting - * FEC capability. + * This bit must be '1' for the pri7_cos_queue_id field to be + * configured. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \ - UINT32_C(0x1) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \ + UINT32_C(0x80) /* - * When set to 1, then FEC autonegotiation is supported on this port. - * When set to 0, then FEC autonegotiation is not supported on this port. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \ - UINT32_C(0x2) + uint8_t port_id; /* - * When set to 1, then FEC autonegotiation is enabled on this port. - * When set to 0, then FEC autonegotiation is disabled if supported. - * This flag should be ignored if FEC autonegotiation is not supported on this port. + * CoS Queue assigned to priority 0. This value can only + * be changed before traffic has started. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \ - UINT32_C(0x4) + uint8_t pri0_cos_queue_id; /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port. + * CoS Queue assigned to priority 1. This value can only + * be changed before traffic has started. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \ - UINT32_C(0x8) + uint8_t pri1_cos_queue_id; /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. - * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. + * CoS Queue assigned to priority 2 This value can only + * be changed before traffic has started. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \ - UINT32_C(0x10) + uint8_t pri2_cos_queue_id; /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port. + * CoS Queue assigned to priority 3. This value can only + * be changed before traffic has started. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \ - UINT32_C(0x20) + uint8_t pri3_cos_queue_id; /* - * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port. - * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported. - * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. + * CoS Queue assigned to priority 4. This value can only + * be changed before traffic has started. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \ - UINT32_C(0x40) + uint8_t pri4_cos_queue_id; /* - * This value is indicates the duplex of the current - * connection state. + * CoS Queue assigned to priority 5. This value can only + * be changed before traffic has started. */ - uint8_t duplex_state; - /* Half Duplex connection. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0) - /* Full duplex connection. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1) - #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \ - HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL - /* Option flags fields. */ - uint8_t option_flags; - /* When this bit is '1', Media auto detect is enabled. */ - #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \ - UINT32_C(0x1) + uint8_t pri5_cos_queue_id; /* - * Up to 16 bytes of null padded ASCII string representing - * PHY vendor. - * If the string is set to null, then the vendor name is not - * available. + * CoS Queue assigned to priority 6. This value can only + * be changed before traffic has started. */ - char phy_vendor_name[16]; + uint8_t pri6_cos_queue_id; /* - * Up to 16 bytes of null padded ASCII string that - * identifies vendor specific part number of the PHY. - * If the string is set to null, then the vendor specific - * part number is not available. + * CoS Queue assigned to priority 7. This value can only + * be changed before traffic has started. */ - char phy_vendor_partnumber[16]; - uint8_t unused_2[7]; + uint8_t pri7_cos_queue_id; + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ +struct hwrm_queue_pri2cos_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9840,13 +14885,13 @@ struct hwrm_port_phy_qcfg_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_port_mac_cfg * - *********************/ +/************************** + * hwrm_queue_cos2bw_qcfg * + **************************/ -/* hwrm_port_mac_cfg_input (size:320b/40B) */ -struct hwrm_port_mac_cfg_input { +/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ +struct hwrm_queue_cos2bw_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -9875,396 +14920,1003 @@ struct hwrm_port_mac_cfg_input { */ uint64_t resp_addr; /* - * In this field, there are a number of CoS mappings related flags - * that are used to configure CoS mappings and their corresponding - * priorities in the hardware. - * For the priorities of CoS mappings, the HWRM uses the following - * priority order (high to low) by default: - * # vlan pri - * # ip_dscp - * # tunnel_vlan_pri - * # default cos - * - * A subset of CoS mappings can be enabled. - * If a priority is not specified for an enabled CoS mapping, the - * priority will be assigned in the above order for the enabled CoS - * mappings. For example, if vlan_pri and ip_dscp CoS mappings are - * enabled and their priorities are not specified, the following - * priority order (high to low) will be used by the HWRM: - * # vlan_pri - * # ip_dscp - * # default cos - * - * vlan_pri CoS mapping together with default CoS with lower priority - * are enabled by default by the HWRM. - */ - uint32_t flags; - /* - * When this bit is '1', this command will configure - * the MAC to match the current link state of the PHY. - * If the link is not established on the PHY, then this - * bit has no effect. - */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \ - UINT32_C(0x1) - /* - * When this bit is set to '1', the inner VLAN PRI to CoS mapping - * is requested to be enabled. - */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \ - UINT32_C(0x2) - /* - * When this bit is set to '1', tunnel VLAN PRI field to - * CoS mapping is requested to be enabled. - */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \ - UINT32_C(0x4) - /* - * When this bit is set to '1', the IP DSCP to CoS mapping is - * requested to be enabled. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure TC BW assignment on this port. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \ - UINT32_C(0x8) + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ +struct hwrm_queue_cos2bw_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* ID of CoS Queue 0. */ + uint8_t queue_id0; + uint8_t unused_0; + uint16_t unused_1; /* - * When this bit is '1', the HWRM is requested to - * enable timestamp capture capability on the receive side - * of this port. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \ - UINT32_C(0x10) + uint32_t queue_id0_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID /* - * When this bit is '1', the HWRM is requested to - * disable timestamp capture capability on the receive side - * of this port. + * Maximum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \ - UINT32_C(0x20) + uint32_t queue_id0_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id0_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * When this bit is '1', the HWRM is requested to - * enable timestamp capture capability on the transmit side - * of this port. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \ - UINT32_C(0x40) + uint8_t queue_id0_pri_lvl; /* - * When this bit is '1', the HWRM is requested to - * disable timestamp capture capability on the transmit side - * of this port. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \ - UINT32_C(0x80) + uint8_t queue_id0_bw_weight; + /* ID of CoS Queue 1. */ + uint8_t queue_id1; /* - * When this bit is '1', the Out-Of-Box WoL is requested to - * be enabled on this port. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \ - UINT32_C(0x100) + uint32_t queue_id1_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID /* - * When this bit is '1', the the Out-Of-Box WoL is requested to - * be disabled on this port. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \ - UINT32_C(0x200) + uint32_t queue_id1_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id1_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * When this bit is set to '1', the inner VLAN PRI to CoS mapping - * is requested to be disabled. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \ - UINT32_C(0x400) + uint8_t queue_id1_pri_lvl; /* - * When this bit is set to '1', tunnel VLAN PRI field to - * CoS mapping is requested to be disabled. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \ - UINT32_C(0x800) + uint8_t queue_id1_bw_weight; + /* ID of CoS Queue 2. */ + uint8_t queue_id2; /* - * When this bit is set to '1', the IP DSCP to CoS mapping is - * requested to be disabled. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \ - UINT32_C(0x1000) - uint32_t enables; + uint32_t queue_id2_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This bit must be '1' for the ipg field to be - * configured. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \ + uint32_t queue_id2_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id2_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ UINT32_C(0x1) - /* - * This bit must be '1' for the lpbk field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \ + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This bit must be '1' for the vlan_pri2cos_map_pri field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \ - UINT32_C(0x4) - /* - * This bit must be '1' for the tunnel_pri2cos_map_pri field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \ - UINT32_C(0x10) - /* - * This bit must be '1' for the dscp2cos_map_pri field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \ - UINT32_C(0x20) - /* - * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \ - UINT32_C(0x40) - /* - * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the cos_field_cfg field to be - * configured. - */ - #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \ - UINT32_C(0x100) - /* Port ID of port that is to be configured. */ - uint16_t port_id; - /* - * This value is used to configure the minimum IPG that will - * be sent between packets by this port. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t ipg; - /* This value controls the loopback setting for the MAC. */ - uint8_t lpbk; - /* No loopback is selected. Normal operation. */ - #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + uint8_t queue_id2_pri_lvl; /* - * The HW will be configured with local loopback such that - * host data is sent back to the host without modification. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + uint8_t queue_id2_bw_weight; + /* ID of CoS Queue 3. */ + uint8_t queue_id3; /* - * The HW will be configured with remote loopback such that - * port logic will send packets back out the transmitter that - * are received. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) - #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \ - HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE + uint32_t queue_id3_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This value controls the priority setting of VLAN PRI to CoS - * mapping based on VLAN Tags of inner packet headers of - * tunneled packets or packet headers of non-tunneled packets. - * - * # Each XXX_pri variable shall have a unique priority value - * when it is being specified. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t vlan_pri2cos_map_pri; - /* Reserved field. */ - uint8_t reserved1; + uint32_t queue_id3_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id3_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This value controls the priority setting of VLAN PRI to CoS - * mapping based on VLAN Tags of tunneled header. - * This mapping only applies when tunneled headers - * are present. - * - * # Each XXX_pri variable shall have a unique priority value - * when it is being specified. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t tunnel_pri2cos_map_pri; + uint8_t queue_id3_pri_lvl; /* - * This value controls the priority setting of IP DSCP to CoS - * mapping based on inner IP header of tunneled packets or - * IP header of non-tunneled packets. - * - * # Each XXX_pri variable shall have a unique priority value - * when it is being specified. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint8_t dscp2pri_map_pri; + uint8_t queue_id3_bw_weight; + /* ID of CoS Queue 4. */ + uint8_t queue_id4; /* - * This is a 16-bit bit mask that is used to request a - * specific configuration of time stamp capture of PTP messages - * on the receive side of this port. - * This field shall be ignored if the ptp_rx_ts_capture_enable - * flag is not set in this command. - * Otherwise, if bit 'i' is set, then the HWRM is being - * requested to configure the receive side of the port to - * capture the time stamp of every received PTP message - * with messageType field value set to i. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t rx_ts_capture_ptp_msg_type; + uint32_t queue_id4_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This is a 16-bit bit mask that is used to request a - * specific configuration of time stamp capture of PTP messages - * on the transmit side of this port. - * This field shall be ignored if the ptp_tx_ts_capture_enable - * flag is not set in this command. - * Otherwise, if bit 'i' is set, then the HWRM is being - * requested to configure the transmit sied of the port to - * capture the time stamp of every transmitted PTP message - * with messageType field value set to i. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t tx_ts_capture_ptp_msg_type; - /* Configuration of CoS fields. */ - uint8_t cos_field_cfg; - /* Reserved */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \ + uint32_t queue_id4_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id4_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This field is used to specify selection of VLAN PRI value - * based on whether one or two VLAN Tags are present in - * the inner packet headers of tunneled packets or - * non-tunneled packets. - * This field is valid only if inner VLAN PRI to CoS mapping - * is enabled. - * If VLAN PRI to CoS mapping is not enabled, then this - * field shall be ignored. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \ - UINT32_C(0x6) - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \ - 1 + uint8_t queue_id4_pri_lvl; /* - * Select inner VLAN PRI when 1 or 2 VLAN Tags are - * present in the inner packet headers + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \ - (UINT32_C(0x0) << 1) + uint8_t queue_id4_bw_weight; + /* ID of CoS Queue 5. */ + uint8_t queue_id5; /* - * Select outer VLAN Tag PRI when 2 VLAN Tags are - * present in the inner packet headers. - * No VLAN PRI shall be selected for this configuration - * if only one VLAN Tag is present in the inner - * packet headers. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \ - (UINT32_C(0x1) << 1) + uint32_t queue_id5_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Select outermost VLAN PRI when 1 or 2 VLAN Tags - * are present in the inner packet headers + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \ - (UINT32_C(0x2) << 1) - /* Unspecified */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \ - (UINT32_C(0x3) << 1) - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \ - HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED + uint32_t queue_id5_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id5_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This field is used to specify selection of tunnel VLAN - * PRI value based on whether one or two VLAN Tags are - * present in tunnel headers. - * This field is valid only if tunnel VLAN PRI to CoS mapping - * is enabled. - * If tunnel VLAN PRI to CoS mapping is not enabled, then this - * field shall be ignored. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \ - UINT32_C(0x18) - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \ - 3 + uint8_t queue_id5_pri_lvl; /* - * Select inner VLAN PRI when 1 or 2 VLAN Tags are - * present in the tunnel packet headers + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \ - (UINT32_C(0x0) << 3) + uint8_t queue_id5_bw_weight; + /* ID of CoS Queue 6. */ + uint8_t queue_id6; /* - * Select outer VLAN Tag PRI when 2 VLAN Tags are - * present in the tunnel packet headers. - * No tunnel VLAN PRI shall be selected for this - * configuration if only one VLAN Tag is present in - * the tunnel packet headers. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \ - (UINT32_C(0x1) << 3) + uint32_t queue_id6_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Select outermost VLAN PRI when 1 or 2 VLAN Tags - * are present in the tunnel packet headers + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \ - (UINT32_C(0x2) << 3) - /* Unspecified */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \ - (UINT32_C(0x3) << 3) - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \ - HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED + uint32_t queue_id6_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id6_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This field shall be used to provide default CoS value - * that has been configured on this port. - * This field is valid only if default CoS mapping - * is enabled. - * If default CoS mapping is not enabled, then this - * field shall be ignored. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \ - UINT32_C(0xe0) - #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ - 5 - uint8_t unused_0[3]; -} __attribute__((packed)); - -/* hwrm_port_mac_cfg_output (size:128b/16B) */ -struct hwrm_port_mac_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t queue_id6_pri_lvl; /* - * This is the configured maximum length of Ethernet packet - * payload that is allowed to be received on the port. - * This value does not include the number of bytes used by - * Ethernet header and trailer (CRC). + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t mru; + uint8_t queue_id6_bw_weight; + /* ID of CoS Queue 7. */ + uint8_t queue_id7; /* - * This is the configured maximum length of Ethernet packet - * payload that is allowed to be transmitted on the port. - * This value does not include the number of bytes used by - * Ethernet header and trailer (CRC). + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t mtu; - /* Current configuration of the IPG value. */ - uint8_t ipg; - /* Current value of the loopback value. */ - uint8_t lpbk; - /* No loopback is selected. Normal operation. */ - #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + uint32_t queue_id7_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id7_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id7_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * The HW will be configured with local loopback such that - * host data is sent back to the host without modification. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + uint8_t queue_id7_pri_lvl; /* - * The HW will be configured with remote loopback such that - * port logic will send packets back out the transmitter that - * are received. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) - #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \ - HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE - uint8_t unused_0; + uint8_t queue_id7_bw_weight; + uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10275,13 +15927,13 @@ struct hwrm_port_mac_cfg_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_port_mac_qcfg * - **********************/ +/************************* + * hwrm_queue_cos2bw_cfg * + *************************/ -/* hwrm_port_mac_qcfg_input (size:192b/24B) */ -struct hwrm_port_mac_qcfg_input { +/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ +struct hwrm_queue_cos2bw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10309,420 +15961,1044 @@ struct hwrm_port_mac_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port that is to be configured. */ - uint16_t port_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_port_mac_qcfg_output (size:192b/24B) */ -struct hwrm_port_mac_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint32_t flags; + uint32_t enables; /* - * This is the configured maximum length of Ethernet packet - * payload that is allowed to be received on the port. - * This value does not include the number of bytes used by the - * Ethernet header and trailer (CRC). + * If this bit is set to 1, then all queue_id0 related + * parameters in this command are valid. */ - uint16_t mru; + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \ + UINT32_C(0x1) /* - * This is the configured maximum length of Ethernet packet - * payload that is allowed to be transmitted on the port. - * This value does not include the number of bytes used by the - * Ethernet header and trailer (CRC). + * If this bit is set to 1, then all queue_id1 related + * parameters in this command are valid. */ - uint16_t mtu; + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \ + UINT32_C(0x2) /* - * The minimum IPG that will - * be sent between packets by this port. + * If this bit is set to 1, then all queue_id2 related + * parameters in this command are valid. */ - uint8_t ipg; - /* The loopback setting for the MAC. */ - uint8_t lpbk; - /* No loopback is selected. Normal operation. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \ + UINT32_C(0x4) /* - * The HW will be configured with local loopback such that - * host data is sent back to the host without modification. + * If this bit is set to 1, then all queue_id3 related + * parameters in this command are valid. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \ + UINT32_C(0x8) /* - * The HW will be configured with remote loopback such that - * port logic will send packets back out the transmitter that - * are received. + * If this bit is set to 1, then all queue_id4 related + * parameters in this command are valid. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) - #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \ - HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \ + UINT32_C(0x10) /* - * Priority setting for VLAN PRI to CoS mapping. - * # Each XXX_pri variable shall have a unique priority value - * when it is being used. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this - * field should be ignored. - * # This value indicates the normalized priority value retained - * in the HWRM. + * If this bit is set to 1, then all queue_id5 related + * parameters in this command are valid. */ - uint8_t vlan_pri2cos_map_pri; + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \ + UINT32_C(0x20) /* - * In this field, a number of CoS mappings related flags - * are used to indicate configured CoS mappings. + * If this bit is set to 1, then all queue_id6 related + * parameters in this command are valid. */ - uint8_t flags; + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \ + UINT32_C(0x40) /* - * When this bit is set to '1', the inner VLAN PRI to CoS mapping - * is enabled. + * If this bit is set to 1, then all queue_id7 related + * parameters in this command are valid. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure TC BW assignment on this port. + */ + uint16_t port_id; + /* ID of CoS Queue 0. */ + uint8_t queue_id0; + uint8_t unused_0; + /* + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id0_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID + /* + * Maximum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. + */ + uint32_t queue_id0_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id0_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ UINT32_C(0x1) - /* - * When this bit is set to '1', tunnel VLAN PRI field to - * CoS mapping is enabled. - */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \ + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * When this bit is set to '1', the IP DSCP to CoS mapping is - * enabled. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \ - UINT32_C(0x4) + uint8_t queue_id0_pri_lvl; /* - * When this bit is '1', the Out-Of-Box WoL is enabled on this - * port. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \ - UINT32_C(0x8) - /* When this bit is '1', PTP is enabled for RX on this port. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \ - UINT32_C(0x10) - /* When this bit is '1', PTP is enabled for TX on this port. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \ - UINT32_C(0x20) + uint8_t queue_id0_bw_weight; + /* ID of CoS Queue 1. */ + uint8_t queue_id1; /* - * Priority setting for tunnel VLAN PRI to CoS mapping. - * # Each XXX_pri variable shall have a unique priority value - * when it is being used. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this - * field should be ignored. - * # This value indicates the normalized priority value retained - * in the HWRM. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t tunnel_pri2cos_map_pri; + uint32_t queue_id1_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Priority setting for DSCP to PRI mapping. - * # Each XXX_pri variable shall have a unique priority value - * when it is being used. - * # When comparing priorities of mappings, higher value - * indicates higher priority. - * For example, a value of 0-3 is returned where 0 is being - * the lowest priority and 3 is being the highest priority. - * # If the correspoding CoS mapping is not enabled, then this - * field should be ignored. - * # This value indicates the normalized priority value retained - * in the HWRM. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t dscp2pri_map_pri; + uint32_t queue_id1_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id1_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This is a 16-bit bit mask that represents the - * current configuration of time stamp capture of PTP messages - * on the receive side of this port. - * If bit 'i' is set, then the receive side of the port - * is configured to capture the time stamp of every - * received PTP message with messageType field value set - * to i. - * If all bits are set to 0 (i.e. field value set 0), - * then the receive side of the port is not configured - * to capture timestamp for PTP messages. - * If all bits are set to 1, then the receive side of the - * port is configured to capture timestamp for all PTP - * messages. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint16_t rx_ts_capture_ptp_msg_type; + uint8_t queue_id1_pri_lvl; /* - * This is a 16-bit bit mask that represents the - * current configuration of time stamp capture of PTP messages - * on the transmit side of this port. - * If bit 'i' is set, then the transmit side of the port - * is configured to capture the time stamp of every - * received PTP message with messageType field value set - * to i. - * If all bits are set to 0 (i.e. field value set 0), - * then the transmit side of the port is not configured - * to capture timestamp for PTP messages. - * If all bits are set to 1, then the transmit side of the - * port is configured to capture timestamp for all PTP - * messages. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t tx_ts_capture_ptp_msg_type; - /* Configuration of CoS fields. */ - uint8_t cos_field_cfg; - /* Reserved */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \ - UINT32_C(0x1) + uint8_t queue_id1_bw_weight; + /* ID of CoS Queue 2. */ + uint8_t queue_id2; /* - * This field is used for selecting VLAN PRI value - * based on whether one or two VLAN Tags are present in - * the inner packet headers of tunneled packets or - * non-tunneled packets. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \ - UINT32_C(0x6) - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \ - 1 + uint32_t queue_id2_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Select inner VLAN PRI when 1 or 2 VLAN Tags are - * present in the inner packet headers + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \ - (UINT32_C(0x0) << 1) + uint32_t queue_id2_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id2_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * Select outer VLAN Tag PRI when 2 VLAN Tags are - * present in the inner packet headers. - * No VLAN PRI is selected for this configuration - * if only one VLAN Tag is present in the inner - * packet headers. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \ - (UINT32_C(0x1) << 1) + uint8_t queue_id2_pri_lvl; /* - * Select outermost VLAN PRI when 1 or 2 VLAN Tags - * are present in the inner packet headers + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \ - (UINT32_C(0x2) << 1) - /* Unspecified */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \ - (UINT32_C(0x3) << 1) - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \ - HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED + uint8_t queue_id2_bw_weight; + /* ID of CoS Queue 3. */ + uint8_t queue_id3; /* - * This field is used for selecting tunnel VLAN PRI value - * based on whether one or two VLAN Tags are present in - * the tunnel headers of tunneled packets. This selection - * does not apply to non-tunneled packets. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \ - UINT32_C(0x18) - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \ - 3 + uint32_t queue_id3_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID /* - * Select inner VLAN PRI when 1 or 2 VLAN Tags are - * present in the tunnel packet headers + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \ - (UINT32_C(0x0) << 3) + uint32_t queue_id3_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id3_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * Select outer VLAN Tag PRI when 2 VLAN Tags are - * present in the tunnel packet headers. - * No VLAN PRI is selected for this configuration - * if only one VLAN Tag is present in the tunnel - * packet headers. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \ - (UINT32_C(0x1) << 3) + uint8_t queue_id3_pri_lvl; /* - * Select outermost VLAN PRI when 1 or 2 VLAN Tags - * are present in the tunnel packet headers + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \ - (UINT32_C(0x2) << 3) - /* Unspecified */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \ - (UINT32_C(0x3) << 3) - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \ - HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED + uint8_t queue_id3_bw_weight; + /* ID of CoS Queue 4. */ + uint8_t queue_id4; /* - * This field is used to provide default CoS value that - * has been configured on this port. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \ - UINT32_C(0xe0) - #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ - 5 + uint32_t queue_id4_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t valid; -} __attribute__((packed)); - -/************************** - * hwrm_port_mac_ptp_qcfg * - **************************/ - - -/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ -struct hwrm_port_mac_ptp_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t queue_id4_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id4_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint16_t cmpl_ring; + uint8_t queue_id4_pri_lvl; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t seq_id; + uint8_t queue_id4_bw_weight; + /* ID of CoS Queue 5. */ + uint8_t queue_id5; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t target_id; + uint32_t queue_id5_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint64_t resp_addr; - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ -struct hwrm_port_mac_ptp_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint32_t queue_id5_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id5_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * In this field, a number of PTP related flags - * are used to indicate configured PTP capabilities. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint8_t flags; + uint8_t queue_id5_pri_lvl; /* - * When this bit is set to '1', the PTP related registers are - * directly accessible by the host. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ - UINT32_C(0x1) + uint8_t queue_id5_bw_weight; + /* ID of CoS Queue 6. */ + uint8_t queue_id6; /* - * When this bit is set to '1', the PTP information is accessible - * via HWRM commands. + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ - UINT32_C(0x2) - uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ - uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ - uint32_t rx_ts_reg_off_upper; - /* Offset of the PTP register for the sequence ID for RX. */ - uint32_t rx_ts_reg_off_seq_id; - /* Offset of the first PTP source ID for RX. */ - uint32_t rx_ts_reg_off_src_id_0; - /* Offset of the second PTP source ID for RX. */ - uint32_t rx_ts_reg_off_src_id_1; - /* Offset of the third PTP source ID for RX. */ - uint32_t rx_ts_reg_off_src_id_2; - /* Offset of the domain ID for RX. */ - uint32_t rx_ts_reg_off_domain_id; - /* Offset of the PTP FIFO register for RX. */ - uint32_t rx_ts_reg_off_fifo; - /* Offset of the PTP advance FIFO register for RX. */ - uint32_t rx_ts_reg_off_fifo_adv; - /* PTP timestamp granularity for RX. */ - uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ - uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ - uint32_t tx_ts_reg_off_upper; - /* Offset of the PTP register for the sequence ID for TX. */ - uint32_t tx_ts_reg_off_seq_id; - /* Offset of the PTP FIFO register for TX. */ - uint32_t tx_ts_reg_off_fifo; - /* PTP timestamp granularity for TX. */ - uint32_t tx_ts_reg_off_granularity; - uint8_t unused_1[7]; + uint32_t queue_id6_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint8_t valid; -} __attribute__((packed)); - -/******************** - * hwrm_port_qstats * - ********************/ - - -/* hwrm_port_qstats_input (size:320b/40B) */ -struct hwrm_port_qstats_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t queue_id6_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id6_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint16_t cmpl_ring; + uint8_t queue_id6_pri_lvl; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint16_t seq_id; + uint8_t queue_id6_bw_weight; + /* ID of CoS Queue 7. */ + uint8_t queue_id7; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Minimum BW allocated to CoS Queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint16_t target_id; + uint32_t queue_id7_min_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Maximum BW allocated to CoS queue. + * The HWRM will translate this value into byte counter and + * time interval used for this COS inside the device. */ - uint64_t resp_addr; - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[6]; + uint32_t queue_id7_max_bw; + /* The bandwidth value. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + uint8_t queue_id7_tsa_assign; + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + UINT32_C(0x1) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + UINT32_C(0x2) + /* reserved. */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + UINT32_C(0xff) /* - * This is the host address where - * Tx port statistics will be stored + * Priority level for strict priority. Valid only when the + * tsa_assign is 0 - Strict Priority (SP) + * 0..7 - Valid values. + * 8..255 - Reserved. */ - uint64_t tx_stat_host_addr; + uint8_t queue_id7_pri_lvl; /* - * This is the host address where - * Rx port statistics will be stored + * Weight used to allocate remaining BW for this COS after + * servicing guaranteed bandwidths for all COS. */ - uint64_t rx_stat_host_addr; + uint8_t queue_id7_bw_weight; + uint8_t unused_1[5]; } __attribute__((packed)); -/* hwrm_port_qstats_output (size:128b/16B) */ -struct hwrm_port_qstats_output { +/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ +struct hwrm_queue_cos2bw_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10731,11 +17007,7 @@ struct hwrm_port_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The size of TX port statistics block in bytes. */ - uint16_t tx_stat_size; - /* The size of RX port statistics block in bytes. */ - uint16_t rx_stat_size; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10746,13 +17018,13 @@ struct hwrm_port_qstats_output { uint8_t valid; } __attribute__((packed)); -/************************ - * hwrm_port_qstats_ext * - ************************/ +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ -/* hwrm_port_qstats_ext_input (size:320b/40B) */ -struct hwrm_port_qstats_ext_input { +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10780,33 +17052,17 @@ struct hwrm_port_qstats_ext_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port that is being queried. */ - uint16_t port_id; - /* - * The size of TX port extended - * statistics block in bytes. - */ - uint16_t tx_stat_size; - /* - * The size of RX port extended - * statistics block in bytes - */ - uint16_t rx_stat_size; - uint8_t unused_0[2]; /* - * This is the host address where - * Tx port statistics will be stored - */ - uint64_t tx_stat_host_addr; - /* - * This is the host address where - * Rx port statistics will be stored + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - uint64_t rx_stat_host_addr; + uint8_t port_id; + uint8_t unused_0[7]; } __attribute__((packed)); -/* hwrm_port_qstats_ext_output (size:128b/16B) */ -struct hwrm_port_qstats_ext_output { +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10815,11 +17071,12 @@ struct hwrm_port_qstats_ext_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The size of TX port statistics block in bytes. */ - uint16_t tx_stat_size; - /* The size of RX port statistics block in bytes. */ - uint16_t rx_stat_size; - uint8_t unused_0[3]; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10830,13 +17087,13 @@ struct hwrm_port_qstats_ext_output { uint8_t valid; } __attribute__((packed)); -/************************* - * hwrm_port_lpbk_qstats * - *************************/ +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ -/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ -struct hwrm_port_lpbk_qstats_input { +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10864,10 +17121,25 @@ struct hwrm_port_lpbk_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ -struct hwrm_port_lpbk_qstats_output { +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10876,27 +17148,17 @@ struct hwrm_port_lpbk_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast frames */ - uint64_t lpbk_ucast_frames; - /* Number of transmitted multicast frames */ - uint64_t lpbk_mcast_frames; - /* Number of transmitted broadcast frames */ - uint64_t lpbk_bcast_frames; - /* Number of transmitted bytes for unicast traffic */ - uint64_t lpbk_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t lpbk_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t lpbk_bcast_bytes; - /* Total Tx Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_discard; - /* Total Tx Error Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_error; - /* Total Rx Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_discard; - /* Total Rx Error Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_error; - uint8_t unused_0[7]; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; + /* + * This is the default PRI which un-initialized DSCP values are + * mapped to. + */ + uint8_t default_pri; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -10907,13 +17169,13 @@ struct hwrm_port_lpbk_qstats_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_port_clr_stats * - ***********************/ +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ -/* hwrm_port_clr_stats_input (size:192b/24B) */ -struct hwrm_port_clr_stats_input { +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -10941,13 +17203,43 @@ struct hwrm_port_clr_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[6]; + /* + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. + */ + uint64_t src_data_addr; + uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the default_pri field to be + * configured. + */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + UINT32_C(0x1) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + /* + * This is the default PRI which un-initialized DSCP values will be + * mapped to. + */ + uint8_t default_pri; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. + */ + uint16_t entry_cnt; + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_port_clr_stats_output (size:128b/16B) */ -struct hwrm_port_clr_stats_output { +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -10967,13 +17259,13 @@ struct hwrm_port_clr_stats_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_port_lpbk_clr_stats * - ****************************/ +/******************* + * hwrm_vnic_alloc * + *******************/ -/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ -struct hwrm_port_lpbk_clr_stats_input { +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11000,11 +17292,18 @@ struct hwrm_port_lpbk_clr_stats_input { * physical address (HPA) or a guest physical address (GPA) and must * point to a physically contiguous block of memory. */ - uint64_t resp_addr; + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ -struct hwrm_port_lpbk_clr_stats_output { +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11013,7 +17312,9 @@ struct hwrm_port_lpbk_clr_stats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11024,13 +17325,13 @@ struct hwrm_port_lpbk_clr_stats_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_port_ts_query * - **********************/ +/****************** + * hwrm_vnic_free * + ******************/ -/* hwrm_port_ts_query_input (size:192b/24B) */ -struct hwrm_port_ts_query_input { +/* hwrm_vnic_free_input (size:192b/24B) */ +struct hwrm_vnic_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11058,26 +17359,13 @@ struct hwrm_port_ts_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \ - HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[2]; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_port_ts_query_output (size:192b/24B) */ -struct hwrm_port_ts_query_output { +/* hwrm_vnic_free_output (size:128b/16B) */ +struct hwrm_vnic_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11086,11 +17374,7 @@ struct hwrm_port_ts_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Timestamp value of PTP message captured. */ - uint64_t ptp_msg_ts; - /* Sequence ID of the PTP message captured. */ - uint16_t ptp_msg_seqid; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11101,13 +17385,13 @@ struct hwrm_port_ts_query_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_port_phy_qcaps * - ***********************/ +/***************** + * hwrm_vnic_cfg * + *****************/ -/* hwrm_port_phy_qcaps_input (size:192b/24B) */ -struct hwrm_port_phy_qcaps_input { +/* hwrm_vnic_cfg_input (size:320b/40B) */ +struct hwrm_vnic_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11135,208 +17419,177 @@ struct hwrm_port_phy_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_port_phy_qcaps_output (size:192b/24B) */ -struct hwrm_port_phy_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* PHY capability flags */ - uint8_t flags; + uint32_t flags; /* - * If set to 1, then this field indicates that the - * link is capable of supporting EEE. + * When this bit is '1', the VNIC is requested to + * be the default VNIC for the function. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ UINT32_C(0x1) /* - * If set to 1, then this field indicates that the - * PHY is capable of supporting external loopback. + * When this bit is '1', the VNIC is being configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ UINT32_C(0x2) /* - * Reserved field. The HWRM shall set this field to 0. - * An HWRM client shall ignore this field. + * When this bit is '1', the VNIC is being configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is being configured to be + * disabled on this VNIC. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xfc) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2 - /* Number of front panel ports for this device. */ - uint8_t port_cnt; - /* Not supported or unknown */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0) - /* single port device */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1) - /* 2-port device */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2) - /* 3-port device */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3) - /* 4-port device */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \ - HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 + #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ + UINT32_C(0x4) /* - * This is a bit mask to indicate what speeds are supported - * as forced speeds on this link. - * For each speed that can be forced on this link, the - * corresponding mask bit shall be set to '1'. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to be + * operating in dual VNIC mode. */ - uint16_t supported_speeds_force_mode; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \ - UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \ - UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \ - UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \ - UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \ - UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \ - UINT32_C(0x2000) /* - * This is a bit mask to indicate what speeds are supported - * for autonegotiation on this link. - * For each speed that can be autonegotiated on this link, the - * corresponding mask bit shall be set to '1'. + * When this flag is set to '1', the VNIC is requested to + * be configured to receive only RoCE traffic. + * If this flag is set to '0', then this flag shall be + * ignored by the HWRM. + * If roce_dual_vnic_mode flag is set to '1' + * or roce_mirroring_capable_vnic_mode flag to 1, + * then the HWRM client shall not set this flag to '1'. */ - uint16_t supported_speeds_auto_mode; - /* 100Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \ - UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \ - UINT32_C(0x2) - /* 1Gb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \ - UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \ - UINT32_C(0x8) - /* 2Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ UINT32_C(0x10) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \ + /* + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * This flag is used to enable a mode where + * RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured using hwrm_vnic_rss_cfg. + * + * If this mode is enabled, then the driver should not program + * RSS indirection table for the RSS context that is used for + * computing RSS hash only. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \ - UINT32_C(0x40) - /* 20Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \ - UINT32_C(0x80) - /* 25Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \ - UINT32_C(0x100) - /* 40Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \ - UINT32_C(0x200) - /* 50Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \ - UINT32_C(0x400) - /* 100Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \ - UINT32_C(0x800) - /* 10Mb link speed (Half-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \ - UINT32_C(0x1000) - /* 10Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \ - UINT32_C(0x2000) /* - * This is a bit mask to indicate what speeds are supported - * for EEE on this link. - * For each speed that can be autonegotiated when EEE is enabled - * on this link, the corresponding mask bit shall be set to '1'. - * This field is only valid when the eee_suppotred is set to '1'. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic, but forward only the + * RoCE traffic further. Also, RoCE traffic can be mirrored to + * L2 driver. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ + UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the dflt_ring_grp field to be + * configured. */ - uint16_t supported_speeds_eee_mode; - /* Reserved */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ UINT32_C(0x1) - /* 100Mb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \ + /* + * This bit must be '1' for the rss_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ UINT32_C(0x2) - /* Reserved */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \ + /* + * This bit must be '1' for the cos_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ UINT32_C(0x4) - /* 1Gb link speed (Full-duplex) */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \ + /* + * This bit must be '1' for the lb_rule field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ UINT32_C(0x8) - /* Reserved */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \ + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ UINT32_C(0x10) - /* Reserved */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \ + /* + * This bit must be '1' for the default_rx_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ UINT32_C(0x20) - /* 10Gb link speed */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \ + /* + * This bit must be '1' for the default_cmpl_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ UINT32_C(0x40) - uint32_t tx_lpi_timer_low; + /* Logical vnic ID */ + uint16_t vnic_id; /* - * The lowest value of TX LPI timer that can be set on this link - * when EEE is enabled. This value is in microseconds. - * This field is valid only when_eee_supported is set to '1'. + * Default Completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules and if + * there is no COS rule. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \ - UINT32_C(0xffffff) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0 + uint16_t dflt_ring_grp; /* - * Reserved field. The HWRM shall set this field to 0. - * An HWRM client shall ignore this field. + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \ - UINT32_C(0xff000000) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24 - uint32_t valid_tx_lpi_timer_high; + uint16_t rss_rule; /* - * The highest value of TX LPI timer that can be set on this link - * when EEE is enabled. This value is in microseconds. - * This field is valid only when_eee_supported is set to '1'. + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \ - UINT32_C(0xffffff) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0 + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + /* + * Default Rx ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + * The aggregation ring associated with the Rx ring is + * implied based on the Rx ring specified when the + * aggregation ring was allocated. + */ + uint16_t default_rx_ring_id; + /* + * Default completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + */ + uint16_t default_cmpl_ring_id; +} __attribute__((packed)); + +/* hwrm_vnic_cfg_output (size:128b/16B) */ +struct hwrm_vnic_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11344,18 +17597,16 @@ struct hwrm_port_phy_qcaps_output { * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ - UINT32_C(0xff000000) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 + uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_port_phy_i2c_write * - ***************************/ +/****************** + * hwrm_vnic_qcfg * + ******************/ -/* hwrm_port_phy_i2c_write_input (size:832b/104B) */ -struct hwrm_port_phy_i2c_write_input { +/* hwrm_vnic_qcfg_input (size:256b/32B) */ +struct hwrm_vnic_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11383,36 +17634,21 @@ struct hwrm_port_phy_i2c_write_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; uint32_t enables; /* - * This bit must be '1' for the page_offset field to be + * This bit must be '1' for the vf_id_valid field to be * configured. */ - #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \ - UINT32_C(0x1) - /* Port ID of port. */ - uint16_t port_id; - /* 8-bit I2C slave address. */ - uint8_t i2c_slave_addr; - uint8_t unused_0; - /* The page number that is being accessed over I2C. */ - uint16_t page_number; - /* Offset within the page that is being accessed over I2C. */ - uint16_t page_offset; - /* - * Length of data to write, in bytes starting at the offset - * specified above. If the offset is not specified, then - * the data shall be written from the beginning of the page. - */ - uint8_t data_length; - uint8_t unused_1[7]; - /* Up to 64B of data. */ - uint32_t data[16]; + #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + /* Logical vnic ID */ + uint32_t vnic_id; + /* ID of Virtual Function whose VNIC resource is being queried. */ + uint16_t vf_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_port_phy_i2c_write_output (size:128b/16B) */ -struct hwrm_port_phy_i2c_write_output { +/* hwrm_vnic_qcfg_output (size:256b/32B) */ +struct hwrm_vnic_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11421,7 +17657,94 @@ struct hwrm_port_phy_i2c_write_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Default Completion ring for the VNIC. */ + uint16_t dflt_ring_grp; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* The maximum receive unit of the vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* + * When this bit is '1', the VNIC is the default VNIC for + * the function. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is disabled on + * this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to + * operate in dual VNIC mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ + UINT32_C(0x8) + /* + * When this flag is set to '1', the VNIC is configured to + * receive only RoCE traffic. + * When this flag is set to '0', the VNIC is not configured + * to receive only RoCE traffic. + * If roce_dual_vnic_mode flag and this flag both are set + * to '1', then it is an invalid configuration of the + * VNIC. The HWRM should not allow that type of + * mis-configuration by HWRM clients. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ + UINT32_C(0x10) + /* + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * When this bit is set to '1', then the VNIC is enabled in a + * mode where RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic, but forward only + * RoCE traffic further. Also RoCE traffic can be mirrored to + * L2 driver. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ + UINT32_C(0x40) + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11432,13 +17755,13 @@ struct hwrm_port_phy_i2c_write_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_port_phy_i2c_read * - **************************/ +/******************* + * hwrm_vnic_qcaps * + *******************/ -/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ -struct hwrm_port_phy_i2c_read_input { +/* hwrm_vnic_qcaps_input (size:192b/24B) */ +struct hwrm_vnic_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11466,34 +17789,12 @@ struct hwrm_port_phy_i2c_read_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; uint32_t enables; - /* - * This bit must be '1' for the page_offset field to be - * configured. - */ - #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \ - UINT32_C(0x1) - /* Port ID of port. */ - uint16_t port_id; - /* 8-bit I2C slave address. */ - uint8_t i2c_slave_addr; - uint8_t unused_0; - /* The page number that is being accessed over I2C. */ - uint16_t page_number; - /* Offset within the page that is being accessed over I2C. */ - uint16_t page_offset; - /* - * Length of data to read, in bytes starting at the offset - * specified above. If the offset is not specified, then - * the data shall be read from the beginning of the page. - */ - uint8_t data_length; - uint8_t unused_1[7]; + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ -struct hwrm_port_phy_i2c_read_output { +/* hwrm_vnic_qcaps_output (size:192b/24B) */ +struct hwrm_vnic_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11502,9 +17803,74 @@ struct hwrm_port_phy_i2c_read_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Up to 64B of data. */ - uint32_t data[16]; - uint8_t unused_0[7]; + /* The maximum receive unit that is settable on a vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* Unused. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ + UINT32_C(0x1) + /* + * When this bit is '1', the capability of stripping VLAN in + * the RX path is supported on VNIC(s). + * If set to '0', then VLAN stripping capability is + * not supported on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ + UINT32_C(0x2) + /* + * When this bit is '1', the capability to buffer receive + * packets in the hardware until the host posts new receive buffers + * is supported on VNIC(s). + * If set to '0', then bd_stall capability is not supported + * on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ + UINT32_C(0x4) + /* + * When this bit is '1', the capability to + * receive both RoCE and non-RoCE traffic on VNIC(s) is + * supported. + * If set to '0', then the capability to receive + * both RoCE and non-RoCE traffic on VNIC(s) is + * not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ + UINT32_C(0x8) + /* + * When this bit is set to '1', the capability to configure + * a VNIC to receive only RoCE traffic is supported. + * When this flag is set to '0', the VNIC capability to + * configure to receive only RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ + UINT32_C(0x10) + /* + * When this bit is set to '1', then the capability to enable + * a VNIC in a mode where RSS context without configuring + * RSS indirection table is supported (for RSS hash computation). + * When this bit is set to '0', then a VNIC can not be configured + * with a mode to enable RSS context without configuring RSS + * indirection table. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ + UINT32_C(0x20) + /* + * When this bit is '1', the capability to + * mirror the the RoCE traffic is supported. + * If set to '0', then the capability to mirror the + * RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ + UINT32_C(0x40) + /* + * When this bit is '1', the outermost RSS hashing capability + * is supported. If set to '0', then the outermost RSS hashing + * capability is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ + UINT32_C(0x80) + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -11516,12 +17882,12 @@ struct hwrm_port_phy_i2c_read_output { } __attribute__((packed)); /********************* - * hwrm_port_led_cfg * + * hwrm_vnic_tpa_cfg * *********************/ -/* hwrm_port_led_cfg_input (size:512b/64B) */ -struct hwrm_port_led_cfg_input { +/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ +struct hwrm_vnic_tpa_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11538,387 +17904,156 @@ struct hwrm_port_led_cfg_input { /* * The target ID of the command: * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the led0_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the led0_state field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the led0_color field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \ - UINT32_C(0x4) - /* - * This bit must be '1' for the led0_blink_on field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \ - UINT32_C(0x8) - /* - * This bit must be '1' for the led0_blink_off field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \ - UINT32_C(0x10) - /* - * This bit must be '1' for the led0_group_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the led1_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the led1_state field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the led1_color field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \ - UINT32_C(0x100) - /* - * This bit must be '1' for the led1_blink_on field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \ - UINT32_C(0x200) - /* - * This bit must be '1' for the led1_blink_off field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \ - UINT32_C(0x400) - /* - * This bit must be '1' for the led1_group_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \ - UINT32_C(0x800) - /* - * This bit must be '1' for the led2_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the led2_state field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the led2_color field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the led2_blink_on field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the led2_blink_off field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the led2_group_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the led3_id field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \ - UINT32_C(0x40000) - /* - * This bit must be '1' for the led3_state field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \ - UINT32_C(0x80000) - /* - * This bit must be '1' for the led3_color field to be - * configured. - */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \ - UINT32_C(0x100000) - /* - * This bit must be '1' for the led3_blink_on field to be - * configured. + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \ - UINT32_C(0x200000) + uint16_t target_id; /* - * This bit must be '1' for the led3_blink_off field to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \ - UINT32_C(0x400000) + uint64_t resp_addr; + uint32_t flags; /* - * This bit must be '1' for the led3_group_id field to be - * configured. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. */ - #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \ - UINT32_C(0x800000) - /* Port ID of port whose LEDs are configured. */ - uint16_t port_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + UINT32_C(0x1) /* - * The number of LEDs that are being configured. - * Up to 4 LEDs can be configured with this command. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. */ - uint8_t num_leds; - /* Reserved field. */ - uint8_t rsvd; - /* An identifier for the LED #0. */ - uint8_t led0_id; - /* The requested state of the LED #0. */ - uint8_t led0_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT - /* The requested color of LED #0. */ - uint8_t led0_color; - /* Default */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER - uint8_t unused_0; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + UINT32_C(0x2) /* - * If the LED #0 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. */ - uint16_t led0_blink_on; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + UINT32_C(0x4) /* - * If the LED #0 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. */ - uint16_t led0_blink_off; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + UINT32_C(0x8) /* - * An identifier for the group of LEDs that LED #0 belongs - * to. - * If set to 0, then the LED #0 shall not be grouped and - * shall be treated as an individual resource. - * For all other non-zero values of this field, LED #0 shall - * be grouped together with the LEDs with the same group ID - * value. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. */ - uint8_t led0_group_id; - /* Reserved field. */ - uint8_t rsvd0; - /* An identifier for the LED #1. */ - uint8_t led1_id; - /* The requested state of the LED #1. */ - uint8_t led1_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT - /* The requested color of LED #1. */ - uint8_t led1_color; - /* Default */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER - uint8_t unused_1; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + UINT32_C(0x10) /* - * If the LED #1 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. */ - uint16_t led1_blink_on; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + UINT32_C(0x20) /* - * If the LED #1 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. */ - uint16_t led1_blink_off; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + UINT32_C(0x40) /* - * An identifier for the group of LEDs that LED #1 belongs - * to. - * If set to 0, then the LED #1 shall not be grouped and - * shall be treated as an individual resource. - * For all other non-zero values of this field, LED #1 shall - * be grouped together with the LEDs with the same group ID + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) * value. */ - uint8_t led1_group_id; - /* Reserved field. */ - uint8_t rsvd1; - /* An identifier for the LED #2. */ - uint8_t led2_id; - /* The requested state of the LED #2. */ - uint8_t led2_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT - /* The requested color of LED #2. */ - uint8_t led2_color; - /* Default */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER - uint8_t unused_2; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + UINT32_C(0x80) + uint32_t enables; /* - * If the LED #2 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * This bit must be '1' for the max_agg_segs field to be + * configured. */ - uint16_t led2_blink_on; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) /* - * If the LED #2 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * This bit must be '1' for the max_aggs field to be + * configured. */ - uint16_t led2_blink_off; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) /* - * An identifier for the group of LEDs that LED #2 belongs - * to. - * If set to 0, then the LED #2 shall not be grouped and - * shall be treated as an individual resource. - * For all other non-zero values of this field, LED #2 shall - * be grouped together with the LEDs with the same group ID - * value. + * This bit must be '1' for the max_agg_timer field to be + * configured. */ - uint8_t led2_group_id; - /* Reserved field. */ - uint8_t rsvd2; - /* An identifier for the LED #3. */ - uint8_t led3_id; - /* The requested state of the LED #3. */ - uint8_t led3_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT - /* The requested color of LED #3. */ - uint8_t led3_color; - /* Default */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \ - HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER - uint8_t unused_3; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + /* + * This bit must be '1' for the min_agg_len field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + /* Logical vnic ID */ + uint16_t vnic_id; /* - * If the LED #3 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. */ - uint16_t led3_blink_on; + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX /* - * If the LED #3 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7 */ - uint16_t led3_blink_off; + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX + uint8_t unused_0[2]; /* - * An identifier for the group of LEDs that LED #3 belongs - * to. - * If set to 0, then the LED #3 shall not be grouped and - * shall be treated as an individual resource. - * For all other non-zero values of this field, LED #3 shall - * be grouped together with the LEDs with the same group ID - * value. + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. */ - uint8_t led3_group_id; - /* Reserved field. */ - uint8_t rsvd3; + uint32_t max_agg_timer; + /* + * This is the minimum amount of payload length required to + * start an aggregation context. + */ + uint32_t min_agg_len; } __attribute__((packed)); -/* hwrm_port_led_cfg_output (size:128b/16B) */ -struct hwrm_port_led_cfg_output { +/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ +struct hwrm_vnic_tpa_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11939,12 +18074,12 @@ struct hwrm_port_led_cfg_output { } __attribute__((packed)); /********************** - * hwrm_port_led_qcfg * + * hwrm_vnic_tpa_qcfg * **********************/ -/* hwrm_port_led_qcfg_input (size:192b/24B) */ -struct hwrm_port_led_qcfg_input { +/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_tpa_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -11972,13 +18107,13 @@ struct hwrm_port_led_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port whose LED configuration is being queried. */ - uint16_t port_id; + /* Logical vnic ID */ + uint16_t vnic_id; uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_port_led_qcfg_output (size:448b/56B) */ -struct hwrm_port_led_qcfg_output { +/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ +struct hwrm_vnic_tpa_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -11987,252 +18122,268 @@ struct hwrm_port_led_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint32_t flags; /* - * The number of LEDs that are configured on this port. - * Up to 4 LEDs can be returned in the response. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. */ - uint8_t num_leds; - /* An identifier for the LED #0. */ - uint8_t led0_id; - /* The type of LED #0. */ - uint8_t led0_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID - /* The current state of the LED #0. */ - uint8_t led0_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT - /* The color of LED #0. */ - uint8_t led0_color; - /* Default */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER - uint8_t unused_0; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \ + UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \ + UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \ + UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \ + UINT32_C(0x8) + /* + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \ + UINT32_C(0x10) + /* + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + UINT32_C(0x20) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \ + UINT32_C(0x40) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) + * value. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \ + UINT32_C(0x80) + /* + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. + */ + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \ + HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX + /* + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7 + */ + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \ + HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX + /* + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. + */ + uint32_t max_agg_timer; + /* + * This is the minimum amount of payload length required to + * start an aggregation context. + */ + uint32_t min_agg_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_vnic_rss_cfg * + *********************/ + + +/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ +struct hwrm_vnic_rss_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; /* - * If the LED #0 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t led0_blink_on; + uint16_t seq_id; /* - * If the LED #0 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint16_t led0_blink_off; + uint16_t target_id; /* - * An identifier for the group of LEDs that LED #0 belongs - * to. - * If set to 0, then the LED #0 is not grouped. - * For all other non-zero values of this field, LED #0 is - * grouped together with the LEDs with the same group ID - * value. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t led0_group_id; - /* An identifier for the LED #1. */ - uint8_t led1_id; - /* The type of LED #1. */ - uint8_t led1_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID - /* The current state of the LED #1. */ - uint8_t led1_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT - /* The color of LED #1. */ - uint8_t led1_color; - /* Default */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER - uint8_t unused_1; + uint64_t resp_addr; + uint32_t hash_type; /* - * If the LED #1 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - uint16_t led1_blink_on; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * If the LED #1 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - uint16_t led1_blink_off; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * An identifier for the group of LEDs that LED #1 belongs - * to. - * If set to 0, then the LED #1 is not grouped. - * For all other non-zero values of this field, LED #1 is - * grouped together with the LEDs with the same group ID - * value. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - uint8_t led1_group_id; - /* An identifier for the LED #2. */ - uint8_t led2_id; - /* The type of LED #2. */ - uint8_t led2_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID - /* The current state of the LED #2. */ - uint8_t led2_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT - /* The color of LED #2. */ - uint8_t led2_color; - /* Default */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER - uint8_t unused_2; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * If the LED #2 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - uint16_t led2_blink_on; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * If the LED #2 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - uint16_t led2_blink_off; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * An identifier for the group of LEDs that LED #2 belongs - * to. - * If set to 0, then the LED #2 is not grouped. - * For all other non-zero values of this field, LED #2 is - * grouped together with the LEDs with the same group ID - * value. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - uint8_t led2_group_id; - /* An identifier for the LED #3. */ - uint8_t led3_id; - /* The type of LED #3. */ - uint8_t led3_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID - /* The current state of the LED #3. */ - uint8_t led3_state; - /* Default state of the LED */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0) - /* Off */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1) - /* On */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2) - /* Blink */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3) - /* Blink Alternately */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT - /* The color of LED #3. */ - uint8_t led3_color; - /* Default */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0) - /* Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1) - /* Green */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2) - /* Green or Amber */ - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3) - #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \ - HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER - uint8_t unused_3; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* VNIC ID of VNIC associated with RSS table being configured. */ + uint16_t vnic_id; /* - * If the LED #3 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED on between cycles. + * Specifies which VNIC ring table pair to configure. + * Valid values range from 0 to 7. */ - uint16_t led3_blink_on; + uint8_t ring_table_pair_index; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; /* - * If the LED #3 state is "blink" or "blinkalt", then - * this field represents the requested time in milliseconds - * to keep LED off between cycles. + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. */ - uint16_t led3_blink_off; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) /* - * An identifier for the group of LEDs that LED #3 belongs - * to. - * If set to 0, then the LED #3 is not grouped. - * For all other non-zero values of this field, LED #3 is - * grouped together with the LEDs with the same group ID - * value. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - uint8_t led3_group_id; - uint8_t unused_4[6]; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t unused_1[6]; +} __attribute__((packed)); + +/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ +struct hwrm_vnic_rss_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12243,13 +18394,13 @@ struct hwrm_port_led_qcfg_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_port_led_qcaps * - ***********************/ +/********************** + * hwrm_vnic_rss_qcfg * + **********************/ -/* hwrm_port_led_qcaps_input (size:192b/24B) */ -struct hwrm_port_led_qcaps_input { +/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_rss_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -12277,13 +18428,13 @@ struct hwrm_port_led_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port whose LED configuration is being queried. */ - uint16_t port_id; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_port_led_qcaps_output (size:384b/48B) */ -struct hwrm_port_led_qcaps_output { +/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ +struct hwrm_vnic_rss_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -12292,298 +18443,89 @@ struct hwrm_port_led_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint32_t hash_type; /* - * The number of LEDs that are configured on this port. - * Up to 4 LEDs can be returned in the response. - */ - uint8_t num_leds; - /* Reserved for future use. */ - uint8_t unused[3]; - /* An identifier for the LED #0. */ - uint8_t led0_id; - /* The type of LED #0. */ - uint8_t led0_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \ - HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID - /* - * An identifier for the group of LEDs that LED #0 belongs - * to. - * If set to 0, then the LED #0 cannot be grouped. - * For all other non-zero values of this field, LED #0 is - * grouped together with the LEDs with the same group ID - * value. - */ - uint8_t led0_group_id; - uint8_t unused_0; - /* The states supported by LED #0. */ - uint16_t led0_state_caps; - /* - * If set to 1, this LED is enabled. - * If set to 0, this LED is disabled. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \ - UINT32_C(0x1) - /* - * If set to 1, off state is supported on this LED. - * If set to 0, off state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, on state is supported on this LED. - * If set to 0, on state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \ - UINT32_C(0x4) - /* - * If set to 1, blink state is supported on this LED. - * If set to 0, blink state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \ - UINT32_C(0x8) - /* - * If set to 1, blink_alt state is supported on this LED. - * If set to 0, blink_alt state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \ - UINT32_C(0x10) - /* The colors supported by LED #0. */ - uint16_t led0_color_caps; - /* reserved. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \ - UINT32_C(0x1) - /* - * If set to 1, Amber color is supported on this LED. - * If set to 0, Amber color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, Green color is supported on this LED. - * If set to 0, Green color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \ - UINT32_C(0x4) - /* An identifier for the LED #1. */ - uint8_t led1_id; - /* The type of LED #1. */ - uint8_t led1_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \ - HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID - /* - * An identifier for the group of LEDs that LED #1 belongs - * to. - * If set to 0, then the LED #0 cannot be grouped. - * For all other non-zero values of this field, LED #0 is - * grouped together with the LEDs with the same group ID - * value. - */ - uint8_t led1_group_id; - uint8_t unused_1; - /* The states supported by LED #1. */ - uint16_t led1_state_caps; - /* - * If set to 1, this LED is enabled. - * If set to 0, this LED is disabled. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \ - UINT32_C(0x1) - /* - * If set to 1, off state is supported on this LED. - * If set to 0, off state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, on state is supported on this LED. - * If set to 0, on state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \ - UINT32_C(0x4) - /* - * If set to 1, blink state is supported on this LED. - * If set to 0, blink state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \ - UINT32_C(0x8) - /* - * If set to 1, blink_alt state is supported on this LED. - * If set to 0, blink_alt state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \ - UINT32_C(0x10) - /* The colors supported by LED #1. */ - uint16_t led1_color_caps; - /* reserved. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \ - UINT32_C(0x1) - /* - * If set to 1, Amber color is supported on this LED. - * If set to 0, Amber color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, Green color is supported on this LED. - * If set to 0, Green color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \ - UINT32_C(0x4) - /* An identifier for the LED #2. */ - uint8_t led2_id; - /* The type of LED #2. */ - uint8_t led2_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \ - HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID - /* - * An identifier for the group of LEDs that LED #0 belongs - * to. - * If set to 0, then the LED #0 cannot be grouped. - * For all other non-zero values of this field, LED #0 is - * grouped together with the LEDs with the same group ID - * value. - */ - uint8_t led2_group_id; - uint8_t unused_2; - /* The states supported by LED #2. */ - uint16_t led2_state_caps; - /* - * If set to 1, this LED is enabled. - * If set to 0, this LED is disabled. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \ - UINT32_C(0x1) - /* - * If set to 1, off state is supported on this LED. - * If set to 0, off state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, on state is supported on this LED. - * If set to 0, on state is not supported on this LED. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \ - UINT32_C(0x4) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * If set to 1, blink state is supported on this LED. - * If set to 0, blink state is not supported on this LED. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \ - UINT32_C(0x8) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * If set to 1, blink_alt state is supported on this LED. - * If set to 0, blink_alt state is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \ - UINT32_C(0x10) - /* The colors supported by LED #2. */ - uint16_t led2_color_caps; - /* reserved. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \ - UINT32_C(0x1) + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * If set to 1, Amber color is supported on this LED. - * If set to 0, Amber color is not supported on this LED. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \ - UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * If set to 1, Green color is supported on this LED. - * If set to 0, Green color is not supported on this LED. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \ - UINT32_C(0x4) - /* An identifier for the LED #3. */ - uint8_t led3_id; - /* The type of LED #3. */ - uint8_t led3_type; - /* Speed LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0) - /* Activity LED */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1) - /* Invalid */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff) - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \ - HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * An identifier for the group of LEDs that LED #3 belongs - * to. - * If set to 0, then the LED #0 cannot be grouped. - * For all other non-zero values of this field, LED #0 is - * grouped together with the LEDs with the same group ID - * value. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - uint8_t led3_group_id; - uint8_t unused_3; - /* The states supported by LED #3. */ - uint16_t led3_state_caps; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint8_t unused_0[4]; + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; /* - * If set to 1, this LED is enabled. - * If set to 0, this LED is disabled. + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) /* - * If set to 1, off state is supported on this LED. - * If set to 0, off state is not supported on this LED. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ UINT32_C(0x2) /* - * If set to 1, on state is supported on this LED. - * If set to 0, on state is not supported on this LED. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ UINT32_C(0x4) /* - * If set to 1, blink state is supported on this LED. - * If set to 0, blink state is not supported on this LED. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ UINT32_C(0x8) /* - * If set to 1, blink_alt state is supported on this LED. - * If set to 0, blink_alt state is not supported on this LED. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ UINT32_C(0x10) - /* The colors supported by LED #3. */ - uint16_t led3_color_caps; - /* reserved. */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \ - UINT32_C(0x1) - /* - * If set to 1, Amber color is supported on this LED. - * If set to 0, Amber color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \ - UINT32_C(0x2) - /* - * If set to 1, Green color is supported on this LED. - * If set to 0, Green color is not supported on this LED. - */ - #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \ - UINT32_C(0x4) - uint8_t unused_4[3]; + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12594,13 +18536,13 @@ struct hwrm_port_led_qcaps_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_queue_qportcfg * - ***********************/ +/************************** + * hwrm_vnic_plcmodes_cfg * + **************************/ -/* hwrm_queue_qportcfg_input (size:192b/24B) */ -struct hwrm_queue_qportcfg_input { +/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ +struct hwrm_vnic_plcmodes_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -12630,412 +18572,251 @@ struct hwrm_queue_qportcfg_input { uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When this bit is '1', the VNIC shall be configured to + * use regular placement algorithm. + * By default, the regular placement algorithm shall be + * enabled on the VNIC. */ - #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ + UINT32_C(0x1) /* - * Port ID of port for which the queue configuration is being - * queried. This field is only required when sent by IPC. + * When this bit is '1', the VNIC shall be configured + * use the jumbo placement algorithm. */ - uint16_t port_id; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ + UINT32_C(0x2) /* - * Drivers will set this capability when it can use - * queue_idx_service_profile to map the queues to application. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv4 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv4, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv4, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv4 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv4 + * packet. */ - uint8_t drv_qmap_cap; - /* disabled */ - #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0) - /* enabled */ - #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1) - #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \ - HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED - uint8_t unused_0; -} __attribute__((packed)); - -/* hwrm_queue_qportcfg_output (size:256b/32B) */ -struct hwrm_queue_qportcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ + UINT32_C(0x4) /* - * The maximum number of queues that can be configured on this - * port. - * Valid values range from 1 through 8. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv6 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv6, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv6, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv6 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv6 + * packet. */ - uint8_t max_configurable_queues; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) /* - * The maximum number of lossless queues that can be configured - * on this port. - * Valid values range from 0 through 8. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for FCoE packets at the + * beginning of FC payload. */ - uint8_t max_configurable_lossless_queues; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_cfg command. - * - * Each bit represents a specific queue where bit 0 represents - * queue 0 and bit 7 represents queue 7. - * # A value of 0 indicates that the queue is not configurable - * by the hwrm_queue_cfg command. - * # A value of 1 indicates that the queue is configurable. - * # A hwrm_queue_cfg command shall return error when trying to - * configure a queue not configurable. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for RoCE packets at the + * beginning of RoCE payload (after BTH/GRH headers). */ - uint8_t queue_cfg_allowed; - /* Information about queue configuration. */ - uint8_t queue_cfg_info; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) + uint32_t enables; /* - * If this flag is set to '1', then the queues are - * configured asymmetrically on TX and RX sides. - * If this flag is set to '0', then the queues are - * configured symmetrically on TX and RX sides. For - * symmetric configuration, the queue configuration - * including queue ids and service profiles on the - * TX side is the same as the corresponding queue - * configuration on the RX side. + * This bit must be '1' for the jumbo_thresh_valid field to be + * configured. */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ UINT32_C(0x1) /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_pfcenable_cfg command. - * - * Each bit represents a specific priority where bit 0 represents - * priority 0 and bit 7 represents priority 7. - * # A value of 0 indicates that the priority is not configurable by - * the hwrm_queue_pfcenable_cfg command. - * # A value of 1 indicates that the priority is configurable. - * # A hwrm_queue_pfcenable_cfg command shall return error when - * trying to configure a priority that is not configurable. + * This bit must be '1' for the hds_offset_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hds_threshold_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ + UINT32_C(0x4) + /* Logical vnic ID */ + uint32_t vnic_id; + /* + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. */ - uint8_t queue_pfcenable_cfg_allowed; + uint16_t jumbo_thresh; /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_pri2cos_cfg command. + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of of HDS placement algorithm. * - * Each bit represents a specific queue where bit 0 represents - * queue 0 and bit 7 represents queue 7. - * # A value of 0 indicates that the queue is not configurable - * by the hwrm_queue_pri2cos_cfg command. - * # A value of 1 indicates that the queue is configurable. - * # A hwrm_queue_pri2cos_cfg command shall return error when - * trying to configure a queue that is not configurable. + * The lengths of packet buffers provided for split data + * shall be larger than this value. */ - uint8_t queue_pri2cos_cfg_allowed; + uint16_t hds_offset; /* - * Bitmask indicating which queues can be configured by the - * hwrm_queue_pri2cos_cfg command. - * - * Each bit represents a specific queue where bit 0 represents - * queue 0 and bit 7 represents queue 7. - * # A value of 0 indicates that the queue is not configurable - * by the hwrm_queue_pri2cos_cfg command. - * # A value of 1 indicates that the queue is configurable. - * # A hwrm_queue_pri2cos_cfg command shall return error when - * trying to configure a queue not configurable. + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. */ - uint8_t queue_cos2bw_cfg_allowed; + uint16_t hds_threshold; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ +struct hwrm_vnic_plcmodes_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * ID of CoS Queue 0. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t queue_id0; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id0_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_vnic_plcmodes_qcfg * + ***************************/ + + +/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * ID of CoS Queue 1. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t queue_id1; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id1_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN + uint16_t cmpl_ring; /* - * ID of CoS Queue 2. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id2; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id2_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN + uint16_t seq_id; /* - * ID of CoS Queue 3. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t queue_id3; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id3_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN + uint16_t target_id; /* - * ID of CoS Queue 4. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', the VNIC is configured to + * use regular placement algorithm. */ - uint8_t queue_id4; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id4_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN /* - * ID of CoS Queue 5. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * When this bit is '1', the VNIC is configured to + * use the jumbo placement algorithm. */ - uint8_t queue_id5; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id5_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN /* - * ID of CoS Queue 6. - * FF - Invalid id - * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv4 packets. */ - uint8_t queue_id6; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id6_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ + UINT32_C(0x4) /* - * ID of CoS Queue 7. - * FF - Invalid id + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv6 packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for FCoE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) + /* + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for RoCE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is configured + * to be the default VNIC of the requesting function. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ + UINT32_C(0x40) + /* + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. + */ + uint16_t jumbo_thresh; + /* + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of of HDS placement algorithm. * - * # This ID can be used on any subsequent call to an hwrm command - * that takes a queue id. - * # IDs must always be queried by this command before any use - * by the driver or software. - * # Any driver or software should not make any assumptions about - * queue IDs. - * # A value of 0xff indicates that the queue is not available. - * # Available queues may not be in sequential order. + * The lengths of packet buffers provided for split data + * shall be larger than this value. */ - uint8_t queue_id7; - /* This value is applicable to CoS queues only. */ - uint8_t queue_id7_service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \ - UINT32_C(0x0) - /* Lossless (legacy) */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \ - UINT32_C(0x1) - /* Lossless RoCE */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \ - UINT32_C(0x1) - /* Lossy RoCE CNP */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \ - UINT32_C(0x2) - /* Lossless NIC */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \ - UINT32_C(0x3) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \ - UINT32_C(0xff) - #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN + uint16_t hds_offset; + /* + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. + */ + uint16_t hds_threshold; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -13046,13 +18827,13 @@ struct hwrm_queue_qportcfg_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_queue_qcfg * - *******************/ +/********************************** + * hwrm_vnic_rss_cos_lb_ctx_alloc * + **********************************/ -/* hwrm_queue_qcfg_input (size:192b/24B) */ -struct hwrm_queue_qcfg_input { +/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13080,25 +18861,72 @@ struct hwrm_queue_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; +} __attribute__((packed)); + +/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[5]; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX - /* Queue ID of the queue. */ - uint32_t queue_id; + uint8_t valid; +} __attribute__((packed)); + +/********************************* + * hwrm_vnic_rss_cos_lb_ctx_free * + *********************************/ + + +/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_queue_qcfg_output (size:128b/16B) */ -struct hwrm_queue_qcfg_output { +/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13107,32 +18935,7 @@ struct hwrm_queue_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This value is a the estimate packet length used in the - * TX arbiter. - */ - uint32_t queue_len; - /* This value is applicable to CoS queues only. */ - uint8_t service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) - /* Lossless */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) - #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN - /* Information about queue configuration. */ - uint8_t queue_cfg_info; - /* - * If this flag is set to '1', then the queue is - * configured asymmetrically on TX and RX sides. - * If this flag is set to '0', then this queue is - * configured symmetrically on TX and RX sides. - */ - #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ - UINT32_C(0x1) - uint8_t unused_0; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -13143,13 +18946,13 @@ struct hwrm_queue_qcfg_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_queue_cfg * - ******************/ +/******************* + * hwrm_ring_alloc * + *******************/ -/* hwrm_queue_cfg_input (size:320b/40B) */ -struct hwrm_queue_cfg_input { +/* hwrm_ring_alloc_input (size:640b/80B) */ +struct hwrm_ring_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13177,120 +18980,268 @@ struct hwrm_queue_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint32_t enables; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This bit must be '1' for the ring_arb_cfg field to be + * configured. */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 - /* tx path */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - /* Bi-directional (Symmetrically applicable to TX and RX paths) */ - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) - #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR - uint32_t enables; + #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ + UINT32_C(0x2) /* - * This bit must be '1' for the dflt_len field to be + * This bit must be '1' for the stat_ctx_id_valid field to be * configured. */ - #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ + UINT32_C(0x8) /* - * This bit must be '1' for the service_profile field to be + * This bit must be '1' for the max_bw_valid field to be * configured. */ - #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2) - /* Queue ID of queue that is to be configured by this function. */ - uint32_t queue_id; + #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ + UINT32_C(0x20) /* - * This value is a the estimate packet length used in the - * TX arbiter. - * Set to 0xFF... (All Fs) to not adjust this value. + * This bit must be '1' for the rx_ring_id field to be + * configured. */ - uint32_t dflt_len; - /* This value is applicable to CoS queues only. */ - uint8_t service_profile; - /* Lossy (best-effort) */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) - /* Lossless */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) - /* Set to 0xFF... (All Fs) if there is no service profile specified */ - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) - #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ - HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN - uint8_t unused_0[7]; -} __attribute__((packed)); - -/* hwrm_queue_cfg_output (size:128b/16B) */ -struct hwrm_queue_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ + UINT32_C(0x40) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the nq_ring_id field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ + UINT32_C(0x80) + /* + * This bit must be '1' for the rx_buf_size field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ + UINT32_C(0x100) + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ + HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ + uint8_t unused_0[3]; + /* + * This value is a pointer to the page table for the + * Ring. + */ + uint64_t page_tbl_addr; + /* First Byte Offset of the first entry in the first page. */ + uint32_t fbo; + /* + * Actual page size in 2^page_size. The supported range is increments + * in powers of 2 from 16 bytes to 1GB. + * - 4 = 16 B + * Page size is 16 B. + * - 12 = 4 KB + * Page size is 4 KB. + * - 13 = 8 KB + * Page size is 8 KB. + * - 16 = 64 KB + * Page size is 64 KB. + * - 21 = 2 MB + * Page size is 2 MB. + * - 22 = 4 MB + * Page size is 4 MB. + * - 30 = 1 GB + * Page size is 1 GB. + */ + uint8_t page_size; + /* + * This value indicates the depth of page table. + * For this version of the specification, value other than 0 or + * 1 shall be considered as an invalid value. + * When the page_tbl_depth = 0, then it is treated as a + * special case with the following. + * 1. FBO and page size fields are not valid. + * 2. page_tbl_addr is the physical address of the first + * element of the ring. + */ + uint8_t page_tbl_depth; + uint8_t unused_1[2]; + /* + * Number of 16B units in the ring. Minimum size for + * a ring is 16 16B entries. + */ + uint32_t length; + /* + * Logical ring number for the ring to be allocated. + * This value determines the position in the doorbell + * area where the update to the ring will be made. + * + * For completion rings, this value is also the MSI-X + * vector number for the function the completion ring is + * associated with. + */ + uint16_t logical_id; + /* + * This field is used only when ring_type is a TX ring. + * This value indicates what completion ring the TX ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * This field is used only when ring_type is a TX ring. + * This value indicates what CoS queue the TX ring + * is associated with. + */ + uint16_t queue_id; + /* + * When allocating a Rx ring or Rx aggregation ring, this field + * specifies the size of the buffer descriptors posted to the ring. + */ + uint16_t rx_buf_size; + /* + * When allocating an Rx aggregation ring, this field + * specifies the associated Rx ring ID. + */ + uint16_t rx_ring_id; + /* + * When allocating a completion ring, this field + * specifies the associated NQ ring ID. + */ + uint16_t nq_ring_id; + /* + * This field is used only when ring_type is a TX ring. + * This field is used to configure arbitration related + * parameters for a TX ring. + */ + uint16_t ring_arb_cfg; + /* Arbitration policy used for the ring. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ + UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + /* + * Use strict priority for the TX ring. + * Priority value is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ + UINT32_C(0x1) + /* + * Use weighted fair queue arbitration for the TX ring. + * Weight is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ + UINT32_C(0x2) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ + HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ + /* Reserved field. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + /* + * Arbitration policy specific parameter. + * # For strict priority arbitration policy, this field + * represents a priority value. If set to 0, then the priority + * is not specified and the HWRM is allowed to select + * any priority for this TX ring. + * # For weighted fair queue arbitration policy, this field + * represents a weight value. If set to 0, then the weight + * is not specified and the HWRM is allowed to select + * any weight for this TX ring. */ - uint8_t valid; -} __attribute__((packed)); - -/***************************** - * hwrm_queue_pfcenable_qcfg * - *****************************/ - - -/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ + UINT32_C(0xff00) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 + uint16_t unused_3; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint16_t cmpl_ring; + uint32_t reserved3; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This field is used only when ring_type is a TX ring. + * This input indicates what statistics context this ring + * should be associated with. */ - uint16_t seq_id; + uint32_t stat_ctx_id; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This field is reserved for the future use. + * It shall be set to 0. */ - uint16_t target_id; + uint32_t reserved4; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This field is used only when ring_type is a TX ring + * to specify maximum BW allocated to the TX ring. + * The HWRM will translate this value into byte counter and + * time interval used for this ring inside the device. */ - uint64_t resp_addr; + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * This field is used only when ring_type is a Completion ring. + * This value indicates what interrupt mode should be used + * on this completion ring. + * Note: In the legacy interrupt mode, no more than 16 + * completion rings are allowed. */ - uint16_t port_id; - uint8_t unused_0[6]; + uint8_t int_mode; + /* Legacy INTA */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) + /* Reserved */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) + /* MSI-X */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) + /* No Interrupt - Polled mode */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ + HWRM_RING_ALLOC_INPUT_INT_MODE_POLL + uint8_t unused_4[3]; } __attribute__((packed)); -/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_qcfg_output { +/* hwrm_ring_alloc_output (size:128b/16B) */ +struct hwrm_ring_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13299,31 +19250,13 @@ struct hwrm_queue_pfcenable_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* If set to 1, then PFC is enabled on PRI 0. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \ - UINT32_C(0x1) - /* If set to 1, then PFC is enabled on PRI 1. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \ - UINT32_C(0x2) - /* If set to 1, then PFC is enabled on PRI 2. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \ - UINT32_C(0x4) - /* If set to 1, then PFC is enabled on PRI 3. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \ - UINT32_C(0x8) - /* If set to 1, then PFC is enabled on PRI 4. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \ - UINT32_C(0x10) - /* If set to 1, then PFC is enabled on PRI 5. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \ - UINT32_C(0x20) - /* If set to 1, then PFC is enabled on PRI 6. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \ - UINT32_C(0x40) - /* If set to 1, then PFC is enabled on PRI 7. */ - #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ - UINT32_C(0x80) + /* + * Physical number of ring allocated. + * This value shall be unique for a ring type. + */ + uint16_t ring_id; + /* Logical number of ring allocated. */ + uint16_t logical_ring_id; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -13335,13 +19268,13 @@ struct hwrm_queue_pfcenable_qcfg_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_queue_pfcenable_cfg * - ****************************/ +/****************** + * hwrm_ring_free * + ******************/ -/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ -struct hwrm_queue_pfcenable_cfg_input { +/* hwrm_ring_free_input (size:192b/24B) */ +struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13369,42 +19302,30 @@ struct hwrm_queue_pfcenable_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* If set to 1, then PFC is requested to be enabled on PRI 0. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \ - UINT32_C(0x1) - /* If set to 1, then PFC is requested to be enabled on PRI 1. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ - UINT32_C(0x2) - /* If set to 1, then PFC is requested to be enabled on PRI 2. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ - UINT32_C(0x4) - /* If set to 1, then PFC is requested to be enabled on PRI 3. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ - UINT32_C(0x8) - /* If set to 1, then PFC is requested to be enabled on PRI 4. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ - UINT32_C(0x10) - /* If set to 1, then PFC is requested to be enabled on PRI 5. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ - UINT32_C(0x20) - /* If set to 1, then PFC is requested to be enabled on PRI 6. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ - UINT32_C(0x40) - /* If set to 1, then PFC is requested to be enabled on PRI 7. */ - #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint16_t port_id; - uint8_t unused_0[2]; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ + HWRM_RING_FREE_INPUT_RING_TYPE_NQ + uint8_t unused_0; + /* Physical number of ring allocated. */ + uint16_t ring_id; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ -struct hwrm_queue_pfcenable_cfg_output { +/* hwrm_ring_free_output (size:128b/16B) */ +struct hwrm_ring_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13424,13 +19345,13 @@ struct hwrm_queue_pfcenable_cfg_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_queue_pri2cos_qcfg * - ***************************/ +/************************************** + * hwrm_ring_cmpl_ring_qaggint_params * + **************************************/ -/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_input { +/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13458,37 +19379,13 @@ struct hwrm_queue_pri2cos_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX - /* - * When this bit is set to '0', the query is - * for VLAN PRI field in tunnel headers. - * When this bit is set to '1', the query is - * for VLAN PRI field in inner packet headers. - */ - #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[3]; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ -struct hwrm_queue_pri2cos_qcfg_output { +/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13497,73 +19394,53 @@ struct hwrm_queue_pri2cos_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint16_t flags; /* - * CoS Queue assigned to priority 0. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. - */ - uint8_t pri0_cos_queue_id; - /* - * CoS Queue assigned to priority 1. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * When this bit is set to '1', interrupt max + * timer is reset whenever a completion is received. */ - uint8_t pri1_cos_queue_id; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) /* - * CoS Queue assigned to priority 2 This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. */ - uint8_t pri2_cos_queue_id; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) /* - * CoS Queue assigned to priority 3. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Number of completions to aggregate before DMA + * during the normal mode. */ - uint8_t pri3_cos_queue_id; + uint16_t num_cmpl_dma_aggr; /* - * CoS Queue assigned to priority 4. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Number of completions to aggregate before DMA + * during the interrupt mode. */ - uint8_t pri4_cos_queue_id; + uint16_t num_cmpl_dma_aggr_during_int; /* - * CoS Queue assigned to priority 5. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Timer in unit of 80-nsec used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). */ - uint8_t pri5_cos_queue_id; + uint16_t cmpl_aggr_dma_tmr; /* - * CoS Queue assigned to priority 6. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Timer in unit of 80-nsec used to aggregate completions before + * DMA during the interrupt mode. */ - uint8_t pri6_cos_queue_id; + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time (in unit of 80-nsec) between two interrupts. */ + uint16_t int_lat_tmr_min; /* - * CoS Queue assigned to priority 7. This value can only - * be changed before traffic has started. - * A value of 0xff indicates that no CoS queue is assigned to the - * specified priority. + * Maximum wait time (in unit of 80-nsec) spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. */ - uint8_t pri7_cos_queue_id; - /* Information about queue configuration. */ - uint8_t queue_cfg_info; + uint16_t int_lat_tmr_max; /* - * If this flag is set to '1', then the PRI to CoS - * configuration is asymmetric on TX and RX sides. - * If this flag is set to '0', then PRI to CoS configuration - * is symmetric on TX and RX sides. + * Minimum number of completions aggregated before signaling + * an interrupt. */ - #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ - UINT32_C(0x1) - uint8_t unused_0[6]; + uint16_t num_cmpl_aggr_int; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -13574,13 +19451,13 @@ struct hwrm_queue_pri2cos_qcfg_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_queue_pri2cos_cfg * - **************************/ +/***************************************** + * hwrm_ring_cmpl_ring_cfg_aggint_params * + *****************************************/ -/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ -struct hwrm_queue_pri2cos_cfg_input { +/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13608,129 +19485,260 @@ struct hwrm_queue_pri2cos_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When this bit is set to '1', interrupt latency max + * timer is reset whenever a completion is received. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 - /* tx path */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - /* Bi-directional (Symmetrically applicable to TX and RX paths) */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2) - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) /* - * When this bit is set to '0', the mapping is requested - * for VLAN PRI field in tunnel headers. - * When this bit is set to '1', the mapping is requested - * for VLAN PRI field in inner packet headers. + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) - uint32_t enables; + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) /* - * This bit must be '1' for the pri0_cos_queue_id field to be + * Set this flag to 1 when configuring parameters on a + * notification queue. Set this flag to 0 when configuring + * parameters on a completion queue. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer in unit of 80-nsec used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer in unit of 80-nsec used to aggregate completions before + * DMA during the interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time (in unit of 80-nsec) between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time (in unit of 80-nsec) spent aggregating + * cmpls before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + /* + * Bitfield that indicates which parameters are to be applied. Only + * required when configuring devices with notification queues, and + * used in that case to set certain parameters on completion queues + * and others on notification queues. + */ + uint16_t enables; + /* + * This bit must be '1' for the num_cmpl_dma_aggr field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ UINT32_C(0x1) /* - * This bit must be '1' for the pri1_cos_queue_id field to be + * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ UINT32_C(0x2) /* - * This bit must be '1' for the pri2_cos_queue_id field to be + * This bit must be '1' for the cmpl_aggr_dma_tmr field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ UINT32_C(0x4) /* - * This bit must be '1' for the pri3_cos_queue_id field to be + * This bit must be '1' for the int_lat_tmr_min field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ UINT32_C(0x8) /* - * This bit must be '1' for the pri4_cos_queue_id field to be + * This bit must be '1' for the int_lat_tmr_max field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ UINT32_C(0x10) /* - * This bit must be '1' for the pri5_cos_queue_id field to be + * This bit must be '1' for the num_cmpl_aggr_int field to be * configured. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ UINT32_C(0x20) + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the pri6_cos_queue_id field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \ - UINT32_C(0x40) + uint8_t valid; +} __attribute__((packed)); + +/******************* + * hwrm_ring_reset * + *******************/ + + +/* hwrm_ring_reset_input (size:192b/24B) */ +struct hwrm_ring_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the pri7_cos_queue_id field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \ - UINT32_C(0x80) + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ + HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __attribute__((packed)); + +/* hwrm_ring_reset_output (size:128b/16B) */ +struct hwrm_ring_reset_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t port_id; + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_ring_grp_alloc * + ***********************/ + + +/* hwrm_ring_grp_alloc_input (size:192b/24B) */ +struct hwrm_ring_grp_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * CoS Queue assigned to priority 0. This value can only - * be changed before traffic has started. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t pri0_cos_queue_id; + uint16_t cmpl_ring; /* - * CoS Queue assigned to priority 1. This value can only - * be changed before traffic has started. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t pri1_cos_queue_id; + uint16_t seq_id; /* - * CoS Queue assigned to priority 2 This value can only - * be changed before traffic has started. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t pri2_cos_queue_id; + uint16_t target_id; /* - * CoS Queue assigned to priority 3. This value can only - * be changed before traffic has started. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t pri3_cos_queue_id; + uint64_t resp_addr; /* - * CoS Queue assigned to priority 4. This value can only - * be changed before traffic has started. + * This value identifies the CR associated with the ring + * group. */ - uint8_t pri4_cos_queue_id; + uint16_t cr; /* - * CoS Queue assigned to priority 5. This value can only - * be changed before traffic has started. + * This value identifies the main RR associated with the ring + * group. */ - uint8_t pri5_cos_queue_id; + uint16_t rr; /* - * CoS Queue assigned to priority 6. This value can only - * be changed before traffic has started. + * This value identifies the aggregation RR associated with + * the ring group. If this value is 0xFF... (All Fs), then no + * Aggregation ring will be set. */ - uint8_t pri6_cos_queue_id; + uint16_t ar; /* - * CoS Queue assigned to priority 7. This value can only - * be changed before traffic has started. + * This value identifies the statistics context associated + * with the ring group. */ - uint8_t pri7_cos_queue_id; - uint8_t unused_0[7]; + uint16_t sc; } __attribute__((packed)); -/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ -struct hwrm_queue_pri2cos_cfg_output { +/* hwrm_ring_grp_alloc_output (size:128b/16B) */ +struct hwrm_ring_grp_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13739,7 +19747,13 @@ struct hwrm_queue_pri2cos_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This is the ring group ID value. Use this value to program + * the default ring group for the VNIC or as table entries + * in an RSS/COS context. + */ + uint32_t ring_group_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -13750,13 +19764,13 @@ struct hwrm_queue_pri2cos_cfg_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_queue_cos2bw_qcfg * - **************************/ +/********************** + * hwrm_ring_grp_free * + **********************/ -/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ -struct hwrm_queue_cos2bw_qcfg_input { +/* hwrm_ring_grp_free_input (size:192b/24B) */ +struct hwrm_ring_grp_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -13784,17 +19798,13 @@ struct hwrm_queue_cos2bw_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure TC BW assignment on this port. - */ - uint16_t port_id; - uint8_t unused_0[6]; + /* This is the ring group ID value. */ + uint32_t ring_group_id; + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ -struct hwrm_queue_cos2bw_qcfg_output { +/* hwrm_ring_grp_free_output (size:128b/16B) */ +struct hwrm_ring_grp_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -13803,985 +19813,558 @@ struct hwrm_queue_cos2bw_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* ID of CoS Queue 0. */ - uint8_t queue_id0; - uint8_t unused_0; - uint16_t unused_1; - /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. - */ - uint32_t queue_id0_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t unused_0[7]; /* - * Maximum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t queue_id0_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id0_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \ + uint8_t valid; +} __attribute__((packed)); + +/**************************** + * hwrm_cfa_l2_filter_alloc * + ****************************/ + + +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ +struct hwrm_cfa_l2_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ + /* rx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. */ - uint8_t queue_id0_pri_lvl; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ + UINT32_C(0x4) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * If this flag is set, all t_l2_* fields are invalid + * and they should not be specified. + * If this flag is set, then l2_* fields refer to + * fields of outermost L2 header. */ - uint8_t queue_id0_bw_weight; - /* ID of CoS Queue 1. */ - uint8_t queue_id1; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ + UINT32_C(0x8) + uint32_t enables; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the l2_addr field to be + * configured. */ - uint32_t queue_id1_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ + UINT32_C(0x1) /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the l2_addr_mask field to be + * configured. */ - uint32_t queue_id1_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id1_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This bit must be '1' for the l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ + UINT32_C(0x4) + /* + * This bit must be '1' for the l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ + UINT32_C(0x8) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x10) + /* + * This bit must be '1' for the l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the t_l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ + UINT32_C(0x80) + /* + * This bit must be '1' for the t_l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ + UINT32_C(0x100) + /* + * This bit must be '1' for the t_l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ + UINT32_C(0x200) + /* + * This bit must be '1' for the t_l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ + UINT32_C(0x400) + /* + * This bit must be '1' for the t_l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ + UINT32_C(0x800) + /* + * This bit must be '1' for the src_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. */ - uint8_t queue_id1_pri_lvl; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4000) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This bit must be '1' for the dst_id field to be + * configured. */ - uint8_t queue_id1_bw_weight; - /* ID of CoS Queue 2. */ - uint8_t queue_id2; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - uint32_t queue_id2_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This value sets the match value for the L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. */ - uint32_t queue_id2_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id2_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint8_t l2_addr[6]; + uint8_t unused_0[2]; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This value sets the mask value for the L2 address. + * A value of 0 will mask the corresponding bit from + * compare. */ - uint8_t queue_id2_pri_lvl; + uint8_t l2_addr_mask[6]; + /* This value sets VLAN ID value for outer VLAN. */ + uint16_t l2_ovlan; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This value sets the mask value for the ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. */ - uint8_t queue_id2_bw_weight; - /* ID of CoS Queue 3. */ - uint8_t queue_id3; + uint16_t l2_ovlan_mask; + /* This value sets VLAN ID value for inner VLAN. */ + uint16_t l2_ivlan; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This value sets the mask value for the ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. */ - uint32_t queue_id3_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t l2_ivlan_mask; + uint8_t unused_1[2]; + /* + * This value sets the match value for the tunnel + * L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t t_l2_addr[6]; + uint8_t unused_2[2]; + /* + * This value sets the mask value for the tunnel L2 + * address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t t_l2_addr_mask[6]; + /* This value sets VLAN ID value for tunnel outer VLAN. */ + uint16_t t_l2_ovlan; + /* + * This value sets the mask value for the tunnel ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ovlan_mask; + /* This value sets VLAN ID value for tunnel inner VLAN. */ + uint16_t t_l2_ivlan; + /* + * This value sets the mask value for the tunnel ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ivlan_mask; + /* This value identifies the type of source of the packet. */ + uint8_t src_type; + /* Network port */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) + /* Physical function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) + /* Virtual function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) + /* Virtual NIC of a function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) + /* Embedded processor for CFA management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) + /* Embedded processor for OOB management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) + /* Embedded processor for RoCE */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) + /* Embedded processor for network proxy functions */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG + uint8_t unused_3; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This value is the id of the source. + * For a network port, it represents port_id. + * For a physical function, it represents fid. + * For a virtual function, it represents vf_id. + * For a vnic, it represents vnic_id. + * For embedded processors, this id is not valid. + * + * Notes: + * 1. The function ID is implied if it src_id is + * not provided for a src_type that is either */ - uint32_t queue_id3_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id3_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \ + uint32_t src_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_4; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. - */ - uint8_t queue_id3_pri_lvl; - /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - uint8_t queue_id3_bw_weight; - /* ID of CoS Queue 4. */ - uint8_t queue_id4; + uint16_t dst_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - uint32_t queue_id4_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t mirror_vnic_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This hint is provided to help in placing + * the filter in the filter table. */ - uint32_t queue_id4_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id4_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ + /* Above the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ + /* Below the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + /* As high as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ + UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN + uint8_t unused_5; + uint32_t unused_6; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + * + * This field is valid only for the following values. + * 1 - Above the given filter + * 2 - Below the given filter + */ + uint64_t l2_filter_id_hint; +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_l2_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - uint8_t queue_id4_pri_lvl; + uint64_t l2_filter_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This is the ID of the flow associated with this + * filter. + * This value shall be used to match and associate the + * flow identifier returned in completion records. + * A value of 0xFFFFFFFF shall indicate no flow id. */ - uint8_t queue_id4_bw_weight; - /* ID of CoS Queue 5. */ - uint8_t queue_id5; + uint32_t flow_id; + uint8_t unused_0[3]; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t queue_id5_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_cfa_l2_filter_free * + ***************************/ + + +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_l2_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t queue_id5_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id5_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t cmpl_ring; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id5_pri_lvl; + uint16_t seq_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t queue_id5_bw_weight; - /* ID of CoS Queue 6. */ - uint8_t queue_id6; + uint16_t target_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id6_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID + uint64_t resp_addr; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_cfa_l2_filter_cfg * + **************************/ + + +/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ +struct hwrm_cfa_l2_filter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t queue_id6_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id6_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t cmpl_ring; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id6_pri_lvl; + uint16_t seq_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t queue_id6_bw_weight; - /* ID of CoS Queue 7. */ - uint8_t queue_id7; + uint16_t target_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id7_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + uint64_t resp_addr; + uint32_t flags; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint32_t queue_id7_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id7_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) + uint32_t enables; + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - uint8_t queue_id7_pri_lvl; + uint64_t l2_filter_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - uint8_t queue_id7_bw_weight; - uint8_t unused_2[4]; + uint32_t dst_id; + /* + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t new_mirror_vnic_id; +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14792,13 +20375,13 @@ struct hwrm_queue_cos2bw_qcfg_output { uint8_t valid; } __attribute__((packed)); -/************************* - * hwrm_queue_cos2bw_cfg * - *************************/ +/*************************** + * hwrm_cfa_l2_set_rx_mask * + ***************************/ -/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ -struct hwrm_queue_cos2bw_cfg_input { +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ +struct hwrm_cfa_l2_set_rx_mask_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14826,1044 +20409,563 @@ struct hwrm_queue_cos2bw_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - uint32_t enables; - /* - * If this bit is set to 1, then all queue_id0 related - * parameters in this command are valid. - */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \ - UINT32_C(0x1) + /* VNIC ID */ + uint32_t vnic_id; + uint32_t mask; /* - * If this bit is set to 1, then all queue_id1 related - * parameters in this command are valid. + * When this bit is '1', the function is requested to accept + * multi-cast packets specified by the multicast addr table. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ UINT32_C(0x2) /* - * If this bit is set to 1, then all queue_id2 related - * parameters in this command are valid. + * When this bit is '1', the function is requested to accept + * all multi-cast packets. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ UINT32_C(0x4) /* - * If this bit is set to 1, then all queue_id3 related - * parameters in this command are valid. + * When this bit is '1', the function is requested to accept + * broadcast packets. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ UINT32_C(0x8) /* - * If this bit is set to 1, then all queue_id4 related - * parameters in this command are valid. - */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \ - UINT32_C(0x10) - /* - * If this bit is set to 1, then all queue_id5 related - * parameters in this command are valid. - */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \ - UINT32_C(0x20) - /* - * If this bit is set to 1, then all queue_id6 related - * parameters in this command are valid. - */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \ - UINT32_C(0x40) - /* - * If this bit is set to 1, then all queue_id7 related - * parameters in this command are valid. - */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \ - UINT32_C(0x80) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure TC BW assignment on this port. - */ - uint16_t port_id; - /* ID of CoS Queue 0. */ - uint8_t queue_id0; - uint8_t unused_0; - /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. - */ - uint32_t queue_id0_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID - /* - * Maximum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. - */ - uint32_t queue_id0_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id0_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) - /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. - */ - uint8_t queue_id0_pri_lvl; - /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. - */ - uint8_t queue_id0_bw_weight; - /* ID of CoS Queue 1. */ - uint8_t queue_id1; - /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. - */ - uint32_t queue_id1_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID + * When this bit is '1', the function is requested to be + * put in the promiscuous mode. + * + * The HWRM should accept any function to set up + * promiscuous mode. + * + * The HWRM shall follow the semantics below for the + * promiscuous mode support. + * # When partitioning is not enabled on a port + * (i.e. single PF on the port), then the PF shall + * be allowed to be in the promiscuous mode. When the + * PF is in the promiscuous mode, then it shall + * receive all host bound traffic on that port. + * # When partitioning is enabled on a port + * (i.e. multiple PFs per port) and a PF on that + * port is in the promiscuous mode, then the PF + * receives all traffic within that partition as + * identified by a unique identifier for the + * PF (e.g. S-Tag). If a unique outer VLAN + * for the PF is specified, then the setting of + * promiscuous mode on that PF shall result in the + * PF receiving all host bound traffic with matching + * outer VLAN. + * # A VF shall can be set in the promiscuous mode. + * In the promiscuous mode, the VF does not receive any + * traffic unless a unique outer VLAN for the + * VF is specified. If a unique outer VLAN + * for the VF is specified, then the setting of + * promiscuous mode on that VF shall result in the + * VF receiving all host bound traffic with the + * matching outer VLAN. + * # The HWRM shall allow the setting of promiscuous + * mode on a function independently from the + * promiscuous mode settings on other functions. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ + UINT32_C(0x10) /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the outermost Layer 2 destination MAC + * address field. */ - uint32_t queue_id1_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id1_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ + UINT32_C(0x20) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the VLAN-tagged packets that match the + * TPID and VID fields of VLAN tags in the VLAN tag + * table specified in this command. */ - uint8_t queue_id1_pri_lvl; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ + UINT32_C(0x40) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets that match the TPID and VID fields of VLAN + * tags in the VLAN tag table specified in this command. */ - uint8_t queue_id1_bw_weight; - /* ID of CoS Queue 2. */ - uint8_t queue_id2; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ + UINT32_C(0x80) /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets matching any VLAN tag. + * + * If this flag is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan + * flags is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * The HWRM client shall set at most one flag out of + * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. */ - uint32_t queue_id2_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ + UINT32_C(0x100) + /* This is the address for mcast address tbl. */ + uint64_t mc_tbl_addr; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This value indicates how many entries in mc_tbl are valid. + * Each entry is 6 bytes. */ - uint32_t queue_id2_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id2_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \ + uint32_t num_mc_entries; + uint8_t unused_0[4]; + /* + * This is the address for VLAN tag table. + * Each VLAN entry in the table is 4 bytes of a VLAN tag + * including TPID, PCP, DEI, and VID fields in network byte + * order. + */ + uint64_t vlan_tag_tbl_addr; + /* + * This value indicates how many entries in vlan_tag_tbl are + * valid. Each entry is 4 bytes. + */ + uint32_t num_vlan_tags; + uint8_t unused_1[4]; +} __attribute__((packed)); + +/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ +struct hwrm_cfa_l2_set_rx_mask_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ +struct hwrm_cfa_l2_set_rx_mask_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \ + /* Unable to complete operation due to conflict with Ntuple Filter */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ + HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR + uint8_t unused_0[7]; +} __attribute__((packed)); + +/******************************* + * hwrm_cfa_vlan_antispoof_cfg * + *******************************/ + + +/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t queue_id2_pri_lvl; + uint16_t cmpl_ring; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id2_bw_weight; - /* ID of CoS Queue 3. */ - uint8_t queue_id3; + uint16_t seq_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint32_t queue_id3_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID + uint16_t target_id; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id3_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id3_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint64_t resp_addr; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * Function ID of the function that is being configured. + * Only valid for a VF FID configured by the PF. */ - uint8_t queue_id3_pri_lvl; + uint16_t fid; + uint8_t unused_0[2]; + /* Number of VLAN entries in the vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table. Each table entry contains the 16-bit TPID + * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, + * all in network order to match hwrm_cfa_l2_set_rx_mask. + * For an individual VLAN entry, the mask value should be 0xfff + * for the 12-bit VLAN ID. */ - uint8_t queue_id3_bw_weight; - /* ID of CoS Queue 4. */ - uint8_t queue_id4; + uint64_t vlan_tag_mask_tbl_addr; +} __attribute__((packed)); + +/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t queue_id4_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID + uint8_t valid; +} __attribute__((packed)); + +/******************************** + * hwrm_cfa_vlan_antispoof_qcfg * + ********************************/ + + +/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t queue_id4_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id4_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t cmpl_ring; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id4_pri_lvl; + uint16_t seq_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t queue_id4_bw_weight; - /* ID of CoS Queue 5. */ - uint8_t queue_id5; + uint16_t target_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id5_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID + uint64_t resp_addr; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * Function ID of the function that is being queried. + * Only valid for a VF FID queried by the PF. */ - uint32_t queue_id5_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id5_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \ - UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \ - UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) + uint16_t fid; + uint8_t unused_0[2]; /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * Maximum number of VLAN entries the firmware is allowed to DMA + * to vlan_tag_mask_tbl. + */ + uint32_t max_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table to which firmware will DMA to. Each table + * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), + * 16-bit VLAN ID, and a 16-bit mask, all in network order to + * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, + * the mask value should be 0xfff for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} __attribute__((packed)); + +/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************** + * hwrm_cfa_tunnel_filter_alloc * + ********************************/ + + +/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ +struct hwrm_cfa_tunnel_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t queue_id5_pri_lvl; + uint16_t seq_id; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint8_t queue_id5_bw_weight; - /* ID of CoS Queue 6. */ - uint8_t queue_id6; + uint16_t target_id; /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t queue_id6_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID + uint64_t resp_addr; + uint32_t flags; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + uint32_t enables; /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the l2_filter_id field to be + * configured. */ - uint32_t queue_id6_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id6_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \ - UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \ + /* + * This bit must be '1' for the l2_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \ - UINT32_C(0xff) /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * This bit must be '1' for the l2_ivlan field to be + * configured. */ - uint8_t queue_id6_pri_lvl; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x4) /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * This bit must be '1' for the l3_addr field to be + * configured. */ - uint8_t queue_id6_bw_weight; - /* ID of CoS Queue 7. */ - uint8_t queue_id7; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \ + UINT32_C(0x8) /* - * Minimum BW allocated to CoS Queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the l3_addr_type field to be + * configured. */ - uint32_t queue_id7_min_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \ + UINT32_C(0x10) /* - * Maximum BW allocated to CoS queue. - * The HWRM will translate this value into byte counter and - * time interval used for this COS inside the device. + * This bit must be '1' for the t_l3_addr_type field to be + * configured. */ - uint32_t queue_id7_max_bw; - /* The bandwidth value. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID - /* Transmission Selection Algorithm (TSA) for CoS Queue. */ - uint8_t queue_id7_tsa_assign; - /* Strict Priority */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l3_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the vni field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dst_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \ + UINT32_C(0x200) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x400) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * This value sets the match value for the inner L2 + * MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* + * This value sets VLAN ID value for inner VLAN. + * Only 12-bits of VLAN ID are used in setting the filter. + */ + uint16_t l2_ivlan; + /* + * The value of inner destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t l3_addr[4]; + /* + * The value of tunnel destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t t_l3_addr[4]; + /* + * This value indicates the type of inner IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t l3_addr_type; + /* + * This value indicates the type of tunnel IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t t_l3_addr_type; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ UINT32_C(0x0) - /* Enhanced Transmission Selection */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \ + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ UINT32_C(0x2) - /* reserved. */ - #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \ + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* - * Priority level for strict priority. Valid only when the - * tsa_assign is 0 - Strict Priority (SP) - * 0..7 - Valid values. - * 8..255 - Reserved. + * tunnel_flags allows the user to indicate the tunnel tag detection + * for the tunnel type specified in tunnel_type. */ - uint8_t queue_id7_pri_lvl; + uint8_t tunnel_flags; /* - * Weight used to allocate remaining BW for this COS after - * servicing guaranteed bandwidths for all COS. + * If the tunnel_type is geneve, then this bit indicates if we + * need to match the geneve OAM packet. + * If the tunnel_type is nvgre or gre, then this bit indicates if + * we need to detect checksum present bit in geneve header. + * If the tunnel_type is mpls, then this bit indicates if we need + * to match mpls packet with explicit IPV4/IPV6 null header. */ - uint8_t queue_id7_bw_weight; - uint8_t unused_1[5]; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \ + UINT32_C(0x1) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to detect the critical option bit set in the oam packet. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with key present bit set in + * gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from inner/second label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \ + UINT32_C(0x2) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to match geneve packet with extended header bit set in + * geneve header. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with sequence number + * present bit set in gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from out/first label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \ + UINT32_C(0x4) + /* + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t vni; + /* Logical VNIC ID of the destination VNIC. */ + uint32_t dst_vnic_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t mirror_vnic_id; } __attribute__((packed)); -/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ -struct hwrm_queue_cos2bw_cfg_output { +/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -15872,7 +20974,17 @@ struct hwrm_queue_cos2bw_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; + /* + * This is the ID of the flow associated with this + * filter. + * This value shall be used to match and associate the + * flow identifier returned in completion records. + * A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint32_t flow_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15883,13 +20995,13 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t valid; } __attribute__((packed)); -/************************* - * hwrm_queue_dscp_qcaps * - *************************/ +/******************************* + * hwrm_cfa_tunnel_filter_free * + *******************************/ -/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ -struct hwrm_queue_dscp_qcaps_input { +/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -15917,17 +21029,12 @@ struct hwrm_queue_dscp_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; } __attribute__((packed)); -/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ -struct hwrm_queue_dscp_qcaps_output { +/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_tunnel_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -15936,12 +21043,7 @@ struct hwrm_queue_dscp_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of bits provided by the hardware for the DSCP value. */ - uint8_t num_dscp_bits; - uint8_t unused_0; - /* Max number of DSCP-MASK-PRI entries supported. */ - uint16_t max_entries; - uint8_t unused_1[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15952,13 +21054,13 @@ struct hwrm_queue_dscp_qcaps_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_queue_dscp2pri_qcfg * - ****************************/ +/*************************************** + * hwrm_cfa_redirect_tunnel_type_alloc * + ***************************************/ -/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ -struct hwrm_queue_dscp2pri_qcfg_input { +/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -15986,25 +21088,58 @@ struct hwrm_queue_dscp2pri_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI - * tuple(s) will be copied to. - */ - uint64_t dest_data_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0; - /* Size of the buffer pointed to by dest_data_addr. */ - uint16_t dest_data_buffer_size; - uint8_t unused_1[4]; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* Tunnel alloc flags. */ + uint8_t flags; + /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ + UINT32_C(0x1) + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_qcfg_output { +/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16013,17 +21148,107 @@ struct hwrm_queue_dscp2pri_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint8_t unused_0[7]; /* - * A count of the number of DSCP-MASK-PRI tuple(s) pointed to - * by the dest_data_addr. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t entry_cnt; + uint8_t valid; +} __attribute__((packed)); + +/************************************** + * hwrm_cfa_redirect_tunnel_type_free * + **************************************/ + + +/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is the default PRI which un-initialized DSCP values are - * mapped to. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t default_pri; - uint8_t unused_0[4]; + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; +} __attribute__((packed)); + +/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16034,13 +21259,13 @@ struct hwrm_queue_dscp2pri_qcfg_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_queue_dscp2pri_cfg * - ***************************/ +/************************************** + * hwrm_cfa_redirect_tunnel_type_info * + **************************************/ -/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ -struct hwrm_queue_dscp2pri_cfg_input { +/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16068,43 +21293,53 @@ struct hwrm_queue_dscp2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI tuple - * will be copied from. - */ - uint64_t src_data_addr; - uint32_t flags; - /* use_hw_default_pri is 1 b */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ - UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the default_pri field to be - * configured. - */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ + /* The source function id. */ + uint16_t src_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - /* - * This is the default PRI which un-initialized DSCP values will be - * mapped to. - */ - uint8_t default_pri; - /* - * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed - * to by src_data_addr. - */ - uint16_t entry_cnt; - uint8_t unused_0[4]; + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; } __attribute__((packed)); -/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_cfg_output { +/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16113,7 +21348,9 @@ struct hwrm_queue_dscp2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16124,13 +21361,113 @@ struct hwrm_queue_dscp2pri_cfg_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_vnic_alloc * - *******************/ +/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ +struct hwrm_vxlan_ipv4_hdr { + /* IPv4 version and header length. */ + uint8_t ver_hlen; + /* IPv4 header length */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 + /* Version */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 + /* IPv4 type of service. */ + uint8_t tos; + /* IPv4 identification. */ + uint16_t ip_id; + /* IPv4 flags and offset. */ + uint16_t flags_frag_offset; + /* IPv4 TTL. */ + uint8_t ttl; + /* IPv4 protocol. */ + uint8_t protocol; + /* IPv4 source address. */ + uint32_t src_ip_addr; + /* IPv4 destination address. */ + uint32_t dest_ip_addr; +} __attribute__((packed)); + +/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ +struct hwrm_vxlan_ipv6_hdr { + /* IPv6 version, traffic class and flow label. */ + uint32_t ver_tc_flow_label; + /* IPv6 version shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \ + UINT32_C(0x1c) + /* IPv6 version mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \ + UINT32_C(0xf0000000) + /* IPv6 TC shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \ + UINT32_C(0x14) + /* IPv6 TC mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \ + UINT32_C(0xff00000) + /* IPv6 flow label shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \ + UINT32_C(0x0) + /* IPv6 flow label mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \ + UINT32_C(0xfffff) + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \ + HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK + /* IPv6 payload length. */ + uint16_t payload_len; + /* IPv6 next header. */ + uint8_t next_hdr; + /* IPv6 TTL. */ + uint8_t ttl; + /* IPv6 source address. */ + uint32_t src_ip_addr[4]; + /* IPv6 destination address. */ + uint32_t dest_ip_addr[4]; +} __attribute__((packed)); + +/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */ +struct hwrm_cfa_encap_data_vxlan { + /* Source MAC address. */ + uint8_t src_mac_addr[6]; + /* reserved. */ + uint16_t unused_0; + /* Destination MAC address. */ + uint8_t dst_mac_addr[6]; + /* Number of VLAN tags. */ + uint8_t num_vlan_tags; + /* reserved. */ + uint8_t unused_1; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + /* L3 header fields. */ + uint32_t l3[10]; + /* IP version mask. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) + /* IP version 4. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) + /* IP version 6. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \ + HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 + /* UDP source port. */ + uint16_t src_port; + /* UDP destination port. */ + uint16_t dst_port; + /* VXLAN Network Identifier. */ + uint32_t vni; +} __attribute__((packed)); + +/******************************* + * hwrm_cfa_encap_record_alloc * + *******************************/ -/* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { +/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ +struct hwrm_cfa_encap_record_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16159,16 +21496,44 @@ struct hwrm_vnic_alloc_input { */ uint64_t resp_addr; uint32_t flags; - /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. - */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - uint8_t unused_0[4]; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ + UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ + UINT32_C(0x8) + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE + uint8_t unused_0[3]; + /* This value is encap data used for the given encap type. */ + uint32_t encap_data[20]; } __attribute__((packed)); -/* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { +/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16177,8 +21542,8 @@ struct hwrm_vnic_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -16190,13 +21555,13 @@ struct hwrm_vnic_alloc_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_vnic_free * - ******************/ +/****************************** + * hwrm_cfa_encap_record_free * + ******************************/ -/* hwrm_vnic_free_input (size:192b/24B) */ -struct hwrm_vnic_free_input { +/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ +struct hwrm_cfa_encap_record_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16224,13 +21589,13 @@ struct hwrm_vnic_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_vnic_free_output (size:128b/16B) */ -struct hwrm_vnic_free_output { +/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16250,13 +21615,13 @@ struct hwrm_vnic_free_output { uint8_t valid; } __attribute__((packed)); -/***************** - * hwrm_vnic_cfg * - *****************/ +/******************************** + * hwrm_cfa_ntuple_filter_alloc * + ********************************/ -/* hwrm_vnic_cfg_input (size:320b/40B) */ -struct hwrm_vnic_cfg_input { +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16276,176 +21641,324 @@ struct hwrm_vnic_cfg_input { * * 0xFFF8-0xFFFE - Reserved for internal processors * * 0xFFFF - HWRM */ - uint16_t target_id; + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ + UINT32_C(0x2) + /* + * Setting of this flag indicates that a meter is expected to be attached + * to this flow. This hint can be used when choosing the action record + * format required for the flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ + UINT32_C(0x4) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the src_macaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x20) + /* + * This bit must be '1' for the src_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ + UINT32_C(0x40) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x80) + /* + * This bit must be '1' for the dst_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ + UINT32_C(0x100) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x200) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x400) + /* + * This bit must be '1' for the src_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ + UINT32_C(0x800) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the dst_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ + UINT32_C(0x2000) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the pri_hint field to be + * configured. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ + UINT32_C(0x4000) /* - * When this bit is '1', the VNIC is requested to - * be the default VNIC for the function. + * This bit must be '1' for the ntuple_filter_id field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ - UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ + UINT32_C(0x8000) /* - * When this bit is '1', the VNIC is being configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. + * This bit must be '1' for the dst_id field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x10000) /* - * When this bit is '1', the VNIC is being configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is being configured to be - * disabled on this VNIC. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x20000) /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to be - * operating in dual VNIC mode. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ + UINT32_C(0x40000) /* - * When this flag is set to '1', the VNIC is requested to - * be configured to receive only RoCE traffic. - * If this flag is set to '0', then this flag shall be - * ignored by the HWRM. - * If roce_dual_vnic_mode flag is set to '1' - * or roce_mirroring_capable_vnic_mode flag to 1, - * then the HWRM client shall not set this flag to '1'. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) + uint64_t l2_filter_id; /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * This flag is used to enable a mode where - * RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured using hwrm_vnic_rss_cfg. - * - * If this mode is enabled, then the driver should not program - * RSS indirection table for the RSS context that is used for - * computing RSS hash only. + * This value indicates the source MAC address in + * the Ethernet header. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) + uint8_t src_macaddr[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic, but forward only the - * RoCE traffic further. Also, RoCE traffic can be mirrored to - * L2 driver. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) - uint32_t enables; + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * This bit must be '1' for the dflt_ring_grp field to be - * configured. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ - UINT32_C(0x1) + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP /* - * This bit must be '1' for the rss_rule field to be - * configured. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ - UINT32_C(0x2) + uint16_t dst_id; /* - * This bit must be '1' for the cos_rule field to be - * configured. + * Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ - UINT32_C(0x4) + uint16_t mirror_vnic_id; /* - * This bit must be '1' for the lb_rule field to be - * configured. + * This value indicates the tunnel type for this filter. + * If this field is not specified, then the filter shall + * apply to both non-tunneled and tunneled packets. + * If this field conflicts with the tunnel_type specified + * in the l2_filter_id, then the HWRM shall return an + * error for this command. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* - * This bit must be '1' for the mru field to be - * configured. + * This hint is provided to help in placing + * the filter in the filter table. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ - UINT32_C(0x10) + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ + UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ + UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ + UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST /* - * This bit must be '1' for the default_rx_ring_id field to be - * configured. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ - UINT32_C(0x20) + uint32_t src_ipaddr[4]; /* - * This bit must be '1' for the default_cmpl_ring_id field to be - * configured. + * The value of source IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ - UINT32_C(0x40) - /* Logical vnic ID */ - uint16_t vnic_id; + uint32_t src_ipaddr_mask[4]; /* - * Default Completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules and if - * there is no COS rule. + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint16_t dflt_ring_grp; + uint32_t dst_ipaddr[4]; /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. + * The value of destination IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. */ - uint16_t rss_rule; + uint32_t dst_ipaddr_mask[4]; /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t cos_rule; + uint16_t src_port; /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. + * The value of source port mask to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t lb_rule; + uint16_t src_port_mask; /* - * The maximum receive unit of the vnic. - * Each vnic is associated with a function. - * The vnic mru value overwrites the mru setting of the - * associated function. - * The HWRM shall make sure that vnic mru does not exceed - * the mru of the port the function is associated with. + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t mru; + uint16_t dst_port; /* - * Default Rx ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. - * The aggregation ring associated with the Rx ring is - * implied based on the Rx ring specified when the - * aggregation ring was allocated. + * The value of destination port mask to be used in + * filtering. + * Applies to UDP and TCP traffic. */ - uint16_t default_rx_ring_id; + uint16_t dst_port_mask; /* - * Default completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. + * This is the ID of the filter that goes along with + * the pri_hint. */ - uint16_t default_cmpl_ring_id; + uint64_t ntuple_filter_id_hint; } __attribute__((packed)); -/* hwrm_vnic_cfg_output (size:128b/16B) */ -struct hwrm_vnic_cfg_output { +/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16454,7 +21967,17 @@ struct hwrm_vnic_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * This is the ID of the flow associated with this + * filter. + * This value shall be used to match and associate the + * flow identifier returned in completion records. + * A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint32_t flow_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16465,13 +21988,31 @@ struct hwrm_vnic_cfg_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_vnic_qcfg * - ******************/ +/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ +struct hwrm_cfa_ntuple_filter_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* Unable to complete operation due to conflict with Rx Mask VLAN */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ + UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR + uint8_t unused_0[7]; +} __attribute__((packed)); + +/******************************* + * hwrm_cfa_ntuple_filter_free * + *******************************/ -/* hwrm_vnic_qcfg_input (size:256b/32B) */ -struct hwrm_vnic_qcfg_input { +/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16499,21 +22040,12 @@ struct hwrm_vnic_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vf_id_valid field to be - * configured. - */ - #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) - /* Logical vnic ID */ - uint32_t vnic_id; - /* ID of Virtual Function whose VNIC resource is being queried. */ - uint16_t vf_id; - uint8_t unused_0[6]; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; } __attribute__((packed)); -/* hwrm_vnic_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_qcfg_output { +/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -16522,94 +22054,7 @@ struct hwrm_vnic_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Default Completion ring for the VNIC. */ - uint16_t dflt_ring_grp; - /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. - */ - uint16_t rss_rule; - /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. - */ - uint16_t cos_rule; - /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. - */ - uint16_t lb_rule; - /* The maximum receive unit of the vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* - * When this bit is '1', the VNIC is the default VNIC for - * the function. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to - * operate in dual VNIC mode. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) - /* - * When this flag is set to '1', the VNIC is configured to - * receive only RoCE traffic. - * When this flag is set to '0', the VNIC is not configured - * to receive only RoCE traffic. - * If roce_dual_vnic_mode flag and this flag both are set - * to '1', then it is an invalid configuration of the - * VNIC. The HWRM should not allow that type of - * mis-configuration by HWRM clients. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) - /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * When this bit is set to '1', then the VNIC is enabled in a - * mode where RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) - /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic, but forward only - * RoCE traffic further. Also RoCE traffic can be mirrored to - * L2 driver. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16620,13 +22065,13 @@ struct hwrm_vnic_qcfg_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_vnic_qcaps * - *******************/ +/****************************** + * hwrm_cfa_ntuple_filter_cfg * + ******************************/ -/* hwrm_vnic_qcaps_input (size:192b/24B) */ -struct hwrm_vnic_qcaps_input { +/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ +struct hwrm_cfa_ntuple_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16655,87 +22100,67 @@ struct hwrm_vnic_qcaps_input { */ uint64_t resp_addr; uint32_t enables; - uint8_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_vnic_qcaps_output (size:192b/24B) */ -struct hwrm_vnic_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The maximum receive unit that is settable on a vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* Unused. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ + /* + * This bit must be '1' for the new_dst_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ UINT32_C(0x1) /* - * When this bit is '1', the capability of stripping VLAN in - * the RX path is supported on VNIC(s). - * If set to '0', then VLAN stripping capability is - * not supported on VNIC(s). + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ UINT32_C(0x2) /* - * When this bit is '1', the capability to buffer receive - * packets in the hardware until the host posts new receive buffers - * is supported on VNIC(s). - * If set to '0', then bd_stall capability is not supported - * on VNIC(s). + * This bit must be '1' for the new_meter_instance_id field to be + * configured. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ UINT32_C(0x4) + uint8_t unused_0[4]; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; /* - * When this bit is '1', the capability to - * receive both RoCE and non-RoCE traffic on VNIC(s) is - * supported. - * If set to '0', then the capability to receive - * both RoCE and non-RoCE traffic on VNIC(s) is - * not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ - UINT32_C(0x8) - /* - * When this bit is set to '1', the capability to configure - * a VNIC to receive only RoCE traffic is supported. - * When this flag is set to '0', the VNIC capability to - * configure to receive only RoCE traffic is not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ - UINT32_C(0x10) - /* - * When this bit is set to '1', then the capability to enable - * a VNIC in a mode where RSS context without configuring - * RSS indirection table is supported (for RSS hash computation). - * When this bit is set to '0', then a VNIC can not be configured - * with a mode to enable RSS context without configuring RSS - * indirection table. + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and new network port id of the destination port for + * the TX path. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ - UINT32_C(0x20) + uint32_t new_dst_id; /* - * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. - * If set to '0', then the capability to mirror the - * RoCE traffic is not supported. + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ - UINT32_C(0x40) + uint32_t new_mirror_vnic_id; /* - * When this bit is '1', the outermost RSS hashing capability - * is supported. If set to '0', then the outermost RSS hashing - * capability is not supported. + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ - UINT32_C(0x80) - uint8_t unused_1[7]; + uint16_t new_meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ + HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID + uint8_t unused_1[6]; +} __attribute__((packed)); + +/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16746,13 +22171,13 @@ struct hwrm_vnic_qcaps_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_vnic_tpa_cfg * - *********************/ +/************************** + * hwrm_cfa_em_flow_alloc * + **************************/ -/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ -struct hwrm_vnic_tpa_cfg_input { +/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ +struct hwrm_cfa_em_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -16782,323 +22207,324 @@ struct hwrm_vnic_tpa_cfg_input { uint64_t resp_addr; uint32_t flags; /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates enabling of a byte counter for a given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) + /* + * Setting of this flag indicates enabling of a packet counter for a given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) + /* Setting of this flag indicates de-capsulation action for the given flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) + /* Setting of this flag indicates encapsulation action for the given flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) + /* + * Setting of this flag indicates that a meter is expected to be attached + * to this flow. This hint can be used when choosing the action record + * format required for the flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ UINT32_C(0x1) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. + * This bit must be '1' for the tunnel_type field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ UINT32_C(0x2) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. + * This bit must be '1' for the tunnel_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ UINT32_C(0x4) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. + * This bit must be '1' for the src_macaddr field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ UINT32_C(0x8) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x10) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. + * This bit must be '1' for the ovlan_vid field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ UINT32_C(0x20) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. + * This bit must be '1' for the ivlan_vid field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ UINT32_C(0x40) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x80) - uint32_t enables; /* - * This bit must be '1' for the max_agg_segs field to be + * This bit must be '1' for the src_ipaddr field to be * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x100) /* - * This bit must be '1' for the max_aggs field to be + * This bit must be '1' for the dst_ipaddr field to be * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x200) /* - * This bit must be '1' for the max_agg_timer field to be + * This bit must be '1' for the ipaddr_type field to be * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x400) /* - * This bit must be '1' for the min_agg_len field to be + * This bit must be '1' for the ip_protocol field to be * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) - /* Logical vnic ID */ - uint16_t vnic_id; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x800) /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. + * This bit must be '1' for the src_port field to be + * configured. */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x1000) /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7 + * This bit must be '1' for the dst_port field to be + * configured. */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX - uint8_t unused_0[2]; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x2000) /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. + * This bit must be '1' for the dst_id field to be + * configured. */ - uint32_t max_agg_timer; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x4000) /* - * This is the minimum amount of payload length required to - * start an aggregation context. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - uint32_t min_agg_len; -} __attribute__((packed)); - -/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ -struct hwrm_vnic_tpa_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x8000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the encap_record_id field to be + * configured. */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_vnic_tpa_qcfg * - **********************/ - - -/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_tpa_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ + UINT32_C(0x10000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the meter_instance_id field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ + UINT32_C(0x20000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - uint16_t seq_id; + uint64_t l2_filter_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[3]; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. */ - uint16_t target_id; + uint32_t tunnel_id; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value indicates the source MAC address in + * the Ethernet header. */ - uint64_t resp_addr; - /* Logical vnic ID */ - uint16_t vnic_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_tpa_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + uint8_t src_macaddr[6]; + /* The meter instance to attach to the flow. */ + uint16_t meter_instance_id; /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. + * A value of 0xfff is considered invalid and implies the + * instance is not configured. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \ - UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. + * This value indicates the destination MAC address in + * the Ethernet header. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \ - UINT32_C(0x2) + uint8_t dst_macaddr[6]; /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \ - UINT32_C(0x4) + uint16_t ovlan_vid; /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \ - UINT32_C(0x8) + uint16_t ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \ - UINT32_C(0x10) + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ - UINT32_C(0x20) + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP + uint8_t unused_1[2]; /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \ - UINT32_C(0x40) + uint32_t src_ipaddr[4]; /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. + * big_endian = True + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \ - UINT32_C(0x80) + uint32_t dst_ipaddr[4]; /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \ - HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX + uint16_t src_port; /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7 + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \ - HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX + uint16_t dst_port; /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - uint32_t max_agg_timer; + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* Logical ID of the encapsulation record. */ + uint32_t encap_record_id; + uint8_t unused_2[4]; +} __attribute__((packed)); + +/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ +struct hwrm_cfa_em_flow_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; /* - * This is the minimum amount of payload length required to - * start an aggregation context. + * This is the ID of the flow associated with this + * filter. + * This value shall be used to match and associate the + * flow identifier returned in completion records. + * A value of 0xFFFFFFFF shall indicate no flow id. */ - uint32_t min_agg_len; - uint8_t unused_0[7]; + uint32_t flow_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17109,13 +22535,13 @@ struct hwrm_vnic_tpa_qcfg_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_vnic_rss_cfg * - *********************/ +/************************* + * hwrm_cfa_em_flow_free * + *************************/ -/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ -struct hwrm_vnic_rss_cfg_input { +/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ +struct hwrm_cfa_em_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17143,103 +22569,12 @@ struct hwrm_vnic_rss_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* VNIC ID of VNIC associated with RSS table being configured. */ - uint16_t vnic_id; - /* - * Specifies which VNIC ring table pair to configure. - * Valid values range from 0 to 7. - */ - uint8_t ring_table_pair_index; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; - /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) - /* This is the address for rss ring group table */ - uint64_t ring_grp_tbl_addr; - /* This is the address for rss hash key table */ - uint64_t hash_key_tbl_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; } __attribute__((packed)); -/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ -struct hwrm_vnic_rss_cfg_output { +/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ +struct hwrm_cfa_em_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17259,13 +22594,13 @@ struct hwrm_vnic_rss_cfg_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_vnic_rss_qcfg * - **********************/ +/************************ + * hwrm_cfa_em_flow_cfg * + ************************/ -/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_rss_qcfg_input { +/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */ +struct hwrm_cfa_em_flow_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17293,104 +22628,68 @@ struct hwrm_vnic_rss_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ -struct hwrm_vnic_rss_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + uint32_t enables; /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. + * This bit must be '1' for the new_dst_id field to be + * configured. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \ + UINT32_C(0x1) /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ + UINT32_C(0x2) /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * This bit must be '1' for the new_meter_instance_id field to be + * configured. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ + UINT32_C(0x4) uint8_t unused_0[4]; - /* This is the value of rss hash key */ - uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; - /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) + uint32_t new_dst_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) + uint32_t new_mirror_vnic_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + uint16_t new_meter_instance_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * A value of 0xfff is considered invalid and implies the + * instance is not configured. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ + HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID uint8_t unused_1[6]; +} __attribute__((packed)); + +/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */ +struct hwrm_cfa_em_flow_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17401,13 +22700,13 @@ struct hwrm_vnic_rss_qcfg_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_vnic_plcmodes_cfg * - **************************/ +/******************************** + * hwrm_cfa_meter_profile_alloc * + ********************************/ -/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ -struct hwrm_vnic_plcmodes_cfg_input { +/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17435,116 +22734,314 @@ struct hwrm_vnic_plcmodes_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint8_t flags; /* - * When this bit is '1', the VNIC shall be configured to - * use regular placement algorithm. - * By default, the regular placement algorithm shall be - * enabled on the VNIC. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) - /* - * When this bit is '1', the VNIC shall be configured - * use the jumbo placement algorithm. - */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ + UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv4 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv4, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv4, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv4 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv4 - * packet. + * This field is reserved for the future use. + * It shall be set to 0. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ - UINT32_C(0x4) + uint16_t reserved1; /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv6 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv6, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv6, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv6 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv6 - * packet. + * This field is reserved for the future use. + * It shall be set to 0. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ - UINT32_C(0x8) + uint32_t reserved2; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID +} __attribute__((packed)); + +/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for FCoE packets at the - * beginning of FC payload. + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ - UINT32_C(0x10) + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID + uint8_t unused_0[5]; /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for RoCE packets at the - * beginning of RoCE payload (after BTH/GRH headers). + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ - UINT32_C(0x20) - uint32_t enables; + uint8_t valid; +} __attribute__((packed)); + +/******************************* + * hwrm_cfa_meter_profile_free * + *******************************/ + + +/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_profile_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the jumbo_thresh_valid field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * This bit must be '1' for the hds_offset_valid field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ - UINT32_C(0x2) + uint16_t seq_id; /* - * This bit must be '1' for the hds_threshold_valid field to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ - UINT32_C(0x4) - /* Logical vnic ID */ - uint32_t vnic_id; + uint16_t target_id; /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t jumbo_thresh; + uint64_t resp_addr; + uint8_t flags; /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint16_t hds_offset; + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - uint16_t hds_threshold; - uint8_t unused_0[6]; + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ -struct hwrm_vnic_plcmodes_cfg_output { +/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17564,13 +23061,13 @@ struct hwrm_vnic_plcmodes_cfg_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_vnic_plcmodes_qcfg * - ***************************/ +/****************************** + * hwrm_cfa_meter_profile_cfg * + ******************************/ -/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_input { +/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17598,13 +23095,223 @@ struct hwrm_vnic_plcmodes_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ + UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ + UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID } __attribute__((packed)); -/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_output { +/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17613,75 +23320,7 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When this bit is '1', the VNIC is configured to - * use regular placement algorithm. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * use the jumbo placement algorithm. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv4 packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv6 packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ - UINT32_C(0x8) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for FCoE packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ - UINT32_C(0x10) - /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for RoCE packets. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ - UINT32_C(0x20) - /* - * When this bit is '1', the VNIC is configured - * to be the default VNIC of the requesting function. - */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ - UINT32_C(0x40) - /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. - */ - uint16_t jumbo_thresh; - /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. - */ - uint16_t hds_offset; - /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. - */ - uint16_t hds_threshold; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17692,13 +23331,13 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint8_t valid; } __attribute__((packed)); -/********************************** - * hwrm_vnic_rss_cos_lb_ctx_alloc * - **********************************/ +/********************************* + * hwrm_cfa_meter_instance_alloc * + *********************************/ -/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { +/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17726,10 +23365,38 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { +/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17738,8 +23405,16 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -17751,13 +23426,13 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { uint8_t valid; } __attribute__((packed)); -/********************************* - * hwrm_vnic_rss_cos_lb_ctx_free * - *********************************/ - +/******************************** + * hwrm_cfa_meter_instance_free * + ********************************/ -/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_input { + +/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17785,13 +23460,37 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[6]; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_output { +/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -17811,13 +23510,13 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_ring_alloc * - *******************/ +/******************************* + * hwrm_cfa_decap_filter_alloc * + *******************************/ -/* hwrm_ring_alloc_input (size:640b/80B) */ -struct hwrm_ring_alloc_input { +/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ +struct hwrm_cfa_decap_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -17845,268 +23544,529 @@ struct hwrm_ring_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; + /* ovs_tunnel is 1 b */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \ + UINT32_C(0x1) uint32_t enables; /* - * This bit must be '1' for the ring_arb_cfg field to be + * This bit must be '1' for the tunnel_type field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the tunnel_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \ UINT32_C(0x2) /* - * This bit must be '1' for the stat_ctx_id_valid field to be + * This bit must be '1' for the src_macaddr field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + UINT32_C(0x4) + /* + * This bit must be '1' for the dst_macaddr field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x8) /* - * This bit must be '1' for the max_bw_valid field to be + * This bit must be '1' for the ovlan_vid field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ivlan_vid field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \ UINT32_C(0x20) /* - * This bit must be '1' for the rx_ring_id field to be + * This bit must be '1' for the t_ovlan_vid field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \ UINT32_C(0x40) /* - * This bit must be '1' for the nq_ring_id field to be + * This bit must be '1' for the t_ivlan_vid field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \ UINT32_C(0x80) /* - * This bit must be '1' for the rx_buf_size field to be + * This bit must be '1' for the ethertype field to be * configured. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x100) - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ - HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0[3]; /* - * This value is a pointer to the page table for the - * Ring. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - uint64_t page_tbl_addr; - /* First Byte Offset of the first entry in the first page. */ - uint32_t fbo; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x200) /* - * Actual page size in 2^page_size. The supported range is increments - * in powers of 2 from 16 bytes to 1GB. - * - 4 = 16 B - * Page size is 16 B. - * - 12 = 4 KB - * Page size is 4 KB. - * - 13 = 8 KB - * Page size is 8 KB. - * - 16 = 64 KB - * Page size is 64 KB. - * - 21 = 2 MB - * Page size is 2 MB. - * - 22 = 4 MB - * Page size is 4 MB. - * - 30 = 1 GB - * Page size is 1 GB. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - uint8_t page_size; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x400) /* - * This value indicates the depth of page table. - * For this version of the specification, value other than 0 or - * 1 shall be considered as an invalid value. - * When the page_tbl_depth = 0, then it is treated as a - * special case with the following. - * 1. FBO and page size fields are not valid. - * 2. page_tbl_addr is the physical address of the first - * element of the ring. + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x800) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0; + uint16_t unused_1; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + uint8_t unused_2[2]; + /* + * This value indicates the destination MAC address in + * the Ethernet header. + */ + uint8_t dst_macaddr[6]; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. + */ + uint16_t ivlan_vid; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the tunnel Ethernet header. + */ + uint16_t t_ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the tunnel Ethernet header. + */ + uint16_t t_ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + uint16_t unused_3; + uint32_t unused_4; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path. */ - uint8_t page_tbl_depth; - uint8_t unused_1[2]; + uint16_t dst_id; /* - * Number of 16B units in the ring. Minimum size for - * a ring is 16 16B entries. + * If set, this value shall represent the L2 context that matches the L2 + * information of the decap filter. */ - uint32_t length; + uint16_t l2_ctxt_ref_id; +} __attribute__((packed)); + +/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[3]; /* - * Logical ring number for the ring to be allocated. - * This value determines the position in the doorbell - * area where the update to the ring will be made. - * - * For completion rings, this value is also the MSI-X - * vector number for the function the completion ring is - * associated with. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t logical_id; + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_cfa_decap_filter_free * + ******************************/ + + +/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_decap_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field is used only when ring_type is a TX ring. - * This value indicates what completion ring the TX ring - * is associated with. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t cmpl_ring_id; + uint16_t cmpl_ring; /* - * This field is used only when ring_type is a TX ring. - * This value indicates what CoS queue the TX ring - * is associated with. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t queue_id; + uint16_t seq_id; /* - * When allocating a Rx ring or Rx aggregation ring, this field - * specifies the size of the buffer descriptors posted to the ring. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint16_t rx_buf_size; + uint16_t target_id; /* - * When allocating an Rx aggregation ring, this field - * specifies the associated Rx ring ID. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t rx_ring_id; + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * When allocating a completion ring, this field - * specifies the associated NQ ring ID. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t nq_ring_id; + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_cfa_flow_alloc * + ***********************/ + + +/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_flow_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field is used only when ring_type is a TX ring. - * This field is used to configure arbitration related - * parameters for a TX ring. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t ring_arb_cfg; - /* Arbitration policy used for the ring. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ - UINT32_C(0xf) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + uint16_t cmpl_ring; /* - * Use strict priority for the TX ring. - * Priority value is specified in arb_policy_param + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ - UINT32_C(0x1) + uint16_t seq_id; /* - * Use weighted fair queue arbitration for the TX ring. - * Weight is specified in arb_policy_param + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ - UINT32_C(0x2) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ - HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ - /* Reserved field. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + uint16_t target_id; /* - * Arbitration policy specific parameter. - * # For strict priority arbitration policy, this field - * represents a priority value. If set to 0, then the priority - * is not specified and the HWRM is allowed to select - * any priority for this TX ring. - * # For weighted fair queue arbitration policy, this field - * represents a weight value. If set to 0, then the weight - * is not specified and the HWRM is allowed to select - * any weight for this TX ring. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ - UINT32_C(0xff00) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 - uint16_t unused_3; + uint64_t resp_addr; + uint16_t flags; + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1) + /* num_vlan is 2 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 + /* no tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ + (UINT32_C(0x0) << 1) + /* 1 tag */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \ + (UINT32_C(0x1) << 1) + /* 2 tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \ + (UINT32_C(0x2) << 1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO + /* Enumeration denoting the Flow Type. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 + /* L2 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ + (UINT32_C(0x0) << 3) + /* IPV4 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \ + (UINT32_C(0x1) << 3) + /* IPV6 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \ + (UINT32_C(0x2) << 3) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * This field is reserved for the future use. - * It shall be set to 0. + * Tx Flow: vf fid. + * Rx Flow: pf fid. */ - uint32_t reserved3; + uint16_t src_fid; + /* Tunnel handle valid when tunnel flag is set. */ + uint32_t tunnel_handle; + uint16_t action_flags; /* - * This field is used only when ring_type is a TX ring. - * This input indicates what statistics context this ring - * should be associated with. + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. */ - uint32_t stat_ctx_id; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ + UINT32_C(0x1) + /* recycle is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ + UINT32_C(0x2) /* - * This field is reserved for the future use. - * It shall be set to 0. + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. */ - uint32_t reserved4; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ + UINT32_C(0x4) + /* meter is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \ + UINT32_C(0x8) + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \ + UINT32_C(0x10) + /* nat_src is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \ + UINT32_C(0x20) + /* nat_dest is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \ + UINT32_C(0x40) + /* nat_ipv4_address is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \ + UINT32_C(0x80) + /* l2_header_rewrite is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \ + UINT32_C(0x100) + /* ttl_decrement is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ + UINT32_C(0x200) /* - * This field is used only when ring_type is a TX ring - * to specify maximum BW allocated to the TX ring. - * The HWRM will translate this value into byte counter and - * time interval used for this ring inside the device. + * Tx Flow: pf or vf fid. + * Rx Flow: vf fid. + */ + uint16_t dst_fid; + /* VLAN tpid, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tci; + /* Meter id, valid when meter flag is set. */ + uint16_t act_meter_id; + /* Flow with the same l2 context tcam key. */ + uint16_t ref_flow_handle; + /* This value sets the match value for the ethertype. */ + uint16_t ethertype; + /* valid when num tags is 1 or 2. */ + uint16_t outer_vlan_tci; + /* This value sets the match value for the Destination MAC address. */ + uint16_t dmac[3]; + /* valid when num tags is 2. */ + uint16_t inner_vlan_tci; + /* This value sets the match value for the Source MAC address. */ + uint16_t smac[3]; + /* The bit length of destination IP address mask. */ + uint8_t ip_dst_mask_len; + /* The bit length of source IP address mask. */ + uint8_t ip_src_mask_len; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; + /* + * The value of source port. + * Applies to UDP and TCP traffic. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + uint16_t l4_src_port; /* - * This field is used only when ring_type is a Completion ring. - * This value indicates what interrupt mode should be used - * on this completion ring. - * Note: In the legacy interrupt mode, no more than 16 - * completion rings are allowed. + * The value of source port mask. + * Applies to UDP and TCP traffic. */ - uint8_t int_mode; - /* Legacy INTA */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) - /* Reserved */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) - /* MSI-X */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) - /* No Interrupt - Polled mode */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ - HWRM_RING_ALLOC_INPUT_INT_MODE_POLL - uint8_t unused_4[3]; + uint16_t l4_src_port_mask; + /* + * The value of destination port. + * Applies to UDP and TCP traffic. + */ + uint16_t l4_dst_port; + /* + * The value of destination port mask. + * Applies to UDP and TCP traffic. + */ + uint16_t l4_dst_port_mask; + /* + * NAT IPv4/6 address based on address type flag. + * 0 values are ignored. + */ + uint32_t nat_ip_address[4]; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; + /* + * The NAT source/destination port based on direction flag. + * Applies to UDP and TCP traffic. + * 0 values are ignored. + */ + uint16_t nat_port; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* The value of ip protocol. */ + uint8_t ip_proto; + uint8_t unused_0; } __attribute__((packed)); -/* hwrm_ring_alloc_output (size:128b/16B) */ -struct hwrm_ring_alloc_output { +/* hwrm_cfa_flow_alloc_output (size:128b/16B) */ +struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18115,14 +24075,9 @@ struct hwrm_ring_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Physical number of ring allocated. - * This value shall be unique for a ring type. - */ - uint16_t ring_id; - /* Logical number of ring allocated. */ - uint16_t logical_ring_id; - uint8_t unused_0[3]; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18133,13 +24088,13 @@ struct hwrm_ring_alloc_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_ring_free * - ******************/ +/********************** + * hwrm_cfa_flow_free * + **********************/ -/* hwrm_ring_free_input (size:192b/24B) */ -struct hwrm_ring_free_input { +/* hwrm_cfa_flow_free_input (size:192b/24B) */ +struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18167,30 +24122,13 @@ struct hwrm_ring_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ - HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; - /* Physical number of ring allocated. */ - uint16_t ring_id; - uint8_t unused_1[4]; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_ring_free_output (size:128b/16B) */ -struct hwrm_ring_free_output { +/* hwrm_cfa_flow_free_output (size:256b/32B) */ +struct hwrm_cfa_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18199,6 +24137,10 @@ struct hwrm_ring_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet is 64 b */ + uint64_t packet; + /* byte is 64 b */ + uint64_t byte; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -18210,13 +24152,13 @@ struct hwrm_ring_free_output { uint8_t valid; } __attribute__((packed)); -/************************************** - * hwrm_ring_cmpl_ring_qaggint_params * - **************************************/ +/********************** + * hwrm_cfa_flow_info * + **********************/ -/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_input { +/* hwrm_cfa_flow_info_input (size:192b/24B) */ +struct hwrm_cfa_flow_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18244,13 +24186,23 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; + /* Flow record index. */ + uint16_t flow_handle; + /* Max flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ + UINT32_C(0xfff) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ + UINT32_C(0x1000) + /* Direction rx = 1 */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ + UINT32_C(0x8000) uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_output { +/* hwrm_cfa_flow_info_output (size:448b/56B) */ +struct hwrm_cfa_flow_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18259,52 +24211,28 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* - * When this bit is set to '1', interrupt max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ - UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ - UINT32_C(0x2) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; - /* - * Number of completions to aggregate before DMA - * during the interrupt mode. - */ - uint16_t num_cmpl_dma_aggr_during_int; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). - */ - uint16_t cmpl_aggr_dma_tmr; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. - */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; - /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. - */ - uint16_t int_lat_tmr_max; - /* - * Minimum number of completions aggregated before signaling - * an interrupt. - */ - uint16_t num_cmpl_aggr_int; + /* flags is 8 b */ + uint8_t flags; + /* profile is 8 b */ + uint8_t profile; + /* src_fid is 16 b */ + uint16_t src_fid; + /* dst_fid is 16 b */ + uint16_t dst_fid; + /* l2_ctxt_id is 16 b */ + uint16_t l2_ctxt_id; + /* em_info is 64 b */ + uint64_t em_info; + /* tcam_info is 64 b */ + uint64_t tcam_info; + /* vfp_tcam_info is 64 b */ + uint64_t vfp_tcam_info; + /* ar_id is 16 b */ + uint16_t ar_id; + /* flow_handle is 16 b */ + uint16_t flow_handle; + /* tunnel_handle is 32 b */ + uint32_t tunnel_handle; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -18316,13 +24244,13 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output { uint8_t valid; } __attribute__((packed)); -/***************************************** - * hwrm_ring_cmpl_ring_cfg_aggint_params * - *****************************************/ +/*********************** + * hwrm_cfa_flow_flush * + ***********************/ -/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +/* hwrm_cfa_flow_flush_input (size:192b/24B) */ +struct hwrm_cfa_flow_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18350,109 +24278,92 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint16_t flags; - /* - * When this bit is set to '1', interrupt latency max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ - UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ - UINT32_C(0x2) - /* - * Set this flag to 1 when configuring parameters on a - * notification queue. Set this flag to 0 when configuring - * parameters on a completion queue. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ - UINT32_C(0x4) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; - /* - * Number of completions to aggregate before DMA - * during the interrupt mode. - */ - uint16_t num_cmpl_dma_aggr_during_int; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). - */ - uint16_t cmpl_aggr_dma_tmr; - /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. - */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; - /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * cmpls before signaling the interrupt after the - * interrupt is enabled. - */ - uint16_t int_lat_tmr_max; - /* - * Minimum number of completions aggregated before signaling - * an interrupt. - */ - uint16_t num_cmpl_aggr_int; - /* - * Bitfield that indicates which parameters are to be applied. Only - * required when configuring devices with notification queues, and - * used in that case to set certain parameters on completion queues - * and others on notification queues. - */ - uint16_t enables; - /* - * This bit must be '1' for the num_cmpl_dma_aggr field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ - UINT32_C(0x1) + uint32_t flags; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_cfa_flow_flush_output (size:128b/16B) */ +struct hwrm_cfa_flow_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ - UINT32_C(0x2) + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_cfa_flow_stats * + ***********************/ + + +/* hwrm_cfa_flow_stats_input (size:320b/40B) */ +struct hwrm_cfa_flow_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the cmpl_aggr_dma_tmr field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ - UINT32_C(0x4) + uint16_t cmpl_ring; /* - * This bit must be '1' for the int_lat_tmr_min field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ - UINT32_C(0x8) + uint16_t seq_id; /* - * This bit must be '1' for the int_lat_tmr_max field to be - * configured. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ - UINT32_C(0x10) + uint16_t target_id; /* - * This bit must be '1' for the num_cmpl_aggr_int field to be - * configured. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ - UINT32_C(0x20) - uint8_t unused_0[4]; + uint64_t resp_addr; + /* Flow handle. */ + uint16_t num_flows; + /* Flow handle. */ + uint16_t flow_handle_0; + /* Flow handle. */ + uint16_t flow_handle_1; + /* Flow handle. */ + uint16_t flow_handle_2; + /* Flow handle. */ + uint16_t flow_handle_3; + /* Flow handle. */ + uint16_t flow_handle_4; + /* Flow handle. */ + uint16_t flow_handle_5; + /* Flow handle. */ + uint16_t flow_handle_6; + /* Flow handle. */ + uint16_t flow_handle_7; + /* Flow handle. */ + uint16_t flow_handle_8; + /* Flow handle. */ + uint16_t flow_handle_9; + uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { +/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ +struct hwrm_cfa_flow_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18461,6 +24372,46 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet_0 is 64 b */ + uint64_t packet_0; + /* packet_1 is 64 b */ + uint64_t packet_1; + /* packet_2 is 64 b */ + uint64_t packet_2; + /* packet_3 is 64 b */ + uint64_t packet_3; + /* packet_4 is 64 b */ + uint64_t packet_4; + /* packet_5 is 64 b */ + uint64_t packet_5; + /* packet_6 is 64 b */ + uint64_t packet_6; + /* packet_7 is 64 b */ + uint64_t packet_7; + /* packet_8 is 64 b */ + uint64_t packet_8; + /* packet_9 is 64 b */ + uint64_t packet_9; + /* byte_0 is 64 b */ + uint64_t byte_0; + /* byte_1 is 64 b */ + uint64_t byte_1; + /* byte_2 is 64 b */ + uint64_t byte_2; + /* byte_3 is 64 b */ + uint64_t byte_3; + /* byte_4 is 64 b */ + uint64_t byte_4; + /* byte_5 is 64 b */ + uint64_t byte_5; + /* byte_6 is 64 b */ + uint64_t byte_6; + /* byte_7 is 64 b */ + uint64_t byte_7; + /* byte_8 is 64 b */ + uint64_t byte_8; + /* byte_9 is 64 b */ + uint64_t byte_9; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -18472,13 +24423,13 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_ring_reset * - *******************/ +/************************** + * hwrm_cfa_vf_pair_alloc * + **************************/ -/* hwrm_ring_reset_input (size:192b/24B) */ -struct hwrm_ring_reset_input { +/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18506,26 +24457,17 @@ struct hwrm_ring_reset_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ - HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL - uint8_t unused_0; - /* Physical number of the ring. */ - uint16_t ring_id; - uint8_t unused_1[4]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + uint8_t unused_0[4]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; } __attribute__((packed)); -/* hwrm_ring_reset_output (size:128b/16B) */ -struct hwrm_ring_reset_output { +/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18545,13 +24487,13 @@ struct hwrm_ring_reset_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_ring_grp_alloc * - ***********************/ +/************************* + * hwrm_cfa_vf_pair_free * + *************************/ -/* hwrm_ring_grp_alloc_input (size:192b/24B) */ -struct hwrm_ring_grp_alloc_input { +/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ +struct hwrm_cfa_vf_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18579,31 +24521,12 @@ struct hwrm_ring_grp_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies the CR associated with the ring - * group. - */ - uint16_t cr; - /* - * This value identifies the main RR associated with the ring - * group. - */ - uint16_t rr; - /* - * This value identifies the aggregation RR associated with - * the ring group. If this value is 0xFF... (All Fs), then no - * Aggregation ring will be set. - */ - uint16_t ar; - /* - * This value identifies the statistics context associated - * with the ring group. - */ - uint16_t sc; + /* VF Pair name (32 byte string). */ + char pair_name[32]; } __attribute__((packed)); -/* hwrm_ring_grp_alloc_output (size:128b/16B) */ -struct hwrm_ring_grp_alloc_output { +/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_vf_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18612,13 +24535,7 @@ struct hwrm_ring_grp_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This is the ring group ID value. Use this value to program - * the default ring group for the VNIC or as table entries - * in an RSS/COS context. - */ - uint32_t ring_group_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18629,13 +24546,13 @@ struct hwrm_ring_grp_alloc_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_ring_grp_free * - **********************/ +/************************* + * hwrm_cfa_vf_pair_info * + *************************/ -/* hwrm_ring_grp_free_input (size:192b/24B) */ -struct hwrm_ring_grp_free_input { +/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_vf_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18663,13 +24580,18 @@ struct hwrm_ring_grp_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the ring group ID value. */ - uint32_t ring_group_id; - uint8_t unused_0[4]; + uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* vf pair table index. */ + uint16_t vf_pair_index; + uint8_t unused_0[2]; + /* VF Pair name (32 byte string). */ + char vf_pair_name[32]; } __attribute__((packed)); -/* hwrm_ring_grp_free_output (size:128b/16B) */ -struct hwrm_ring_grp_free_output { +/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ +struct hwrm_cfa_vf_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18678,7 +24600,28 @@ struct hwrm_ring_grp_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* vf pair table index. */ + uint16_t next_vf_pair_index; + /* vf pair member a's vf_fid. */ + uint16_t vf_a_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* vf pair member b's vf_fid. */ + uint16_t vf_b_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* vf pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + uint8_t unused_0[5]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18689,13 +24632,13 @@ struct hwrm_ring_grp_free_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_cfa_l2_filter_alloc * - ****************************/ +/*********************** + * hwrm_cfa_pair_alloc * + ***********************/ -/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ -struct hwrm_cfa_l2_filter_alloc_input { +/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ +struct hwrm_cfa_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18717,330 +24660,98 @@ struct hwrm_cfa_l2_filter_alloc_input { */ uint16_t target_id; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x2) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x4) - /* - * If this flag is set, all t_l2_* fields are invalid - * and they should not be specified. - * If this flag is set, then l2_* fields refer to - * fields of outermost L2 header. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ - UINT32_C(0x8) - uint32_t enables; - /* - * This bit must be '1' for the l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ - UINT32_C(0x1) - /* - * This bit must be '1' for the l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ - UINT32_C(0x2) - /* - * This bit must be '1' for the l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ - UINT32_C(0x4) - /* - * This bit must be '1' for the l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ - UINT32_C(0x8) - /* - * This bit must be '1' for the l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ - UINT32_C(0x10) - /* - * This bit must be '1' for the l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ - UINT32_C(0x20) - /* - * This bit must be '1' for the t_l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ - UINT32_C(0x40) - /* - * This bit must be '1' for the t_l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ - UINT32_C(0x80) - /* - * This bit must be '1' for the t_l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ - UINT32_C(0x100) - /* - * This bit must be '1' for the t_l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ - UINT32_C(0x200) - /* - * This bit must be '1' for the t_l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ - UINT32_C(0x400) - /* - * This bit must be '1' for the t_l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ - UINT32_C(0x800) - /* - * This bit must be '1' for the src_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the src_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x10000) - /* - * This value sets the match value for the L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t l2_addr[6]; - uint8_t unused_0[2]; - /* - * This value sets the mask value for the L2 address. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint8_t l2_addr_mask[6]; - /* This value sets VLAN ID value for outer VLAN. */ - uint16_t l2_ovlan; - /* - * This value sets the mask value for the ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ovlan_mask; - /* This value sets VLAN ID value for inner VLAN. */ - uint16_t l2_ivlan; - /* - * This value sets the mask value for the ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ivlan_mask; - uint8_t unused_1[2]; - /* - * This value sets the match value for the tunnel - * L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t t_l2_addr[6]; - uint8_t unused_2[2]; + uint64_t resp_addr; + /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */ + uint8_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + /* Modify exiting rep2fn pair and move pair to new PF. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) + /* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL + uint8_t unused_0; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical Host (0xff-local host). */ + uint8_t host_b_id; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + /* Loopback port (0xff-internal loopback), valid for mode-3. */ + uint8_t port_id; + /* Priority used for encap of loopback packets valid for mode-3. */ + uint8_t pri; + /* New PF for rep2fn modify, valid for mode 5. */ + uint16_t new_pf_fid; + uint32_t enables; /* - * This value sets the mask value for the tunnel L2 - * address. - * A value of 0 will mask the corresponding bit from - * compare. + * This bit must be '1' for the q_ab field to be + * configured. */ - uint8_t t_l2_addr_mask[6]; - /* This value sets VLAN ID value for tunnel outer VLAN. */ - uint16_t t_l2_ovlan; + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) /* - * This value sets the mask value for the tunnel ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * This bit must be '1' for the q_ba field to be + * configured. */ - uint16_t t_l2_ovlan_mask; - /* This value sets VLAN ID value for tunnel inner VLAN. */ - uint16_t t_l2_ivlan; + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) /* - * This value sets the mask value for the tunnel ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * This bit must be '1' for the fc_ab field to be + * configured. */ - uint16_t t_l2_ivlan_mask; - /* This value identifies the type of source of the packet. */ - uint8_t src_type; - /* Network port */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) - /* Physical function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) - /* Virtual function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) - /* Virtual NIC of a function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) - /* Embedded processor for CFA management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) - /* Embedded processor for OOB management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) - /* Embedded processor for RoCE */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) - /* Embedded processor for network proxy functions */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG - uint8_t unused_3; + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) /* - * This value is the id of the source. - * For a network port, it represents port_id. - * For a physical function, it represents fid. - * For a virtual function, it represents vf_id. - * For a vnic, it represents vnic_id. - * For embedded processors, this id is not valid. - * - * Notes: - * 1. The function ID is implied if it src_id is - * not provided for a src_type that is either + * This bit must be '1' for the fc_ba field to be + * configured. */ - uint32_t src_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Any tunneled traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_4; + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) + /* VF Pair name (32 byte string). */ + char pair_name[32]; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * The q_ab value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the A to B direction of + * the interface pair. The default value is 0. */ - uint16_t dst_id; + uint8_t q_ab; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * The q_ba value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the B to A direction of + * the interface pair. The default value is 1. */ - uint16_t mirror_vnic_id; + uint8_t q_ba; /* - * This hint is provided to help in placing - * the filter in the filter table. + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the A to B direction. The default value is 0, meaning that + * packets will be dropped when the B-side RX rings are full. */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ - UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ - UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ - UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ - UINT32_C(0x4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN - uint8_t unused_5; - uint32_t unused_6; + uint8_t fc_ab; /* - * This is the ID of the filter that goes along with - * the pri_hint. - * - * This field is valid only for the following values. - * 1 - Above the given filter - * 2 - Below the given filter + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the B to A direction. The default value is 1, meaning that + * the RX CoS queue will be flow controlled when the A-side RX rings + * are full. */ - uint64_t l2_filter_id_hint; + uint8_t fc_ba; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_l2_filter_alloc_output { +/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ +struct hwrm_cfa_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19049,20 +24760,15 @@ struct hwrm_cfa_l2_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This is the ID of the flow associated with this - * filter. - * This value shall be used to match and associate the - * flow identifier returned in completion records. - * A value of 0xFFFFFFFF shall indicate no flow id. - */ - uint32_t flow_id; - uint8_t unused_0[3]; + /* Only valid for modes 1 and 2. */ + uint16_t rx_cfa_code_a; + /* Only valid for modes 1 and 2. */ + uint16_t tx_cfa_action_a; + /* Only valid for mode 2. */ + uint16_t rx_cfa_code_b; + /* Only valid for mode 2. */ + uint16_t tx_cfa_action_b; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -19073,13 +24779,13 @@ struct hwrm_cfa_l2_filter_alloc_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_cfa_l2_filter_free * - ***************************/ +/********************** + * hwrm_cfa_pair_free * + **********************/ -/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_l2_filter_free_input { +/* hwrm_cfa_pair_free_input (size:384b/48B) */ +struct hwrm_cfa_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19107,15 +24813,12 @@ struct hwrm_cfa_l2_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; + /* VF Pair name (32 byte string). */ + char pair_name[32]; } __attribute__((packed)); -/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_free_output { +/* hwrm_cfa_pair_free_output (size:128b/16B) */ +struct hwrm_cfa_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19135,13 +24838,13 @@ struct hwrm_cfa_l2_filter_free_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_cfa_l2_filter_cfg * - **************************/ +/********************** + * hwrm_cfa_pair_info * + **********************/ -/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ -struct hwrm_cfa_l2_filter_cfg_input { +/* hwrm_cfa_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19170,57 +24873,139 @@ struct hwrm_cfa_l2_filter_cfg_input { */ uint64_t resp_addr; uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* If this flag is set, lookup by PF id and VF id. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) + /* Pair table index. */ + uint16_t pair_index; + /* Pair pf index. */ + uint8_t pair_pfid; + /* Pair vf index. */ + uint8_t pair_vfid; + /* Pair name (32 byte string). */ + char pair_name[32]; +} __attribute__((packed)); + +/* hwrm_cfa_pair_info_output (size:576b/72B) */ +struct hwrm_cfa_pair_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Pair table index. */ + uint16_t next_pair_index; + /* Pair member a's fid. */ + uint16_t a_fid; + /* Logical host number. */ + uint8_t host_a_index; + /* Logical PF number. */ + uint8_t pf_a_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_a; + /* Tx CFA action. */ + uint16_t tx_cfa_action_a; + /* Pair member b's fid. */ + uint16_t b_fid; + /* Logical host number. */ + uint8_t host_b_index; + /* Logical PF number. */ + uint8_t pf_b_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_b; + /* Tx CFA action. */ + uint16_t tx_cfa_action_b; + /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ + uint8_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR + /* Pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + /* Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_0[7]; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) - uint32_t enables; + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ + + +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vfr_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the dst_id field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ - UINT32_C(0x1) + uint16_t cmpl_ring; /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) + uint16_t seq_id; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t l2_filter_id; + uint16_t target_id; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t dst_id; + uint64_t resp_addr; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint32_t new_mirror_vnic_id; + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; } __attribute__((packed)); -/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_cfg_output { +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vfr_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19229,7 +25014,11 @@ struct hwrm_cfa_l2_filter_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -19240,13 +25029,13 @@ struct hwrm_cfa_l2_filter_cfg_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_cfa_l2_set_rx_mask * - ***************************/ +/********************* + * hwrm_cfa_vfr_free * + *********************/ -/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ -struct hwrm_cfa_l2_set_rx_mask_input { +/* hwrm_cfa_vfr_free_input (size:384b/48B) */ +struct hwrm_cfa_vfr_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19274,134 +25063,12 @@ struct hwrm_cfa_l2_set_rx_mask_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VNIC ID */ - uint32_t vnic_id; - uint32_t mask; - /* - * When this bit is '1', the function is requested to accept - * multi-cast packets specified by the multicast addr table. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ - UINT32_C(0x2) - /* - * When this bit is '1', the function is requested to accept - * all multi-cast packets. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ - UINT32_C(0x4) - /* - * When this bit is '1', the function is requested to accept - * broadcast packets. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ - UINT32_C(0x8) - /* - * When this bit is '1', the function is requested to be - * put in the promiscuous mode. - * - * The HWRM should accept any function to set up - * promiscuous mode. - * - * The HWRM shall follow the semantics below for the - * promiscuous mode support. - * # When partitioning is not enabled on a port - * (i.e. single PF on the port), then the PF shall - * be allowed to be in the promiscuous mode. When the - * PF is in the promiscuous mode, then it shall - * receive all host bound traffic on that port. - * # When partitioning is enabled on a port - * (i.e. multiple PFs per port) and a PF on that - * port is in the promiscuous mode, then the PF - * receives all traffic within that partition as - * identified by a unique identifier for the - * PF (e.g. S-Tag). If a unique outer VLAN - * for the PF is specified, then the setting of - * promiscuous mode on that PF shall result in the - * PF receiving all host bound traffic with matching - * outer VLAN. - * # A VF shall can be set in the promiscuous mode. - * In the promiscuous mode, the VF does not receive any - * traffic unless a unique outer VLAN for the - * VF is specified. If a unique outer VLAN - * for the VF is specified, then the setting of - * promiscuous mode on that VF shall result in the - * VF receiving all host bound traffic with the - * matching outer VLAN. - * # The HWRM shall allow the setting of promiscuous - * mode on a function independently from the - * promiscuous mode settings on other functions. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ - UINT32_C(0x10) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the outermost Layer 2 destination MAC - * address field. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ - UINT32_C(0x20) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the VLAN-tagged packets that match the - * TPID and VID fields of VLAN tags in the VLAN tag - * table specified in this command. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ - UINT32_C(0x40) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets that match the TPID and VID fields of VLAN - * tags in the VLAN tag table specified in this command. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ - UINT32_C(0x80) - /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets matching any VLAN tag. - * - * If this flag is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan - * flags is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * The HWRM client shall set at most one flag out of - * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. - */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ - UINT32_C(0x100) - /* This is the address for mcast address tbl. */ - uint64_t mc_tbl_addr; - /* - * This value indicates how many entries in mc_tbl are valid. - * Each entry is 6 bytes. - */ - uint32_t num_mc_entries; - uint8_t unused_0[4]; - /* - * This is the address for VLAN tag table. - * Each VLAN entry in the table is 4 bytes of a VLAN tag - * including TPID, PCP, DEI, and VID fields in network byte - * order. - */ - uint64_t vlan_tag_tbl_addr; - /* - * This value indicates how many entries in vlan_tag_tbl are - * valid. Each entry is 4 bytes. - */ - uint32_t num_vlan_tags; - uint8_t unused_1[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; } __attribute__((packed)); -/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ -struct hwrm_cfa_l2_set_rx_mask_output { +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +struct hwrm_cfa_vfr_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19421,31 +25088,13 @@ struct hwrm_cfa_l2_set_rx_mask_output { uint8_t valid; } __attribute__((packed)); -/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ -struct hwrm_cfa_l2_set_rx_mask_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* Unable to complete operation due to conflict with Ntuple Filter */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ - HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR - uint8_t unused_0[7]; -} __attribute__((packed)); - -/******************************* - * hwrm_cfa_vlan_antispoof_cfg * - *******************************/ +/****************************** + * hwrm_tunnel_dst_port_query * + ******************************/ -/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_cfg_input { +/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ +struct hwrm_tunnel_dst_port_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19473,27 +25122,27 @@ struct hwrm_cfa_vlan_antispoof_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being configured. - * Only valid for a VF FID configured by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* Number of VLAN entries in the vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table. Each table entry contains the 16-bit TPID - * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, - * all in network order to match hwrm_cfa_l2_set_rx_mask. - * For an individual VLAN entry, the mask value should be 0xfff - * for the 12-bit VLAN ID. - */ - uint64_t vlan_tag_mask_tbl_addr; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ + HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 + uint8_t unused_0[7]; } __attribute__((packed)); -/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_cfg_output { +/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ +struct hwrm_tunnel_dst_port_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19502,7 +25151,25 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This field represents the identifier of L4 destination port + * used for the given tunnel type. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. + */ + uint16_t tunnel_dst_port_id; + /* + * This field represents the value of L4 destination port + * identified by tunnel_dst_port_id. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. + * This field is in network byte order. + * + * A value of 0 means that the destination port is not + * configured. + */ + uint16_t tunnel_dst_port_val; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -19513,13 +25180,13 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint8_t valid; } __attribute__((packed)); -/******************************** - * hwrm_cfa_vlan_antispoof_qcfg * - ********************************/ +/****************************** + * hwrm_tunnel_dst_port_alloc * + ******************************/ -/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_input { +/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ +struct hwrm_tunnel_dst_port_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19547,30 +25214,39 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 + uint8_t unused_0; /* - * Function ID of the function that is being queried. - * Only valid for a VF FID queried by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* - * Maximum number of VLAN entries the firmware is allowed to DMA - * to vlan_tag_mask_tbl. - */ - uint32_t max_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table to which firmware will DMA to. Each table - * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), - * 16-bit VLAN ID, and a 16-bit mask, all in network order to - * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, - * the mask value should be 0xfff for the 12-bit VLAN ID. + * This field represents the value of L4 destination port used + * for the given tunnel type. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. + * + * This field is in network byte order. + * + * A value of 0 shall fail the command. */ - uint64_t vlan_tag_mask_tbl_addr; + uint16_t tunnel_dst_port_val; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_output { +/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ +struct hwrm_tunnel_dst_port_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19579,9 +25255,12 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - uint8_t unused_0[3]; + /* + * Identifier of a tunnel L4 destination port value. Only applies to tunnel + * types that has l4 destination port parameters. + */ + uint16_t tunnel_dst_port_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -19592,13 +25271,13 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint8_t valid; } __attribute__((packed)); -/******************************** - * hwrm_cfa_ntuple_filter_alloc * - ********************************/ +/***************************** + * hwrm_tunnel_dst_port_free * + *****************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_ntuple_filter_alloc_input { +/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ +struct hwrm_tunnel_dst_port_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19626,316 +25305,160 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x2) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ - UINT32_C(0x4) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x10) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x20) - /* - * This bit must be '1' for the src_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ - UINT32_C(0x40) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x80) - /* - * This bit must be '1' for the dst_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ - UINT32_C(0x100) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x200) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x400) - /* - * This bit must be '1' for the src_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ - UINT32_C(0x800) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the dst_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the pri_hint field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the ntuple_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x40000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ - UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ - UINT32_C(0x6) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ - UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ - UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ - UINT32_C(0x11) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint16_t mirror_vnic_id; - /* - * This value indicates the tunnel type for this filter. - * If this field is not specified, then the filter shall - * apply to both non-tunneled and tunneled packets. - * If this field conflicts with the tunnel_type specified - * in the l2_filter_id, then the HWRM shall return an - * error for this command. - */ + /* Tunnel Type. */ uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) - /* Any tunneled traffic */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* - * This hint is provided to help in placing - * the filter in the filter table. - */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ - UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ - UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ - UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ - UINT32_C(0x4) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \ + HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 + uint8_t unused_0; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Identifier of a tunnel L4 destination port value. Only applies to tunnel + * types that has l4 destination port parameters. */ - uint32_t src_ipaddr[4]; + uint16_t tunnel_dst_port_id; + uint8_t unused_1[4]; +} __attribute__((packed)); + +/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ +struct hwrm_tunnel_dst_port_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_1[7]; /* - * The value of source IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t src_ipaddr_mask[4]; + uint8_t valid; +} __attribute__((packed)); + +/* ctx_hw_stats (size:1280b/160B) */ +struct ctx_hw_stats { + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on received path */ + uint64_t rx_discard_pkts; + /* Number of dropped packets on received path */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of dropped packets on transmit path */ + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA packets */ + uint64_t tpa_pkts; + /* Number of TPA bytes */ + uint64_t tpa_bytes; + /* Number of TPA events */ + uint64_t tpa_events; + /* Number of TPA aborts */ + uint64_t tpa_aborts; +} __attribute__((packed)); + +/*********************** + * hwrm_stat_ctx_alloc * + ***********************/ + + +/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ +struct hwrm_stat_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint32_t dst_ipaddr[4]; + uint16_t cmpl_ring; /* - * The value of destination IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint32_t dst_ipaddr_mask[4]; + uint16_t seq_id; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint16_t src_port; + uint16_t target_id; /* - * The value of source port mask to be used in filtering. - * Applies to UDP and TCP traffic. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t src_port_mask; + uint64_t resp_addr; + /* This is the address for statistic block. */ + uint64_t stats_dma_addr; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * The statistic block update period in ms. + * e.g. 250ms, 500ms, 750ms, 1000ms. + * If update_period_ms is 0, then the stats update + * shall be never done and the DMA address shall not be used. + * In this case, the stat block can only be read by + * hwrm_stat_ctx_query command. */ - uint16_t dst_port; + uint32_t update_period_ms; /* - * The value of destination port mask to be used in - * filtering. - * Applies to UDP and TCP traffic. + * This field is used to specify statistics context specific + * configuration flags. */ - uint16_t dst_port_mask; + uint8_t stat_ctx_flags; /* - * This is the ID of the filter that goes along with - * the pri_hint. + * When this bit is set to '1', the statistics context shall be + * allocated for RoCE traffic only. In this case, traffic other + * than offloaded RoCE traffic shall not be included in this + * statistic context. + * When this bit is set to '0', the statistics context shall be + * used for the network traffic other than offloaded RoCE traffic. */ - uint64_t ntuple_filter_id_hint; + #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1) + uint8_t unused_0[3]; } __attribute__((packed)); -/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_alloc_output { +/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ +struct hwrm_stat_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -19944,16 +25467,8 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * This is the ID of the flow associated with this - * filter. - * This value shall be used to match and associate the - * flow identifier returned in completion records. - * A value of 0xFFFFFFFF shall indicate no flow id. - */ - uint32_t flow_id; + /* This is the statistics context ID value. */ + uint32_t stat_ctx_id; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -19965,31 +25480,13 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint8_t valid; } __attribute__((packed)); -/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_ntuple_filter_alloc_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* Unable to complete operation due to conflict with Rx Mask VLAN */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR - uint8_t unused_0[7]; -} __attribute__((packed)); - -/******************************* - * hwrm_cfa_ntuple_filter_free * - *******************************/ +/********************** + * hwrm_stat_ctx_free * + **********************/ -/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_free_input { +/* hwrm_stat_ctx_free_input (size:192b/24B) */ +struct hwrm_stat_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20017,12 +25514,13 @@ struct hwrm_cfa_ntuple_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t unused_0[4]; } __attribute__((packed)); -/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_free_output { +/* hwrm_stat_ctx_free_output (size:128b/16B) */ +struct hwrm_stat_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -20031,7 +25529,9 @@ struct hwrm_cfa_ntuple_filter_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This is the statistics context ID value. */ + uint32_t stat_ctx_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -20042,13 +25542,13 @@ struct hwrm_cfa_ntuple_filter_free_output { uint8_t valid; } __attribute__((packed)); -/****************************** - * hwrm_cfa_ntuple_filter_cfg * - ******************************/ +/*********************** + * hwrm_stat_ctx_query * + ***********************/ -/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ -struct hwrm_cfa_ntuple_filter_cfg_input { +/* hwrm_stat_ctx_query_input (size:192b/24B) */ +struct hwrm_stat_ctx_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20076,59 +25576,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the new_dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ - UINT32_C(0x4) + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; uint8_t unused_0[4]; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and new network port id of the destination port for - * the TX path. - */ - uint32_t new_dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint32_t new_mirror_vnic_id; - /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. - */ - uint16_t new_meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ - HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; } __attribute__((packed)); -/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_cfg_output { +/* hwrm_stat_ctx_query_output (size:1408b/176B) */ +struct hwrm_stat_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -20137,6 +25591,46 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of transmitted packets with error */ + uint64_t tx_err_pkts; + /* Number of dropped packets on transmit path */ + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of received packets with error */ + uint64_t rx_err_pkts; + /* Number of dropped packets on received path */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes */ + uint64_t rx_agg_bytes; + /* Number of aggregation events */ + uint64_t rx_agg_events; + /* Number of aborted aggregations */ + uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -20148,13 +25642,13 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_cfa_em_flow_alloc * - **************************/ +/*************************** + * hwrm_stat_ctx_clr_stats * + ***************************/ -/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ -struct hwrm_cfa_em_flow_alloc_input { +/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ +struct hwrm_stat_ctx_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20182,600 +25676,517 @@ struct hwrm_cfa_em_flow_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX - /* - * Setting of this flag indicates enabling of a byte counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) - /* - * Setting of this flag indicates enabling of a packet counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) - /* Setting of this flag indicates de-capsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) - /* Setting of this flag indicates encapsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x10) - /* - * This bit must be '1' for the ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x100) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x200) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x400) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x800) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x4000) + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ +struct hwrm_stat_ctx_clr_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x8000) + uint8_t valid; +} __attribute__((packed)); + +/******************** + * hwrm_pcie_qstats * + ********************/ + + +/* hwrm_pcie_qstats_input (size:256b/32B) */ +struct hwrm_pcie_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the encap_record_id field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ - UINT32_C(0x10000) + uint16_t cmpl_ring; /* - * This bit must be '1' for the meter_instance_id field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ - UINT32_C(0x20000) + uint16_t seq_id; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t l2_filter_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Any tunneled traffic */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[3]; + uint16_t target_id; /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t tunnel_id; + uint64_t resp_addr; /* - * This value indicates the source MAC address in - * the Ethernet header. + * The size of PCIe statistics block in bytes. + * Firmware will DMA the PCIe statistics to + * the host with this field size in the response. */ - uint8_t src_macaddr[6]; - /* The meter instance to attach to the flow. */ - uint16_t meter_instance_id; + uint16_t pcie_stat_size; + uint8_t unused_0[6]; /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * This is the host address where + * PCIe statistics will be stored */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID + uint64_t pcie_stat_host_addr; +} __attribute__((packed)); + +/* hwrm_pcie_qstats_output (size:128b/16B) */ +struct hwrm_pcie_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The size of PCIe statistics block in bytes. */ + uint16_t pcie_stat_size; + uint8_t unused_0[5]; /* - * This value indicates the destination MAC address in - * the Ethernet header. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t dst_macaddr[6]; + uint8_t valid; +} __attribute__((packed)); + +/* Port Tx Statistics Formats */ +/* tx_port_stats (size:3264b/408B) */ +struct tx_port_stats { + /* Total Number of 64 Bytes frames transmitted */ + uint64_t tx_64b_frames; + /* Total Number of 65-127 Bytes frames transmitted */ + uint64_t tx_65b_127b_frames; + /* Total Number of 128-255 Bytes frames transmitted */ + uint64_t tx_128b_255b_frames; + /* Total Number of 256-511 Bytes frames transmitted */ + uint64_t tx_256b_511b_frames; + /* Total Number of 512-1023 Bytes frames transmitted */ + uint64_t tx_512b_1023b_frames; + /* Total Number of 1024-1518 Bytes frames transmitted */ + uint64_t tx_1024b_1518_frames; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. + * Total Number of each good VLAN (exludes FCS errors) + * frame transmitted which is 1519 to 1522 bytes in length + * inclusive (excluding framing bits but including FCS bytes). */ - uint16_t ovlan_vid; + uint64_t tx_good_vlan_frames; + /* Total Number of 1519-2047 Bytes frames transmitted */ + uint64_t tx_1519b_2047_frames; + /* Total Number of 2048-4095 Bytes frames transmitted */ + uint64_t tx_2048b_4095b_frames; + /* Total Number of 4096-9216 Bytes frames transmitted */ + uint64_t tx_4096b_9216b_frames; + /* Total Number of 9217-16383 Bytes frames transmitted */ + uint64_t tx_9217b_16383b_frames; + /* Total Number of good frames transmitted */ + uint64_t tx_good_frames; + /* Total Number of frames transmitted */ + uint64_t tx_total_frames; + /* Total number of unicast frames transmitted */ + uint64_t tx_ucast_frames; + /* Total number of multicast frames transmitted */ + uint64_t tx_mcast_frames; + /* Total number of broadcast frames transmitted */ + uint64_t tx_bcast_frames; + /* Total number of PAUSE control frames transmitted */ + uint64_t tx_pause_frames; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. + * Total number of PFC/per-priority PAUSE + * control frames transmitted */ - uint16_t ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; + uint64_t tx_pfc_frames; + /* Total number of jabber frames transmitted */ + uint64_t tx_jabber_frames; + /* Total number of frames transmitted with FCS error */ + uint64_t tx_fcs_err_frames; + /* Total number of control frames transmitted */ + uint64_t tx_control_frames; + /* Total number of over-sized frames transmitted */ + uint64_t tx_oversz_frames; + /* Total number of frames with single deferral */ + uint64_t tx_single_dfrl_frames; + /* Total number of frames with multiple deferrals */ + uint64_t tx_multi_dfrl_frames; + /* Total number of frames with single collision */ + uint64_t tx_single_coll_frames; + /* Total number of frames with multiple collisions */ + uint64_t tx_multi_coll_frames; + /* Total number of frames with late collisions */ + uint64_t tx_late_coll_frames; + /* Total number of frames with excessive collisions */ + uint64_t tx_excessive_coll_frames; + /* Total number of fragmented frames transmitted */ + uint64_t tx_frag_frames; + /* Total number of transmit errors */ + uint64_t tx_err; + /* Total number of single VLAN tagged frames transmitted */ + uint64_t tx_tagged_frames; + /* Total number of double VLAN tagged frames transmitted */ + uint64_t tx_dbl_tagged_frames; + /* Total number of runt frames transmitted */ + uint64_t tx_runt_frames; + /* Total number of TX FIFO under runs */ + uint64_t tx_fifo_underruns; /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * Total number of PFC frames with PFC enabled bit for + * Pri 0 transmitted */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + uint64_t tx_pfc_ena_frames_pri0; /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP - uint8_t unused_1[2]; + * Total number of PFC frames with PFC enabled bit for + * Pri 1 transmitted + */ + uint64_t tx_pfc_ena_frames_pri1; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Total number of PFC frames with PFC enabled bit for + * Pri 2 transmitted */ - uint32_t src_ipaddr[4]; + uint64_t tx_pfc_ena_frames_pri2; /* - * big_endian = True - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Total number of PFC frames with PFC enabled bit for + * Pri 3 transmitted */ - uint32_t dst_ipaddr[4]; + uint64_t tx_pfc_ena_frames_pri3; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * Total number of PFC frames with PFC enabled bit for + * Pri 4 transmitted */ - uint16_t src_port; + uint64_t tx_pfc_ena_frames_pri4; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * Total number of PFC frames with PFC enabled bit for + * Pri 5 transmitted */ - uint16_t dst_port; + uint64_t tx_pfc_ena_frames_pri5; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Total number of PFC frames with PFC enabled bit for + * Pri 6 transmitted */ - uint16_t dst_id; + uint64_t tx_pfc_ena_frames_pri6; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Total number of PFC frames with PFC enabled bit for + * Pri 7 transmitted */ - uint16_t mirror_vnic_id; - /* Logical ID of the encapsulation record. */ - uint32_t encap_record_id; - uint8_t unused_2[4]; + uint64_t tx_pfc_ena_frames_pri7; + /* Total number of EEE LPI Events on TX */ + uint64_t tx_eee_lpi_events; + /* EEE LPI Duration Counter on TX */ + uint64_t tx_eee_lpi_duration; + /* + * Total number of Link Level Flow Control (LLFC) messages + * transmitted + */ + uint64_t tx_llfc_logical_msgs; + /* Total number of HCFC messages transmitted */ + uint64_t tx_hcfc_msgs; + /* Total number of TX collisions */ + uint64_t tx_total_collisions; + /* Total number of transmitted bytes */ + uint64_t tx_bytes; + /* Total number of end-to-end HOL frames */ + uint64_t tx_xthol_frames; + /* Total Tx Drops per Port reported by STATS block */ + uint64_t tx_stat_discard; + /* Total Tx Error Drops per Port reported by STATS block */ + uint64_t tx_stat_error; } __attribute__((packed)); -/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ -struct hwrm_cfa_em_flow_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; +/* Port Rx Statistics Formats */ +/* rx_port_stats (size:4224b/528B) */ +struct rx_port_stats { + /* Total Number of 64 Bytes frames received */ + uint64_t rx_64b_frames; + /* Total Number of 65-127 Bytes frames received */ + uint64_t rx_65b_127b_frames; + /* Total Number of 128-255 Bytes frames received */ + uint64_t rx_128b_255b_frames; + /* Total Number of 256-511 Bytes frames received */ + uint64_t rx_256b_511b_frames; + /* Total Number of 512-1023 Bytes frames received */ + uint64_t rx_512b_1023b_frames; + /* Total Number of 1024-1518 Bytes frames received */ + uint64_t rx_1024b_1518_frames; /* - * This is the ID of the flow associated with this - * filter. - * This value shall be used to match and associate the - * flow identifier returned in completion records. - * A value of 0xFFFFFFFF shall indicate no flow id. + * Total Number of each good VLAN (exludes FCS errors) + * frame received which is 1519 to 1522 bytes in length + * inclusive (excluding framing bits but including FCS bytes). */ - uint32_t flow_id; - uint8_t unused_0[3]; + uint64_t rx_good_vlan_frames; + /* Total Number of 1519-2047 Bytes frames received */ + uint64_t rx_1519b_2047b_frames; + /* Total Number of 2048-4095 Bytes frames received */ + uint64_t rx_2048b_4095b_frames; + /* Total Number of 4096-9216 Bytes frames received */ + uint64_t rx_4096b_9216b_frames; + /* Total Number of 9217-16383 Bytes frames received */ + uint64_t rx_9217b_16383b_frames; + /* Total number of frames received */ + uint64_t rx_total_frames; + /* Total number of unicast frames received */ + uint64_t rx_ucast_frames; + /* Total number of multicast frames received */ + uint64_t rx_mcast_frames; + /* Total number of broadcast frames received */ + uint64_t rx_bcast_frames; + /* Total number of received frames with FCS error */ + uint64_t rx_fcs_err_frames; + /* Total number of control frames received */ + uint64_t rx_ctrl_frames; + /* Total number of PAUSE frames received */ + uint64_t rx_pause_frames; + /* Total number of PFC frames received */ + uint64_t rx_pfc_frames; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Total number of frames received with an unsupported + * opcode */ - uint8_t valid; -} __attribute__((packed)); - -/************************* - * hwrm_cfa_em_flow_free * - *************************/ - - -/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ -struct hwrm_cfa_em_flow_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint64_t rx_unsupported_opcode_frames; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Total number of frames received with an unsupported + * DA for pause and PFC */ - uint16_t cmpl_ring; + uint64_t rx_unsupported_da_pausepfc_frames; + /* Total number of frames received with an unsupported SA */ + uint64_t rx_wrong_sa_frames; + /* Total number of received packets with alignment error */ + uint64_t rx_align_err_frames; + /* Total number of received frames with out-of-range length */ + uint64_t rx_oor_len_frames; + /* Total number of received frames with error termination */ + uint64_t rx_code_err_frames; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Total number of received frames with a false carrier is + * detected during idle, as defined by RX_ER samples active + * and RXD is 0xE. The event is reported along with the + * statistics generated on the next received frame. Only + * one false carrier condition can be detected and logged + * between frames. + * + * Carrier event, valid for 10M/100M speed modes only. */ - uint16_t seq_id; + uint64_t rx_false_carrier_frames; + /* Total number of over-sized frames received */ + uint64_t rx_ovrsz_frames; + /* Total number of jabber packets received */ + uint64_t rx_jbr_frames; + /* Total number of received frames with MTU error */ + uint64_t rx_mtu_err_frames; + /* Total number of received frames with CRC match */ + uint64_t rx_match_crc_frames; + /* Total number of frames received promiscuously */ + uint64_t rx_promiscuous_frames; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Total number of received frames with one or two VLAN + * tags */ - uint16_t target_id; + uint64_t rx_tagged_frames; + /* Total number of received frames with two VLAN tags */ + uint64_t rx_double_tagged_frames; + /* Total number of truncated frames received */ + uint64_t rx_trunc_frames; + /* Total number of good frames (without errors) received */ + uint64_t rx_good_frames; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 0 */ - uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; -} __attribute__((packed)); - -/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint64_t rx_pfc_xon2xoff_frames_pri0; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 1 */ - uint8_t valid; -} __attribute__((packed)); - -/************************ - * hwrm_cfa_em_flow_cfg * - ************************/ - - -/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */ -struct hwrm_cfa_em_flow_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint64_t rx_pfc_xon2xoff_frames_pri1; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 2 */ - uint16_t cmpl_ring; + uint64_t rx_pfc_xon2xoff_frames_pri2; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 3 + */ + uint64_t rx_pfc_xon2xoff_frames_pri3; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 4 */ - uint16_t seq_id; + uint64_t rx_pfc_xon2xoff_frames_pri4; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 5 */ - uint16_t target_id; + uint64_t rx_pfc_xon2xoff_frames_pri5; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 6 */ - uint64_t resp_addr; - uint32_t enables; + uint64_t rx_pfc_xon2xoff_frames_pri6; /* - * This bit must be '1' for the new_dst_id field to be - * configured. + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 7 */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \ - UINT32_C(0x1) + uint64_t rx_pfc_xon2xoff_frames_pri7; /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * Total number of received PFC frames with PFC enabled + * bit for Pri 0 */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) + uint64_t rx_pfc_ena_frames_pri0; /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. + * Total number of received PFC frames with PFC enabled + * bit for Pri 1 */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ - UINT32_C(0x4) - uint8_t unused_0[4]; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; + uint64_t rx_pfc_ena_frames_pri1; /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Total number of received PFC frames with PFC enabled + * bit for Pri 2 */ - uint32_t new_dst_id; + uint64_t rx_pfc_ena_frames_pri2; /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Total number of received PFC frames with PFC enabled + * bit for Pri 3 */ - uint32_t new_mirror_vnic_id; + uint64_t rx_pfc_ena_frames_pri3; /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. + * Total number of received PFC frames with PFC enabled + * bit for Pri 4 */ - uint16_t new_meter_instance_id; + uint64_t rx_pfc_ena_frames_pri4; /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * Total number of received PFC frames with PFC enabled + * bit for Pri 5 */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ - HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; -} __attribute__((packed)); - -/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint64_t rx_pfc_ena_frames_pri5; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Total number of received PFC frames with PFC enabled + * bit for Pri 6 */ - uint8_t valid; -} __attribute__((packed)); - -/****************************** - * hwrm_tunnel_dst_port_query * - ******************************/ - - -/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_query_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint64_t rx_pfc_ena_frames_pri6; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Total number of received PFC frames with PFC enabled + * bit for Pri 7 */ - uint16_t cmpl_ring; + uint64_t rx_pfc_ena_frames_pri7; + /* Total Number of frames received with SCH CRC error */ + uint64_t rx_sch_crc_err_frames; + /* Total Number of under-sized frames received */ + uint64_t rx_undrsz_frames; + /* Total Number of fragmented frames received */ + uint64_t rx_frag_frames; + /* Total number of RX EEE LPI Events */ + uint64_t rx_eee_lpi_events; + /* EEE LPI Duration Counter on RX */ + uint64_t rx_eee_lpi_duration; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Total number of physical type Link Level Flow Control + * (LLFC) messages received */ - uint16_t seq_id; + uint64_t rx_llfc_physical_msgs; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * Total number of logical type Link Level Flow Control + * (LLFC) messages received */ - uint16_t target_id; + uint64_t rx_llfc_logical_msgs; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Total number of logical type Link Level Flow Control + * (LLFC) messages received with CRC error */ - uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 - uint8_t unused_0[7]; + uint64_t rx_llfc_msgs_with_crc_err; + /* Total number of HCFC messages received */ + uint64_t rx_hcfc_msgs; + /* Total number of HCFC messages received with CRC error */ + uint64_t rx_hcfc_msgs_with_crc_err; + /* Total number of received bytes */ + uint64_t rx_bytes; + /* Total number of bytes received in runt frames */ + uint64_t rx_runt_bytes; + /* Total number of runt frames received */ + uint64_t rx_runt_frames; + /* Total Rx Discards per Port reported by STATS block */ + uint64_t rx_stat_discard; + uint64_t rx_stat_err; } __attribute__((packed)); -/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; +/* Port Rx Statistics extended Formats */ +/* rx_port_stats_ext (size:320b/40B) */ +struct rx_port_stats_ext { + /* Number of times link state changed to down */ + uint64_t link_down_events; + /* Number of times the idle rings with pause bit are found */ + uint64_t continuous_pause_events; + /* Number of times the active rings pause bit resumed back */ + uint64_t resume_pause_events; + /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */ + uint64_t continuous_roce_pause_events; + /* Number of times, the ROCE cos queue PFC is enabled back */ + uint64_t resume_roce_pause_events; +} __attribute__((packed)); + +/* PCIe Statistics Formats */ +/* pcie_ctx_hw_stats (size:768b/96B) */ +struct pcie_ctx_hw_stats { + /* Number of physical layer receiver errors */ + uint64_t pcie_pl_signal_integrity; + /* Number of DLLP CRC errors detected by Data Link Layer */ + uint64_t pcie_dl_signal_integrity; /* - * This field represents the identifier of L4 destination port - * used for the given tunnel type. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. + * Number of TLP LCRC and sequence number errors detected + * by Data Link Layer */ - uint16_t tunnel_dst_port_id; + uint64_t pcie_tl_signal_integrity; + /* Number of times LTSSM entered Recovery state */ + uint64_t pcie_link_integrity; + /* Number of TLP bytes that have been trasmitted */ + uint64_t pcie_tx_traffic_rate; + /* Number of TLP bytes that have been received */ + uint64_t pcie_rx_traffic_rate; + /* Number of DLLP bytes that have been trasmitted */ + uint64_t pcie_tx_dllp_statistics; + /* Number of DLLP bytes that have been received */ + uint64_t pcie_rx_dllp_statistics; /* - * This field represents the value of L4 destination port - * identified by tunnel_dst_port_id. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. - * This field is in network byte order. - * - * A value of 0 means that the destination port is not - * configured. + * Number of times spent in each phase of gen3 + * equalization */ - uint16_t tunnel_dst_port_val; - uint8_t unused_0[3]; + uint64_t pcie_equalization_time; + /* Records the last 16 transitions of the LTSSM */ + uint32_t pcie_ltssm_histogram[4]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Record the last 8 reasons on why LTSSM transitioned + * to Recovery */ - uint8_t valid; + uint64_t pcie_recovery_histogram; } __attribute__((packed)); -/****************************** - * hwrm_tunnel_dst_port_alloc * - ******************************/ +/********************** + * hwrm_exec_fwd_resp * + **********************/ -/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_alloc_input { +/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ +struct hwrm_exec_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20803,39 +26214,26 @@ struct hwrm_tunnel_dst_port_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 - uint8_t unused_0; /* - * This field represents the value of L4 destination port used - * for the given tunnel type. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. - * - * This field is in network byte order. - * - * A value of 0 shall fail the command. + * This is an encapsulated request. This request should + * be executed by the HWRM and the response should be + * provided in the response buffer inside the encapsulated + * request. */ - uint16_t tunnel_dst_port_val; - uint8_t unused_1[4]; + uint32_t encap_request[26]; + /* + * This value indicates the target id of the response to + * the encapsulated request. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t encap_resp_target_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_alloc_output { +/* hwrm_exec_fwd_resp_output (size:128b/16B) */ +struct hwrm_exec_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -20844,12 +26242,7 @@ struct hwrm_tunnel_dst_port_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. - */ - uint16_t tunnel_dst_port_id; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -20860,13 +26253,13 @@ struct hwrm_tunnel_dst_port_alloc_output { uint8_t valid; } __attribute__((packed)); -/***************************** - * hwrm_tunnel_dst_port_free * - *****************************/ +/************************ + * hwrm_reject_fwd_resp * + ************************/ -/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ -struct hwrm_tunnel_dst_port_free_input { +/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ +struct hwrm_reject_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -20894,33 +26287,26 @@ struct hwrm_tunnel_dst_port_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 - uint8_t unused_0; /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. + * This is an encapsulated request. This request should + * be rejected by the HWRM and the error response should be + * provided in the response buffer inside the encapsulated + * request. */ - uint16_t tunnel_dst_port_id; - uint8_t unused_1[4]; + uint32_t encap_request[26]; + /* + * This value indicates the target id of the response to + * the encapsulated request. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t encap_resp_target_id; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ -struct hwrm_tunnel_dst_port_free_output { +/* hwrm_reject_fwd_resp_output (size:128b/16B) */ +struct hwrm_reject_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -20929,7 +26315,7 @@ struct hwrm_tunnel_dst_port_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -20940,57 +26326,13 @@ struct hwrm_tunnel_dst_port_free_output { uint8_t valid; } __attribute__((packed)); -/* ctx_hw_stats (size:1280b/160B) */ -struct ctx_hw_stats { - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ - uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of discarded packets on transmit path */ - uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of TPA packets */ - uint64_t tpa_pkts; - /* Number of TPA bytes */ - uint64_t tpa_bytes; - /* Number of TPA events */ - uint64_t tpa_events; - /* Number of TPA aborts */ - uint64_t tpa_aborts; -} __attribute__((packed)); - -/*********************** - * hwrm_stat_ctx_alloc * - ***********************/ +/***************** + * hwrm_fwd_resp * + *****************/ -/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ -struct hwrm_stat_ctx_alloc_input { +/* hwrm_fwd_resp_input (size:1024b/128B) */ +struct hwrm_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21018,98 +26360,41 @@ struct hwrm_stat_ctx_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the address for statistic block. */ - uint64_t stats_dma_addr; - /* - * The statistic block update period in ms. - * e.g. 250ms, 500ms, 750ms, 1000ms. - * If update_period_ms is 0, then the stats update - * shall be never done and the DMA address shall not be used. - * In this case, the stat block can only be read by - * hwrm_stat_ctx_query command. - */ - uint32_t update_period_ms; - /* - * This field is used to specify statistics context specific - * configuration flags. - */ - uint8_t stat_ctx_flags; - /* - * When this bit is set to '1', the statistics context shall be - * allocated for RoCE traffic only. In this case, traffic other - * than offloaded RoCE traffic shall not be included in this - * statistic context. - * When this bit is set to '0', the statistics context shall be - * used for the network traffic other than offloaded RoCE traffic. - */ - #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1) - uint8_t unused_0[3]; -} __attribute__((packed)); - -/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ -struct hwrm_stat_ctx_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This is the statistics context ID value. */ - uint32_t stat_ctx_id; - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_stat_ctx_free * - **********************/ - - -/* hwrm_stat_ctx_free_input (size:192b/24B) */ -struct hwrm_stat_ctx_free_input { - /* The HWRM command request type. */ - uint16_t req_type; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value indicates the target id of the encapsulated + * response. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM */ - uint16_t seq_id; + uint16_t encap_resp_target_id; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM + * This value indicates the completion ring the encapsulated + * response will be optionally completed on. If the value is + * -1, then no CR completion shall be generated for the + * encapsulated response. Any other value must be a + * valid CR ring_id value. If a valid encap_resp_cmpl_ring + * is provided, then a CR completion shall be generated for + * the encapsulated response. */ - uint16_t target_id; + uint16_t encap_resp_cmpl_ring; + /* This field indicates the length of encapsulated response. */ + uint16_t encap_resp_len; + uint8_t unused_0; + uint8_t unused_1; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This is the host address where the encapsulated response + * will be written. + * This area must be 16B aligned and must be cleared to zero + * before the original request is made. */ - uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; + uint64_t encap_resp_addr; + /* This is an encapsulated response. */ + uint32_t encap_resp[24]; } __attribute__((packed)); -/* hwrm_stat_ctx_free_output (size:128b/16B) */ -struct hwrm_stat_ctx_free_output { +/* hwrm_fwd_resp_output (size:128b/16B) */ +struct hwrm_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21118,9 +26403,7 @@ struct hwrm_stat_ctx_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This is the statistics context ID value. */ - uint32_t stat_ctx_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21131,13 +26414,13 @@ struct hwrm_stat_ctx_free_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_stat_ctx_query * - ***********************/ +/***************************** + * hwrm_fwd_async_event_cmpl * + *****************************/ -/* hwrm_stat_ctx_query_input (size:192b/24B) */ -struct hwrm_stat_ctx_query_input { +/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ +struct hwrm_fwd_async_event_cmpl_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21165,13 +26448,22 @@ struct hwrm_stat_ctx_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; + /* + * This value indicates the target id of the encapsulated + * asynchronous event. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - Broadcast to all children VFs (only applicable when + * a PF is the requester) + */ + uint16_t encap_async_event_target_id; + uint8_t unused_0[6]; + /* This is an encapsulated asynchronous event completion. */ + uint32_t encap_async_event_cmpl[4]; } __attribute__((packed)); -/* hwrm_stat_ctx_query_output (size:1408b/176B) */ -struct hwrm_stat_ctx_query_output { +/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ +struct hwrm_fwd_async_event_cmpl_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21180,46 +26472,6 @@ struct hwrm_stat_ctx_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of transmitted packets with error */ - uint64_t tx_err_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of received packets with error */ - uint64_t rx_err_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes */ - uint64_t rx_agg_bytes; - /* Number of aggregation events */ - uint64_t rx_agg_events; - /* Number of aborted aggregations */ - uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -21231,13 +26483,13 @@ struct hwrm_stat_ctx_query_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_stat_ctx_clr_stats * - ***************************/ +/************************** + * hwrm_nvm_raw_write_blk * + **************************/ -/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ -struct hwrm_stat_ctx_clr_stats_input { +/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */ +struct hwrm_nvm_raw_write_blk_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21265,13 +26517,22 @@ struct hwrm_stat_ctx_clr_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; + /* + * 64-bit Host Source Address. + * This is the loation of the source data to be written. + */ + uint64_t host_src_addr; + /* + * 32-bit Destination Address. + * This is the NVRAM byte-offset where the source data will be written to. + */ + uint32_t dest_addr; + /* Length of data to be written, in bytes. */ + uint32_t len; } __attribute__((packed)); -/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ -struct hwrm_stat_ctx_clr_stats_output { +/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ +struct hwrm_nvm_raw_write_blk_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21291,13 +26552,13 @@ struct hwrm_stat_ctx_clr_stats_output { uint8_t valid; } __attribute__((packed)); -/******************** - * hwrm_pcie_qstats * - ********************/ +/***************** + * hwrm_nvm_read * + *****************/ -/* hwrm_pcie_qstats_input (size:256b/32B) */ -struct hwrm_pcie_qstats_input { +/* hwrm_nvm_read_input (size:320b/40B) */ +struct hwrm_nvm_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21326,456 +26587,358 @@ struct hwrm_pcie_qstats_input { */ uint64_t resp_addr; /* - * The size of PCIe statistics block in bytes. - * Firmware will DMA the PCIe statistics to - * the host with this field size in the response. - */ - uint16_t pcie_stat_size; - uint8_t unused_0[6]; - /* - * This is the host address where - * PCIe statistics will be stored + * 64-bit Host Destination Address. + * This is the host address where the data will be written to. */ - uint64_t pcie_stat_host_addr; + uint64_t host_dest_addr; + /* The 0-based index of the directory entry. */ + uint16_t dir_idx; + uint8_t unused_0[2]; + /* The NVRAM byte-offset to read from. */ + uint32_t offset; + /* The length of the data to be read, in bytes. */ + uint32_t len; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_pcie_qstats_output (size:128b/16B) */ -struct hwrm_pcie_qstats_output { +/* hwrm_nvm_read_output (size:128b/16B) */ +struct hwrm_nvm_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The size of PCIe statistics block in bytes. */ - uint16_t pcie_stat_size; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/* Port Tx Statistics Formats */ -/* tx_port_stats (size:3264b/408B) */ -struct tx_port_stats { - /* Total Number of 64 Bytes frames transmitted */ - uint64_t tx_64b_frames; - /* Total Number of 65-127 Bytes frames transmitted */ - uint64_t tx_65b_127b_frames; - /* Total Number of 128-255 Bytes frames transmitted */ - uint64_t tx_128b_255b_frames; - /* Total Number of 256-511 Bytes frames transmitted */ - uint64_t tx_256b_511b_frames; - /* Total Number of 512-1023 Bytes frames transmitted */ - uint64_t tx_512b_1023b_frames; - /* Total Number of 1024-1518 Bytes frames transmitted */ - uint64_t tx_1024b_1518_frames; - /* - * Total Number of each good VLAN (exludes FCS errors) - * frame transmitted which is 1519 to 1522 bytes in length - * inclusive (excluding framing bits but including FCS bytes). - */ - uint64_t tx_good_vlan_frames; - /* Total Number of 1519-2047 Bytes frames transmitted */ - uint64_t tx_1519b_2047_frames; - /* Total Number of 2048-4095 Bytes frames transmitted */ - uint64_t tx_2048b_4095b_frames; - /* Total Number of 4096-9216 Bytes frames transmitted */ - uint64_t tx_4096b_9216b_frames; - /* Total Number of 9217-16383 Bytes frames transmitted */ - uint64_t tx_9217b_16383b_frames; - /* Total Number of good frames transmitted */ - uint64_t tx_good_frames; - /* Total Number of frames transmitted */ - uint64_t tx_total_frames; - /* Total number of unicast frames transmitted */ - uint64_t tx_ucast_frames; - /* Total number of multicast frames transmitted */ - uint64_t tx_mcast_frames; - /* Total number of broadcast frames transmitted */ - uint64_t tx_bcast_frames; - /* Total number of PAUSE control frames transmitted */ - uint64_t tx_pause_frames; - /* - * Total number of PFC/per-priority PAUSE - * control frames transmitted - */ - uint64_t tx_pfc_frames; - /* Total number of jabber frames transmitted */ - uint64_t tx_jabber_frames; - /* Total number of frames transmitted with FCS error */ - uint64_t tx_fcs_err_frames; - /* Total number of control frames transmitted */ - uint64_t tx_control_frames; - /* Total number of over-sized frames transmitted */ - uint64_t tx_oversz_frames; - /* Total number of frames with single deferral */ - uint64_t tx_single_dfrl_frames; - /* Total number of frames with multiple deferrals */ - uint64_t tx_multi_dfrl_frames; - /* Total number of frames with single collision */ - uint64_t tx_single_coll_frames; - /* Total number of frames with multiple collisions */ - uint64_t tx_multi_coll_frames; - /* Total number of frames with late collisions */ - uint64_t tx_late_coll_frames; - /* Total number of frames with excessive collisions */ - uint64_t tx_excessive_coll_frames; - /* Total number of fragmented frames transmitted */ - uint64_t tx_frag_frames; - /* Total number of transmit errors */ - uint64_t tx_err; - /* Total number of single VLAN tagged frames transmitted */ - uint64_t tx_tagged_frames; - /* Total number of double VLAN tagged frames transmitted */ - uint64_t tx_dbl_tagged_frames; - /* Total number of runt frames transmitted */ - uint64_t tx_runt_frames; - /* Total number of TX FIFO under runs */ - uint64_t tx_fifo_underruns; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 0 transmitted - */ - uint64_t tx_pfc_ena_frames_pri0; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 1 transmitted - */ - uint64_t tx_pfc_ena_frames_pri1; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 2 transmitted - */ - uint64_t tx_pfc_ena_frames_pri2; + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Total number of PFC frames with PFC enabled bit for - * Pri 3 transmitted + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t tx_pfc_ena_frames_pri3; + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_nvm_raw_dump * + *********************/ + + +/* hwrm_nvm_raw_dump_input (size:256b/32B) */ +struct hwrm_nvm_raw_dump_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Total number of PFC frames with PFC enabled bit for - * Pri 4 transmitted + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint64_t tx_pfc_ena_frames_pri4; + uint16_t cmpl_ring; /* - * Total number of PFC frames with PFC enabled bit for - * Pri 5 transmitted + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint64_t tx_pfc_ena_frames_pri5; + uint16_t seq_id; /* - * Total number of PFC frames with PFC enabled bit for - * Pri 6 transmitted + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t tx_pfc_ena_frames_pri6; + uint16_t target_id; /* - * Total number of PFC frames with PFC enabled bit for - * Pri 7 transmitted + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint64_t tx_pfc_ena_frames_pri7; - /* Total number of EEE LPI Events on TX */ - uint64_t tx_eee_lpi_events; - /* EEE LPI Duration Counter on TX */ - uint64_t tx_eee_lpi_duration; + uint64_t resp_addr; /* - * Total number of Link Level Flow Control (LLFC) messages - * transmitted + * 64-bit Host Destination Address. + * This is the host address where the data will be written to. */ - uint64_t tx_llfc_logical_msgs; - /* Total number of HCFC messages transmitted */ - uint64_t tx_hcfc_msgs; - /* Total number of TX collisions */ - uint64_t tx_total_collisions; - /* Total number of transmitted bytes */ - uint64_t tx_bytes; - /* Total number of end-to-end HOL frames */ - uint64_t tx_xthol_frames; - /* Total Tx Drops per Port reported by STATS block */ - uint64_t tx_stat_discard; - /* Total Tx Error Drops per Port reported by STATS block */ - uint64_t tx_stat_error; + uint64_t host_dest_addr; + /* 32-bit NVRAM byte-offset to read from. */ + uint32_t offset; + /* Total length of NVRAM contents to be read, in bytes. */ + uint32_t len; } __attribute__((packed)); -/* Port Rx Statistics Formats */ -/* rx_port_stats (size:4224b/528B) */ -struct rx_port_stats { - /* Total Number of 64 Bytes frames received */ - uint64_t rx_64b_frames; - /* Total Number of 65-127 Bytes frames received */ - uint64_t rx_65b_127b_frames; - /* Total Number of 128-255 Bytes frames received */ - uint64_t rx_128b_255b_frames; - /* Total Number of 256-511 Bytes frames received */ - uint64_t rx_256b_511b_frames; - /* Total Number of 512-1023 Bytes frames received */ - uint64_t rx_512b_1023b_frames; - /* Total Number of 1024-1518 Bytes frames received */ - uint64_t rx_1024b_1518_frames; - /* - * Total Number of each good VLAN (exludes FCS errors) - * frame received which is 1519 to 1522 bytes in length - * inclusive (excluding framing bits but including FCS bytes). - */ - uint64_t rx_good_vlan_frames; - /* Total Number of 1519-2047 Bytes frames received */ - uint64_t rx_1519b_2047b_frames; - /* Total Number of 2048-4095 Bytes frames received */ - uint64_t rx_2048b_4095b_frames; - /* Total Number of 4096-9216 Bytes frames received */ - uint64_t rx_4096b_9216b_frames; - /* Total Number of 9217-16383 Bytes frames received */ - uint64_t rx_9217b_16383b_frames; - /* Total number of frames received */ - uint64_t rx_total_frames; - /* Total number of unicast frames received */ - uint64_t rx_ucast_frames; - /* Total number of multicast frames received */ - uint64_t rx_mcast_frames; - /* Total number of broadcast frames received */ - uint64_t rx_bcast_frames; - /* Total number of received frames with FCS error */ - uint64_t rx_fcs_err_frames; - /* Total number of control frames received */ - uint64_t rx_ctrl_frames; - /* Total number of PAUSE frames received */ - uint64_t rx_pause_frames; - /* Total number of PFC frames received */ - uint64_t rx_pfc_frames; - /* - * Total number of frames received with an unsupported - * opcode - */ - uint64_t rx_unsupported_opcode_frames; - /* - * Total number of frames received with an unsupported - * DA for pause and PFC - */ - uint64_t rx_unsupported_da_pausepfc_frames; - /* Total number of frames received with an unsupported SA */ - uint64_t rx_wrong_sa_frames; - /* Total number of received packets with alignment error */ - uint64_t rx_align_err_frames; - /* Total number of received frames with out-of-range length */ - uint64_t rx_oor_len_frames; - /* Total number of received frames with error termination */ - uint64_t rx_code_err_frames; +/* hwrm_nvm_raw_dump_output (size:128b/16B) */ +struct hwrm_nvm_raw_dump_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Total number of received frames with a false carrier is - * detected during idle, as defined by RX_ER samples active - * and RXD is 0xE. The event is reported along with the - * statistics generated on the next received frame. Only - * one false carrier condition can be detected and logged - * between frames. - * - * Carrier event, valid for 10M/100M speed modes only. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t rx_false_carrier_frames; - /* Total number of over-sized frames received */ - uint64_t rx_ovrsz_frames; - /* Total number of jabber packets received */ - uint64_t rx_jbr_frames; - /* Total number of received frames with MTU error */ - uint64_t rx_mtu_err_frames; - /* Total number of received frames with CRC match */ - uint64_t rx_match_crc_frames; - /* Total number of frames received promiscuously */ - uint64_t rx_promiscuous_frames; + uint8_t valid; +} __attribute__((packed)); + +/**************************** + * hwrm_nvm_get_dir_entries * + ****************************/ + + +/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ +struct hwrm_nvm_get_dir_entries_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Total number of received frames with one or two VLAN - * tags + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint64_t rx_tagged_frames; - /* Total number of received frames with two VLAN tags */ - uint64_t rx_double_tagged_frames; - /* Total number of truncated frames received */ - uint64_t rx_trunc_frames; - /* Total number of good frames (without errors) received */ - uint64_t rx_good_frames; + uint16_t cmpl_ring; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 0 + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint64_t rx_pfc_xon2xoff_frames_pri0; + uint16_t seq_id; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 1 + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t rx_pfc_xon2xoff_frames_pri1; + uint16_t target_id; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 2 + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint64_t rx_pfc_xon2xoff_frames_pri2; + uint64_t resp_addr; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 3 + * 64-bit Host Destination Address. + * This is the host address where the directory will be written. */ - uint64_t rx_pfc_xon2xoff_frames_pri3; + uint64_t host_dest_addr; +} __attribute__((packed)); + +/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ +struct hwrm_nvm_get_dir_entries_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 4 + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t rx_pfc_xon2xoff_frames_pri4; + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_nvm_get_dir_info * + *************************/ + + +/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ +struct hwrm_nvm_get_dir_info_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 5 + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint64_t rx_pfc_xon2xoff_frames_pri5; + uint16_t cmpl_ring; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 6 + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint64_t rx_pfc_xon2xoff_frames_pri6; + uint16_t seq_id; /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 7 + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t rx_pfc_xon2xoff_frames_pri7; + uint16_t target_id; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 0 + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint64_t rx_pfc_ena_frames_pri0; + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ +struct hwrm_nvm_get_dir_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of directory entries in the directory. */ + uint32_t entries; + /* Size of each directory entry, in bytes. */ + uint32_t entry_length; + uint8_t unused_0[7]; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 1 + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t rx_pfc_ena_frames_pri1; + uint8_t valid; +} __attribute__((packed)); + +/****************** + * hwrm_nvm_write * + ******************/ + + +/* hwrm_nvm_write_input (size:384b/48B) */ +struct hwrm_nvm_write_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 2 + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint64_t rx_pfc_ena_frames_pri2; + uint16_t cmpl_ring; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 3 + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint64_t rx_pfc_ena_frames_pri3; + uint16_t seq_id; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 4 + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM */ - uint64_t rx_pfc_ena_frames_pri4; + uint16_t target_id; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 5 + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint64_t rx_pfc_ena_frames_pri5; + uint64_t resp_addr; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 6 + * 64-bit Host Source Address. + * This is where the source data is. */ - uint64_t rx_pfc_ena_frames_pri6; + uint64_t host_src_addr; + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ + uint16_t dir_type; /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 7 + * Directory ordinal. + * The 0-based instance of the combined Directory Entry Type and Extension. */ - uint64_t rx_pfc_ena_frames_pri7; - /* Total Number of frames received with SCH CRC error */ - uint64_t rx_sch_crc_err_frames; - /* Total Number of under-sized frames received */ - uint64_t rx_undrsz_frames; - /* Total Number of fragmented frames received */ - uint64_t rx_frag_frames; - /* Total number of RX EEE LPI Events */ - uint64_t rx_eee_lpi_events; - /* EEE LPI Duration Counter on RX */ - uint64_t rx_eee_lpi_duration; + uint16_t dir_ordinal; + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ + uint16_t dir_ext; + /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ + uint16_t dir_attr; /* - * Total number of physical type Link Level Flow Control - * (LLFC) messages received + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ - uint64_t rx_llfc_physical_msgs; + uint32_t dir_data_length; + /* Option. */ + uint16_t option; + uint16_t flags; /* - * Total number of logical type Link Level Flow Control - * (LLFC) messages received + * When this bit is '1', the original active image + * will not be removed. TBD: what purpose is this? */ - uint64_t rx_llfc_logical_msgs; + #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ + UINT32_C(0x1) /* - * Total number of logical type Link Level Flow Control - * (LLFC) messages received with CRC error + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). + * If this value is less than the specified data length, it will be ignored. + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ - uint64_t rx_llfc_msgs_with_crc_err; - /* Total number of HCFC messages received */ - uint64_t rx_hcfc_msgs; - /* Total number of HCFC messages received with CRC error */ - uint64_t rx_hcfc_msgs_with_crc_err; - /* Total number of received bytes */ - uint64_t rx_bytes; - /* Total number of bytes received in runt frames */ - uint64_t rx_runt_bytes; - /* Total number of runt frames received */ - uint64_t rx_runt_frames; - /* Total Rx Discards per Port reported by STATS block */ - uint64_t rx_stat_discard; - uint64_t rx_stat_err; -} __attribute__((packed)); - -/* Port Rx Statistics extended Formats */ -/* rx_port_stats_ext (size:320b/40B) */ -struct rx_port_stats_ext { - /* Number of times link state changed to down */ - uint64_t link_down_events; - /* Number of times the idle rings with pause bit are found */ - uint64_t continuous_pause_events; - /* Number of times the active rings pause bit resumed back */ - uint64_t resume_pause_events; - /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */ - uint64_t continuous_roce_pause_events; - /* Number of times, the ROCE cos queue PFC is enabled back */ - uint64_t resume_roce_pause_events; + uint32_t dir_item_length; + uint32_t unused_0; } __attribute__((packed)); -/* PCIe Statistics Formats */ -/* pcie_ctx_hw_stats (size:768b/96B) */ -struct pcie_ctx_hw_stats { - /* Number of physical layer receiver errors */ - uint64_t pcie_pl_signal_integrity; - /* Number of DLLP CRC errors detected by Data Link Layer */ - uint64_t pcie_dl_signal_integrity; +/* hwrm_nvm_write_output (size:128b/16B) */ +struct hwrm_nvm_write_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * Number of TLP LCRC and sequence number errors detected - * by Data Link Layer + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ - uint64_t pcie_tl_signal_integrity; - /* Number of times LTSSM entered Recovery state */ - uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been trasmitted */ - uint64_t pcie_tx_traffic_rate; - /* Number of TLP bytes that have been received */ - uint64_t pcie_rx_traffic_rate; - /* Number of DLLP bytes that have been trasmitted */ - uint64_t pcie_tx_dllp_statistics; - /* Number of DLLP bytes that have been received */ - uint64_t pcie_rx_dllp_statistics; + uint32_t dir_item_length; + /* The directory index of the created or modified item. */ + uint16_t dir_idx; + uint8_t unused_0; /* - * Number of times spent in each phase of gen3 - * equalization + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t pcie_equalization_time; - /* Records the last 16 transitions of the LTSSM */ - uint32_t pcie_ltssm_histogram[4]; + uint8_t valid; +} __attribute__((packed)); + +/* hwrm_nvm_write_cmd_err (size:64b/8B) */ +struct hwrm_nvm_write_cmd_err { /* - * Record the last 8 reasons on why LTSSM transitioned - * to Recovery + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. */ - uint64_t pcie_recovery_histogram; + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to fragmentation */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + /* nvm is completely full. */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ + HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE + uint8_t unused_0[7]; } __attribute__((packed)); -/********************** - * hwrm_exec_fwd_resp * - **********************/ - +/******************* + * hwrm_nvm_modify * + *******************/ -/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ -struct hwrm_exec_fwd_resp_input { + +/* hwrm_nvm_modify_input (size:320b/40B) */ +struct hwrm_nvm_modify_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21804,25 +26967,25 @@ struct hwrm_exec_fwd_resp_input { */ uint64_t resp_addr; /* - * This is an encapsulated request. This request should - * be executed by the HWRM and the response should be - * provided in the response buffer inside the encapsulated - * request. + * 64-bit Host Source Address. + * This is where the modified data is. */ - uint32_t encap_request[26]; + uint64_t host_src_addr; + /* 16-bit directory entry index. */ + uint16_t dir_idx; + uint8_t unused_0[2]; + /* 32-bit NVRAM byte-offset to modify content from. */ + uint32_t offset; /* - * This value indicates the target id of the response to - * the encapsulated request. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * Length of data to be modified, in bytes. The length shall + * be non-zero. */ - uint16_t encap_resp_target_id; - uint8_t unused_0[6]; + uint32_t len; + uint8_t unused_1[4]; } __attribute__((packed)); -/* hwrm_exec_fwd_resp_output (size:128b/16B) */ -struct hwrm_exec_fwd_resp_output { +/* hwrm_nvm_modify_output (size:128b/16B) */ +struct hwrm_nvm_modify_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21842,13 +27005,13 @@ struct hwrm_exec_fwd_resp_output { uint8_t valid; } __attribute__((packed)); -/************************ - * hwrm_reject_fwd_resp * - ************************/ +/*************************** + * hwrm_nvm_find_dir_entry * + ***************************/ -/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ -struct hwrm_reject_fwd_resp_input { +/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ +struct hwrm_nvm_find_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21876,26 +27039,42 @@ struct hwrm_reject_fwd_resp_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * This is an encapsulated request. This request should - * be rejected by the HWRM and the error response should be - * provided in the response buffer inside the encapsulated - * request. + * This bit must be '1' for the dir_idx_valid field to be + * configured. */ - uint32_t encap_request[26]; + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \ + UINT32_C(0x1) + /* Directory Entry Index */ + uint16_t dir_idx; + /* Directory Entry (Image) Type */ + uint16_t dir_type; /* - * This value indicates the target id of the response to - * the encapsulated request. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * Directory ordinal. + * The instance of this Directory Type */ - uint16_t encap_resp_target_id; - uint8_t unused_0[6]; + uint16_t dir_ordinal; + /* The Directory Entry Extension flags. */ + uint16_t dir_ext; + /* This value indicates the search option using dir_ordinal. */ + uint8_t opt_ordinal; + /* This value indicates the search option using dir_ordinal. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 + /* Equal to specified ordinal value. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) + /* Greater than or equal to specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) + /* Greater than specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ + HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT + uint8_t unused_0[3]; } __attribute__((packed)); -/* hwrm_reject_fwd_resp_output (size:128b/16B) */ -struct hwrm_reject_fwd_resp_output { +/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ +struct hwrm_nvm_find_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21904,6 +27083,19 @@ struct hwrm_reject_fwd_resp_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Allocated NVRAM for this directory entry, in bytes. */ + uint32_t dir_item_length; + /* Size of the stored data for this directory entry, in bytes. */ + uint32_t dir_data_length; + /* + * Firmware version. + * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. + */ + uint32_t fw_ver; + /* Directory ordinal. */ + uint16_t dir_ordinal; + /* Directory Entry Index */ + uint16_t dir_idx; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -21915,13 +27107,13 @@ struct hwrm_reject_fwd_resp_output { uint8_t valid; } __attribute__((packed)); -/***************** - * hwrm_fwd_resp * - *****************/ +/**************************** + * hwrm_nvm_erase_dir_entry * + ****************************/ -/* hwrm_fwd_resp_input (size:1024b/128B) */ -struct hwrm_fwd_resp_input { +/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ +struct hwrm_nvm_erase_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21949,41 +27141,13 @@ struct hwrm_fwd_resp_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value indicates the target id of the encapsulated - * response. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM - */ - uint16_t encap_resp_target_id; - /* - * This value indicates the completion ring the encapsulated - * response will be optionally completed on. If the value is - * -1, then no CR completion shall be generated for the - * encapsulated response. Any other value must be a - * valid CR ring_id value. If a valid encap_resp_cmpl_ring - * is provided, then a CR completion shall be generated for - * the encapsulated response. - */ - uint16_t encap_resp_cmpl_ring; - /* This field indicates the length of encapsulated response. */ - uint16_t encap_resp_len; - uint8_t unused_0; - uint8_t unused_1; - /* - * This is the host address where the encapsulated response - * will be written. - * This area must be 16B aligned and must be cleared to zero - * before the original request is made. - */ - uint64_t encap_resp_addr; - /* This is an encapsulated response. */ - uint32_t encap_resp[24]; + /* Directory Entry Index */ + uint16_t dir_idx; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_fwd_resp_output (size:128b/16B) */ -struct hwrm_fwd_resp_output { +/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ +struct hwrm_nvm_erase_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22003,13 +27167,13 @@ struct hwrm_fwd_resp_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_nvm_raw_write_blk * - **************************/ +/************************* + * hwrm_nvm_get_dev_info * + *************************/ -/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */ -struct hwrm_nvm_raw_write_blk_input { +/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ +struct hwrm_nvm_get_dev_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22037,22 +27201,10 @@ struct hwrm_nvm_raw_write_blk_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * 64-bit Host Source Address. - * This is the loation of the source data to be written. - */ - uint64_t host_src_addr; - /* - * 32-bit Destination Address. - * This is the NVRAM byte-offset where the source data will be written to. - */ - uint32_t dest_addr; - /* Length of data to be written, in bytes. */ - uint32_t len; } __attribute__((packed)); -/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ -struct hwrm_nvm_raw_write_blk_output { +/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ +struct hwrm_nvm_get_dev_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22061,7 +27213,18 @@ struct hwrm_nvm_raw_write_blk_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Manufacturer ID. */ + uint16_t manufacturer_id; + /* Device ID. */ + uint16_t device_id; + /* Sector size of the NVRAM device. */ + uint32_t sector_size; + /* Total size, in bytes of the NVRAM device. */ + uint32_t nvram_size; + uint32_t reserved_size; + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ + uint32_t available_size; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22072,13 +27235,13 @@ struct hwrm_nvm_raw_write_blk_output { uint8_t valid; } __attribute__((packed)); -/***************** - * hwrm_nvm_read * - *****************/ +/************************** + * hwrm_nvm_mod_dir_entry * + **************************/ -/* hwrm_nvm_read_input (size:320b/40B) */ -struct hwrm_nvm_read_input { +/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ +struct hwrm_nvm_mod_dir_entry_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22106,23 +27269,32 @@ struct hwrm_nvm_read_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * 64-bit Host Destination Address. - * This is the host address where the data will be written to. + * This bit must be '1' for the checksum field to be + * configured. */ - uint64_t host_dest_addr; - /* The 0-based index of the directory entry. */ + #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1) + /* Directory Entry Index */ uint16_t dir_idx; - uint8_t unused_0[2]; - /* The NVRAM byte-offset to read from. */ - uint32_t offset; - /* The length of the data to be read, in bytes. */ - uint32_t len; - uint8_t unused_1[4]; + /* + * Directory ordinal. + * The (0-based) instance of this Directory Type. + */ + uint16_t dir_ordinal; + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ + uint16_t dir_ext; + /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ + uint16_t dir_attr; + /* + * If valid, then this field updates the checksum + * value of the content in the directory entry. + */ + uint32_t checksum; } __attribute__((packed)); -/* hwrm_nvm_read_output (size:128b/16B) */ -struct hwrm_nvm_read_output { +/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ +struct hwrm_nvm_mod_dir_entry_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22142,13 +27314,13 @@ struct hwrm_nvm_read_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_nvm_raw_dump * - *********************/ +/************************** + * hwrm_nvm_verify_update * + **************************/ -/* hwrm_nvm_raw_dump_input (size:256b/32B) */ -struct hwrm_nvm_raw_dump_input { +/* hwrm_nvm_verify_update_input (size:192b/24B) */ +struct hwrm_nvm_verify_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22176,19 +27348,26 @@ struct hwrm_nvm_raw_dump_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Directory Entry Type, to be verified. */ + uint16_t dir_type; /* - * 64-bit Host Destination Address. - * This is the host address where the data will be written to. + * Directory ordinal. + * The instance of the Directory Type to be verified. */ - uint64_t host_dest_addr; - /* 32-bit NVRAM byte-offset to read from. */ - uint32_t offset; - /* Total length of NVRAM contents to be read, in bytes. */ - uint32_t len; + uint16_t dir_ordinal; + /* + * The Directory Entry Extension flags. + * The "UPDATE" extension flag must be set in this value. + * A corresponding directory entry with the same type and ordinal values but *without* + * the "UPDATE" extension flag must also exist. The other flags of the extension must + * be identical between the active and update entries. + */ + uint16_t dir_ext; + uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_nvm_raw_dump_output (size:128b/16B) */ -struct hwrm_nvm_raw_dump_output { +/* hwrm_nvm_verify_update_output (size:128b/16B) */ +struct hwrm_nvm_verify_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22208,13 +27387,13 @@ struct hwrm_nvm_raw_dump_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_nvm_get_dir_entries * - ****************************/ +/*************************** + * hwrm_nvm_install_update * + ***************************/ -/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ -struct hwrm_nvm_get_dir_entries_input { +/* hwrm_nvm_install_update_input (size:192b/24B) */ +struct hwrm_nvm_install_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22243,14 +27422,49 @@ struct hwrm_nvm_get_dir_entries_input { */ uint64_t resp_addr; /* - * 64-bit Host Destination Address. - * This is the host address where the directory will be written. + * Installation type. If the value 3 through 0xffff is used, + * only packaged items with that type value will be installed and + * conditional installation directives for those packaged items + * will be over-ridden (i.e. 'create' or 'replace' will be treated + * as 'install'). */ - uint64_t host_dest_addr; + uint32_t install_type; + /* + * Perform a normal package installation. Conditional installation + * directives (e.g. 'create' and 'replace') of packaged items + * will be followed. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0) + /* + * Install all packaged items regardless of installation directive + * (i.e. treat all packaged items as though they have an installation + * directive of 'install'). + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \ + UINT32_C(0xffffffff) + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \ + HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL + uint16_t flags; + /* If set to 1, then securely erase all unused locations in persistent storage. */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ + UINT32_C(0x1) + /* + * If set to 1, then unspecifed images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ + UINT32_C(0x2) + /* + * If set to 1, FW will defragment the NVM if defragmentation is required for the update. + * Allow additional time for this command to complete if this bit is set to 1. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ + UINT32_C(0x4) + uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ -struct hwrm_nvm_get_dir_entries_output { +/* hwrm_nvm_install_update_output (size:192b/24B) */ +struct hwrm_nvm_install_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22259,7 +27473,55 @@ struct hwrm_nvm_get_dir_entries_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * Bit-mask of successfully installed items. + * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc. + * A value of 0 indicates that no items were successfully installed. + */ + uint64_t installed_items; + /* result is 8 b */ + uint8_t result; + /* There was no problem with the package installation. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \ + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS + /* problem_item is 8 b */ + uint8_t problem_item; + /* There was no problem with any packaged items. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \ + UINT32_C(0x0) + /* There was a problem with the NVM package itself. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \ + UINT32_C(0xff) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \ + HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE + /* reset_required is 8 b */ + uint8_t reset_required; + /* + * No reset is required for installed/updated firmware or + * microcode to take effect. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \ + UINT32_C(0x0) + /* + * A PCIe reset (e.g. system reboot) is + * required for newly installed/updated firmware or + * microcode to take effect. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \ + UINT32_C(0x1) + /* + * A controller power reset (e.g. system power-cycle) is + * required for newly installed/updated firmware or + * microcode to take effect. Some newly installed/updated + * firmware or microcode may still take effect upon the + * next PCIe reset. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \ + UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \ + HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22270,13 +27532,31 @@ struct hwrm_nvm_get_dir_entries_output { uint8_t valid; } __attribute__((packed)); -/************************* - * hwrm_nvm_get_dir_info * - *************************/ +/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ +struct hwrm_nvm_install_update_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to fragmentation */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + /* nvm is completely full. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + uint8_t unused_0[7]; +} __attribute__((packed)); + +/****************** + * hwrm_nvm_flush * + ******************/ -/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ -struct hwrm_nvm_get_dir_info_input { +/* hwrm_nvm_flush_input (size:128b/16B) */ +struct hwrm_nvm_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22306,8 +27586,8 @@ struct hwrm_nvm_get_dir_info_input { uint64_t resp_addr; } __attribute__((packed)); -/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ -struct hwrm_nvm_get_dir_info_output { +/* hwrm_nvm_flush_output (size:128b/16B) */ +struct hwrm_nvm_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22316,10 +27596,6 @@ struct hwrm_nvm_get_dir_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of directory entries in the directory. */ - uint32_t entries; - /* Size of each directory entry, in bytes. */ - uint32_t entry_length; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -22331,13 +27607,29 @@ struct hwrm_nvm_get_dir_info_output { uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_nvm_write * - ******************/ +/* hwrm_nvm_flush_cmd_err (size:64b/8B) */ +struct hwrm_nvm_flush_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* flush could not be performed */ + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \ + HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __attribute__((packed)); +/************************* + * hwrm_nvm_get_variable * + *************************/ -/* hwrm_nvm_write_input (size:384b/48B) */ -struct hwrm_nvm_write_input { + +/* hwrm_nvm_get_variable_input (size:320b/40B) */ +struct hwrm_nvm_get_variable_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22366,48 +27658,49 @@ struct hwrm_nvm_write_input { */ uint64_t resp_addr; /* - * 64-bit Host Source Address. - * This is where the source data is. - */ - uint64_t host_src_addr; - /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ - uint16_t dir_type; - /* - * Directory ordinal. - * The 0-based instance of the combined Directory Entry Type and Extension. - */ - uint16_t dir_ordinal; - /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */ - uint16_t dir_ext; - /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ - uint16_t dir_attr; - /* - * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to reflect this value once the write is complete. + * This is the host address where + * nvm variable will be stored */ - uint32_t dir_data_length; - /* Option. */ - uint16_t option; - uint16_t flags; + uint64_t dest_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \ + UINT32_C(0xffff) + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \ + HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF + /* + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth + */ + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t flags; /* - * When this bit is '1', the original active image - * will not be removed. TBD: what purpose is this? + * When this bit is set to 1, the factory default value will be returned, + * 0 returns the operational value. */ - #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ + #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \ UINT32_C(0x1) - /* - * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). - * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate - * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). - */ - uint32_t dir_item_length; - uint32_t unused_0; + uint8_t unused_0; } __attribute__((packed)); -/* hwrm_nvm_write_output (size:128b/16B) */ -struct hwrm_nvm_write_output { +/* hwrm_nvm_get_variable_output (size:128b/16B) */ +struct hwrm_nvm_get_variable_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22416,14 +27709,25 @@ struct hwrm_nvm_write_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* size of data of the actual variable retrieved in bits */ + uint16_t data_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. + * option_num is the option number for the data retrieved. It is possible in the + * future that the option number returned would be different than requested. This + * condition could occur if an option is deprecated and a new option id is defined + * with similar characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable result with + * the option id from the response. */ - uint32_t dir_item_length; - /* The directory index of the created or modified item. */ - uint16_t dir_idx; - uint8_t unused_0; + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \ + UINT32_C(0xffff) + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \ + HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22434,31 +27738,33 @@ struct hwrm_nvm_write_output { uint8_t valid; } __attribute__((packed)); -/* hwrm_nvm_write_cmd_err (size:64b/8B) */ -struct hwrm_nvm_write_cmd_err { +/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ +struct hwrm_nvm_get_variable_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) - /* nvm is completely full. */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) - #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ - HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* variable does not exist */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) + /* configuration is corrupted and the variable cannot be saved */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) + /* length specified is too small */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3) + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \ + HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT uint8_t unused_0[7]; } __attribute__((packed)); -/******************* - * hwrm_nvm_modify * - *******************/ +/************************* + * hwrm_nvm_set_variable * + *************************/ -/* hwrm_nvm_modify_input (size:320b/40B) */ -struct hwrm_nvm_modify_input { +/* hwrm_nvm_set_variable_input (size:320b/40B) */ +struct hwrm_nvm_set_variable_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22487,25 +27793,64 @@ struct hwrm_nvm_modify_input { */ uint64_t resp_addr; /* - * 64-bit Host Source Address. - * This is where the modified data is. - */ - uint64_t host_src_addr; - /* 16-bit directory entry index. */ - uint16_t dir_idx; - uint8_t unused_0[2]; - /* 32-bit NVRAM byte-offset to modify content from. */ - uint32_t offset; - /* - * Length of data to be modified, in bytes. The length shall - * be non-zero. + * This is the host address where + * nvm variable will be copied from */ - uint32_t len; - uint8_t unused_1[4]; + uint64_t src_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \ + UINT32_C(0xffff) + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \ + HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF + /* + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth + */ + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t flags; + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ + UINT32_C(0x1) + /* encryption method */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \ + UINT32_C(0xe) + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1 + /* No encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \ + (UINT32_C(0x0) << 1) + /* one-way encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \ + (UINT32_C(0x1) << 1) + /* symmetric AES256 encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \ + (UINT32_C(0x2) << 1) + /* SHA1 digest appended to plaintext contents, for authentication */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \ + (UINT32_C(0x3) << 1) + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \ + HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH + uint8_t unused_0; } __attribute__((packed)); -/* hwrm_nvm_modify_output (size:128b/16B) */ -struct hwrm_nvm_modify_output { +/* hwrm_nvm_set_variable_output (size:128b/16B) */ +struct hwrm_nvm_set_variable_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22525,13 +27870,31 @@ struct hwrm_nvm_modify_output { uint8_t valid; } __attribute__((packed)); -/*************************** - * hwrm_nvm_find_dir_entry * - ***************************/ +/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ +struct hwrm_nvm_set_variable_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* variable does not exist */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) + /* configuration is corrupted and the variable cannot be saved */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \ + HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR + uint8_t unused_0[7]; +} __attribute__((packed)); + +/**************************** + * hwrm_nvm_validate_option * + ****************************/ -/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ -struct hwrm_nvm_find_dir_entry_input { +/* hwrm_nvm_validate_option_input (size:320b/40B) */ +struct hwrm_nvm_validate_option_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22559,42 +27922,44 @@ struct hwrm_nvm_find_dir_entry_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the dir_idx_valid field to be - * configured. - */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \ - UINT32_C(0x1) - /* Directory Entry Index */ - uint16_t dir_idx; - /* Directory Entry (Image) Type */ - uint16_t dir_type; /* - * Directory ordinal. - * The instance of this Directory Type + * This is the host address where + * nvm variable will be copied from */ - uint16_t dir_ordinal; - /* The Directory Entry Extension flags. */ - uint16_t dir_ext; - /* This value indicates the search option using dir_ordinal. */ - uint8_t opt_ordinal; - /* This value indicates the search option using dir_ordinal. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 - /* Equal to specified ordinal value. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) - /* Greater than or equal to specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) - /* Greater than specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ - HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT - uint8_t unused_0[3]; + uint64_t src_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \ + UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \ + UINT32_C(0xffff) + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \ + HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF + /* + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth + */ + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ -struct hwrm_nvm_find_dir_entry_output { +/* hwrm_nvm_validate_option_output (size:128b/16B) */ +struct hwrm_nvm_validate_option_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22603,20 +27968,14 @@ struct hwrm_nvm_find_dir_entry_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Allocated NVRAM for this directory entry, in bytes. */ - uint32_t dir_item_length; - /* Size of the stored data for this directory entry, in bytes. */ - uint32_t dir_data_length; - /* - * Firmware version. - * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format. - */ - uint32_t fw_ver; - /* Directory ordinal. */ - uint16_t dir_ordinal; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[7]; + uint8_t result; + /* indicates that the value provided for the option is not matching with the saved data. */ + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) + /* indicates that the value provided for the option is matching the saved data. */ + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \ + HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22627,13 +27986,27 @@ struct hwrm_nvm_find_dir_entry_output { uint8_t valid; } __attribute__((packed)); -/**************************** - * hwrm_nvm_erase_dir_entry * - ****************************/ +/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ +struct hwrm_nvm_validate_option_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \ + HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN + uint8_t unused_0[7]; +} __attribute__((packed)); +/***************************** + * hwrm_nvm_factory_defaults * + *****************************/ -/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ -struct hwrm_nvm_erase_dir_entry_input { + +/* hwrm_nvm_factory_defaults_input (size:192b/24B) */ +struct hwrm_nvm_factory_defaults_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22661,13 +28034,19 @@ struct hwrm_nvm_erase_dir_entry_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[6]; + /* mode is 8 b */ + uint8_t mode; + /* If set to 1, it will trigger restoration of factory default settings */ + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0) + /* If set to 1, it will trigger creation of factory default settings */ + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1) + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \ + HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE + uint8_t unused_0[7]; } __attribute__((packed)); -/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ -struct hwrm_nvm_erase_dir_entry_output { +/* hwrm_nvm_factory_defaults_output (size:128b/16B) */ +struct hwrm_nvm_factory_defaults_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22676,7 +28055,19 @@ struct hwrm_nvm_erase_dir_entry_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t result; + /* factory defaults created successfully. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \ + UINT32_C(0x0) + /* factory defaults restored successfully. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \ + UINT32_C(0x1) + /* factory defaults already created. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \ + UINT32_C(0x2) + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \ + HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22687,5 +28078,25 @@ struct hwrm_nvm_erase_dir_entry_output { uint8_t valid; } __attribute__((packed)); +/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */ +struct hwrm_nvm_factory_defaults_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* valid configuration not present to create defaults */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \ + UINT32_C(0x1) + /* No saved configuration present to restore, restore failed */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \ + UINT32_C(0x2) + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \ + HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG + uint8_t unused_0[7]; +} __attribute__((packed)); #endif /* _HSI_STRUCT_DEF_DPDK_H_ */